Display device, method of manufacturing the display device and electronic device comprising the same

Abstract

The present specification discloses a display device, a method for manufacturing a display device, and an electronic device including the same. According to various embodiments of the present specification, a display device comprises a substrate including a first region and a second region, an anode conductive layer disposed on the substrate and including an auxiliary electrode, a pixel defining film disposed to cover one end of an auxiliary electrode so as to expose at least a portion of the upper surface of the auxiliary electrode, a light-emitting layer disposed on the anode conductive layer so as to expose at least a portion of the upper surface of the auxiliary electrode, and a common electrode disposed on the light-emitting layer so as to contact the auxiliary electrode, wherein the first region includes an area exposed by the pixel defining film on the upper surface of the auxiliary electrode, and the second region includes an area exposed by the light-emitting layer on the upper surface of the auxiliary electrode, and the area of ​​the region where the first region and the second region overlap in the thickness direction of the substrate may be smaller than the area of ​​the second region.

Description

Technology Field

[0001] This specification relates to a display device, a method for manufacturing a display device, and an electronic device including the same. Background Technology

[0002] Electroluminescence displays can be classified into inorganic and organic light-emitting displays depending on the material of the light-emitting layer. Active matrix type organic light-emitting displays include self-emissive Organic Light Emitting Diodes (OLEDs) and have the advantages of fast response speed, high luminous efficiency, brightness, and high viewing angles. In organic light-emitting displays, OLEDs are formed in each pixel. Organic light-emitting displays not only offer fast response speeds, excellent luminous efficiency, brightness, and viewing angles, but also superior contrast ratio and color reproduction because they can express black gradations as perfect black. The problem to be solved

[0003] The present specification aims to provide a display device with improved power consumption.

[0004] The problems of this specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by a person skilled in the art from the description below. means of solving the problem

[0005] According to various embodiments of the present specification, a display device comprises a substrate including a first region and a second region, an anode conductive layer disposed on the substrate and including an auxiliary electrode, a pixel defining film disposed to cover one end of an auxiliary electrode so as to expose at least a portion of the upper surface of the auxiliary electrode, a light-emitting layer disposed on the anode conductive layer so as to expose at least a portion of the upper surface of the auxiliary electrode, and a common electrode disposed on the light-emitting layer so as to contact the auxiliary electrode, wherein the first region includes an area exposed by the pixel defining film on the upper surface of the auxiliary electrode, and the second region includes an area exposed by the light-emitting layer on the upper surface of the auxiliary electrode, and the area of ​​the region where the first region and the second region overlap in the thickness direction of the substrate may be smaller than the area of ​​the second region.

[0006] According to various embodiments of the present specification, the anode conductive layer further comprises a pixel electrode, and at least a portion of the light-emitting layer may be disposed between the pixel electrode and the common electrode.

[0007] According to various embodiments of the present specification, the substrate may further include a display area comprising a first area and a second area, and a non-display area surrounding the display area.

[0008] According to various embodiments of the present specification, a first boundary is defined from the boundary of a first region, and a second boundary is defined from the boundary of a second region, and the first boundary may include a plurality of points that overlap with the second boundary in the thickness direction.

[0009] According to various embodiments of the present specification, a first boundary is defined from the boundary of a first region, and a second boundary is defined from the boundary of a second region, and the first boundary may include a first point and a second point that overlap with the second boundary in the thickness direction.

[0010] According to various embodiments of the present specification, a first center is defined from the center of a first region, a second center is defined from the center of a second region, and an imaginary straight line connecting a first point and a second point may be defined.

[0011] According to various embodiments of the present specification, a second center, a virtual straight line, and a first center may be arranged sequentially.

[0012] According to various embodiments of the present specification, the second center may overlap with a virtual straight line and thickness direction.

[0013] According to various embodiments of the present specification, a virtual straight line, a second center, and a first center may be arranged sequentially.

[0014] According to various embodiments of the present specification, an auxiliary electrode may be positioned to contact a common electrode in an area where a first region and a second region overlap in the thickness direction of the substrate.

[0015] According to a method for manufacturing a display device according to various embodiments of the present specification, the method comprises the steps of: forming a substrate including a first region and a second region; forming an anode conductive layer disposed on the substrate and including an auxiliary electrode; forming a pixel defining film disposed to cover one end of an auxiliary electrode so as to expose at least a portion of the upper surface of the auxiliary electrode; forming a light-emitting layer disposed on the anode conductive layer; removing at least a portion of the light-emitting layer so as to expose at least a portion of the upper surface of the auxiliary electrode; and detecting the location of the first region and the location of the second region, wherein the first region includes an area exposed by the pixel defining film on the upper surface of the auxiliary electrode, and the second region includes an area exposed by the light-emitting layer on the upper surface of the auxiliary electrode, and the area of ​​the region where the first region and the second region overlap in the thickness direction of the substrate may be smaller than the area of ​​the second region.

[0016] According to various embodiments of the present specification, the step of detecting the location of a first region and the location of a second region may be performed using a deep learning detection method that detects the type and location of an object (Object Detection).

[0017] According to various embodiments of the present specification, a step of comparing the positional relationship between a first region and a second region may be further included.

[0018] According to various embodiments of the present specification, the step of comparing the positional relationship between a first region and a second region may include: defining a first boundary from a boundary of the first region; defining a second boundary from a boundary of the second region; defining a virtual straight line by connecting a plurality of points where the first boundary and the second boundary overlap in the thickness direction; defining a first center from a center of the first region; and defining a second center from a center of the second region.

[0019] According to various embodiments of the present specification, the step of comparing the positional relationship between a first region and a second region may further include the step of comparing the positional relationship between a virtual straight line, a second center, and a first center.

[0020] According to various embodiments of the present specification, an electronic device comprises a processor that provides an image signal, a display module that receives an image signal from the processor and displays an image, and a power module that supplies power to the display module. The display module comprises a substrate having a first region and a second region, an anode conductive layer disposed on the substrate and including an auxiliary electrode, a pixel defining film disposed to cover one end of an auxiliary electrode so as to expose at least a portion of the upper surface of the auxiliary electrode, a light-emitting layer disposed on the anode conductive layer so as to expose at least a portion of the upper surface of the auxiliary electrode, and a common electrode disposed on the light-emitting layer so as to contact the auxiliary electrode. The first region includes an area exposed by the pixel defining film on the upper surface of the auxiliary electrode, and the second region includes an area exposed by the light-emitting layer on the upper surface of the auxiliary electrode. The area of ​​the region where the first region and the second region overlap in the thickness direction of the substrate may be smaller than the area of ​​the second region.

[0021] According to various embodiments of the present specification, an auxiliary electrode may be positioned to contact a common electrode in an area where a first region and a second region overlap in the thickness direction of the substrate.

[0022] According to various embodiments of the present specification, a first boundary is defined from the boundary of a first region, and a second boundary is defined from the boundary of a second region, and the first boundary may include a first point and a second point that overlap with the second boundary in the thickness direction.

[0023] According to various embodiments of the present specification, a first center is defined from the center of a first region, a second center is defined from the center of a second region, and an imaginary straight line connecting a first point and a second point may be defined.

[0024] According to various embodiments of the present specification, a virtual straight line, a second center, and a first center may be arranged sequentially. Effects of the invention

[0025] The detection unit clearly outputs a first subsequent signal when the second area completely overlaps with the first area. When the second area completely does not overlap with (misaligns with) the first area, it clearly outputs a second subsequent signal. However, if the area of ​​the overlapping region between the second area and the first area (e.g., the second contact area) is smaller than the area of ​​the second area, the detection unit may output a third subsequent signal. The output of a third subsequent signal may indicate a case where the detection unit fails to make a clear judgment regarding whether an appropriate contact area (e.g., the second contact area) has been secured or not secured. By providing a detailed judgment process for a display device that outputs a third subsequent signal, the present specification can induce the restart of the process.

[0026] In addition, according to the means disclosed in this specification, the type of recognition signal generated for a display device that outputs a third subsequent signal can be distinguished. Specifically, it can be distinguished whether the recognition signal is generated due to the inability to determine the positional relationship between the first area and the second area, or whether the contact area is adequately secured even though the recognition signal has been generated.

[0027] The present specification can provide a display device with reduced voltage drop and improved power consumption by distinguishing a display device with an appropriately secured contact area. Brief explanation of the drawing

[0028] FIG. 1 is a perspective view showing a display device according to one embodiment of the present specification. Figure 2 is a cross-sectional view taken along X1-X1' of Figure 1. FIG. 3 is a cross-sectional view showing a display device according to another embodiment of the present specification. FIG. 4 is a plan view showing a state in which a connecting film is attached to a wiring pad of a display device according to one embodiment of the present specification. FIG. 5 is a plan view showing a state in which a connection film is not attached to a wiring pad of a display device according to one embodiment of the present specification. FIG. 6 is a drawing showing pixels and wiring of a display device according to one embodiment of the present specification. FIG. 7 is a plan view schematically showing a part of the display area of ​​a display substrate according to one embodiment of the present specification. Figure 8 is a cross-sectional view taken along X2-X2' of Figure 7. FIG. 9 is an equivalent circuit diagram of a pixel according to one embodiment of the present specification. FIG. 10 is a cross-sectional view showing an example of a first transistor of a circuit layer according to an embodiment of the present specification. FIG. 11 is a cross-sectional view showing an example of a second transistor and a third transistor of a circuit layer according to an embodiment of the present specification. Figure 12 is a cross-sectional view showing the process of removing a portion of the light-emitting layer through a laser drilling process. Figure 13 is a plan view showing the location where the laser drilling margin area is placed. FIG. 14 is a block diagram illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 15 is a plan view showing a display device according to embodiments of the present specification. Fig. 16 is a cross-sectional view corresponding to Fig. 15. FIG. 17 is a block diagram illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 18 is a plan view showing a display device according to embodiments of the present specification. Fig. 19 is a cross-sectional view corresponding to Fig. 18. FIG. 20 is a block diagram for illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 21 is a flowchart for explaining a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 22 is a flowchart that explains in detail the determination process of a method for manufacturing a display device according to one embodiment of the present specification. FIG. 23 is a block diagram for illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 24 is a plan view showing a display device according to embodiments of the present specification. FIG. 25 is a cross-sectional view corresponding to FIG. 24. FIG. 26 is a block diagram illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 27 is a plan view showing a display device according to embodiments of the present specification. FIG. 28 is a cross-sectional view corresponding to FIG. 27. FIG. 29 is a plan view showing a display device according to embodiments of the present specification. FIG. 30 is a cross-sectional view corresponding to FIG. 29. FIG. 31 is a block diagram of an electronic device according to one embodiment of the present specification. FIG. 32 is a schematic diagram of an electronic device according to various embodiments of the present specification. Specific details for implementing the invention

[0029] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the invention according to this specification is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of this specification is complete and to fully inform those skilled in the art of the scope of the invention, and the invention according to this specification is defined only by the scope of the claims.

[0030] When elements or a layer are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout this specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for describing embodiments are exemplary and are not limited to those depicted in this specification.

[0031] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0032] The features of each of the various embodiments disclosed in this specification may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0033] Specific embodiments are described below with reference to the attached drawings. Components having substantially the same function among the embodiments are assigned the same reference numerals, and repetitive descriptions thereof are omitted.

[0034] FIG. 1 is a perspective view showing a display device according to one embodiment of the present specification. FIG. 2 is a cross-sectional view taken along X1-X1' of FIG. 1. FIG. 3 is a cross-sectional view showing a display device according to another embodiment of the present specification.

[0035] Referring to FIGS. 1 to 3, the display device (10) can be applied to various electronic devices such as tablet PCs, smartphones, car navigation units, cameras, center information displays (CID) provided in cars, wristwatch-type electronic devices, PDA (Personal Digital Assistant), PMP (Portable Multimedia Player), game consoles, small and medium-sized electronic devices, televisions, external billboards, monitors, personal computers, and laptop computers. These are presented merely as examples and may be adopted in other electronic devices as long as they do not deviate from the concept of the present invention.

[0036] In one embodiment, the display device (10) may be formed in a planar rectangular shape. The display device (10) may include two long sides extending in a first direction (DR1) and two short sides extending in a second direction (DR2) that intersects the first direction (DR1). The corners where the long sides and the short sides of the display device (10) meet may be right angles, but are not limited thereto, and may form a curved surface. In another embodiment, the long sides may extend in the second direction (DR2) and the short sides may extend in the first direction (DR1). The planar shape of the display device (10) is not limited to the examples provided and may be circular or other shapes.

[0037] In the illustrated drawing, the first direction (DR1) and the second direction (DR2) are each horizontal directions that intersect each other. For example, the first direction (DR1) and the second direction (DR2) may be mutually orthogonal. Additionally, the third direction (DR3) intersects the first direction (DR1) and the second direction (DR2), and may be, for example, an orthogonal vertical direction. Unless otherwise defined, in this specification, the direction indicated by the arrows of the first to third directions (DR1, DR2, DR3) may be referred to as one side, and the opposite direction may be referred to as the other side. Furthermore, in this specification, “up,” “upper side,” “top,” “top surface,” and “upper surface” refer to the direction in which the arrow of the drawing points among the third direction (DR3) based on the drawing, and “lower,” “lower side,” “lower part,” “bottom,” and “lower surface” refer to the direction opposite to the direction in which the arrow of the third direction (DR3) points based on the drawing.

[0038] The display device (10) may include a display area (DA) for displaying an image and a non-display area (NDA) for not displaying an image. In one embodiment, the non-display area (NDA) may be located around the display area (DA) and may surround the display area (DA).

[0039] In one embodiment, the display device (10) includes a display substrate (100), a color conversion substrate (200) facing the display substrate (100), and may further include a sealing portion (400) that combines the display substrate (100) and the color conversion substrate (200), and a filler material (300) filled between the display substrate (100) and the color conversion substrate (200).

[0040] A display substrate (100) may include elements and circuits for displaying an image, such as a pixel circuit such as a switching element, a pixel defining film that defines a light-emitting region and a non-light-emitting region to be described later in a display area (DA), and a self-light emitting element. In one embodiment, the self-light emitting element may include at least one of an organic light-emitting diode, a quantum dot light-emitting diode, an inorganic-based micro light-emitting diode (e.g., Micro LED), and an inorganic-based nano light-emitting diode (e.g., nano LED). For convenience of explanation, the case where the self-light emitting element is an organic light-emitting diode will be described as an example below.

[0041] A color conversion substrate (200) may be positioned on a display substrate (100) and may face the display substrate (100). In one embodiment, the color conversion substrate (200) may include a color conversion pattern that converts the color of incident light. In one embodiment, the color conversion pattern may include at least one of a color filter and a wavelength conversion pattern.

[0042] A sealing portion (400) may be located between the display substrate (100) and the color conversion substrate (200) in the non-display area (NDA). The sealing portion (400) may be positioned along the edges of the display substrate (100) and the color conversion substrate (200) in the non-display area (NDA) to surround the display area (DA) on a plane. The display substrate (100) and the color conversion substrate (200) may be mutually coupled through the sealing portion (400).

[0043] In one embodiment, the sealing portion (400) may be made of an organic material. For example, the sealing portion (400) may be made of an epoxy resin, but is not limited thereto.

[0044] A filler material (300) may be located in the space between the display substrate (100) and the color conversion substrate (200) surrounded by the sealing portion (400). The filler material (300) may fill the space between the display substrate (100) and the color conversion substrate (200).

[0045] In one embodiment, the filler (300) may be made of a material capable of transmitting light. In one embodiment, the filler (300) may be made of an organic material. For example, the filler (300) may be made of a silicone-based organic material, an epoxy-based organic material, etc., but is not limited thereto. In another embodiment, the filler (300) may be omitted.

[0046] In another embodiment, the display device (10_1) may not include a sealing portion (400). For example, the color conversion substrate (200_1) of the display device (10_1) may be an encapsulation substrate. The color conversion substrate (200_1) may include a protrusion disposed along the outer edge of the color conversion substrate (200_1) and protruding toward the display substrate (100) in a third direction (DR3), and a recess portion surrounded by said protrusion. The internal space may be sealed by the display substrate (100), the color conversion substrate (200_1), and said protrusion. A filler (300) may be filled into the recess portion.

[0047] FIG. 4 is a plan view showing a state in which a connecting film is attached to a wiring pad of a display device according to one embodiment of the present specification. FIG. 5 is a plan view showing a state in which a connecting film is not attached to a wiring pad of a display device according to one embodiment of the present specification.

[0048] Referring to FIGS. 4 and 5, the display device (10) may include a display substrate (100), a connecting film (510), a display driving unit (520), a circuit board (530), a timing control unit (540), a power supply unit (550), and a gate driving unit (560).

[0049] The display substrate (100) may be formed in a rectangular shape on a plane. For example, the display substrate (100) may have a rectangular planar shape having a long side in the first direction (DR1) and a short side in the second direction (DR2). The corner where the long side in the first direction (DR1) and the short side in the second direction (DR2) meet may be formed at a right angle or rounded to have a predetermined curvature. The planar shape of the display substrate (100) is not limited to a rectangle and may be formed in other polygons, circles, or ellipses. For example, the display substrate (100) may be formed flat, but is not limited thereto. As another example, the display substrate (100) may be formed to be bent with a predetermined curvature.

[0050] The display substrate (100) may include a display area (DA) and a non-display area (NDA).

[0051] The display area (DA) is an area for displaying images and can be defined as the central area of ​​the display substrate (100). In one embodiment, the display area (DA) may include a pixel (SP), a gate line (GL), a data line (DL), an initialization voltage line (VIL), a first voltage line (VDL), a horizontal voltage line (HVDL), a vertical voltage line (VVSL), and a second voltage line (VSL).

[0052] A pixel (SP) may be formed in each pixel region intersected by data lines (DL) and gate lines (GL). In one embodiment, the pixel (SP) may include first to third pixels (SP1, SP2, SP3). Each of the first to third pixels (SP1, SP2, SP3) may be connected to a gate line (GL) and a data line (DL). Each of the first to third pixels (SP1, SP2, SP3) may be defined as a minimum unit region that outputs light.

[0053] Each of the first to third pixels (SP1, SP2, SP3) may include an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (Quantum Dot LED) including a quantum dot light-emitting layer, a micro light-emitting diode (Micro LED), or an inorganic light-emitting diode (Inorganic LED) including an inorganic semiconductor.

[0054] The first pixel (SP1) can emit light of a first color or red light, the second pixel (SP2) can emit light of a second color or green light, and the third pixel (SP3) can emit light of a third color or blue light. The pixel circuit of the first pixel (SP1), the pixel circuit of the second pixel (SP2), and the pixel circuit of the third pixel (SP3) may be arranged in order in the opposite direction of the second direction (DR2), but the order of the pixel circuits is not limited thereto.

[0055] A gate line (GL) may include a first gate line (GL1) and a second gate line (GL2). The first gate lines (GL1) may extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2). The first gate line (GL1) may receive a first gate signal from a gate driver (560) and supply the first gate signal to the first to third pixels (SP1, SP2, SP3).

[0056] The second gate lines (GL2) can be extended in the first direction (DR1) and spaced apart from each other in the second direction (DR2). The second gate lines (GL2) can receive a second gate signal from the gate driver (560) and supply the second gate signal to the first to third pixels (SP1, SP2, SP3).

[0057] Data lines (DL) may be extended in a second direction (DR2) and spaced apart from each other in a first direction (DR1). Data lines (DL) may include first to third data lines (DL1, DL2, DL3). Each of the first to third data lines (DL1, DL2, DL3) may supply data voltage to each of the first to third pixels (SP1, SP2, SP3).

[0058] The initialization voltage lines (VIL) can be extended in a second direction (DR2) and spaced apart from each other in a first direction (DR1). The initialization voltage lines (VIL) can supply an initialization voltage received from the display driver (520) to each pixel circuit of the first to third pixels (SP1, SP2, SP3). The initialization voltage lines (VIL) can receive a sensing signal from each pixel circuit of the first to third pixels (SP1, SP2, SP3) and supply it to the display driver (520).

[0059] The first voltage lines (VDL) can be extended in the second direction (DR2) and spaced apart from each other in the first direction (DR1). The first voltage lines (VDL) can supply a driving voltage or high potential voltage received from the power supply unit (550) to the first to third pixels (SP1, SP2, SP3).

[0060] Horizontal voltage lines (HVDL) may extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2). A horizontal voltage line (HVDL) may be connected to a first voltage line (VDL). A horizontal voltage line (HVDL) may receive a driving voltage or a high potential voltage from the first voltage line (VDL).

[0061] The vertical voltage lines (VVSL) can be extended in a second direction (DR2) and spaced apart from each other in a first direction (DR1). The vertical voltage lines (VVSL) can be connected to the second voltage lines (VSL). The vertical voltage lines (VVSL) can supply a low potential voltage received from the power supply unit (550) to the second voltage lines (VSL).

[0062] The second voltage lines (VSL) can be extended in the first direction (DR1) and spaced apart from each other in the second direction (DR2). The second voltage lines (VSL) can supply low potential voltage to the first to third pixels (SP1, SP2, SP3).

[0063] The connection relationships of the pixel (SP), gate line (GL), data line (DL), initialization voltage line (VIL), first voltage line (VDL), horizontal voltage line (HVDL), vertical voltage line (VVSL), and second voltage line (VSL) can be designed and changed in various ways depending on the number and arrangement of the pixels (SP).

[0064] The non-display area (NDA) may be defined as the remaining area of ​​the display substrate (100) excluding the display area (DA). For example, the non-display area (NDA) may include a data line (DL), an initialization voltage line (VIL), a first voltage line (VDL), and fan-out lines connecting the vertical voltage line (VVSL) and the display driver (520), a gate driver (560), and a wiring pad (WPD) connected to the connection film (510).

[0065] The non-display area (NDA) may include a pad area (PDA), which is an area where a wiring pad (WPD) is placed. The pad area (PDA) may be located adjacent to one side of the display device (10). For example, the pad area (PDA) may be located adjacent to the lower side of the display device (10). In one embodiment, the pad area (PDA) may extend along a first direction (DR1).

[0066] The connection film (510) can be connected to a wiring pad (WPD) located on the lower side of the non-display area (NDA) and a board pad (BPD) located on the upper side of the circuit board (530). For example, input terminals, such as bumps, provided on one side and the other side of the connection film (510) can be attached to the wiring pad (WPD) and the board pad (BPD) by a film attachment process. For example, the connection film (510) can be bent like a tape carrier package or a chip on film. The connection film (510) can be bent to the lower side of the display substrate (100) to reduce the bezel area of ​​the display device (10).

[0067] The display driver (520) can be mounted on the connecting film (510). For example, the display driver (520) can be implemented as an integrated circuit (IC). The display driver (520) receives digital video data and a data control signal from the timing control unit (540), and converts the digital video data into an analog data voltage according to the data control signal and supplies it to the data lines (DL) through the fan-out lines.

[0068] The circuit board (530) supports the timing control unit (540) and the power supply unit (550) and can supply signals and power to the display driving unit (520). For example, the circuit board (530) can supply signals supplied from the timing control unit (540) and power voltage supplied from the power supply unit (550) to the connecting film (510) and the display driving unit (520) through the board pad (BPD) to display an image on each pixel. To this end, signal lines and power lines may be provided on the circuit board (530).

[0069] The timing control unit (540) is mounted on the circuit board (530) and can receive image data and timing synchronization signals supplied from a display driving system or a graphics device through a user connector provided on the circuit board (530). The timing control unit (540) can generate digital video data by aligning the image data to suit the pixel arrangement structure based on the timing synchronization signal, and can supply the generated digital video data to the display driving unit (520). The timing control unit (540) can generate a data control signal and a gate control signal based on the timing synchronization signal. The timing control unit (540) can control the supply timing of the data voltage of the display driving unit (520) based on the data control signal, and can control the supply timing of the gate signal of the gate driving unit (560) based on the gate control signal.

[0070] The power supply unit (550) is positioned on the circuit board (530) and can supply power voltage to the connection film (510) and the display driving unit (520). For example, the power supply unit (550) can generate a driving voltage or a high potential voltage and supply it to the first voltage line (VDL), generate a low potential voltage and supply it to the vertical voltage line (VVSL), and generate an initialization voltage and supply it to the initialization voltage line (VIL).

[0071] The gate driver (560) may be positioned on at least one of the left and right sides of the non-display area (NDA). The gate driver (560) may generate a gate signal based on a gate control signal supplied from the timing control unit (540). The gate control signal may include, but is not limited to, a start signal, a clock signal, and a power supply voltage. The gate driver (560) may supply the gate signal to the gate line (GL) according to a set order.

[0072] FIG. 6 is a drawing showing pixels and wiring of a display device according to one embodiment of the present specification.

[0073] Referring to FIG. 6, the pixel (SP) may include first to third pixels (SP1, SP2, SP3). The pixel circuit of the first pixel (SP1), the pixel circuit of the second pixel (SP2), and the pixel circuit of the third pixel (SP3) may be arranged in order opposite to the second direction (DR2), but the order of the pixel circuits is not limited thereto.

[0074] Each of the first to third pixels (SP1, SP2, SP3) can be connected to a first voltage line (VDL), an initialization voltage line (VIL), a gate line (GL), and a data line (DL).

[0075] The first voltage line (VDL) may be extended in the second direction (DR2). The first voltage line (VDL) may be positioned to the left of the pixel circuit of the first to third pixels (SP1, SP2, SP3). The first voltage line (VDL) may supply a driving voltage or a high potential voltage to each transistor of the first to third pixels (SP1, SP2, SP3).

[0076] The horizontal voltage line (HVDL) can be extended in the first direction (DR1). The horizontal voltage line (HVDL) is in the k-th row (ROW k A horizontal voltage line (HVDL) can be placed on the upper side of a first gate line (GL1) placed at (where k is a positive integer). A horizontal voltage line (HVDL) can be connected to a first voltage line (VDL). The horizontal voltage line (HVDL) can receive a driving voltage or a high potential voltage from the first voltage line (VDL).

[0077] The initialization voltage line (VIL) may be extended to the second direction (DR2). The initialization voltage line (VIL) may be positioned to the left of the auxiliary line of the second gate line (GL2) branched to the second direction (DR2). The initialization voltage line (VIL) may be positioned between the auxiliary line of the second gate line (GL2) branched to the second direction (DR2) and the vertical voltage line (VVSL). The initialization voltage line (VIL) may supply an initialization voltage to the pixel circuits of each of the first to third pixels (SP1, SP2, SP3). The initialization voltage line (VIL) may receive a sensing signal from the pixel circuits of each of the first to third pixels (SP1, SP2, SP3) and supply it to the display driver (520).

[0078] The vertical voltage line (VVSL) can be extended in a second direction (DR2). The vertical voltage line (VVSL) can be positioned to the left of the initial voltage line (VIL). The vertical voltage line (VVSL) can be connected between the power supply (550) and the second voltage line (VSL). The vertical voltage line (VVSL) can supply a low potential voltage supplied from the power supply (550) to the second voltage line (VSL).

[0079] The second voltage line (VSL) can be extended in the first direction (DR1). The second voltage line (VSL) is in the k+1th row (ROW k+1 It can be placed on the upper side of the first gate line (GL1) placed in ). The second voltage line (VSL) can supply a low potential voltage received from the vertical voltage line (VVSL) to the light-emitting element layer (EML) (see FIG. 8) of the first to third pixels (SP1, SP2, SP3).

[0080] The first gate line (GL1) may be extended in the first direction (DR1). The first gate line (GL1) may be positioned above the pixel circuit of the first pixel (SP1). The first gate line (GL1) may be branched so that a portion extends in the opposite direction of the second direction (DR2). For example, the first gate line (GL1) may include an auxiliary line that branches off from the right side of the first to third pixels (SP1, SP2, SP3) and extends in the opposite direction of the second direction (DR2). The auxiliary line of the first gate line (GL1) may be positioned to the right side of the pixel circuit of the first to third pixels (SP1, SP2, SP3). The first gate line (GL1) may supply a first gate signal received from the gate driver (560) to the pixel circuit of the first to third pixels (SP1, SP2, SP3) through the auxiliary line extending in the opposite direction of the second direction (DR2).

[0081] The second gate line (GL2) may be extended in the first direction (DR1). The second gate line (GL2) may be positioned below the pixel circuit of the third pixel (SP3). The second gate line (GL2) may be branched so that a portion of it extends in the second direction (DR2). For example, the second gate line (GL2) may include an auxiliary line that branches off from the left side of the first voltage line (VDL) and extends in the second direction (DR2). The auxiliary line of the second gate line (GL2) may be positioned to the left side of the first voltage line (VDL). The second gate line (GL2) may supply a second gate signal received from the gate driver (560) to the pixel circuits of the first to third pixels (SP1, SP2, SP3) through the auxiliary line extended in the second direction (DR2).

[0082] Data lines (DL) can be extended in a second direction (DR2). Data lines (DL) can supply data voltage to a pixel (SP). Data lines (DL) may include first to third data lines (DL1, DL2, DL3).

[0083] The second data line (DL2) can be extended in the second direction (DR2). The second data line (DL2) can be positioned to the right of the auxiliary line of the first gate line (GL1). The second data line (DL2) can supply the data voltage received from the display driver (520) to the pixel circuit of the second pixel (SP2).

[0084] The third data line (DL3) can be extended in the second direction (DR2). The third data line (DL3) can be positioned to the right of the second data line (DL2). The third data line (DL3) can supply the data voltage received from the display driver (520) to the pixel circuit of the third pixel (SP3).

[0085] The first data line (DL1) can be extended in the second direction (DR2). The first data line (DL1) can be positioned to the right of the third data line (DL3). The first data line (DL1) can supply the data voltage received from the display driver (520) to the pixel circuit of the first pixel (SP1).

[0086] In the drawing, the second data line (DL2), the third data line (DL3), and the first data line (DL1) are shown arranged in order in the first direction (DR1), but are not limited thereto. The order of the first to third data lines (DL1, DL2, DL3) can be varied in the first direction (DR1).

[0087] FIG. 7 is a plan view schematically showing a part of the display area of ​​a display substrate according to one embodiment of the present specification.

[0088] Referring to FIG. 7, a plurality of light-emitting regions (LA) and non-light-emitting regions (NLA) may be defined in the display area (DA) of the display substrate (100). The plurality of light-emitting regions (LA) may be regions where light generated from a light-emitting element of the display substrate (100) is emitted to the outside of the display substrate (100), and the non-light-emitting region (NLA) may be regions where light generated from a light-emitting element of the display substrate (100) is not emitted to the outside of the display substrate (100). In some embodiments, the plurality of light-emitting regions (LA) may include a first light-emitting region (LA1), a second light-emitting region (LA2), and a third light-emitting region (LA3).

[0089] In some embodiments, the light-emitting region (LA) and the non-light-emitting region (NLA) may be defined by a pixel defining film (PDL) (see FIG. 8). For example, the light-emitting region (LA) may be an area that overlaps with the opening of the pixel defining film (PDL), and the non-light-emitting region (NLA) may be an area that does not overlap with the opening of the pixel defining film (PDL).

[0090] In one embodiment, the light emitted by the display substrate (100) to the color conversion substrate (200) in a plurality of light-emitting regions (LA) may be light of a third color. For example, the light of the third color may be blue light and may have a peak wavelength in the range of about 440 nm to about 480 nm. A peak wavelength may refer to a wavelength in which the intensity is maximized within a wavelength range. However, it is not limited thereto, and the light emitted by the display substrate (100) to the color conversion substrate (200) in a plurality of light-emitting regions (LA) may be light in the ultraviolet region.

[0091] When light of the same color is emitted from the first to third light-emitting regions (LA1, LA2, LA3), the first to third pixels (SP1, SP2, SP3) can express various colors through a color conversion pattern included in the color conversion substrate (200).

[0092] In another embodiment, different colored light may be emitted in the first to third light-emitting regions (LA1, LA2, LA3). For example, the color of the light emitted in the first light-emitting region (LA1) may be red light, the color of the light emitted in the second light-emitting region (LA2) may be green light, and the color of the light emitted in the third light-emitting region (LA3) may be blue light.

[0093] The first light-emitting region (LA1), the second light-emitting region (LA2), and the third light-emitting region (LA3) can each constitute a first pixel (SP1), a second pixel (SP2), and a third pixel (SP3). The first light-emitting region (LA1), the second light-emitting region (LA2), and the third light-emitting region (LA3) can be repeatedly arranged along the first direction (DR1) and the second direction (DR2) over the entire display area (DA). The first light-emitting region (LA1), the second light-emitting region (LA2), and the third light-emitting region (LA3) can constitute a single unit color pixel.

[0094] In one embodiment, the shape of the first light-emitting region (LA1) may be a rectangle extending in the first direction (DR1) and the second direction (DR2). In the drawings, the shape of the first light-emitting region (LA1) is illustrated as a rectangle. The shape of the second light-emitting region (LA2) may be a rectangle extending in the diagonal direction defined by the first direction (DR1) and the second direction (DR2). In the drawings, the shape of the second light-emitting region (LA2) is illustrated as a rectangle. The shape of the third light-emitting region (LA3) may be a rectangle extending in the first direction (DR1) and the second direction (DR2). In the drawings, the shape of the third light-emitting region (LA3) is illustrated as a rectangle. The shapes of the first to third light-emitting regions (LA1, LA2, LA3) are not limited thereto. In one embodiment, the widths and shapes of the first to third light-emitting regions (LA1, LA2, LA3) may differ from one another.

[0095] A non-emissive region (NLA) may be located around the light-emitting region (LA) of the display substrate (100) within the display area (DA). The non-emissive region (NLA) may be located not only around the light-emitting region (LA), but also between the first light-emitting region (LA1) and the second light-emitting region (LA2), between the second light-emitting region (LA2) and the third light-emitting region (LA3), and between the third light-emitting region (LA3) and the first light-emitting region (LA1).

[0096] Light emitted from the light-emitting region (LA) of the display substrate (100) can be transmitted through the light-transmitting region of the color conversion substrate (200) and provided to the outside of the display device (10).

[0097] A non-luminescent region (NLA) located within a display region (DA) may include a wiring contact region (WCA). The wiring contact region (WCA) may be an area where the electrodes of the light-emitting element layer (EML) (see FIG. 8) and the wiring of the circuit layer (CCL) (see FIG. 8) are connected and in contact with each other. For example, the wiring contact region (WCA) may include openings for connecting the electrodes of the light-emitting element layer (EML) and the wiring of the circuit layer (CCL). In some embodiments, the wiring contact region (WCA) may include a first contact region (CTA1), a second contact region (CTA2), and a laser drilling margin region (LDA).

[0098] Figure 8 is a cross-sectional view taken along X2-X2' of Figure 7.

[0099] Referring to FIG. 8, the display device (10) may include a display substrate (100), a color conversion substrate (200) facing the display substrate (100), and a filler (300) that adheres them.

[0100] The display substrate (100) may include a first substrate (110), a circuit layer (CCL), a light-emitting element layer (EML), and an encapsulation structure (170).

[0101] The first substrate (110) may include a transparent material. For example, the first substrate (110) may include a transparent insulating material such as glass, quartz, etc. The first substrate (110) may be a rigid substrate. However, the first substrate (110) is not limited thereto and may include a plastic such as polyimide, etc., and may have flexible properties that allow it to be bent, folded, or rolled.

[0102] A circuit layer (CCL) (e.g., a thin-film transistor layer) can be disposed on the first substrate (110). A description of the circuit layer (CCL) will be provided later.

[0103] The light-emitting element layer (EML) may be disposed on the circuit layer (CCL). The light-emitting element layer (EML) may include a pixel electrode (PXE), a pixel defining film (PDL), a light-emitting layer (LEL), and a common electrode (CME).

[0104] The pixel electrode (PXE) may be the first electrode of a light-emitting diode, for example, an anode electrode. The pixel electrode (PXE) may have a stacked structure in which a high work function material layer such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), or indium oxide (In2O3) is stacked with a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof is stacked. The high work function material layer may be placed above the reflective material layer and positioned close to the light-emitting layer (LEL). The pixel electrode (PXE) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but is not limited thereto.

[0105] The pixel electrode (PXE) may include a first pixel electrode (PXR), a second pixel electrode (PXG), and a third pixel electrode (PXB). The first pixel electrode (PXR) may be placed overlappingly with the first light-emitting region (LA1). The second pixel electrode (PXG) may be placed overlappingly with the second light-emitting region (LA2). The third pixel electrode (PXB) may be placed overlappingly with the third light-emitting region (LA3).

[0106] A pixel defining film (PDL) may be disposed along the boundary of a pixel (SP) on one side of a first substrate (110). The pixel defining film (PDL) is disposed on a pixel electrode (PXE) and may include an opening that exposes the pixel electrode (PXE). A light-emitting region (LA) and a non-light-emitting region (NLA) may be distinguished by the pixel defining film (PDL) and the opening.

[0107] The pixel defining layer (PDL) may include organic insulating materials such as polyacrylates resin, epoxy resin, phenolic resin, polyamides resin, polyimide resin, unsaturated polyesters resin, polyphenylene ethers resin, polyphenylenesulfides resin, or benzocyclobutene (BCB). The pixel defining layer (PDL) may also include inorganic materials.

[0108] The light-emitting layer (LEL) can be placed on the pixel electrode (PXE) exposed by the pixel defining film (PDL). The light-emitting layer (LEL) can be in contact not only with the pixel electrode (PXE) but also with the side and top surfaces of the pixel defining film (PDL). The light-emitting layer (LEL) can be connected without distinction between the light-emitting region (LA) and the pixel (SP). The light-emitting layer (LEL) can be placed across the entire surface without distinction between the light-emitting region (LA) and the pixel (SP). Accordingly, the wavelength of light emitted by the light-emitting layer (LEL) can be the same for each light-emitting region (LA1, LA2, LA3). For example, the light-emitting layer (LEL) of each light-emitting region (LA1, LA2, LA3) emits blue light or ultraviolet light, and the color conversion substrate (200) described later includes a wavelength conversion layer (WCL), thereby allowing the color for each pixel (SP) to be displayed.

[0109] In another embodiment, the light-emitting layer (LEL) may be spaced apart from each light-emitting region (LA1, LA2, LA3) separated by a pixel defining film (PDL). In this case, the wavelength of light emitted by each light-emitting layer (LEL) may be the same for each light-emitting region (LA1, LA2, LA3).

[0110] In one embodiment where the display device (10) is an organic light-emitting display device, the light-emitting layer (LEL) may include an organic layer containing an organic material. The organic layer includes an organic light-emitting layer and, in some cases, may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer as an auxiliary layer that assists in light emission. In another embodiment, where the display device (10) is a micro LED display device, a nano LED display device, etc., the light-emitting layer (LEL) may include an inorganic material such as an inorganic semiconductor.

[0111] In some embodiments, the light-emitting layer (LEL) may have a tandem structure comprising a plurality of organic light-emitting layers overlapped in the thickness direction (e.g., third direction (DR3)) and a charge-generating layer disposed between them. Each overlapped organic light-emitting layer may emit light of the same wavelength, but may also emit light of different wavelengths. At least some of the layers of the light-emitting layer (LEL) of each pixel (SP) may be separated from or connected to the same layer of an adjacent pixel (SP) by a pixel defining film (PDL).

[0112] A common electrode (CME) may be disposed on a light-emitting layer (LEL). The common electrode (CME) may be connected without distinction between the light-emitting region (LA) and the pixel (SP). The common electrode (CME) may be a front electrode disposed across the entire surface without distinction between the light-emitting region (LA) and the pixel (SP). The common electrode (CME) may be a second electrode of a light-emitting diode, for example, a cathode electrode. The common electrode (CME) may include a material layer with a low work function, such as Li, Ca, LiF / Ca, LiF / Al, Al, Mg, Ag, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF, Ba, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg). The common electrode (CME) may further include a transparent metal oxide layer disposed on the material layer with a low work function.

[0113] The pixel electrode (PXE), the light-emitting layer (LEL), and the common electrode (CME) can constitute a light-emitting device (e.g., an organic light-emitting device). Light emitted from the light-emitting layer (LEL) can be emitted upward through the common electrode (CME).

[0114] The encapsulation structure (170) may be placed on a common electrode (CME). The encapsulation structure (170) may include at least one thin film encapsulation layer. For example, the encapsulation structure (170) may include a first encapsulation inorganic film (171), an encapsulation organic film (172), and a second encapsulation inorganic film (173).

[0115] The first encapsulating inorganic film (171) can be disposed on the light-emitting element layer (EML). The first encapsulating inorganic film (171) is silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO₂ x N y It may include ) etc.

[0116] The encapsulating organic film (172) may be placed on the first encapsulating inorganic film (171). The encapsulating organic film (172) may include an organic insulating material such as an acrylic resin (polyacrylates resin), an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ethers resin, a polyphenylene sulfide resin, or benzocyclobutene (BCB).

[0117] The second encapsulating inorganic film (173) may be disposed on the encapsulating organic film (172). The second encapsulating inorganic film (173) may contain the same material as the first encapsulating inorganic film (171) described above. For example, the second encapsulating inorganic film (173) may be silicon nitride (SiN x ), silicon oxide (SiO x ), or silicon oxynitride (SiO₂ x N y It may include ) etc.

[0118] In some embodiments, a portion of the encapsulation structure (170) or the entire encapsulation structure (170) may be omitted. When the encapsulation structure (170) is omitted, the filler (300), the sealing portion (400), and the color conversion substrate (200) may be placed directly on the light-emitting element layer (EML), and the filler (300), the sealing portion (400), and the color conversion substrate (200) may directly perform the encapsulation function.

[0119] A color conversion substrate (200) may be positioned on an encapsulation structure (170) to face a display substrate (100). The color conversion substrate (200) may include a second substrate (210), a light-blocking member (BM), a color filter layer (CFL), a first capping layer (220), a partition (PTL), a wavelength conversion layer (WCL), a light-transmitting layer (TPL), and a second capping layer (230).

[0120] The second substrate (210) may include a transparent material. The second substrate (210) may include a transparent insulating material such as glass, quartz, etc. The second substrate (210) may be a rigid substrate. However, the second substrate (210) is not limited thereto, and the second substrate (210) may include a plastic such as polyimide, etc., and may have flexible properties that allow it to be bent, folded, or rolled.

[0121] The second substrate (210) may be the same substrate as the first substrate (110), but may differ in material, thickness, transmittance, etc. For example, the second substrate (210) may have a higher transmittance than the first substrate (110). The second substrate (210) may be thicker than the first substrate (110) or thinner than it.

[0122] A light-blocking member (BM) may be disposed along the boundary of a pixel (SP) on one side of a second substrate (210) facing the first substrate (110). The light-blocking member (BM) may overlap with the pixel defining film (PDL) of the display substrate (100) and may be located in a non-luminous region (NLA). The light-blocking member (BM) may include an opening that exposes one side of the second substrate (210) that overlaps with a luminous region (LA). The light-blocking member (BM) may be formed in a grid shape in a planar view.

[0123] The light-blocking member (BM) may be composed of organic materials. The light-blocking member (BM) can reduce color distortion caused by external light reflection by absorbing external light. In addition, the light-blocking member (BM) can serve to prevent light emitted from the light-emitting layer (LEL) from intruding into adjacent pixels (SP).

[0124] In one embodiment, the light-blocking member (BM) can absorb all visible light wavelengths. The light-blocking member (BM) may include a light-absorbing material. For example, the light-blocking member (BM) may be made of a material used as a black matrix of a display device (10).

[0125] In another embodiment, the light-blocking member (BM) may absorb light of a specific wavelength among the visible light wavelengths and transmit light of another specific wavelength. For example, the light-blocking member (BM) may include the same material as the color filter layer (CFL). Specifically, the light-blocking member (BM) may be made of the same material as the blue color filter layer. In some embodiments, the light-blocking member (BM) may be formed integrally with the blue color filter layer. Additionally, the light-blocking member (BM) may be omitted.

[0126] A color filter layer (CFL) may be disposed on one side of a second substrate (210) on which a light-blocking member (BM) is disposed. The color filter layer (CFL) may be disposed on one side of the second substrate (210) that is exposed through an opening in the light-blocking member (BM). Furthermore, the color filter layer (CFL) may also be partially disposed on an adjacent light-blocking member (BM).

[0127] A color filter layer (CFL) may include a first color filter layer (CFL1) disposed in a first pixel (SP1), a second color filter layer (CFL2) disposed in a second pixel (SP2), and a third color filter layer (CFL3) disposed in a third pixel (SP3). Each color filter layer (CFL) may include a colorant, such as a dye or pigment, that absorbs wavelengths other than the corresponding color wavelength. The first color filter layer (CFL1) may be a red color filter layer, the second color filter layer (CFL2) may be a green color filter, and the third color filter layer (CFL3) may be a blue color filter layer. Although the drawing illustrates a case where adjacent color filter layers (CFLs) are spaced apart from each other on a light-blocking member (BM), adjacent color filter layers (CFLs) may overlap at least partially on the light-blocking member (BM).

[0128] The first capping layer (220) may be placed on the color filter layer (CFL). The first capping layer (220) can prevent impurities, such as moisture or air, from penetrating from the outside and damaging or contaminating the color filter layer (CFL). Additionally, the first capping layer (220) can prevent the pigment of the color filter layer (CFL) from spreading to other compositions.

[0129] The first capping layer (220) may be in direct contact with one side of the color filter layer (CFL). The first capping layer (220) may be made of an inorganic material. For example, the first capping layer (220) may be made of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, silicon oxynitride, etc.

[0130] A partition (PTL) may be disposed on the first capping layer (220). The partition (PTL) may be located in the non-luminous region (NLA). The partition (PTL) may be disposed to overlap with the light-blocking member (BM). The partition (PTL) may include an opening that exposes the color filter layer (CFL). The partition (PTL) may be made of a photosensitive organic material, but is not limited thereto. The partition (PTL) may further include a light-blocking material.

[0131] The wavelength conversion layer (WCL) and / or light-transmitting layer (TPL) may be disposed within the space exposed by the opening of the partition wall (PTL). The wavelength conversion layer (WCL) and the light-transmitting layer (TPL) may be formed by an inkjet process using the partition wall (PTL) as a bank, but are not limited thereto.

[0132] In one embodiment in which the light-emitting layer (LEL) of each pixel (SP) emits a third color, the wavelength conversion layer (WCL) may include a first wavelength conversion pattern (WCL1) disposed in the first pixel (SP1) and a second wavelength conversion pattern (WCL2) disposed in the second pixel (SP2). A light-transmitting layer (TPL) may be disposed in the third pixel (SP3).

[0133] The first wavelength conversion pattern (WCL1) may include a first base resin (BRS1) and a first wavelength conversion material (WCP1) disposed within the first base resin (BRS1). The second wavelength conversion pattern (WCL2) may include a second base resin (BRS2) and a second wavelength conversion material (WCP2) disposed within the second base resin (BRS2). The light-transmitting layer (TPL) may include a third base resin (BRS3) and a scatterer (SCP) disposed within it.

[0134] The first to third base resins (BRS1, BRS2, ​​BRS3) may include a transparent organic material. For example, the first to third base resins (BRS1, BRS2, ​​BRS3) may be composed of an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first to third base resins (BRS1, BRS2, ​​BRS3) may all be composed of the same material, but are not limited thereto.

[0135] The scattering body (SCP) may be a metal oxide particle or an organic particle. Examples of the metal oxide may include titanium oxide (TiO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), indium oxide (In2O3), zinc oxide (ZnO), or tin oxide (SnO2), and examples of the organic particle material may include acrylic resin or urethane resin.

[0136] The first wavelength conversion material (WCP1) may be a material that converts a third color into a first color, and the second wavelength conversion material (WCP2) may be a material that converts a third color into a second color. The first wavelength conversion material (WCP1) and the second wavelength conversion material (WCP2) may be quantum dots, quantum rods, phosphors, etc. The quantum dots may include group IV nanocrystals, group II-VI compound nanocrystals, group III-V compound nanocrystals, group IV-VI nanocrystals, or a combination thereof. The first wavelength conversion pattern (WCL1) and the second wavelength conversion pattern (WCL2) may further include a scatterer (SCP) that increases wavelength conversion efficiency.

[0137] The light-transmitting layer (TPL) placed in the third pixel (SP3) can transmit the third color light emitted from the light-emitting layer (LEL) while maintaining its wavelength. The scatterer (SCP) of the light-transmitting layer (TPL) can serve to control the emission path of light emitted through the light-transmitting layer (TPL). The light-transmitting layer (TPL) may not contain a wavelength conversion material.

[0138] The second capping layer (230) may be disposed on the wavelength conversion layer (WCL), the light-transmitting layer (TPL), and the barrier (PTL). The second capping layer (230) may be made of an inorganic material. The second capping layer (230) may be made of a material selected from among the materials listed as the material of the first capping layer (220). The second capping layer (230) and the first capping layer (220) may be made of the same material, but are not limited thereto.

[0139] A filler material (300) may be disposed between the display substrate (100) and the color conversion substrate (200). The filler material (300) fills the space between the display substrate (100) and the color conversion substrate (200), while also serving to bond and bond them together. The filler material (300) may be disposed between the encapsulation structure (170) of the display substrate (100) and the second capping layer (230) of the color conversion substrate (200). The filler material (300) may be composed of Si-based organic materials, epoxy-based organic materials, etc., but is not limited thereto.

[0140] FIG. 9 is an equivalent circuit diagram of a pixel according to one embodiment of the present specification.

[0141] Referring to FIG. 9, each of the pixels (SP) can be connected to a first voltage line (VDL), a data line (DL), an initialization voltage line (VIL), a first gate line (GL1), a second gate line (GL2), and a second voltage line (VSL).

[0142] Each of the pixels (SP) may include a pixel circuit and a light-emitting element (ED). In one embodiment, as shown in the drawings, the pixel circuit of each pixel (SP) may be a 3T1C structure including three transistors and one capacitor. For example, the pixel circuit of each pixel (SP) may include first to third transistors (ST1, ST2, ST3) and a capacitor (C1). However, it is not limited thereto, and the number of transistors and capacitors in each pixel circuit can be varied in many ways. For convenience of explanation, the 3T1C structure is described below as an example, but it is not limited thereto, and various other variations such as a 2T1C structure, a 7T1C structure, a 6T1C structure, a 17T3C structure, etc., may be applied.

[0143] The first transistor (ST1) may include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor (ST1) may be connected to a first node (N1), the drain electrode may be connected to a first voltage line (VDL), and the source electrode may be connected to a second node (N2). The first transistor (ST1) may control a drain-source current (or driving current) based on a data voltage applied to the gate electrode. The first transistor (ST1) may be a driving transistor that drives a light-emitting element (ED).

[0144] A light-emitting element (ED) can emit light by receiving a driving current. The amount of light emitted or the brightness of the light-emitting element (ED) may be proportional to the magnitude of the driving current. The light-emitting element (ED) may be an organic light-emitting diode (OLED) including an organic light-emitting layer, a quantum dot light-emitting diode (Quantum Dot LED) including a quantum dot light-emitting layer, a micro light-emitting diode (Micro LED), or an inorganic light-emitting diode (Inorganic LED) including an inorganic semiconductor.

[0145] The first electrode of the light-emitting element (ED) (e.g., pixel electrode) can be connected to the second node (N2), and the second electrode of the light-emitting element (ED) can be connected to the second voltage line (VSL). The first electrode of the light-emitting element (ED) can be connected through the second node (N2) to the source electrode of the first transistor (ST1), the drain electrode of the third transistor (ST3), and the first capacitor electrode of the capacitor (C1).

[0146] The second transistor (ST2) can be turned on by the first gate signal of the first gate line (GL1) to electrically connect the data line (DL) and the first node (N1), which is the gate electrode of the first transistor (ST1). By turning on the second transistor (ST2) based on the first gate signal, it can supply a data voltage to the first node (N1). The gate electrode of the second transistor (ST2) can be connected to the first gate line (GL1), the drain electrode can be connected to the data line (DL), and the source electrode can be connected to the first node (N1). The source electrode of the second transistor (ST2) can be connected to the gate electrode of the first transistor (ST1) and the second capacitor electrode of the capacitor (C1) through the first node (N1). The second transistor (ST2) may be a switching transistor that controls the current flowing through the first transistor (ST1) and the light-emitting element (ED).

[0147] The third transistor (ST3) can be turned on by the second gate signal of the second gate line (GL2) to electrically connect the initialization voltage line (VIL) and the second node (N2), which is the source electrode of the first transistor (ST1). By turning on the third transistor (ST3) based on the second gate signal, it can supply an initialization voltage to the second node (N2). By turning on the third transistor (ST3) based on the second gate signal, it can supply a sensing signal to the initialization voltage line (VIL). The gate electrode of the third transistor (ST3) can be connected to the second gate line (GL2), the drain electrode can be connected to the second node (N2), and the source electrode can be connected to the initialization voltage line (VIL). The drain electrode of the third transistor (ST3) can be connected to the source electrode of the first transistor (ST1), the first capacitor electrode of the capacitor (C1), and the first electrode of the light-emitting element (ED) through the second node (N2). The third transistor (ST3) may be a switching transistor that controls the current flowing through the first transistor (ST1) and the light-emitting element (ED).

[0148] FIG. 10 is a cross-sectional view showing an example of a first transistor of a circuit layer according to an embodiment of the present specification. FIG. 11 is a cross-sectional view showing an example of a second transistor and a third transistor of a circuit layer according to an embodiment of the present specification.

[0149] Referring to FIGS. 9, 10 and 11, the display substrate (100) may include a first substrate (110), a circuit layer (CCL), and a light-emitting element layer (EML).

[0150] The description of the first substrate (110) has been previously described and will be omitted.

[0151] A circuit layer (CCL) may be disposed on a first substrate (110). The circuit layer (CCL) (e.g., a thin film transistor layer) may include a lower conductive layer (BML), a buffer layer (BF), an active layer (ACTL), a gate insulating layer (GI), a gate conductive layer (GML), a protective layer (PV), and a via layer (VIA). The circuit layer (CCL) may include first to third transistors (ST1, ST2, ST3) and a capacitor (C1).

[0152] The lower conductive layer (BML) may be disposed on the first substrate (110). The lower conductive layer (BML) may comprise a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0153] In one embodiment, the lower conductive layer (BML) may include an initialization voltage line (VIL), a data line (DL), a first voltage line (VDL), a second voltage line (VSL), and a first capacitor electrode (CPE1) of a capacitor (C1).

[0154] A buffer film (BF) may be disposed on a lower conductive layer (BML). The buffer film (BF) may include an inorganic material such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer. Alternatively, the buffer film (BF) may include a multilayer film in which a plurality of layers among a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately stacked.

[0155] The active layer (ACTL) may be disposed on the buffer film (BF). The active layer (ACTL) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor material.

[0156] In one embodiment, the active layer (ACTL) may include a first active region (ACT1), a first drain electrode (DE1), and a first source electrode (SE1) of a first transistor (ST1), a second active region (ACT2), a second drain electrode (DE2), and a second source electrode (SE2) of a second transistor (ST2), a third active region (ACT3), a third drain electrode (DE3), and a third source electrode (SE3) of a third transistor (ST3), and a second capacitor electrode (CPE2) of a capacitor (C1).

[0157] A gate insulating film (GI) may be disposed on an active layer (ACTL). The gate insulating film (GI) may include an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0158] A gate conductive layer (GML) may be disposed on a gate insulating film (GI). The gate conductive layer (GML) may comprise a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0159] In one embodiment, the gate conductive layer (GML) may include a first gate line (GL1), a second gate line (GL2), a first gate electrode (GE1) of a first transistor (ST1), a second gate electrode (GE2) of a second transistor (ST2), a third gate electrode (GE3) of a third transistor (ST3), and connecting electrodes (CE1, CE2, CE3, CE4).

[0160] A protective film (PV) may be disposed on the gate conductive layer (GML). The protective film (PV) may include an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0161] A via film (VIA) can be placed on a protective film (PV). The via film (VIA) may include an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0162] The circuit layer (CCL) may include first to third transistors (ST1, ST2, ST3) and a capacitor (C1).

[0163] The first transistor (ST1) may include a first active region (ACT1), a first gate electrode (GE1), a first drain electrode (DE1), and a first source electrode (SE1).

[0164] The first active region (ACT1) may be placed in the active layer (ACTL). The first active region (ACT1) may overlap with the first gate electrode (GE1) in the third direction (DR3). The first active region (ACT1) may be an area where the active layer (ACTL) is not conductive in the area overlapping with the first gate electrode (GE1).

[0165] The first gate electrode (GE1) can be placed on the gate conductive layer (GML). The first gate electrode (GE1) can be connected to the second source electrode (SE2) of the second transistor (ST2) and the second capacitor electrode (CPE2) of the capacitor (C1) through the first node (N1).

[0166] In the drawing, the first transistor (ST1) is depicted as having a top gate structure in which the first gate electrode (GE1) is disposed above the first active region (ACT1), but it is not limited thereto. As an example, the first transistor (ST1) may have a bottom gate structure in which the first gate electrode (GE1) is disposed below the first active region (ACT1). As another example, the first transistor (ST1) may have a double gate structure in which the first gate electrode (GE1) is disposed above and below the first active region (ACT1).

[0167] The first drain electrode (DE1) and the first source electrode (SE1) can be formed by heat-treating the active layer (ACTL) to make it conductive. The first drain electrode (DE1) and the first source electrode (SE1) can be made conductive of a P-type semiconductor or an N-type semiconductor, but are not limited thereto.

[0168] The first drain electrode (DE1) can be electrically connected to the first voltage line (VDL). For example, the first drain electrode (DE1) can be connected to the first voltage line (VDL) through the first connection electrode (CE1). Accordingly, the first drain electrode (DE1) can receive a driving voltage from the first voltage line (VDL).

[0169] The first source electrode (SE1) can be connected to the light-emitting element (ED) through the second node (N2). For example, the first source electrode (SE1) can be connected to the pixel electrode (PXE) through the second connection electrode (CE2). Accordingly, the first source electrode (SE1) can supply a driving current to the light-emitting element (ED).

[0170] The first source electrode (SE1) can be connected to the capacitor (C1) through the second node (N2). For example, the first source electrode (SE1) can be connected to the first capacitor electrode (CPE1) of the capacitor (C1) through the second connection electrode (CE2).

[0171] The second transistor (ST2) may include a second active region (ACT2), a second gate electrode (GE2), a second drain electrode (DE2), and a second source electrode (SE2).

[0172] The second active region (ACT2) may be placed in the active layer (ACTL). The second active region (ACT2) may overlap with the second gate electrode (GE2) in the third direction (DR3). The second active region (ACT2) may be an area where the active layer (ACTL) is not conductive in the area overlapping with the second gate electrode (GE2).

[0173] The second gate electrode (GE2) can be placed on the gate conductive layer (GML). The second gate electrode (GE2) can be connected to the first gate line (GL1). Accordingly, the second gate electrode (GE2) can receive a first gate signal from the first gate line (GL1).

[0174] In the drawing, the second transistor (ST2) is depicted as having a top gate structure in which the second gate electrode (GE2) is disposed above the second active region (ACT2), but it is not limited thereto. As an example, the second transistor (ST2) may have a bottom gate structure in which the second gate electrode (GE2) is disposed below the second active region (ACT2). As another example, the second transistor (ST2) may have a double gate structure in which the second gate electrode (GE2) is disposed above and below the second active region (ACT2).

[0175] The second drain electrode (DE2) and the second source electrode (SE2) can be formed by heat-treating the active layer (ACTL) to make it conductive. The second drain electrode (DE2) and the second source electrode (SE2) can be made conductive of a P-type semiconductor or an N-type semiconductor, but are not limited thereto.

[0176] The second drain electrode (DE2) can be electrically connected to the data line (DL). For example, the second drain electrode (DE2) can be connected to the data line (DL) through the third connection electrode (CE3). Accordingly, the second drain electrode (DE2) can receive a data voltage from the data line (DL).

[0177] The second source electrode (SE2) can be connected to the first gate electrode (GE1) of the first transistor (ST1) through the first node (N1). Accordingly, the second source electrode (SE2) can supply a data voltage to the first gate electrode (GE1) of the first transistor (ST1) through the first node (N1). The first transistor (ST1) can control the driving current based on the data voltage received from the second source electrode (SE2).

[0178] The second source electrode (SE2) can be connected to the capacitor (C1) through the first node (N1). For example, although not shown in the drawing, the second source electrode (SE2) can be connected to the second capacitor electrode (CPE2) of the capacitor (C1) through a separate connecting electrode placed on the gate conductive layer (GML).

[0179] The third transistor (ST3) may include a third active region (ACT3), a third gate electrode (GE3), a third drain electrode (DE3), and a third source electrode (SE3).

[0180] The third active region (ACT3) may be placed in the active layer (ACTL). The third active region (ACT3) may overlap with the third gate electrode (GE3) in the third direction (DR3). The third active region (ACT3) may be an area where the active layer (ACTL) is not conductive in the area overlapping with the third gate electrode (GE3).

[0181] The third gate electrode (GE3) can be placed on the gate conductive layer (GML). The third gate electrode (GE3) can be connected to the second gate line (GL2). Accordingly, the third gate electrode (GE3) can receive a second gate signal from the second gate line (GL2).

[0182] In the drawing, the third transistor (ST3) is depicted as having a top gate structure in which the third gate electrode (GE3) is positioned above the third active region (ACT3), but it is not limited thereto. As an example, the third transistor (ST3) may have a bottom gate structure in which the third gate electrode (GE3) is positioned below the third active region (ACT3). As another example, the third transistor (ST3) may have a double gate structure in which the third gate electrode (GE3) is positioned above and below the third active region (ACT3).

[0183] The third drain electrode (DE3) and the third source electrode (SE3) can be formed by heat-treating the active layer (ACTL) to make it conductive. The third drain electrode (DE3) and the third source electrode (SE3) can be made conductive of a P-type semiconductor or an N-type semiconductor, but are not limited thereto.

[0184] The third drain electrode (DE3) can be electrically connected to the first source electrode (SE1) of the first transistor (ST1). For example, although not shown in the drawing, the third drain electrode (DE3) can be connected to the first source electrode (SE1) of the first transistor (ST1) through a separate connecting electrode placed on the gate conductive layer (GML).

[0185] The third drain electrode (DE3) can be connected to the capacitor (C1). For example, although not shown in the drawing, the third drain electrode (DE3) can be connected to the first capacitor electrode (CPE1) of the capacitor (C1) through a separate connecting electrode placed on the gate conductive layer (GML).

[0186] The third source electrode (SE3) can be connected to the initialization voltage line (VIL). For example, the third source electrode (SE3) can be connected to the initialization voltage line (VIL) through the fourth connection electrode (CE4). Accordingly, the third source electrode (SE3) can receive an initialization voltage from the initialization voltage line (VIL), and the third source electrode (SE3) can supply a sensing signal to the initialization voltage line (VIL).

[0187] The capacitor (C1) may include a first capacitor electrode (CPE1) and a second capacitor electrode (CPE2).

[0188] The first capacitor electrode (CPE1) may be placed on the lower conductive layer (BML). The first capacitor electrode (CPE1) may be connected to the first source electrode (SE1) of the first transistor (ST1) through the second connecting electrode (CE2). The first capacitor electrode (CPE1) may be connected to the third drain electrode (DE3) of the third transistor (ST3) through a separate connecting electrode placed on the gate conductive layer (GML).

[0189] The second capacitor electrode (CPE2) may be placed in the active layer (ACTL). The second capacitor electrode (CPE2) may be connected to the first gate electrode (GE1) of the first transistor (ST1) through a separate connecting electrode placed in the gate conductive layer (GML). The second capacitor electrode (CPE2) may be connected to the second source electrode (SE2) of the second transistor (ST2) through a separate connecting electrode placed in the gate conductive layer (GML).

[0190] The light-emitting element layer (EML) may include an anode conductive layer (AML), a pixel defining layer (PDL), a light-emitting layer (LEL), and a common electrode (CME).

[0191] The anode conductive layer (AML) may be disposed on a circuit layer (CCL). For example, the anode conductive layer (AML) may be disposed on a via film (VIA). In one embodiment, the anode conductive layer (AML) may include a pixel electrode (PXE).

[0192] The anode conductive layer (AML) may have a stacked structure in which a high work function material layer of indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3) and a reflective material layer of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof are stacked. The high work function material layer may be placed above the reflective material layer and positioned close to the light-emitting layer (LEL). The pixel electrode (PXE) may have a multilayer structure of ITO / Mg, ITO / MgF, ITO / Ag, or ITO / Ag / ITO, but is not limited thereto.

[0193] The display device (10) according to the present embodiment can improve process efficiency by reducing the number of masks required for patterning each layer by minimizing the number of layers of the circuit layer (CCL).

[0194] For example, by placing wiring such as a data line (DL), an initial voltage line (VIL), a first voltage line (VDL), and a second voltage line (VSL) in the lower conductive layer (BML), and placing wiring such as a gate line (GL), a horizontal voltage line (HVDL), and a second voltage line (VSL) in the gate conductive layer (GML), the number of layers can be minimized by not adding a separate layer for wiring placement.

[0195] As another example, by placing the first capacitor electrode (CPE1) in the lower conductive layer (BML) and the second capacitor electrode (CPE2) in the active layer (ACTL), the number of layers can be minimized by not adding a separate layer for placing the capacitor (C1).

[0196] As another example, the number of layers can be minimized by placing connecting electrodes for connecting the lower conductive layer (BML), the active layer (ACTL), and the gate conductive layer (GML) on the gate conductive layer (GML), thereby not adding a separate layer for connecting electrode placement.

[0197] In the display device (10) according to the present embodiment, by minimizing the number of layers of the circuit layer (CCL), the distance between the light-emitting element layer (EML) and the lower conductive layer (BML) in the third direction (DR3) can be reduced. Accordingly, the distance between wirings such as the data line (DL), initialization voltage line (VIL), first voltage line (VDL), and second voltage line (VSL) and electrodes of the light-emitting element layer (EML), such as the pixel electrode (PXE) and common electrode (CME), can be reduced. Additionally, the number of connecting electrodes for connecting the wirings and the electrodes can be reduced. Accordingly, the voltage drop (IR-drop) phenomenon, in which the voltage provided from the wirings to the electrodes drops, can be minimized.

[0198] Figure 12 is a cross-sectional view showing the process of removing a portion of the light-emitting layer through a laser drilling process.

[0199] Referring to FIG. 12, the lower conductive layer (BML) may further include a second voltage line (VSL). The gate conductive layer (GML) may further include a fifth connecting electrode (CE5). The anode conductive layer (AML) may further include an auxiliary electrode (VCE).

[0200] The second voltage line (VSL) can receive a low potential voltage from the vertical voltage line (VVSL) (see FIG. 6). The second voltage line (VSL) can be connected to the fifth connecting electrode (CE5). The fifth connecting electrode (CE5) can connect the second voltage line (VSL) and the auxiliary electrode (VCE). The auxiliary electrode (VCE) can connect the fifth connecting electrode (CE5) and the common electrode (CME). The second voltage line (VSL) can provide a low potential voltage to the common electrode (CME) through the fifth connecting electrode (CE5) and the auxiliary electrode (VCE).

[0201] The display substrate (100) may include a wiring contact area (WCA). The wiring contact area (WCA) may be an area where the electrode of the light-emitting element layer (EML) and the wiring of the circuit layer (CCL) are connected and in contact with each other. For example, as shown in FIG. 12, a second voltage line (VSL) in the wiring contact area (WCA) may be connected and connected to a common electrode (CME) through a fifth connecting electrode (CE5) and an auxiliary electrode (VCE).

[0202] In some embodiments, the embodiment may include a contact hole (CNT), a first opening (OP1), a second opening (OP2), a third opening (OP3), and a fourth opening (OP4).

[0203] The contact hole (CNT) can penetrate the buffer film (BF) and the gate insulating film (GI). The contact hole (CNT) can expose at least a portion of the upper surface of the second voltage line (VSL). The second voltage line (VSL) and the fifth connecting electrode (CE5) can be connected to each other through the contact hole (CNT). The contact hole (CNT) can be formed through a photolithography process during the formation of the buffer film (BF) and the gate insulating film (GI). In some embodiments, if the second voltage line (VSL) is directly connected to the auxiliary electrode (VCE) without the fifth connecting electrode (CE5), the contact hole (CNT) may be omitted.

[0204] The first opening (OP1) can penetrate the protective film (PV). The first opening (OP1) can expose at least a portion of the upper surface of the fifth connecting electrode (CE5). The auxiliary electrode (VCE) and the fifth connecting electrode (CE5) can be connected to each other through the first opening (OP1). The first opening (OP1) can be formed through a photolithography process when the protective film (PV) is formed.

[0205] The second opening (OP2) can penetrate the via film (VIA). The second opening (OP2) can expose at least a portion of the upper surface of the fifth connecting electrode (CE5). The auxiliary electrode (VCE) and the fifth connecting electrode (CE5) can be connected to each other through the first opening (OP1) and the second opening (OP2). The second opening (OP2) can be formed through a photolithography process when forming the via film (VIA). A first contact region (CTA1) where the auxiliary electrode (VCE) and the fifth connecting electrode (CE5) come into contact can be formed by the second opening (OP2).

[0206] In some embodiments, when the second voltage line (VSL) is directly connected to the auxiliary electrode (VCE) without the fifth connecting electrode (CE5), the auxiliary electrode (VCE) and the second voltage line (VSL) may be connected to each other through the first opening (OP1) and the second opening (OP2). In some embodiments, the width of the first opening (OP1) may be smaller than the width of the second opening (OP2), but the embodiments of this specification are not limited thereto.

[0207] The third opening (OP3) can penetrate the pixel defining film (PDL). The third opening (OP3) can expose at least a portion of the upper surface of the auxiliary electrode (VCE). The common electrode (CME) and the auxiliary electrode (VCE) can be connected to each other through the third opening (OP3). The third opening (OP3) can be formed through a photolithography process during the formation of the pixel defining film (PDL). Through the third opening (OP3), a laser drilling margin region (LDA) can be formed where the light-emitting layer (LEL) and the auxiliary electrode (VCE) come into contact and a portion of the light-emitting layer (LEL) is removed.

[0208] The light-emitting layer (LEL) can be removed by a laser drilling process. For example, laser generators (HD1, HD2) can irradiate a laser (LS) onto a portion of the light-emitting layer (LEL). The light-emitting layer (LEL) in the area irradiated by the laser (LS) can be removed by the energy of the laser (LS). In one embodiment, the wavelength of the laser (LS) may be approximately 300 nm to 400 nm. In one embodiment, the output energy per unit area of ​​the laser (LS) is approximately 200 mJ / cm² 2 It could be.

[0209] The laser generating device (HD1, HD2) may irradiate a laser (LS) at a first position (HD1) or at a second position (HD2). In a preferred embodiment, the laser generating device (HD1, HD2) may irradiate a laser (LS) at the first position (HD1). However, due to errors occurring during the process, the laser (LS) may be irradiated at the second position (HD2).

[0210] The present specification can correct errors in the detection process caused by a laser (LS) being irradiated at different locations depending on the position of the laser generating device (HD1, HD2) during the manufacturing process of a display device. Preferably, the laser (LS) should be irradiated at a first location (HD1), but if the laser (LS) is irradiated at a second location (HD2) or elsewhere, the light-emitting layer (LEL) may not be removed at the designed location.

[0211] The auxiliary electrode (VCE) may come into contact with a common electrode to be placed thereafter. When a laser (LS) is irradiated at a second position (HD2), etc., and the light-emitting layer (LEL) corresponding to the second position (HD2) is removed, a problem arises in which the contact area between the auxiliary electrode (VCE) and the common electrode is not sufficiently secured. However, even in this case, in one embodiment, the contact area should be treated as sufficiently secured, and in another embodiment, the contact area should be treated as not sufficiently secured. The present specification provides a manufacturing process, a manufacturing method, or a manufacturing system capable of determining whether the contact area is sufficiently secured, and may provide a display device manufactured accordingly.

[0212] Figure 13 is a plan view showing the location where the laser drilling margin area is placed.

[0213] Referring to FIG. 13, a laser drilling margin area (LDA) according to an embodiment may be formed in a display area (DA) and a non-display area (NDA). The laser drilling margin area (LDA) may be an area in which an auxiliary electrode is disposed, including an upper surface exposed by a pixel (SP) defining film. Preferably, the laser drilling margin area (LDA) may include an area where the auxiliary electrode and the common electrode come into contact. In the case of a display device including a relatively large display panel, the length of the wiring disposed within the display area (DA) may increase, and parasitic resistance within the wiring may increase. The common electrode is disposed entirely in at least a portion of the display area (DA), and as the length of the wiring increases, the common voltage value transmitted through the common electrode may not be constant due to voltage drop or the like across the entire display area (DA). In the display device according to the embodiment, as the auxiliary electrode and the common electrode come into contact, the aforementioned voltage drop phenomenon, etc. is improved, and power consumption may be improved because it is not necessary to increase the voltage applied to the common electrode.

[0214] FIG. 14 is a block diagram illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented.

[0215] Referring to FIG. 14, the laser drilling process may be a process for removing at least a portion of the light-emitting layer. A manufacturing method according to an embodiment of the present specification may include a process section (LDP) in which a step of performing a laser drilling process is performed, a pre-process section (PR-LDP) in which a step before the laser drilling process is performed is performed, and a post-process section (PO-LDP1, PO-LDP2) in which a step after the laser drilling process is performed is performed. In the pre-process section (PR-LDP), a step that must be performed before the process section (LDP) in which at least a portion of the light-emitting layer is removed may be performed. In the post-process section (PO-LDP1, PO-LDP2), a step that must be performed after the process section (LDP) may be performed. The post-process section (PO-LDP1, PO-LDP2) may include a first post-process section (PO-LDP1) and a second post-process section (PO-LDP2).

[0216] After the laser drilling process is performed, a detection step by the detection unit (TP) may be carried out. The detection unit (TP) may perform a step of verifying whether the laser has been properly irradiated at an appropriate location and determining whether the contact area between the auxiliary electrode and the common electrode is sufficiently secured. In one embodiment, the detection unit (TP) may inspect a display device in which at least a portion of the light-emitting layer has been removed and determine whether to proceed to a step performed in the first post-processing unit (PO-LDP1) or to a step performed in the second post-processing unit (PO-LDP2). In one embodiment, the detection unit (TP) may transmit a post-signal (POSI). The post-signal (POSI) is a signal that determines whether to proceed to a step performed in the first post-processing unit (PO-LDP1) or to a step performed in the second post-processing unit (PO-LDP2).

[0217] The post-signal (POSI) may include a first post-signal (SI1), a second post-signal (SI2), and a third post-signal (SI3). A display device that receives the first post-signal (SI1) proceeds to a step performed in the first post-processing unit (PO-LDP1). A display device that receives the second post-signal (SI2) proceeds to a step performed in the second post-processing unit (PO-LDP2).

[0218] A first response path (RSI1) may proceed for a first subsequent signal (SI1). A second response path (RSI2) may proceed for a second subsequent signal (SI2). When the first response path (RSI1) proceeds, the step performed in the first subsequent process unit (PO-LDP1) proceeds, and when the second response path (RSI2) proceeds, the step performed in the second subsequent process unit (PO-LDP2) proceeds.

[0219] The detection unit (TP) performs a detection step as described above. If the signal determining which step to proceed for an already manufactured display device is the post-signal (POSI) as the detection step is performed, the pre-signal (PRSI) can transmit a signal containing information that needs to be corrected in the process unit (LDP) as the detection step is performed.

[0220] The full signal (PRSI) can be output from the system unit (SYS) connected to the detection unit (TP) and transmitted to the process unit (LDP). Based on the results detected by the detection unit (TP), the full signal (PRSI) can transmit a signal that improves the precision of the drilling process performed in the process unit (LDP) so that the laser can be irradiated at an appropriate location. For example, the full signal (PRSI) may include a signal for applying an offset to the position of the laser generator or a signal for correcting the size and / or position of the laser, but the embodiments of this specification are not limited thereto. The signal for correcting the size of the laser may include a correction signal regarding whether the laser has removed the light-emitting layer with appropriate output energy. For example, it may include a correction signal regarding the output energy value of the laser, a correction signal regarding whether the light-emitting layer has been removed with an appropriate thickness, etc. The signal for correcting the position of the laser may include a signal related to position adjustment using an align key, but the embodiments of this specification are not limited thereto.

[0221] In this way, after the step performed in the process unit (LDP) is completed, a post-signal (POSI) may be output from the detection unit (TP), and a pre-signal (PRSI) may be output from the system unit (SYS) connected to the detection unit (TP). The pre-signal (PRSI) may include a signal that corrects factors prior to the laser drilling process, and the post-signal (POSI) may include a signal that corrects factors after the laser drilling process.

[0222] The method for manufacturing a display device according to the present specification can provide a means to solve problems that occur upon receiving a post-signal (POSI).

[0223] The post-signal (POSI) may include a first post-signal (SI1), a second post-signal (SI2), and a third post-signal (SI3). The first post-signal (SI1) triggers a first response path (RSI1), and for a display device manufactured according to the first response path (RSI1), a step performed in the first post-processing unit (PO-LDP1) is carried out. The second post-signal (SI2) triggers a second response path (RSI2), and for a display device manufactured according to the second response path (RSI2), a step performed in the second post-processing unit (PO-LDP2) is carried out. The third post-signal (SI3) will be described later.

[0224] The steps performed in the first post-processing unit (PO-LDP1) and the steps performed in the second post-processing unit (PO-LDP2) may differ from each other. For example, in a display device where the steps performed in the first post-processing unit (PO-LDP1) are carried out, the contact area between the auxiliary electrode and the common electrode may be sufficiently secured. Therefore, the first post-processing unit (PO-LDP1) can perform steps that must be carried out when manufacturing the display device after the laser drilling process, such as depositing a common electrode.

[0225] In a display device where the steps performed in the second post-processing unit (PO-LDP2) are carried out, the contact area between the auxiliary electrode and the common electrode may not be sufficiently secured. Therefore, the second post-processing unit (PO-LDP2) may perform steps such as those that need to be performed when the common electrode is not deposited or when the display device is identified as a defective product.

[0226] Below, a display device that outputs a first subsequent signal (SI1) from a detection unit (TP) is described.

[0227] FIG. 15 is a plan view showing a display device according to embodiments of the present specification. FIG. 16 is a cross-sectional view corresponding to FIG. 15. FIG. 16 is also a cross-sectional view taken along X2-X2' of FIG. 7.

[0228] Referring to FIGS. 15 and 16, a display device that outputs a first post-signal may include a substrate (110) comprising a first region (AR1) and a second region (AR2). The first region (AR1) may include an area exposed by a pixel defining film (PDL) on the upper surface of an auxiliary electrode (VCE). The second region (AR2) may include an area exposed by a light-emitting layer (LEL) on the upper surface of an auxiliary electrode (VCE). The display device that outputs the first post-signal may be a display device formed by a laser generating device irradiating a laser at a first location.

[0229] The laser drilling margin area (LDA) may be substantially identical to the first area (AR1). A first boundary (BL1) may be defined from the boundary of the first area (AR1), and a first center (CR1) may be defined from the center of the first area (AR1). A second boundary (BL2) may be defined from the boundary of the second area (AR2), and a second center (CR2) may be defined from the center of the second area (AR2). The first boundary (BL1) and the second boundary (BL2) may each be a closed curve or a polygonal shape. In one embodiment, the first boundary (BL1) and the second boundary (BL2) may each be a closed curve, or an ellipse, or a circle, but the embodiments of this specification are not limited thereto.

[0230] In a display device that outputs a first post-signal, the first boundary portion (BL1) may not include multiple points that overlap with the second boundary portion (BL2). In other words, the second region (AR2) may be positioned to be included in the first region (AR1). When a laser is irradiated by a laser generating device positioned at the first location, the first center (CR1) and the second center (CR2) may overlap in a third direction of the substrate (110). However, since the second region (AR2) may be positioned to be included in the first region (AR1) even if the first center (CR1) and the second center (CR2) do not overlap, the embodiments of this specification are not limited thereto.

[0231] When the second region (AR2) is formed to be included in the first region (AR1), the contact area between the auxiliary electrode (VCE) and the common electrode (CME) (e.g., the second contact region (CTA2)) can be sufficiently secured. Accordingly, the display device that outputs the first post-signal can sufficiently improve power consumption.

[0232] The wiring contact area (WCA) may include a first area (AR1), a second area (AR2), a first contact area (CTA1), a second contact area (CTA2), and a laser drilling margin area (LDA).

[0233] A pixel defining layer (PDL) may be positioned to cover one end of an auxiliary electrode (VCE) so as to expose at least a portion of the upper surface of the auxiliary electrode (VCE). A light-emitting layer (LEL) may also be positioned on an anode conductive layer (AML) containing the auxiliary electrode (VCE) so as to expose at least a portion of the upper surface of the auxiliary electrode (VCE).

[0234] The first region (AR1) may include an area exposed by the pixel defining film (PDL) on the upper surface of the auxiliary electrode (VCE). In one embodiment, the first region (AR1) may be substantially the same as the laser drilling margin region (LDA).

[0235] The second region (AR2) may include an area exposed by the light-emitting layer (LEL) on the upper surface of the auxiliary electrode (VCE). In a display device where the first post-signal is output, the second region (AR2) and the second contact region (CTA2) may be substantially the same.

[0236] The first contact area (CTA1) may be an area where the auxiliary electrode (VCE) contacts the second voltage line (VSL) or an area where it contacts a connecting electrode connecting the second voltage line (VSL) and the auxiliary electrode (VCE). For example, if the auxiliary electrode (VCE) is connected to the second voltage line (VSL) through the fifth connecting electrode (CE5), the first contact area (CTA1) may be an area where the auxiliary electrode (VCE) and the fifth connecting electrode (CE5) are in direct contact. For another example, if the auxiliary electrode (VCE) is connected directly to the second voltage line (VSL) without the fifth connecting electrode (CE5), the first contact area (CTA1) may be an area where the auxiliary electrode (VCE) and the second voltage line (VSL) are in direct contact.

[0237] The second contact area (CTA2) may be an area where the common electrode (CME) contacts the auxiliary electrode (VCE). For example, the second contact area (CTA2) may be an area where a portion of the light-emitting layer (LEL) is removed so that the common electrode (CME) contacts the auxiliary electrode (VCE) directly. In a display device where the first post-signal is output, the second area (AR2) and the second contact area (CTA2) may be substantially the same.

[0238] The wiring contact region (WCA) may include openings for connecting the electrode of the light-emitting element layer (EML) and the wiring of the circuit layer (CCL). For example, the wiring contact region (WCA) may include openings located in a non-conductive film to connect the second voltage line (VSL) and the common electrode (CME).

[0239] The fourth opening can penetrate the light-emitting layer (LEL). The fourth opening can expose at least a portion of the upper surface of the auxiliary electrode (VCE). The common electrode (CME) and the auxiliary electrode (VCE) can be connected to each other through the fourth opening. The fourth opening can be formed through a laser drilling process. A second contact region (CTA2) where the auxiliary electrode (VCE) and the fifth connecting electrode (CE5) come into contact can be formed by the fourth opening.

[0240] In some embodiments, the width (W1) of the first contact area (CTA1) and the width (W2) of the second contact area (CTA2) may each be smaller than the width of the laser drilling margin area (LDA). In this specification, the width (W1) of the first contact area (CTA1) may mean the minimum width of the second opening (OP2), the width (W2) of the second contact area (CTA2) may mean the minimum width of the fourth opening, and the width of the laser drilling margin area (LDA) may mean the minimum width of the third opening (OP3).

[0241] In one embodiment, the width of the laser drilling margin area (LDA) may be approximately 20 µm or more. Preferably, the width of the laser drilling margin area (LDA) may be approximately 30 µm or more. In one embodiment, the width (W1) of the first contact area (CTA1) and the width (W2) of the second contact area (CTA2) may be approximately 5 µm or more and 30 µm or less.

[0242] In some embodiments, the first contact region (CTA1) and the second contact region (CTA2) may overlap in the laser drilling margin region (LDA) and the third direction (DR3), respectively. For example, the second opening (OP2) of the via film (VIA) and the fourth opening of the light-emitting layer (LEL) may overlap in the third opening (OP3) of the pixel defining film (PDL) and the third direction (DR3), respectively. The entire portion of the first contact region (CTA1) and the entire portion of the second contact region (CTA2) may each be located within the region overlapping with the laser drilling margin region (LDA).

[0243] Accordingly, the width of the laser drilling margin area (LDA) can be maximized within a wiring contact area (WCA) of the same width. Therefore, the laser drilling process margin can be secured even in high-resolution panels.

[0244] The laser drilling margin region (LDA) may be a region for securing a process margin of the laser (LS) in the laser drilling process. The laser drilling margin region (LDA) may include a region where the light-emitting layer (LEL) contacts the auxiliary electrode (VCE) and a region where the light-emitting layer (LEL) is removed. For example, the laser drilling margin region (LDA) may include a region where the light-emitting layer (LEL) contacts the auxiliary electrode (VCE) and a second contact region (CTA2).

[0245] Below, a display device that outputs the second subsequent signal (SI2) is described.

[0246] FIG. 17 is a block diagram illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 18 is a plan view showing a display device according to embodiments of the present specification. FIG. 19 is a cross-sectional view corresponding to FIG. 18.

[0247] Referring to FIGS. 17, 18, and 19, in a display device that outputs a second post-signal (SI2), the first boundary (BL1) may not include multiple points that overlap with the second boundary (BL2). In other words, the second region (AR2) may not overlap with the first region (AR1). When a laser is irradiated by a laser generator placed at a second location, the first center (CR1) and the second center (CR2) may be misaligned in the third direction (DR3) of the substrate. All second regions (AR2) may not overlap with the first region (AR1) in the thickness direction (e.g., the third direction (DR3)). Therefore, the second contact region (CTA2) does not exist, and the display device that outputs the second post-signal (SI2) does not relatively improve power consumption. For a display device that outputs a second post-signal (SI2), a step performed in a second post-processing unit (PO-LDP2) is carried out, and the second post-processing unit (PO-LDP2) may perform a step of not depositing a common electrode or determining whether an appropriate contact area (e.g., a second contact area (CTA2)) is secured across the entire display area including a plurality of laser drilling margin areas (LDA). However, if a contact area (e.g., a second contact area (CTA2)) is not sufficiently secured in any one laser drilling margin area (LDA), the voltage drop phenomenon of the display device in the display area including the said laser drilling margin area (LDA) may not be improved. For a display device including the said laser drilling margin area (LDA), the second post-processing unit (PO-LDP2) may perform subsequent processes such as removing the light-emitting layer (LEL) and re-performing the laser drilling process, but the embodiments of this specification are not limited thereto.

[0248] FIG. 20 is a block diagram for illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented.

[0249] Referring to FIG. 20, when a display device is manufactured to output a third post-signal (SI3), the detector (TP) may not be able to make a clear determination as to whether an appropriate contact area (e.g., a second contact area (CTA2)) has been secured or not secured. The detector (TP) clearly outputs a first post-signal (SI1) when the second area (AR2) completely overlaps with the first area (AR1). When the second area (AR2) completely does not overlap with the first area (AR1) (is misaligned), it clearly outputs a second post-signal (SI2). However, if the area of ​​the overlapping area of ​​the second area (AR2) and the first area (AR1) (e.g., the second contact area (CTA2)) is smaller than the area of ​​the second area (AR2) (see FIG. 24, FIG. 25, FIG. 27, FIG. 28, FIG. 29, FIG. 30), the detector (TP) can output a third after-signal (SI3).

[0250] When the third subsequent signal (SI3) is output, the manufacturing process may generate an awareness signal including an alarm, but the embodiments of this specification are not limited thereto. The awareness signal is a signal output from the detection unit (TP) when it is relatively difficult to make a clear judgment, and includes all visual and auditory signals, etc. The awareness signal may be omitted. When the third subsequent signal (SI3) is output, the operation of the process may be stopped.

[0251] In this case, the manufacturing process according to the embodiment may perform the steps of the manufacturing method according to the flowchart described below.

[0252] FIG. 21 is a flowchart for explaining a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented.

[0253] Referring to FIG. 21, in one step, a recognition signal may be generated (see S100). The step of generating the recognition signal may be omitted.

[0254] In a subsequent step, a step to identify the cause of the generated cognitive signal may be performed (see S200).

[0255] In a subsequent step, a determination may be made as to whether the occurrence of a cognitive signal is due to the inability to determine the positional relationship between the first region (AR1) and the second region (AR2) (see S300).

[0256] If the perception signal is not caused by the inability to determine the positional relationship described above, a step of identifying the cause of the perception signal and taking measures regarding it may be performed (see SACT1).

[0257] If the recognition signal is generated due to the inability to determine the positional relationship described above, a subsequent step may be performed (see S400). Here, a step of verifying an image in which the first region (AR1) and the second region (AR2) are formed may be performed.

[0258] In a subsequent step, a step of detecting the location of the first region (AR1) and the location of the second region (AR2) may be performed (see S500). A detailed description of the detection determination process will be provided later.

[0259] When a determination regarding the positional relationship between the first region (AR1) and the second region (AR2) is performed, any one of the multiple steps (see SACT2, S600) may subsequently be performed. When the determination regarding the positional relationship is performed first, it may be determined whether the display device is one in which a contact area (e.g., the second contact area (CTA2)) can be properly secured or not.

[0260] If it is determined that the contact area (e.g., the second contact area (CTA2)) is adequately secured even though a recognition signal has been generated, the first response path (RSI1) proceeds according to the third post-signal (SI3), and the step performed in the first post-processing unit (PO-LDP1) on the manufactured display device may proceed (see S600).

[0261] If it is determined that the recognition signal was generated due to the contact area (e.g., the second contact area (CTA2)) not being properly secured, the second response path (RSI2) proceeds according to the third post-signal (SI3), and the step performed in the second post-processing unit (PO-LDP2) on the manufactured display device may proceed (see SACT2).

[0262] In a subsequent step, the interrupted process may be restarted (see S700).

[0263] FIG. 22 is a flowchart that explains in detail the determination process of a method for manufacturing a display device according to one embodiment of the present specification.

[0264] Referring to FIG. 22, a determination process according to one embodiment may include a step of detecting the location of a first region (AR1) and the location of a second region (AR2). In a display device on which the determination process according to the embodiment is performed, the area of ​​the region (e.g., second contact region (CTA2)) where the first region (AR1) and the second region (AR2) overlap in a third direction (DR3) (e.g., thickness direction) may be smaller than the area of ​​the second region (AR2).

[0265] The step of detecting the location of the first region (AR1) and the location of the second region (AR2) can be performed using a deep learning detection method for detecting the type and location of an object (Object Detection). A deep learning detection method is a computer vision technology used to accurately find the class and location (bounding box: x, y, width, length) of a meaningful object in an image or video, as an example of artificial intelligence technology. The deep learning detection method can be utilized to determine the positional relationship between the first region (AR1) and the second region (AR2). For example, a meaningful object may include the first region (AR1) and the second region (AR2).

[0266] In the decision process, a step may be performed in which a plurality of cameras move to a location where a laser drilling margin area (LDA) is placed (see S510). The cameras have coordinate values ​​for said location, and said coordinate values ​​may include corrected coordinate values ​​due to shrinkage and / or expansion of the substrate caused by the process performed in the previous government.

[0267] In a subsequent step, a step of obtaining location information of the first region (AR1) and the second region (AR2) using a deep learning detection method may be performed (see S520).

[0268] In a subsequent step, a first center (CR1) which is the center of the first region (AR1), a second center (CR2) which is the center of the second region (AR2), and a first boundary (BL1) and a second boundary (BL2) may be defined. Additionally, a step of defining multiple points where the first boundary (BL1) and the second boundary (BL2) intersect may be performed (see S530).

[0269] In a subsequent step, a step of defining a virtual straight line (IML) connecting two points among a plurality of points where the first boundary (BL1) and the second boundary (BL2) intersect may be performed (see S540).

[0270] In a subsequent step, a step of determining the positional relationship between the first center (CR1), the second center (CR2), and the imaginary straight line (IML) may be performed (see S550).

[0271] In the case of a display device in which a second center (CR2), a virtual straight line (IML), and a first center (CR1) are arranged sequentially, it may be determined that a recognition signal occurred because the contact area (e.g., the second contact area (CTA2)) was not adequately secured. This may be determined to be a display device in which the contact area (e.g., the second contact area (CTA2)) between the auxiliary electrode and the common electrode cannot be adequately secured.

[0272] In the case of a display device where a virtual straight line (IML) and a second center (CR2) overlap in the thickness direction, it can be determined that a contact area (e.g., a second contact area (CTA2)) is adequately secured even though a recognition signal has been generated. This can be determined as a display device in which the contact area (e.g., a second contact area (CTA2)) between the auxiliary electrode and the common electrode can be adequately secured.

[0273] In the case of a display device in which a virtual straight line (IML), a second center (CR2), and a first center (CR1) are sequentially arranged, it can be determined that a contact area (e.g., a second contact area (CTA2)) is adequately secured even when a recognition signal is generated. This can be determined as a display device in which the contact area (e.g., a second contact area (CTA2)) between an auxiliary electrode and a common electrode can be adequately secured.

[0274] The judgment process according to the embodiment may ultimately be a judgment process regarding whether the contact area (e.g., the second contact area (CTA2)) has been adequately secured. Therefore, it is not limited to a judgment process such as that described in the above-described embodiment. For example, if the overlapping area of ​​the first area (AR1) and the second area (AR2) is simply calculated and it is determined that the overlapping area is greater than or less than a certain ratio, a judgment may be made as to whether the contact area (e.g., the second contact area (CTA2)) has been adequately secured despite the occurrence of a perception signal, or whether the perception signal occurred due to the contact area (e.g., the second contact area (CTA2)) not being adequately secured. The area calculation may be performed using techniques known to a person skilled in the art (e.g., OpenCV, Image Contour function, etc.).

[0275] FIG. 23 is a block diagram illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 24 is a plan view showing a display device according to embodiments of the present specification. FIG. 25 is a cross-sectional view corresponding to FIG. 24.

[0276] Referring to FIGS. 23, 24, and 25, in a display device in which a third follow-up signal (SI3) is output and a second response path (RSI2) proceeds, the area of ​​the region where the first region (AR1) and the second region (AR2) overlap in the third direction (DR3) (e.g., the second contact region (CTA2)) may be smaller than the area of ​​the second region (AR2). The detection unit (TP) transmits the third follow-up signal (SI3) to such a display device, and the above-described judgment process will be performed.

[0277] A first boundary (BL1), a second boundary (BL2), a first center (CR1), and a second center (CR2) may be defined from a first region (AR1) and a second region (AR2). The first boundary (BL1) may include a plurality of points that overlap with the second boundary (BL2) in a third direction (DR3). The plurality of points may include a first point (P1) and a second point (P2). A virtual straight line (IML) connecting the first point (P1) and the second point (P2) may be defined. In one embodiment, the second center (CR2), the virtual straight line (IML), and the first center (CR1) may be arranged sequentially. The detection unit (TP) outputs a third post-signal (SI3), the second response path (RSI2) proceeds, and the step performed in the second post-processing unit (PO-LDP2) for the display device may proceed. This may be a display device corresponding to a case where it is determined that a recognition signal occurred due to the contact area (e.g., the second contact area (CTA2)) not being adequately secured. The interrupted process of the manufacturing process can be restarted.

[0278] FIG. 26 is a block diagram illustrating a system in which a method for manufacturing a display device according to one embodiment of the present specification is implemented. FIG. 27 is a plan view showing a display device according to embodiments of the present specification. FIG. 28 is a cross-sectional view corresponding to FIG. 27.

[0279] Referring to FIGS. 26, 27, and 28, in a display device where a third follow-up signal (SI3) is output and a first response path (RSI1) proceeds, the area of ​​the region where the first area (AR1) and the second area (AR2) overlap in the third direction (DR3) (e.g., the second contact area (CTA2)) may be smaller than the area of ​​the second area (AR2). The detection unit (TP) transmits the third follow-up signal (SI3) to such a display device, and the above-described judgment process will be performed.

[0280] A first boundary (BL1), a second boundary (BL2), a first center (CR1), and a second center (CR2) may be defined from a first region (AR1) and a second region (AR2). The first boundary (BL1) may include a plurality of points that overlap with the second boundary (BL2) in a third direction (DR3). The plurality of points may include a first point (P1) and a second point (P2). A virtual straight line (IML) connecting the first point (P1) and the second point (P2) may be defined. In one embodiment, the second center (CR2) may be positioned to overlap with the virtual straight line (IML) in a third direction (DR3). The detection unit (TP) outputs a third post-signal (SI3), the first response path (RSI1) proceeds, and the step performed in the first post-processing unit (PO-LDP1) for the display device may proceed. This may be a display device in which a contact area (e.g., a second contact area (CTA2)) is adequately secured even though a recognition signal has occurred. The interrupted process of the manufacturing process can be restarted.

[0281] FIG. 29 is a plan view showing a display device according to embodiments of the present specification. FIG. 30 is a cross-sectional view corresponding to FIG. 29.

[0282] Referring to FIGS. 29 and 30, in a display device where a third follow-up signal (SI3) is output and a first response path (RSI1) proceeds, the area of ​​the region where the first region (AR1) and the second region (AR2) overlap in the third direction (DR3) (e.g., the second contact region (CTA2)) may be smaller than the area of ​​the second region (AR2). The detection unit (TP) transmits the third follow-up signal (SI3) to such a display device, and the above-described judgment process will be performed.

[0283] A first boundary (BL1), a second boundary (BL2), a first center (CR1), and a second center (CR2) may be defined from a first region (AR1) and a second region (AR2). The first boundary (BL1) may include a plurality of points that overlap with the second boundary (BL2) in a third direction (DR3). The plurality of points may include a first point (P1) and a second point (P2). A virtual straight line (IML) connecting the first point (P1) and the second point (P2) may be defined. In one embodiment, the virtual straight line (IML), the second center (CR2), and the first center (CR1) may be arranged sequentially. The detection unit (TP) outputs a third post-signal (SI3), the first response path (RSI1) proceeds, and the step performed in the first post-processing unit (PO-LDP1) for the display device may proceed. This may be a display device in which a contact area (e.g., a second contact area (CTA2)) is adequately secured even though a recognition signal has occurred. The interrupted process of the manufacturing process can be restarted.

[0284] In the above embodiments, a circular first region (AR1) and a second region (AR2) are defined as examples, and a virtual straight line (IML) is derived by assuming that the first region (AR1) and the second region (AR2) are circular or elliptical. However, the embodiments of this specification are not limited thereto. For a display device in which the area where the first region (AR1) and the second region (AR2) overlap in the third direction (DR3) satisfies a specific criterion (Speculation), a first response path (RSI1) may proceed. For a display device that satisfies the specific criterion, a first post-processing step (PO-LDP1) will proceed, and for a display device that does not satisfy the specific criterion, a second post-processing step (PO-LDP2) will proceed. In one embodiment, only the display device in which the first post-processing step (PO-DP1) has been performed will be finally produced, but the embodiments of this specification are not limited thereto.

[0285] In this specification, the concept of a virtual straight line (IML) is provided as a specific means for determining whether to proceed to a step performed in the first post-processing unit (PO-LDP1) or a step performed in the second post-processing unit (PO-LDP2) when the first region (AR1) and the second region (AR2) overlap each other. In this specification, the concept of a virtual straight line (IML) is provided as a means for determining whether a sufficient (or insufficient) contact area between the auxiliary electrode and the common electrode has been secured. However, the embodiments of this specification are not limited thereto, and any means capable of determining the area of ​​the overlapping region may be included within the scope of rights of this specification.

[0286] FIG. 31 is a block diagram of an electronic device according to one embodiment of the present specification. FIG. 32 is a schematic diagram of an electronic device according to various embodiments of the present specification.

[0287] Referring to FIG. 31, an electronic device (10) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14).

[0288] The processor (12) may include at least one of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0289] The memory (15) may store data information necessary for the operation of the processor (12) or the display module (11). When the processor (12) executes an application stored in the memory (15), a video data signal and / or an input control signal is transmitted to the display module (11), and the display module (11) can process the received signal and output video information through a display screen.

[0290] The power module (14) may include a power supply module such as a power adapter or a battery device. The power module (14) may include a power conversion module. The power conversion module can convert the power supplied by the power supply module to generate power required for the operation of the electronic device (10).

[0291] At least one of each component of the electronic device (10) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (10) other than the display device.

[0292] Referring to FIG. 32, various electronic devices to which a display device according to the embodiments of the present specification is applied may include image display electronic devices such as a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desk monitor (10_1e). In addition, various electronic devices to which a display device according to the embodiments of the present specification is applied may include wearable electronic devices including display modules such as smart glasses (10_2a), a head-mounted display (10_2b), and a smart watch (10_2c), and automotive electronic devices (10_3) including display modules such as a Center Information Display (CID) and a room mirror display placed on the instrument panel, center fascia, and dashboard of a vehicle.

[0293] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the invention may be implemented in other specific forms without changing the technical spirit or essential features of the present specification. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

[0294] Although embodiments of this specification have been described above with reference to the attached drawings, those skilled in the art will understand that the embodiments disclosed in this specification may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. Explanation of the symbols

[0295] 10: Device 100: Display board 10_1: Display device 10_1a: Smartphone 10_1b: Tablet PC 10_1c: Laptop 10_1d: TV 10_1e: Desk Monitor 10_2a: Smart Glasses 10_2b: Head-mounted display 10_2c: Smartwatch 10_3: Automotive Electronic Devices 11: Display Module 110: Substrate 12: Processor 13: Memory 14: Power Module 15: Memory 170: Bag structure 171: 1st Bag Inorganic Barrier 172: Bag organic film 173: Second Bag Weapon Barrier 200: Color conversion substrate 200_1: Color conversion board 210: Second substrate 220: First capping layer 230: Second capping layer 300: Filler 400: Sealing part 510: Connecting film 520: Display drive unit 530: Circuit board 540: Timing control unit 550: Power supply 560: Gate drive unit AML: Anode Challenge Layer AR1: Area 1 AR2: Area 2 Ag: A layer of material with a high work function and silver Al: Aluminum Au: Gold BF: Buffer membrane BL1: The First Boundary BL2: The Second Boundary BM: Shading component BML: Lower conductive layer BPD: Board pad BRS1, BRS2, ​​BRS3: 1st to 3rd base resins C1: Capacitor CCL: Circuit layer CE1: First connecting electrode CE1, CE2, CE3, CE4: Connecting electrodes CE2: Second connecting electrode CE3: Third connecting electrode CE4: 4th connecting electrode CE5: 5th connecting electrode CFL: Color filter layer CME: Common electrode CNT: Contact hole CR1: 1st center CR2: Second Center Ca: Calcium Cr: Chrome Cu: Copper DA: Display area DE1: First drain electrode DE2: Second drain electrode DE3: Third drain electrode DL: Data line DL1: 1st data line DL1, DL2, DL3: 1st to 3rd data lines DL2: 2nd data line DL3: Third data line DR1: First direction DR1, DR2, DR3: First to third directions DR2: Second Direction DR3: Third Direction ED: Light-emitting element EML: Light-emitting diode layer GE1: First gate electrode GE2: Second gate electrode GE3: Third gate electrode GI: Gate insulating layer GL: Gate line GL1: 1st Gate Line GL2: Second Gate Line GML: Gate Challenge Layer HD1: 1st position HD1, HD2: Laser generator HD2: Second Location IC: Integrated Circuit IML: Imaginary straight line Ir: Iridium LA: Emissive region LA1: First light emission region LA1, LA2, LA3: Emission regions LA2: Second light emission region LA3: Third light emission region LDA: Laser drilling margin area LDP: Process Department LEL: Emissive layer LS: Laser Li: Lithium Mg: Magnesium Mo: Molybdenum N1: Node 1 N2: Node 2 NDA: Non-display area NLA: Non-luminescent region Nd: Neodymium Ni: Nickel OP1: 1st opening OP2: Second Opening OP3: Third Opening OP4: The 4th Opening P1: Point 1 P2: 2nd branch PDA: Pad area PDL: Pixel Definition Layer PTL: Bulkhead PV: Shield PXB: Third pixel electrode PXE: Pixel electrode PXG: Second pixel electrode PXR: 1st pixel electrode Pd: Lead Pt: Platinum SCP: Spawner SE1: First source electrode SE2: Second source electrode SE3: Third source electrode SI1: First after signal SI2: Second after signal SI3: Third after-signal SP: Pixel SP1: 1st pixel SP1, SP2, SP3: 1st to 3rd pixels SP2: The Second Pixel SP3: The Third Pixel ST1: First transistor ST1, ST2, ST3: 1st to 3rd transistors ST2: Second transistor ST3: Third transistor SYS: System section TP: Detector TPL: Light-transmitting layer Ti: Titanium VCE: Auxiliary electrode VDL: 1st voltage line VIA: ViaMak VIL: Initialization voltage line VSL: Second voltage line W1: Width W2: Width WCA: Wiring Contact Area WCL: Wavelength conversion layer WPD: Wiring pad

Claims

Claim 1 A display device comprising: a substrate including a first region and a second region; an anode conductive layer disposed on the substrate and including an auxiliary electrode; a pixel defining film disposed to cover one end of the auxiliary electrode so as to expose at least a portion of the upper surface of the auxiliary electrode; a light-emitting layer disposed on the anode conductive layer so as to expose at least a portion of the upper surface of the auxiliary electrode; and a common electrode disposed on the light-emitting layer so as to contact the auxiliary electrode, wherein the first region includes an area exposed by the pixel defining film on the upper surface of the auxiliary electrode, and the second region includes an area exposed by the light-emitting layer on the upper surface of the auxiliary electrode, and the area of ​​the region where the first region and the second region overlap in the thickness direction of the substrate is smaller than the area of ​​the second region. Claim 2 A display device according to claim 1, wherein the anode conductive layer further comprises a pixel electrode, and at least a portion of the light-emitting layer is disposed between the pixel electrode and the common electrode. Claim 3 A display device according to claim 1, wherein the substrate further comprises a display area including the first region and the second region; and a non-display area surrounding the display area. Claim 4 A display device according to claim 1, wherein a first boundary is defined from the boundary of the first region and a second boundary is defined from the boundary of the second region, and the first boundary includes a plurality of points that overlap with the second boundary in the thickness direction. Claim 5 A display device according to claim 1, wherein a first boundary is defined from the boundary of the first region and a second boundary is defined from the boundary of the second region, and the first boundary includes a first point and a second point that overlap with the second boundary in the thickness direction. Claim 6 A display device according to claim 5, wherein a first center is defined from the center of the first region, a second center is defined from the center of the second region, and a virtual straight line connecting the first point and the second point is defined. Claim 7 A display device according to claim 6, wherein the second center, the virtual straight line, and the first center are arranged sequentially. Claim 8 In claim 6, the display device wherein the second center overlaps the virtual straight line and the thickness direction. Claim 9 A display device according to claim 6, wherein the virtual straight line, the second center, and the first center are arranged sequentially. Claim 10 A display device according to claim 1, wherein the auxiliary electrode is positioned to contact the common electrode in an area where the first region and the second region overlap in the thickness direction of the substrate. Claim 11 A method for manufacturing a display device comprising: forming a substrate including a first region and a second region; forming an anode conductive layer disposed on the substrate and including an auxiliary electrode; forming a pixel defining film disposed to cover one end of the auxiliary electrode so as to expose at least a portion of the upper surface of the auxiliary electrode; forming a light-emitting layer disposed on the anode conductive layer; removing at least a portion of the light-emitting layer so as to expose at least a portion of the upper surface of the auxiliary electrode; and detecting the location of the first region and the location of the second region, wherein the first region includes an area exposed by the pixel defining film on the upper surface of the auxiliary electrode, and the second region includes an area exposed by the light-emitting layer on the upper surface of the auxiliary electrode, and the area of ​​the region where the first region and the second region overlap in the thickness direction of the substrate is smaller than the area of ​​the second region. Claim 12 A method for manufacturing a display device according to claim 11, wherein the step of detecting the location of the first region and the location of the second region is performed using a deep learning detection method for detecting the type and location of an object (Object Detection). Claim 13 A method for manufacturing a display device according to claim 11, further comprising the step of comparing the positional relationship between the first region and the second region. Claim 14 A method for manufacturing a display device according to claim 13, wherein the step of comparing the positional relationship between the first region and the second region comprises: a step of defining a first boundary from the boundary of the first region; a step of defining a second boundary from the boundary of the second region; a step of defining a virtual straight line by connecting a plurality of points where the first boundary and the second boundary overlap in the thickness direction; a step of defining a first center from the center of the first region; and a step of defining a second center from the center of the second region. Claim 15 A method for manufacturing a display device according to claim 14, wherein the step of comparing the positional relationship between the first region and the second region further includes the step of comparing the positional relationship between the virtual straight line, the second center, and the first center. Claim 16 An electronic device comprising: a processor that provides a video signal; a display module that receives a video signal from the processor and displays a video; and a power module that supplies power to the display module, wherein the display module comprises: a substrate having a first region and a second region; an anode conductive layer disposed on the substrate and including an auxiliary electrode; a pixel defining film disposed to cover one end of the auxiliary electrode so as to expose at least a portion of the upper surface of the auxiliary electrode; a light emitting layer disposed on the anode conductive layer so as to expose at least a portion of the upper surface of the auxiliary electrode; and a common electrode disposed on the light emitting layer so as to contact the auxiliary electrode, wherein the first region includes an area exposed by the pixel defining film on the upper surface of the auxiliary electrode, and the second region includes an area exposed by the light emitting layer on the upper surface of the auxiliary electrode, and the area of ​​the region where the first region and the second region overlap in the thickness direction of the substrate is smaller than the area of ​​the second region. Claim 17 An electronic device according to claim 16, wherein the auxiliary electrode is positioned to contact the common electrode in an area where the first region and the second region overlap in the thickness direction of the substrate. Claim 18 An electronic device according to claim 16, wherein a first boundary is defined from the boundary of the first region and a second boundary is defined from the boundary of the second region, and the first boundary includes a first point and a second point that overlap with the second boundary in the thickness direction. Claim 19 An electronic device according to claim 18, wherein a first center is defined from the center of the first region, a second center is defined from the center of the second region, and an imaginary straight line connecting the first point and the second point is defined. Claim 20 An electronic device according to claim 19, wherein the virtual straight line, the second center, and the first center are arranged sequentially.

Images