Method and apparatus for improving throughput for LDPC codes

Abstract

The present disclosure relates to a 5G or 6G communication system for supporting higher data transmission rates.

Description

Technology Field

[0001] The present disclosure relates to the operation of a terminal and a base station in a wireless communication system. Specifically, the present disclosure relates to a method for improving the throughput of LDPC codes and an apparatus capable of performing the same. Background Technology

[0002] Looking back at the evolution of wireless communication through successive generations, technologies have been developed primarily for human-oriented services, such as voice, multimedia, and data. Following the commercialization of 5G (5th Generation) communication systems, connected devices, which have been increasing explosively, are expected to be connected to communication networks. Examples of networked objects include vehicles, robots, drones, home appliances, displays, smart sensors installed in various infrastructures, construction machinery, and factory equipment. Mobile devices are expected to evolve into various form factors, such as augmented reality glasses, virtual reality headsets, and holographic devices. In the 6G (6th Generation) era, efforts are underway to develop improved 6G communication systems to connect hundreds of billions of devices and objects to provide diverse services. For this reason, 6G communication systems are being referred to as "beyond 5G" systems.

[0003] In the 6G communication system predicted to be realized around 2030, the maximum transmission speed is tera (i.e., 1,000 gigabit) bps (bit per second), and the wireless latency is 100 microseconds (μsec). In other words, compared to the 5G communication system, the transmission speed in the 6G communication system is 50 times faster, and the wireless latency is reduced to one-tenth.

[0004] To achieve such high data transmission speeds and ultra-low latency, 6G communication systems are being considered for implementation in the terahertz (THz) band (e.g., the 95 gigahertz (GHz) to 3 terahertz (3THz) band). Due to more severe path loss and atmospheric absorption phenomena compared to the millimeter wave (mmWave) band introduced in 5G, the importance of technologies capable of guaranteeing signal reach, or coverage, is expected to increase in the terahertz band. As key technologies to ensure coverage, new waveforms, beamforming, and multi-antenna transmission technologies such as massive Multiple-Input and Multiple-Output (MIMO), Full Dimensional MIMO (FD-MIMO), array antennas, and large-scale antennas, which are superior in terms of coverage compared to RF (Radio Frequency) devices, antennas, and OFDM (Orthogonal Frequency Division Multiplexing), must be developed. In addition, new technologies such as metamaterial-based lenses and antennas, high-dimensional spatial multiplexing technology using Orbital Angular Momentum (OAM), and Reconfigurable Intelligent Surface (RIS) are being discussed to improve the coverage of terahertz band signals.

[0005] In addition, to improve frequency efficiency and system network, development is underway in 6G communication systems for full duplex technology, in which uplink and downlink simultaneously utilize the same frequency resources at the same time; network technology that integrates satellites and HAPS (High-Altitude Platform Stations); network structure innovation technology that supports mobile base stations and enables network operation optimization and automation; dynamic spectrum sharing technology through collision avoidance based on spectrum usage prediction; AI-based communication technology that utilizes AI (Artificial Intelligence) from the design stage and internalizes end-to-end AI support functions to realize system optimization; and next-generation distributed computing technology that realizes services of complexity exceeding the limits of terminal computing capabilities by utilizing ultra-high performance communication and computing resources (Mobile Edge Computing (MEC), cloud, etc.). In addition, attempts are continuing to further strengthen connectivity between devices, further optimize networks, promote the softwareization of network entities, and increase the openness of wireless communication through the design of new protocols to be used in 6G communication systems, the implementation of hardware-based security environments, the development of mechanisms for the safe utilization of data, and the development of technologies regarding privacy maintenance methods.

[0006] Due to the research and development of such 6G communication systems, it is expected that a new dimension of hyper-connected experience will become possible through the hyper-connectivity of 6G communication systems, which encompasses not only connections between objects but also connections between people and objects. Specifically, it is projected that 6G communication systems will enable the provision of services such as truly immersive eXtended Reality (XR), high-fidelity mobile holograms, and digital replicas. Furthermore, services such as remote surgery, industrial automation, and emergency response, which are provided through 6G communication systems with enhanced security and reliability, will be applied in various fields including industry, healthcare, automotive, and home appliances. The problem to be solved

[0007] According to one embodiment of the present disclosure, performance degradation, processing speed degradation, and delay may occur due to the limitation of the maximum lifting size. Therefore, in order to solve such problems, the present disclosure [describes] the maximum lifting size This invention provides a method to compensate for performance degradation by extending the maximum size of a single code block of LDPC codes provided by existing NR. Additionally, by extending and utilizing the parallelization properties of the existing system as the maximum lifting size increases, it is possible to provide processing speeds that are the same or faster. In other words, this invention proposes a method to improve error rate performance without additional delay or computational complexity. means of solving the problem

[0008] The present disclosure for solving the above-mentioned problems comprises, in a method performed by a transmitting device in a first system, a step of determining a transport block size (TBS); a step of determining a base matrix based on the TBS and a code rate; a step of determining a lifting size; a step of determining a parity check matrix based on the lifting size and the base matrix; and a step of performing encoding for a code block based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor.

[0009] In addition, the present disclosure for solving the above-mentioned problems comprises a method performed by a receiving device in a first system, the method including: receiving a signal; checking a TBS (transport block size); checking a base matrix based on the TBS and the code rate; checking a lifting size; checking a parity check matrix based on the lifting size and the base matrix; and performing decoding on the signal based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor.

[0010] In addition, the present disclosure for solving the above-mentioned problems comprises, in a first system a transmitting device: a transmitting and receiving unit; and a control unit connected to the transmitting and receiving unit, wherein the control unit checks a transport block size (TBS), checks a base matrix based on the TBS and the code rate, checks a lifting size, checks a parity check matrix based on the lifting size and the base matrix, and performs encoding for a code block based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor.

[0011] In addition, the present disclosure for solving the above-mentioned problems comprises, in a receiving device of a first system, a transmitting and receiving unit; and a control unit connected to the transmitting and receiving unit, wherein the control unit receives a signal, checks a transport block size (TBS), checks a base matrix based on the TBS and the code rate, checks a lifting size, checks a parity check matrix based on the lifting size and the base matrix, and performs decoding on the signal based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor. Effects of the invention

[0012] According to an embodiment of the present disclosure, as the maximum code block size increases, the length that can be supported in a specific code block may be increased. Additionally, the total number of code blocks may be reduced, and as the length of the code block increases, error rate performance compared to the existing method may be improved. Consequently, delay and complexity may be mitigated because the retransmission probability and the number of retransmission blocks are reduced.

[0013] In addition, as the maximum lifting size increases, the throughput that can be processed at once also increases; therefore, the time required to process code blocks longer than before is offset, preventing additional delays or complexity. Brief explanation of the drawing

[0014] Figure 1 is a diagram illustrating a systematic LDPC codeword structure. Figure 2 is a diagram showing the base graph and tanner graph of an LDPC code. FIG. 3 is a diagram illustrating a method for performing LDPC encoding according to the present disclosure. FIG. 4 is a diagram illustrating a method for performing LDPC decoding according to the present disclosure. FIG. 5 is a drawing illustrating an example of a basic matrix having a size of 3*4 according to the present disclosure. Figure 6 is a diagram illustrating an exponential matrix according to the basic matrix of Figure 4. Figure 7 is a diagram illustrating a parity check matrix according to the exponential matrix of Figure 6. FIG. 8 is a diagram illustrating the performance when the number of code blocks based on the same parity check matrix increases as the amount of data to be transmitted increases according to the present disclosure. FIG. 9 is a diagram illustrating the processing delay occurring in an existing system according to the present disclosure. FIG. 10 is a drawing illustrating a method for increasing the size of the maximum symbol block and the maximum lifting size according to one embodiment of the present disclosure. FIG. 11 is a drawing illustrating an example of a parity check matrix as the size of the maximum code block and the maximum lifting size increase according to one embodiment of the present disclosure. FIG. 12A is a drawing illustrating an example for increasing the maximum lifting size according to one embodiment of the present disclosure. FIG. 12B is a drawing illustrating an example for increasing the maximum lifting size according to one embodiment of the present disclosure. FIG. 12C is a drawing illustrating an example for increasing the maximum lifting size according to one embodiment of the present disclosure. FIG. 13 is a drawing illustrating that the maximum lifting size is increased according to one embodiment of the present disclosure, thereby increasing the throughput of the decoder. FIG. 14 is a diagram showing that, according to one embodiment of the present disclosure, the maximum lifting size is increased so that the processing delay time of the decoder is shortened. FIG. 15 is a drawing illustrating the operation of a transmitter according to one embodiment of the present disclosure. FIG. 16 is a drawing illustrating the operation of a receiver according to one embodiment of the present disclosure. FIG. 17 is a block diagram of a transmitting device according to one embodiment of the present disclosure. FIG. 18 is a block diagram of a receiving device according to one embodiment of the present disclosure. Specific details for implementing the invention

[0015] Hereinafter, embodiments of the present invention will be described in detail together with the accompanying drawings.

[0016] In describing the embodiments, technical details that are well known in the technical field to which the present invention belongs and are not directly related to the present invention are omitted. This is intended to convey the essence of the present invention more clearly without obscuring it by omitting unnecessary explanations.

[0017] For the same reason, some components in the attached drawings have been emphasized, omitted, or depicted schematically. Additionally, the dimensions of each component do not fully reflect their actual dimensions. Identical or corresponding components in each drawing have been assigned the same reference numbers.

[0018] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but can be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Throughout the specification, the same reference numerals refer to the same components.

[0019] At this time, it will be understood that each block of the process flow diagrams and combinations of the flow diagrams can be executed by computer program instructions. Since these computer program instructions can be loaded into the processor of a general-purpose computer, a special-purpose computer, or other programmable data processing equipment, the computer also creates means for the instructions executed through the processor of other programmable data processing equipment to perform the functions described in the flow diagram block(s). Since these computer program instructions can also be stored in computer-available or computer-readable memory that can be directed toward the computer or other programmable data processing equipment to implement the function in a specific way, the instructions stored in such computer-available or computer-readable memory can also produce a manufactured item containing means of instruction that perform the function described in the flow diagram block(s). Since computer program instructions can be loaded onto a computer or other programmable data processing equipment, instructions that perform a series of operation steps on the computer or other programmable data processing equipment to create a process executed by the computer can also provide steps for executing the functions described in the flowchart block(s).

[0020] Additionally, each block may represent a module, segment, or part of code containing one or more executable instructions for executing a specified logical function(s). It should also be noted that in some alternative execution examples, the functions mentioned in the blocks may occur out of order. For instance, two blocks described in succession may actually be executed substantially simultaneously, or the blocks may be executed in reverse order according to their corresponding functions.

[0021] In this embodiment, the term "part" refers to a software or hardware component, such as an FPGA or ASIC, and the "part" performs certain roles. However, the meaning of "part" is not limited to software or hardware. The "part" may be configured to reside in an addressable storage medium or configured to operate one or more processors. Accordingly, as an example, the "part" includes components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and "parts" may be combined into a smaller number of components and "parts" or further separated into additional components and "parts." Furthermore, the components and "parts" may be implemented to operate one or more CPUs within a device or secure multimedia card.

[0022] Hereinafter, various embodiments are described in detail with reference to the attached drawings. It should be noted that identical components in the attached drawings are indicated by the same reference numerals whenever possible. Furthermore, it should be noted that the drawings of the present invention attached below are provided to aid in understanding the present invention, and that the present invention is not limited to the forms or arrangements exemplified in the drawings. Additionally, detailed descriptions of known functions and configurations that may obscure the essence of the present invention will be omitted. It should be noted that in the following description, only the parts necessary for understanding the operation according to various embodiments of the present invention will be explained, and descriptions of other parts will be omitted so as not to distract from the essence of the present invention.

[0023] Low-density parity-check (LDPC) codes play a pivotal role in modern communication systems, making a significant contribution to improving their reliability and performance. LDPC is a code class that achieves performance close to theoretical performance limits and capacities as its length increases. Furthermore, the belief propagation (BP) algorithm, known as a representative LDPC decoder, possesses a structure highly suitable for parallel implementation; consequently, it is ideal for systems requiring high throughput and stable reliability. Recently, the 3GPP (3rd Generation Partnership Project) adopted LDPC codes as the 5G new radio (NR) standard, and they are now used as coding technology for data channels.

[0024] In addition to the features mentioned above, 5G NR LDPC codes primarily adopt quasi-cyclic (QC) and raptor-like structures. By defining only the base graph (BG) or base matrix that serves as the basis for the parity-check matrix (PCM) defining the LDPC code, they provide stable error correction performance while supporting various code lengths and rates. Furthermore, the quasi-cyclic structure enables the application of layered scheduling to the BP decoding algorithm, providing a structure more suitable for parallelization implementation and thereby enabling a higher level of low-latency communication. Moreover, through the combination of HARQ (Hybrid Automatic Repeat and request) technology and block interleavers, LDPC codes demonstrate robust and stable performance in various channel environments and are fully fulfilling their roles in 5G NR data channels.

[0025] Of course, the excellent strengths of 5G NR LDPC codes, such as superior performance, low decoding complexity, and low latency, can be achieved through highly sophisticated code design. Code design refers to the sequential design of the base graph (or base matrix) and the parity check matrix. LDPC code design is a complex process that considers various factors together, ranging from the low-density matrix of the most basic LDPC parity check matrix to the weight distribution, minimum distance between codewords, minimum cycle length (girth), and EMD (extrinsic message degree), which are key characteristics of the Tanner graph, another representation of PCM.

[0026] Depending on the length or code rate of the data to be transmitted, a parity check matrix is ​​constructed based on one of two base graphs (BG1, BG2), and encoding is performed at the transmitter and decoding at the receiver. In a transmission environment where the information length is relatively long and the code rate is high, the parity check matrix is ​​determined based on BG1, and in the opposite case, the parity check matrix is ​​determined based on BG2, each having strengths in error rate performance in the respective environment. However, assuming the same code parameter environment, there is a difference in the level of parallelism because the number of blocks that can be processed at once by the receiver's decoder can differ by up to twice compared to BG1 in the case of BG2. When considering this, if error rate performance is not taken into account, there is an advantage in that BG2 can have a relatively higher throughput.

[0027] Figure 1 is a diagram illustrating a systematic LDPC codeword structure.

[0028] According to FIG. 1, a device performing LDPC encoding receives an information word consisting of K bits or symbols as input, performs encoding to generate a codeword consisting of N bits or symbols. For the convenience of the following explanation, it is assumed that an information word containing K bits is received as input and a codeword consisting of N bits is generated. That is, an information word consisting of K input bits If you encode it, the codeword is generated. That is, the information word and the codeword are bit sequences composed of multiple bits, and the information word bits and codeword bits refer to the respective bits that constitute the information word and the codeword. Typically, the LDPC encoding bits are = = When an information word is fully contained within a codeword, as in the example, it is called a systematic code. Here, is a parity bit, and the number of parity bits N parity is N parity It can be expressed as = N - K.

[0029] LDPC codes are a type of linear block code and include a process for determining a codeword that satisfies conditions such as Equation 1 below.

[0030] [Mathematical Formula 1]

[0031]

[0032] Here, am.

[0033] In Equation 1, H is the parity check matrix, c is the codeword, c i is the i-th bit of the codeword, N ldpc represents the LDPC codeword length, and represents the i-th column of the parity check matrix (H).

[0034] The parity check matrix H is N, which is equal to the number of bits in the LDPC codeword. ldpc It consists of columns. Mathematical Equation 1 is the i-th column of the parity check matrix ( ) and the i-th codeword bit c i Since it means that the sum of the products becomes '0', the i-th column ( ) is the i-th codeword bit c i It means that it is related to.

[0035] Figure 2 is a diagram illustrating the graph representation method of LDPC codes.

[0036] Referring to Fig. 2, we will explain the method of graphing the LDPC code.

[0037] Figure 2 is a diagram showing an example of a parity check matrix H1 of an LDPC code consisting of 4 rows and 8 columns, and a Tanner graph of it. Referring to Figure 2, since the parity check matrix H1 has 8 columns, it generates a codeword of length 8, and the code generated through H1 represents an LDPC code, and each column corresponds to 8 encoded bits.

[0038] Referring to FIG. 2, the Tanner graph of an LDPC code encoded and decoded based on the parity check matrix H1 consists of eight variable nodes, namely x0 (202), x1 (204), x2 (206), x3 (208), x4 (210), x5 (212), x6 (214), and x7 (216), and four check nodes (218, 220, 222, 224). Here, the i-th column and j-th row of the LDPC code's parity check matrix H1 correspond to the variable nodes x i and correspond to the j-th check node. Furthermore, the meaning of the value of 1 at the point where the i-th column and j-th row of the LDPC code parity check matrix H1 intersect—that is, the non-zero value—is the variable node x on the Tanner graph as shown in Fig. 2. i This means that there exists an edge connecting the j-th inspection node.

[0039] In the Tanner graph of an LDPC code, the degree of a variable node and a check node represents the number of line segments connected to each node, which is equivalent to the number of non-zero entries in the column or row corresponding to the node in the parity check matrix of the LDPC code. For example, in FIG. 2, the degrees of the variable nodes x1 (202), x2 (204), x3 (206), x4 (208), x5 (210), x6 (212), x7 (214), and x8 (216) are 4, 3, 3, 3, 2, 2, 2, 2, respectively, and the degrees of the check nodes (218, 220, 222, 224) are 6, 5, 5, 5, respectively. In addition, the number of non-zero elements in each column of the parity check matrix H1 of Fig. 2 corresponding to the variable nodes of Fig. 2 corresponds in order to the degrees of the aforementioned variable nodes, 4, 3, 3, 3, 2, 2, 2, 2, and the number of non-zero elements in each row of the parity check matrix H1 of Fig. 2 corresponding to the check nodes of Fig. 2 corresponds in order to the degrees of the aforementioned check nodes, 6, 5, 5, 5. For this reason, the degree of each variable node is also called the column degree or column weight, and the degree of the check node is also called the row degree or row weight.

[0040] LDPC encoded codeword bits can be decoded based on an iterative decoding algorithm based on a sum-product algorithm on the bipartite graph listed in FIG. 2. Here, the sum-product algorithm is a type of message passing algorithm, and a message passing algorithm represents an algorithm that exchanges messages through edges on a bipartite graph and calculates and updates output messages from messages input to variable nodes or check nodes.

[0041] Here, the value of the i-th code bit can be determined based on the message of the i-th variable node. Both hard decision and soft decision methods are possible for determining the value of the i-th code bit. Therefore, c, which is the i-th bit of the LDPC codeword i The performance of corresponds to the performance of the i-th variable node of the Tanner graph, which can be determined by the position and number of 1s in the i-th column of the parity check matrix. In other words, N of the codeword ldpc The performance of codeword bits can be determined by the position and number of 1s in the parity check matrix, which means that the performance of an LDPC code is significantly influenced by the parity check matrix. Therefore, to design an LDPC code with excellent performance, a method for designing a good parity check matrix is ​​required.

[0042] For ease of implementation, quasi-cyclic LDPC codes (or QC-LDPC codes, hereinafter referred to as QC-LDPC codes) are typically used for parity check matrices in communication and broadcasting systems. Depending on the communication and broadcasting system, there are cases where parity check matrices are used that are not completely quasi-cyclic but have a form similar to a quasi-cyclic structure. Although such LDPC codes may not be strictly classified as QC-LDPC codes algebraically, they are sometimes classified as QC-LDPC codes for convenience.

[0043] For ease of implementation, quasi-cyclic LDPC codes (or QC-LDPC codes, hereinafter referred to as QC-LDPC codes) are typically used for parity check matrices in communication and broadcasting systems. Depending on the communication and broadcasting system, there are cases where parity check matrices are used that are not completely quasi-cyclic but have a form similar to a quasi-cyclic structure. Although such LDPC codes may not be strictly classified as QC-LDPC codes algebraically, they are sometimes classified as QC-LDPC codes for convenience.

[0044] Conventional QC-LDPC codes are characterized by having a parity check matrix composed of zero matrices or circular permutation matrices that take the form of small square matrices. Here, a permutation matrix refers to a matrix in which each row or column contains only one 1 and all other elements are 0. Additionally, a circular permutation matrix refers to a matrix obtained by cyclically shifting each element of the identity matrix to the right or left. Generally, the identity matrix itself is also included in the circular permutation matrix, as it is considered to have cyclically shifted each element of the identity matrix zero times. Therefore, while the term "circular permutation matrix" fundamentally includes the identity matrix, for the sake of convenience in explanation, the identity matrix and the circular permutation matrix that is not the identity matrix may be distinguished.

[0045] Below, the QC-LDPC code is explained in detail.

[0046] First, as in mathematical equation 2-1 A cyclic permutation matrix of size Defines. Here represents the entry of the i-th row and j-th column of the matrix P mentioned above. )

[0047] [Mathematical Formula 2-1]

[0048]

[0049] For the permutation matrix P defined as above (0 ≤ z < Z) is It is a cyclic permutation matrix obtained by circularly shifting each element of an identity matrix of size z to the right. A cyclic permutation matrix can also be defined as in [Equation 2-2], in which case go It is a cyclic permutation matrix in which each element of the identity matrix of size z is cyclically shifted to the left:

[0050] [Mathematical Formula 2-2]

[0051]

[0052] In this disclosure, for convenience, various embodiments are described using a cyclic permutation matrix defined based on [Equation 2-1], but since the cyclic permutation matrices defined in [Equation 2-1] and [Equation 2-2] have the same basic algebraic properties as they differ only in their notation, a cyclic permutation matrix defined based on Equation 2-2 may be used in the embodiments of this disclosure, or various types of cyclic permutation matrices with the same algebraic properties may be used.

[0053] The parity check matrix H of the simplest QC-LDPC code can be expressed in the form of the following mathematical equation 3.

[0054] [Mathematical Formula 3]

[0055]

[0056] For convenience second If defined as a 0-matrix of size , each exponent of the cyclic permutation matrix or 0-matrix in the above Equation 3 It takes one of the values ​​{-1, 0, 1, 2, ..., Z-1}. The identity matrix is Or it can be expressed as I, and the 0-matrix is or It can be expressed as. In addition, the parity check matrix H of the above mathematical formula 3 has a column block A row block Since there are [number], the size of the above parity check matrix H is am.

[0057] If the parity check matrix of the above mathematical formula 3 has a maximum rank (full rank, or full rank), the length of the information word bit of the QC-LDPC code corresponding to the parity check matrix is It is. For convenience, corresponding to the information word bit The number of column blocks is called an information word column block, and the number of information word bits is , corresponding to the remaining parity bits A block of columns can be called a parity column block. In this case, the number of parity bits is is. For reference, if the parity check matrix of the above mathematical formula 3 does not have a maximum rank, the above information word bit is Larger than, the number of information word bits For a larger value, the number of parity bits It has a smaller value.

[0058] Typically, obtained by replacing each cyclic permutation matrix and 0-matrix in the parity check matrix of the above Equation 3 with 1 and 0, respectively A binary matrix of size M is called the mother matrix, base matrix, or base graph of the parity check matrix H, and M(H) or It is expressed as such. In addition, by selecting the indices of each cyclic permutation matrix or zero-matrix, the result obtained as in Equation 4 An integer matrix of size exponent matrix of parity check matrix H It is called [this].

[0059] [Mathematical Formula 4]

[0060]

[0061] Of course, the names of these matrices are merely examples, and the exponential matrix V(H) can be referred to by other names. For instance, since the exponent of each cyclic permutation matrix corresponds to a value that cyclically shifts the identity matrix as in [Equation 2-1] or [Equation 2-2], each exponent may be called a shift value or circular shift value, and V(H) may be called a circular shift value matrix or shift value matrix. In general, a parity check matrix can be determined or identified when a Z value corresponding to the size of the exponential matrix or shift value matrix and the cyclic permutation matrix or zero matrix is ​​given. For this reason, according to the mathematical definition, the parity check matrix refers to a binary matrix H satisfying the conditions of Equation 1, but in some cases, for convenience, the exponential matrix or shift value matrix may be named the parity check matrix.

[0062] Since a single integer included in the exponential matrix or the shift value matrix corresponds to a cyclic permutation matrix in the parity check matrix, the exponential matrix may be expressed as a sequence of integers for convenience. In general, the parity check matrix can be expressed not only as an exponential matrix but also as various sequences capable of expressing algebraically identical characteristics. In this disclosure, for convenience, the parity check matrix is ​​expressed as an exponential matrix or a sequence indicating the position of 1 within the parity check matrix; however, since there are various sequence notations capable of distinguishing the position of 1 or 0 included in the parity check matrix, it may be expressed in the form of various sequences or matrices that exhibit algebraically identical effects, not limited to the method expressed in this specification. To distinguish the sequence from other sequences, it may be referred to in various ways, such as an LDPC sequence, an LDPC code sequence, an LDPC sequence, a parity check matrix sequence, or a (cyclic) shift value sequence.

[0063] In addition, while LDPC encoding and decoding can be performed by directly generating a parity check matrix in the transmitting and receiving device, depending on the implementation characteristics, LDPC encoding and decoding can also be performed based on an exponential matrix, a shift value matrix, or a sequence that produces the same algebraically as the parity check matrix. Therefore, although encoding and decoding using a parity check matrix are described in this disclosure for convenience, actual transmitting and receiving devices can implement encoding and decoding through various methods that can obtain the same effect as the parity check matrix.

[0064] For reference, the effect of being algebraically identical means that for two or more different representations, it is logically or mathematically possible to explain or transform them to be perfectly identical to one another. Particularly in the case of codes that can be defined by matrices, such as LDPC codes, this may mean that algebraic values ​​defined by the matrix—such as minimum distance, rank, or cycle characteristics on a Tanner graph—are identical, or that the basic structure or operation during the encoding / decoding process is identical. For example, if identical matrices are obtained through appropriate column and row permutations, the two matrices can be considered algebraically identical from a code perspective. Furthermore, various transposes that do not alter the actual characteristics of the code can also provide the effect of being algebraically identical.

[0065] The following describes how to perform 5G NR LDPC encoding. The specific process is as follows.

[0066] FIG. 3 is a diagram illustrating a method for performing LDPC encoding according to the present disclosure.

[0067] In step S310, the transmitter determines the transport block size (TBS) or the size of the input sequence A, which is the length of the information to be transmitted, through a series of processes (refer to 3GPP standard document TS38.212 for the specific process).

[0068] Then, A is determined and one of base graphs BG1 or BG2 is determined according to a predetermined code rate R, and each BG has a different max CBS value. In step S320, the transmitter determines whether the TBS is greater than, less than, or equal to the max CBS (max code block size) defined for the BG.

[0069] If TBS is greater than max CBS, the transmitter may determine the CBS by segmenting the transmission block in step S330. If TBS is less than or equal to max CBS, the transmitter skips the segmentation operation and determines the TBS as the CBS (or the transmitter determines the CBS by adding a CRC to the TBS).

[0070] In step S340, the transmitter determines the lifting size (Z) value to be applied to the LDPC encoding based on the CBS.

[0071] Then, in step S350, the transmitter determines a parity check matrix or sequence based on the TBS or CBS or lifting size (Z) value. Alternatively, the transmitter may determine an LDPC exponential matrix or sequence that has the same effect as the parity check matrix algebraically. Additionally, the parity check matrix may be determined based on a base matrix (BG).

[0072] And, in step S360, the transmitter performs LDPC encoding based on a parity check matrix or sequence. Alternatively, the transmitter may perform LDPC encoding based on an exponential matrix or sequence in step S360. Additionally, the transmitter may perform LDPC encoding based on a lifting size and an exponential matrix or sequence in step S360.

[0073] For reference, the above S350 step may, in some cases, include a process of transforming the determined LDPC exponential matrix or sequence based on the determined lifting size. It is obvious that the LDPC exponential matrix or sequence or parity check matrix for LDPC encoding can be determined in various ways based on TBS or CBS depending on the system. For example, it is possible for the transmitter to first determine the base matrix through TBS and then determine the LDPC exponential matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods may also be applied.

[0074] FIG. 4 is a diagram illustrating a method for performing LDPC decoding according to the present disclosure.

[0075] If TBS is determined in step S410, the receiver determines in step S420 whether TBS is greater than, less than, or equal to the max CBS defined for BG.

[0076] If TBS is greater than max CBS, the receiver determines the size of the segmented CBS in step S430. If TBS is determined to be less than or equal to max CBS, TBS is determined to be equal to CBS (or CRC is added to TBS to determine CBS).

[0077] The receiver determines the lifting size (Z) value to be applied to LDPC decoding in step S440.

[0078] And, in step S450, the receiver determines a parity check matrix or sequence based on the TBS or CBS or lifting size (Z) value. Alternatively, the transmitter may determine an exponential matrix or sequence that has the same effect as the parity check matrix algebraically. Additionally, the parity check matrix may be determined based on a base matrix (BG).

[0079] And the receiver may perform LDPC decoding based on a parity check matrix or sequence in step S460. Alternatively, the receiver may perform LDPC decoding using an exponential matrix or sequence in step S460.

[0080] For reference, the above S450 step may, in some cases, include a process of transforming the determined LDPC exponential matrix or sequence based on the determined lifting size. It is obvious that the LDPC exponential matrix or sequence or parity check matrix for LDPC decoding can be determined in various ways based on TBS or CBS depending on the system. For example, it is possible for the receiver to first determine the base matrix through TBS and then determine the LDPC exponential matrix or sequence parity check matrix based on the determined base matrix and CBS, and various other methods may also be applied.

[0081] According to the 3GPP standard document TS 38.212, the TBS or the size of the input sequence A is determined through a series of processes, and the coding rate R can be determined based on the determination of the modulation and coding scheme (MCS). Therefore, BG1 or BG2 can be determined based on the coding rate and the length of the input sequence. Specifically, BG1 or BG2 can be determined according to the coding rate and the length of the input sequence based on Table 1 below. Referring to Table 1 below, In the case of, and In the case of, or In this case, BG2 may be selected, and in other cases, BG1 may be selected.

[0082] [Table 1]

[0083]

[0084] Below, a specific method for determining the parity check matrix is ​​explained.

[0085] First, the following assumes a situation where the number of code blocks (CB) is 1. That is, in steps S320 and S420 of FIGS. 2 and 3, it assumes a situation where TBS is less than or equal to max CBS.

[0086] The BG is determined by referring to Table 1, and in order to define the parity check matrix based on the said BG, the set index, which is a parameter of the quasi-cyclic structure that is the structural core of the 5G NR LDPC code and the lifting size Z (S340 or S440) is determined by the following method.

[0087] First, let B be the length of information considering the junction length L of the CB cyclic redundancy code (CB-CRC) code in TB, so that B can be expressed as B=A+L. As described above, A can mean TBS.

[0088] 1. Length parameter Decide

[0089] A. In the case of BG1,

[0090] B. In the case of BG2,

[0091] i. , if

[0092] ii. , if

[0093] iii. , if

[0094] iv. if

[0095] determined All possible lifting size candidates based on Z middle The smallest Z satisfying It is determined as follows. K' can be calculated as (B+C*L) / C, where C represents the number of code blocks and L represents the length of the CRC. Additionally, the index of the lifting set to which Z belongs is .... Refer to Table 2 below for the candidate lifting sizes and index sets.

[0096] [Table 2] Sets of LDPC lifting size Z

[0097]

[0098] Lifting set index determined according to the above process A parity check matrix (PCM) is defined based on the lifting size Z graph and the base matrix (or base graph, BG), which can be found in Table 3 (3GPP TS 38.212 Table 5.3.2-2) and Table 4 (3GPP TS 38.212 Table 5.3.2-3) below.

[0099] [Table 3]

[0100]

[0101]

[0102]

[0103]

[0104] [Table 4]

[0105]

[0106]

[0107]

[0108] Specifically, the structure of the parity check matrix is ​​explained below.

[0109] FIG. 5 is a drawing illustrating an example of a basic matrix having a size of 3*4 according to the present disclosure.

[0110] In the standard document, the parity check matrix is ​​defined as a matrix of size 46*68 or 42*52, but in this figure, a 3*4 matrix is ​​used as an example. Given a basic matrix (or BG) of size 3*4 as in Figure 5, the value to be inserted at the position corresponding to the non-zero value 1 of the BG as in Tables 3 and 4 is assumed as in Table 5 below.

[0111] [Table 5]

[0112]

[0113] That is, the matrix of Fig. 5 can be defined by referring to Table 5, and an element or element 1 of the matrix of Fig. 5 means that a specific value (exponent value or circularly lifting size) Vi,j is substituted (or replaced) at the corresponding position to form a parity check matrix. Therefore, the exponent matrix determined by referring to the table is as shown in Fig. 6.

[0114] Figure 6 is a diagram illustrating an exponential matrix according to the basic matrix of Figure 5.

[0115] Referring to Fig. 6, the 1 value located in the matrix of Fig. 5 is V in Table 5. i,j Illustrate the matrix with the values ​​substituted. In the matrix of Fig. 6, the exponent value or the element value of the matrix V i,j is a value indicating how many times the Z×Z identity matrix is ​​circularly lifted at that position.

[0116] Figure 7 is a diagram illustrating a parity check matrix according to the exponential matrix of Figure 6.

[0117] Referring to Fig. 7, a parity check matrix is ​​shown assuming the Z value is 5.

[0118] V 1,1 =0 is replaced with the identity matrix that has been cyclically lifted 0 times (i.e., the identity matrix of size 5*5) (701) and V 2,3 =4 can be replaced with the identity matrix (702) in which cyclic lifting has been performed 4 times. Additionally, empty parts of the base matrix and exponential matrix can be filled (or replaced) with zero matrices.

[0119] Here, the NR LDPC code selects either BG1 or BG2 according to the rules in Table 1 and generates (or determines) the parity check matrix required for the encoding and decoding processes through the series of steps described above. However, since the maximum lifting size is determined to be 384 in the standard specification, the maximum size of a single code block, when considering the CRC length, is in the case of BG1 =8448, in the case of BG2 It is limited to =3840. Due to this, K cb When information bits of a length exceeding 1 must be transmitted, the number of code blocks C becomes a positive integer other than 1, and the transport block is composed of multiple code blocks. In this case, the length of the information code assigned to each code block is set to the value obtained by dividing the information bits to be transmitted by C.

[0120] Meanwhile, the Transport Block Size (TBS) calculation formula of the 5G standard document TS 38.214 ( Referring to the case where >3824, it is as shown in Table 6 below.

[0121] [Table 6]

[0122]

[0123] Finally , We can obtain the formula. Additionally, if we calculate the maximum transmission block size that can be transmitted under the current standard based on the conditions below, It can be calculated as.

[0124]

[0125] In this case, the length of each code block can be calculated as K=8416, and the total number of code blocks can be calculated as C=296.

[0126] like this When transmitting larger information bits, the length of the encoded codeword may inevitably be limited, and many of the advantages that can be expected from a longer codeword must be sacrificed. For example, as the length of the codeword increases, the minimum distance characteristics and the minimum size of the cycle of the corresponding LDPC code cannot be increased further, resulting in a degradation of error rate recovery performance in short lengths compared to long lengths. Additionally, from the perspective of the decoder, the maximum lifting size becomes the unit of throughput that can be processed at once. However, since the maximum lifting size is limited to a relatively small value (384), there may be a loss in unit throughput compared to when a relatively larger value is set. Furthermore, when the amount of information bits to be transmitted is very large, a single transmission block consists of tens to hundreds of code blocks, which causes performance degradation, processing speed degradation, and air latency.

[0127] FIG. 8 is a diagram illustrating performance when the number of code blocks increases according to the present disclosure.

[0128] CBLER (810) in FIG. 8 represents the ratio of code blocks with errors among all code blocks, and TBLER (820, 830, 840) represents the ratio of transmission blocks with errors among all transmission blocks. In this case, if an error occurs in one code block within a transmission block, it can be determined that the transmission block is an error.

[0129] Referring to Fig. 8, the same BLER (e.g., 10 -1 The SNR value required to satisfy ) can be checked, and through this, the performance of the system according to the number of code blocks can be checked. Specifically, as the number of code blocks increases, the SNR value required to satisfy the same BLER increases, and the performance of the system may deteriorate.

[0130] Conversely, as the number of code blocks decreases, the SNR value required to satisfy the same BLER decreases, which can lead to an improvement in system performance. Therefore, as described above, if the maximum lifting size is set to a relatively small value, the number of code blocks increases for long information bits (or input bits), which can lead to a degradation in system performance.

[0131] FIG. 9 is a diagram illustrating the processing delay occurring in an existing system according to the present disclosure.

[0132] FIG. 9 assumes a situation where 100 code blocks are processed when there are 10 cores that can be supported to perform decoding (10-core chipset). A 10-core chipset may refer to a device having 10 independent processing units (cores) within a single processor chip. Furthermore, although a device having 10 cores is described as an example in this disclosure, it is obvious to a person skilled in the art that there is no limit to the number of cores.

[0133] Assuming a chipset with 10 cores, the 10 cores can simultaneously process 10 code blocks in parallel through their respective parallel processing. When the unit of time for a single core to process a code block is called a processing time unit (PTU), 10 PTUs must be consumed to process 100 code blocks. However, if the number of code blocks is reduced, the time required to process the code blocks can be reduced, and processing latency can be reduced.

[0134] Therefore, in this disclosure, in order to solve the various problems mentioned above, the existing NR LDPC code established Value and maximum lifting size We provide a method to compensate for performance degradation by extending the maximum size of a single code block of the LDPC code provided by the existing NR. At the same time, as the maximum lifting size increases, we enable the use of processing speeds that are the same or faster by repurposing the existing system and expanding its parallelization properties. In other words, we propose a method for repurposing the existing system that can improve error rate performance without additional delay or computational complexity.

[0135] FIG. 10 is a drawing illustrating a method for increasing the size of the maximum symbol block and the maximum lifting size according to one embodiment of the present disclosure.

[0136] Referring to Fig. 10, the existing maximum sign block size By increasing by a factor of 2 or by any integer multiple (or it can be increased by any value), the maximum lifting size accordingly It can be increased. The relationship between these two values ​​is the size of BG1's information block. It is closely related to, and their relationship It can be expressed as such. Also, in the present disclosure, K cb,BG1 Eun K max,BG1or the size of the maximum code block, or K cb It can be used with the same meaning as . In a situation where it is predetermined and Since they are in a proportional relationship, it can be seen that they increase together. For example, when the upsizing factor is set to 2 times, 4 times, 8 times, or any integer multiple, it can be seen that the two values ​​can increase as shown in Fig. 10.

[0137] Referring to Fig. 10, the maximum sign block size (K max,BG1 ) and maximum lifting size (Z max Since the values ​​of ) are in a proportional relationship, they increase together, and the benefits obtained as each increases can be taken complementarily. That is, K max,BG1 As this increases, the length that can be supported in a specific code block increases, and error rate performance can be improved compared to the existing system. Additionally, the total number of code blocks can be reduced; as the code block length increases and the number of blocks decreases, the retransmission probability and the number of retransmission blocks also decrease, thereby mitigating delay and complexity. Furthermore, as the maximum lifting size increases, the throughput that can be processed at once increases; consequently, the time required to process code blocks longer than before is offset, preventing additional delay or complexity from occurring.

[0138] FIG. 11 is a drawing illustrating an example of a parity check matrix as the size of the maximum code block and the maximum lifting size increase according to one embodiment of the present disclosure.

[0139] The identity matrix of Z*Z can be circularly shifted according to the exponent values ​​or element values ​​within the exponent matrix or parity check matrix of Fig. 11, and the circularly shifted matrix (hereinafter, circularly shifted identity matrix) can be substituted for the exponent values ​​or element values ​​of the matrix to define the parity check matrix.

[0140] Meanwhile, as described above, when the maximum lifting size increases, the size of the circularly shifted identity matrix that replaces the parity check matrix may increase, and accordingly, the size of the parity check matrix may increase. For example, when the maximum lifting size increases by a factor of 2, a circularly shifted identity matrix of size 2Z*2Z may replace the exponent matrix or the exponent values ​​or element values ​​within the parity check matrix, and the size of the entire parity check matrix may increase by a factor of 2.

[0141] FIG. 12A is a drawing illustrating an example for increasing the maximum lifting size according to one embodiment of the present disclosure.

[0142] Referring to Fig. 12A, the maximum lifting size can be doubled to support long code blocks. Accordingly, the maximum value of the lifting size corresponding to each set index can also be doubled. At this time, the maximum value of the lifting size corresponding to all set indices may be doubled, but only the maximum value of the lifting size corresponding to a specific set index may be doubled.

[0143] As the maximum lifting size increases, the maximum lifting size can become 768, and Set indices 0 through 7 may additionally include 512, 768, 640, 448, 576, 704, 416, and 480, respectively. Alternatively, some of Set indices 0 through 7 may maintain the existing set of lifting sizes and have no additional lifting sizes added. That is, appropriate lifting size values ​​can be added or subtracted for each set as needed.

[0144] Additionally, while the above example illustrates a method to double the maximum lifting size in an existing system, the embodiments of the present disclosure are not limited thereto, and a number greater than 768 may be the maximum lifting size. For example, referring to table (1201), since the step size of the last row (1202) is 64 (i.e., the increase is 64), one of 832, 896, 960, or 1024, which are numbers greater than 768 at the same step size, may be the maximum lifting size. Alternatively, any one of the numbers that increase according to each step size, extending up to the next step size, may be the maximum lifting size. In this case, the step size is 2 n-1 It can be set to, and n can be a positive integer. Also, since there are a total of 8 sets, the step size can be increased every 8.

[0145] FIG. 12B is a drawing illustrating an example for increasing the maximum lifting size according to one embodiment of the present disclosure.

[0146] Referring to Fig. 12B, the maximum lifting size can be increased fourfold to support long code blocks. Accordingly, the maximum value of the lifting size corresponding to each set index can also be increased fourfold, and each set index may additionally include values ​​that are increased twofold and fourfold from the existing maximum value. At this time, the maximum value of the lifting size corresponding to all set indices may be increased fourfold, but only the maximum value of the lifting size corresponding to a specific set index may be increased fourfold.

[0147] As the maximum lifting size increases, the maximum lifting size may become 1536, and Set index 0 to 7 each include 512, 768, 640, 448, 576, 704, 416, and 480, and Set index 0 to 7 each may additionally include 1024, 1536, 1280, 896, 1152, 1408, 832, and 960. Alternatively, some of Set index 0 to 7 may maintain the existing set of lifting sizes and not include any additional lifting sizes, or may include the set of lifting sizes disclosed in FIG. 12A. That is, appropriate lifting size values ​​may be added or subtracted for each set as needed.

[0148] Additionally, while the above example illustrates a method to increase the maximum lifting size by four times in an existing system, the embodiments of the present disclosure are not limited thereto, and a number greater than 1536 may be the maximum lifting size. For example, referring to table (1203), since the step size of the last row (1204) is 128, one of 1664, 1792, 1920, or 2048, which are numbers greater than 1536 at the same step size, may be the maximum lifting size. Alternatively, any one of the numbers that increase according to each step size, extending up to the next step size, may be the maximum lifting size. In this case, the step size is 2 n-1 It can be set to, and n can be a positive integer. Also, since there are a total of 8 sets, the step size can be increased every 8.

[0149] FIG. 12C is a drawing illustrating an example for increasing the maximum lifting size according to one embodiment of the present disclosure.

[0150] Referring to Fig. 12C, a method of adjusting the step size can be used as another way to increase the maximum lifting size. Figs. 12A and 12B describe a method of increasing the maximum lifting size by 2 times or 4 times by multiplying the maximum lifting size of 384 by an upsizing factor of 2 and 4, and accordingly, a method of including at least one of the lifting sizes that are increased by 2 times or 4 times the maximum lifting size included in each lifting size set.

[0151] Meanwhile, Fig. 12C proposes a method to determine the maximum value of the total lifting size by multiplying the maximum lifting size of each lifting size set by an upsizing factor.

[0152] Accordingly, the maximum value of the total lifting size can be determined by multiplying the maximum lifting size of any one of Set index 0 to 7 by an upsizing factor, and in this disclosure, an example is described in which 1024, obtained by multiplying the maximum value of Set index 0, 256, by an upsizing factor of 4, is set as the maximum value of the total lifting size.

[0153] For example, referring to Fig. 12B, it can be seen that the maximum value for a step size of 64 is determined to be 1024. Therefore, values ​​up to a step size of 64 can be used as lifting sizes. In this case, the lifting sizes included in each set index may be as follows.

[0154]

[0155] Accordingly, lifting sizes can be included in each lifting set by adjusting the step size as shown in FIG. 12C. Specifically, referring to FIG. 12C, a row (1206) can be added compared to FIG. 12B, and the increase range of each lifting size within the row (1206) is 64, and the increase range of the first value of the row (1206) is 32. Through this method, lifting sizes that do not overlap with FIG. 12B can be included, and there is an advantage in that a wider variety of lifting sizes can be supported.

[0156] Meanwhile, when a lifting size is set as in FIG. 12C, the lifting size table needs to be redefined. That is, there is a problem that the lifting size included in row (1206) cannot be included in the set index of the existing lifting size table. Therefore, the present disclosure proposes a method for defining a new set index. That is, in the present invention, a new set index 8 can be defined, and the set index can include 544,608,672,736,800,864,928,992 included in row (1206).

[0157]

[0158] Meanwhile, as described above, if set index 8 is newly defined, a method for determining the parity check matrix accordingly may be required. For the parity check matrix for the lifting size corresponding to the above set index 8, a parity check matrix corresponding to any one of set index 0 to set index 7 (or a parity check matrix in which any one of set index 0 to set index 7 is modified by a predefined method) may be used. Alternatively, for each lifting value, a parity check matrix corresponding to any one of set index 0 to set index 7 (or a parity check matrix in which any one of set index 0 to set index 7 is modified by a predefined method) may be used. Alternatively, a parity check matrix corresponding to set index 8 may be defined.

[0159] The following explains how to set the exponential value when increasing the maximum value of the lifting size.

[0160] upsizing factor (or expansion factor) When defined as such, the maximum lifting size is ( It can be defined by a formula such as ). In this case, represents the maximum lifting size (=384) in the existing NR, and It can refer to the maximum lifting size increased according to the upsizing factor. Newly defined maximum lifting size Is Not only arbitrary integer multiples of , but also each set index The set maximum lifting size defined in It can also be defined as an integer multiple of, and ( It can be calculated as ). Here The above formula when is 1 It becomes the same as.

[0161] This is the new maximum lifting size If defined, refer to the above for the maximum lifting size for each set index can be newly defined. This is the value of the maximum lifting size ( Maximum lifting size for each set index according to It may be decided whether it will be newly defined.

[0162] Meanwhile, to determine the parity check matrix, the exponent matrix or the exponent value of the parity check matrix or the matrix element value is used in a modulo operation of the lifting size; however, if the maximum lifting size increases, the corresponding exponent value needs to be redefined.

[0163] Accordingly, the present disclosure proposes a method for determining the exponent value as shown in Equation 5 below.

[0164] [Mathematical Formula 5]

[0165]

[0166] Referring to the above mathematical formula 5, indicates the exponent value of the existing system or the element value of the matrix, where i is the row index, j is the column index, and i LS indicates the set index. Also, indicates the maximum value of Z within the set index in the existing system, and represents an expansion factor that corresponds one-to-one with each exponent value for each set index. Also, represents an indicator function and can correspond one-to-one with each set index and each exponent value, and can be set to 0 or 1 as needed. Through this method, encoding and decoding can be performed using a parity check matrix defined in an existing system. In this case, the existing system may refer to a 5G communication system, and can mean an exponential value in a communication system after 5G (e.g., a 6G communication system).

[0167] In this case, the reason the newly defined exponent value is determined based on Equation 5 is that if an integer multiple of the maximum lifting size of each set is added to the existing exponent value, the lifting size Z determined in the actual system is equal to the existing maximum lifting size for each set If it is smaller, the existing exponential value can be utilized through the modulo operation, allowing the existing NR system to be reused, and if Z is the existing maximum lifting size for each set If it is larger, there is an advantage in that various options can be utilized by using a newly defined exponent value. Therefore, the newly defined exponent value can be determined as a strategy to maximize the performance of the LDPC code for various options for each candidate. This can be expressed by the following formula.

[0168] [Mathematical Formula 6]

[0169]

[0170] FIG. 13 is a drawing illustrating that the maximum lifting size is increased according to one embodiment of the present disclosure, thereby increasing the throughput of the decoder.

[0171] Referring to FIG. 13, according to Legacy NR, the structure utilizes a limited lifting size, and since Z rows can be processed in a single core, the throughput is relatively limited. On the other hand, according to the present invention, if the maximum lifting size is increased, more rows can be processed.

[0172] For example, if the maximum lifting size is doubled, the core can process 2Z rows at a time. In this case, more data can be processed by using an upgraded CNU (core node unit) to process 2Z rows.

[0173] Alternatively, faster processing speeds than before can be achieved by maximizing the parallel processing structure through the deployment of multiple CNUs for a single layer. Therefore, even if the lifting size increases, processing is divided among multiple CNUs, so the overall system throughput per hour can be significantly improved while maintaining the same complexity.

[0174] FIG. 14 is a diagram showing that, according to one embodiment of the present disclosure, the maximum lifting size is increased so that the processing delay time of the decoder is shortened.

[0175] FIG. 9 illustrates a situation in which 100 code blocks are processed using 10 cores. Meanwhile, the present disclosure illustrates a situation in which only 50 code blocks are processed as the maximum lifting size increases (for example, when the maximum lifting size is doubled).

[0176] In such a case, as shown in Fig. 9, when processing 10 code blocks in parallel using 10 cores, a total processing time of 5 PTU may be required. Therefore, there is an advantage in that the processing delay time can be reduced by half compared to the case where 10 PTU processing time is required. That is, when the maximum lifting size increases, the number of code blocks determined for the same length of input bits decreases, so the processing delay time can be reduced.

[0177] FIG. 15 is a drawing illustrating the operation of a transmitter according to one embodiment of the present disclosure.

[0178] Referring to Fig. 15, the transmitter can determine the TBS at step 1510. At this time, the specific method for determining the TBS can refer to the method for determining the transmission block size in TS 38.214.

[0179] Specifically, the transmitter can determine N'info. The method for determining N'info is the same as described in Table 6 and is therefore omitted below. However, in the present disclosure, the method for determining TBS may change as the maximum lifting size increases. Specifically, Table 7 below relates to the method for determining TBS in legacy NR, and 8424 may be used to determine the number of code blocks C. In this case, 8424 refers to the value obtained by subtracting the CR length of 24 from the maximum value of Kcb, which is 8448.

[0180] [Table 7]

[0181]

[0182] Meanwhile, in the present disclosure, since the maximum value of Kcb may change as the maximum lifting size increases, Equation 7 may be used to determine the number of code blocks C.

[0183] [Mathematical Formula 7]

[0184]

[0185] At this time, is 22* It can be calculated as, It can specify the maximum lifting size.

[0186] And the transmitter can check the basic matrix at step 1520. The basic matrix can be checked based on TBS and the code rate. The specific details are the same as those described above, so they are omitted below.

[0187] The transmitter can determine the lifting size at step 1530. As described above, among the lifting size candidates, the transmitter The smallest Zc satisfying [condition] can be determined as the lifting size. At this time, the present disclosure proposes a method to expand the maximum lifting size, and candidates for the lifting size according to this can be seen in FIG. 12a, FIG. 12b, and FIG. 12c.

[0188] Subsequently, the transmitter can check the parity check matrix based on the base matrix and lifting size at step 1540. As the lifting size increases, the size of the parity check matrix can increase, allowing for the processing of more data.

[0189] And, the transmitter can perform LDPC encoding based on the parity check matrix in step 1550.

[0190] FIG. 16 is a drawing illustrating the operation of a receiver according to one embodiment of the present disclosure.

[0191] Referring to Fig. 16, the receiver can receive a signal at step 1610. The receiver can also check the lifting size at step 1620.

[0192] The above receiver can receive control information via the PDCCH (physical downlink control channel), and the control information may include parameters necessary to determine the TBS. Therefore, the receiver can determine the TBS and verify the lifting size through the method described above. Among the lifting size candidates The smallest Zc satisfying [condition] can be determined as the lifting size. At this time, the present disclosure proposes a method to expand the maximum lifting size, and candidates for the lifting size according to this can be seen in FIG. 12a, FIG. 12b, and FIG. 12c.

[0193] And, the receiver can check the basic matrix at step 1630. The basic matrix can be checked based on TBS and the code rate. Since the specific details are the same as described above, they are omitted below.

[0194] Subsequently, the receiver can check the parity check matrix based on the base matrix and lifting size at step 1640. As the lifting size increases, the size of the parity check matrix can increase, allowing for the processing of more data.

[0195] And, the receiver can LDPC encode the signal based on the parity check matrix in step 1650.

[0196] FIG. 17 is a block diagram of a transmitting device according to one embodiment of the present disclosure.

[0197] Specifically, as shown in FIG. 17, the transmitting device (1700) may include a segmentation unit (1710), a zero padding unit (1720), an LDPC encoding unit (1730), a rate matching unit (1740), a modulation unit (1750), etc. to process variable-length input bits. The rate matching unit (1740) may include an interleaver (1741) and a puncturing / repetition / zero removal unit (1742), etc.

[0198] Here, the component shown in FIG. 17 is a component that performs encoding and modulation for variable-length input bits, which is just one example, and in some cases, some of the components shown in FIG. 17 may be omitted or changed, and other components may be added.

[0199] Meanwhile, the transmitting device (1700) can determine necessary parameters (e.g., input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), the code rate / codeword length of the LDPC code, parameters for interleaving, parameters for repetition and puncturing, etc., and at least one of the modulation method), and can encode the input bits based on the determined parameters and transmit them to the receiving device (1800).

[0200] Given that the number of input bits is variable, if the number of input bits is greater than a preset value, the input bits can be segmented to have a length less than or equal to the preset value. Additionally, each segmented block can correspond to a single LDPC-coded block. However, if the number of input bits is less than or equal to a preset value, the input bits are not segmented and the input bits can correspond to a single LDPC-coded block.

[0201] Meanwhile, the transmitting device (1700) may store various parameters used for encoding, interleaving, and modulation. Here, the parameter used for encoding may include at least one of the code rate of the LDPC code, the codeword length, and information regarding the parity check matrix. Also, the parameter used for interleaving may include information regarding the interleaving rule, and the parameter used for modulation may include information regarding the modulation method. Additionally, information regarding puncturing may include the puncturing length. Additionally, information regarding repetition may include the repetition length. The information regarding the parity check matrix may include the exponential value of the cyclic matrix or values ​​that are algebraically equivalent thereto when using the parity matrix presented in the present disclosure.

[0202] In this case, each component constituting the transmitting device (1700) can perform an operation using these parameters.

[0203] Meanwhile, although not illustrated, the transmitting device (1700) may additionally include a control unit (not illustrated) for controlling the operation of the transmitting device (1700) depending on the case.

[0204] FIG. 18 is a block diagram of a receiving device according to one embodiment of the present disclosure.

[0205] Specifically, as shown in FIG. 18, the receiving device (1800) may include a demodulation unit (1810), a rate dematching unit (1820), an LDPC decoding unit (1830), a zero removal unit (1840), and a desegmentation unit (1850), etc., to process variable-length information. The rate dematching unit (1820) may include an LLR (log likelihood ratio) insertion unit (1822), an LLR combiner (1823), a deinterleaver (1824), etc.

[0206] Here, the component shown in FIG. 18 is a component that performs a function corresponding to the component shown in FIG. 18, and this is merely an example, and in some cases, some may be omitted or changed, and other components may be added.

[0207] The parity check matrix in the present disclosure may be read using memory, provided in advance at a transmitting or receiving device, or generated directly at a transmitting or receiving device. Additionally, the transmitting device may store or generate a sequence or exponential matrix corresponding to the parity check matrix, or a value that is algebraically equivalent thereto, and apply it to encoding. Similarly, the receiving device may store or generate a sequence or exponential matrix corresponding to the parity check matrix, or a value that is algebraically equivalent thereto, and apply it to decoding.

[0208] Below, a detailed explanation of the receiver operation will be provided based on Fig. 18.

[0209] The demodulator (1810) demodulates the signal received from the transmitting device (1700).

[0210] Specifically, the demodulation unit (1810) is a component corresponding to the modulation unit (1750) of the transmitting device (1700), and can demodulate a signal received from the transmitting device (1700) to generate values ​​corresponding to the bits transmitted from the transmitting device (1700).

[0211] To this end, the receiving device (1800) determines parameters required for demodulation and decoding (e.g., input bit length, ModCod (modulation and code rate), parameters for zero padding (or shortening), the code rate / codeword length of the LDPC code, parameters for interleaving, parameters for repetition and puncturing, etc., and at least one of the modulation method), and based on the determined parameters, the demodulation unit (1810) can demodulate the signal received from the transmitting device (1700) according to the mode and perform a decoding process to generate values ​​corresponding to the LDPC codeword bits.

[0212] Meanwhile, the value corresponding to the bits transmitted by the transmitting device (1700) may be an LR (likelihood ratio) value or an LLR (log likelihood ratio) value.

[0213] Specifically, the LR value represents the ratio of the probability that the bit transmitted by the transmitting device (1700) is 0 to the probability that it is 1, and the LLR value can be represented as the value obtained by taking the logarithm of the ratio of the probability that the bit transmitted by the transmitting device (1700) is 0 to the probability that it is 1. Alternatively, the LR or LLR value may be determined based on the probability or the ratio of the probability or the logarithm of the probability and represented as the bit value itself, or it may be represented as a predefined representative value based on the interval to which the probability or the ratio of the probability or the logarithm of the probability belongs. An example of a method for determining a predefined representative value based on the interval to which the probability or the ratio of the probability or the logarithm of the probability belongs is a method that considers quantization. In addition, various other values ​​corresponding to the probability or the ratio of the probability or the logarithm of the probability may also be used.

[0214] In this disclosure, for convenience, operations based on LLR values ​​are shown to explain the operation of the receiving method and device, but are not limited thereto.

[0215] The above demodulation unit (1810) includes a function to perform multiplexing (not shown) on LLR values. Specifically, the multiplexer (not shown) is a component corresponding to the bit demultiplexer (not shown) of the transmitting device (1700) and can perform an operation corresponding to the bit demultiplexer (not shown).

[0216] To this end, the receiving device (1800) may store information about parameters that the transmitting device (1700) used for demultiplexing and block interleaving. Accordingly, the multiplexer (not shown) can perform the demultiplexing and block interleaving operations performed in the bit demultiplexer (not shown) on the LLR value corresponding to the cell word (information representing the received symbol for the LDPC codeword as a vector value) in reverse, thereby multiplexing the LLR value corresponding to the cell word in bit units.

[0217] The rate dematching unit (1820) can additionally insert LLR values ​​into the LLR values ​​output from the demodulation unit (1810). In this case, the rate dematching unit (1820) can insert pre-agreed LLR values ​​between the LLR values ​​output from the demodulation unit (1810).

[0218] Specifically, the rate dematching unit (1820) is a component corresponding to the rate matching unit (1740) of the transmitting device (1700) and can perform operations corresponding to the interleaver (1741), zero removal and puncturing / repetition / zero removal unit (1742).

[0219] First, the rate dematching unit (1820) performs deinterleaving to correspond to the interleaver (1741) of the transmitter. The LLR insertion unit (1822) can insert LLR values ​​corresponding to zero bits at the positions where zero bits were padded in the LDPC codeword at the output values ​​of the deinterleaver (1824). In this case, the LLR values ​​corresponding to the padded zero bits, i.e., the shortened zero bits, can be ∞ or -∞. However, ∞ or -∞ are theoretical values ​​and can actually be the maximum or minimum value of the LLR value used in the receiving device (1800).

[0220] To this end, the receiving device (1800) may store information about the parameters that the transmitting device (1700) used to pad the zero bits. Accordingly, the rate dematching unit (1820) can determine the location where the zero bits were padded in the LDPC codeword and insert an LLR value corresponding to the shortened zero bits at that location.

[0221] Additionally, the LLR insertion unit (1822) of the rate dematching unit (1820) can insert an LLR value corresponding to the punctured bits at the positions of the punctured bits in the LDPC codeword. In this case, the LLR value corresponding to the punctured bits can be 0 or another value determined in advance. Generally, when parity bits of degree 1 are punctured, there is no effect on performance improvement in the LDPC decoding process, so some or all of the corresponding punctured positions may not be used in the LDPC decoding process without LLR insertion. However, in order to increase the efficiency of the LDPC decoding process based on parallel processing, the LLR insertion unit (1822) can insert a predetermined LLR value at the positions corresponding to some or all of the punctured bits of degree 1, regardless of decoding performance improvement.

[0222] To this end, the receiving device (1800) may store information about the parameters used for puncturing in the transmitting device (1700). Accordingly, the LLR insertion unit (1822) may insert a corresponding LLR value (e.g., LLR = 0) at the location where LDPC information bits or parity bits have been punctured. However, this process may be omitted at some locations of the punctured parity bits.

[0223] The LLR combiner (1823) can combine, that is, sum the LLR values ​​output from the LLR insertion unit (1822) and the demodulation unit (1810). Specifically, the LLR combiner (1823) is a component corresponding to the puncturing / repetition / zero removal unit (1742) of the transmitting device (1700) and can perform an operation corresponding to the repetition unit (1742). First, the LLR combiner (1823) can combine the LLR values ​​corresponding to the repeated bits with other LLR values. Here, the other LLR values ​​may be LLR values ​​for the bits that formed the basis for generating the repeated bits in the transmitting device (1700), that is, LDPC information bits or parity bits that were selected as the repetition target.

[0224] That is, as described above, the transmitting device (1700) selects LDPC encoded bits and repeats them between LDPC information bits and LDPC parity bits and transmits them to the receiving device (1800). Accordingly, the LLR values ​​for the LDPC encoded bits may consist of LLR values ​​for the repeated LDPC encoded bits and LLR values ​​for the non-repeated LDPC encoded bits. The LLR combiner (1823) can combine LLR values ​​for the same LDPC encoded bits.

[0225] To this end, the receiving device (1800) may store information about the parameters used for repetition in the transmitting device (1700). Accordingly, the LLR combiner (1823) may determine the LLR value for the repeated LDPC encoded bits and combine it with the LLR value for the LDPC encoded bits that formed the basis of the repetition.

[0226] Additionally, the LLR combiner (1823) can combine an LLR value corresponding to the retransmitted or IR (increment redundancy) bits with another LLR value. Here, the other LLR value may be an LLR value for some or all of the LDPC codeword bits that formed the basis for generating the retransmitted or IR bits in the transmitting device (1700).

[0227] As described above, the transmitting device (1700) can transmit some or all of the codeword bits to the receiving device (1800) when a NACK occurs for HARQ.

[0228] Accordingly, the LLR combiner (1823) can combine the LLR values ​​for bits received via retransmission or IR with the LLR values ​​for LDPC codeword bits received via the previous frame.

[0229] To this end, the receiving device (1800) may store information about the parameters used for retransmission or IR bit generation in the transmitting device (1700). Accordingly, the LLR combiner (1823) may determine the LLR value for the number of retransmission or IR bits and combine it with the LLR value for the LDPC encoded bits that formed the basis for the generation of the retransmission bits.

[0230] The deinterleaver (1824) can deinterleave the LLR values ​​output from the LLR combiner (1823).

[0231] Specifically, the deinterleaver unit (1824) is a component corresponding to the interleaver (1741) of the transmitting device (1700) and can perform an operation corresponding to the interleaver (1741).

[0232] To this end, the receiving device (1800) may store information about the parameters that the transmitting device (1700) used for interleaving. Accordingly, the deinterleaver (1824) can deinterleave the LLR values ​​corresponding to the transmitted LDPC encoded bits by performing the interleaving operation performed in the interleaver (1741) in reverse on the LLR values ​​corresponding to the transmitted LDPC encoded bits.

[0233] The LDPC decoding unit (1830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (1820).

[0234] Specifically, the LDPC decoding unit (1830) is a component corresponding to the LDPC encoding unit (1730) of the transmitting device (1700) and can perform an operation corresponding to the LDPC encoding unit (1730).

[0235] To this end, the receiving device (1800) may store information regarding parameters used to perform LDPC encoding according to the mode in the transmitting device (1700). Accordingly, the LDPC decoding unit (1830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (1820) according to the mode.

[0236] For example, the LDPC decoding unit (1830) can perform LDPC decoding based on the LLR value output from the rate dematching unit (1820) based on an iterative decoding method based on a convolutional algorithm, and output error-corrected bits according to the LDPC decoding. The LDPC decoding unit (1830) performs LDPC decoding on the LDPC codeword based on a parity check matrix or a corresponding exponential matrix or sequence. Additionally, LDPC decoding can be performed using a parity check matrix defined differently according to the code rate (i.e., the code rate of the LDPC code). The LDPC decoding unit (1830) can generate information word bits by performing LDPC decoding through an iterative decoding algorithm by passing the LLR value corresponding to the LDPC codeword bits. Here, the LLR value is a channel value corresponding to the LDPC codeword bits and can be expressed in various ways.

[0237] The zero removal unit (1840) can remove zero bits from the bits output from the LDPC decoding unit (1830).

[0238] Specifically, the zero removal unit (1840) is a component corresponding to the zero padding unit (1720) of the transmitting device (1700) and can perform an operation corresponding to the zero padding unit (1720).

[0239] To this end, the receiving device (1800) may store information about the parameters used to pad zero bits in the transmitting device (1700). Accordingly, the zero removal unit (1840) can remove the zero bits padded in the zero padding unit (1720) from the bits output from the LDPC decoding unit (1830).

[0240] The dissegmentation unit (1850) is a component corresponding to the segmentation unit (1710) of the transmitting device (1700) and can perform an operation corresponding to the segmentation unit (1710).

[0241] To this end, the receiving device (1800) may store information about the parameters that the transmitting device (1700) used for segmentation. Accordingly, the desegmentation unit (1850) can restore the bits prior to segmentation by combining the bits output from the zero removal unit (1840), i.e., the segments for variable-length input bits.

[0242] Meanwhile, the embodiments of the present disclosure disclosed in this specification and drawings are merely specific examples provided to facilitate the explanation of the technical content of the present disclosure and to aid in understanding the present disclosure, and are not intended to limit the scope of the present disclosure. That is, it is obvious to those skilled in the art that other variations based on the technical concept of the present disclosure are possible.

[0243] In addition, each of the above embodiments may be combined and operated as needed. For example, parts of one embodiment of the present disclosure and another embodiment may be combined to operate a base station and a terminal.

[0244] In addition, the embodiments of the present disclosure are applicable to other communication systems, and other variations based on the technical concept of the embodiments may also be implemented. For example, the embodiments may be applied to LTE systems, 5G, NR systems, or 6G systems.

[0245] Therefore, the scope of the present disclosure should not be limited to the described embodiments, but should be defined by the claims set forth below as well as equivalents thereof.

Claims

Claim 1 A method performed by a transmitting device in a first system comprises: a step of determining a transport block size (TBS); a step of determining a base matrix based on the TBS and the code rate; a step of determining a lifting size; a step of determining a parity check matrix based on the lifting size and the base matrix; and a step of performing encoding for a code block based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor. Claim 2 In paragraph 1, the parity check matrix is It is determined based on, is the exponential value associated with the above parity check matrix, is the index value of the second system above, is the maximum value within the lifting size set in the second system above, is the expansion factor for each set index, A method characterized by being set to 0 or 1. Claim 3 A method according to claim 1, characterized in that the number of the symbol blocks is determined based on the maximum value of the lifting size. Claim 4 A method according to claim 1, characterized in that the first system is a 6G communication system and the second system is a 5G communication system. Claim 5 A method performed by a receiving device in a first system comprises: receiving a signal; checking a TBS (transport block size); checking a base matrix based on the TBS and the code rate; checking a lifting size; checking a parity check matrix based on the lifting size and the base matrix; and performing decoding on the signal based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor. Claim 6 In paragraph 5, the above parity check matrix is It is determined based on, is the exponential value associated with the above parity check matrix, is the index value of the second system above, is the maximum value within the lifting size set in the second system above, is the expansion factor for each set index, A method characterized by being set to 0 or 1. Claim 7 A method according to claim 5, wherein a code block is identified based on decoding of the signal, and the number of code blocks is determined based on the maximum value of the lifting size. Claim 8 A method according to claim 5, characterized in that the first system is a 6G communication system and the second system is a 5G communication system. Claim 9 A transmitting device in a first system comprising: a transmitting and receiving unit; and a control unit connected to the transmitting and receiving unit, wherein the control unit checks a transport block size (TBS), checks a base matrix based on the TBS and the code rate, checks a lifting size, checks a parity check matrix based on the lifting size and the base matrix, and performs encoding for a code block based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor. Claim 10 In paragraph 9, the parity check matrix is It is determined based on, is the exponential value associated with the above parity check matrix, is the index value of the second system above, is the maximum value within the lifting size set in the second system above, is the expansion factor for each set index, A transmitting device characterized by being set to 0 or 1. Claim 11 A transmitting device according to claim 9, characterized in that the number of the code blocks is determined based on the maximum value of the lifting size. Claim 12 A transmitting device according to claim 9, characterized in that the first system is a 6G communication system and the second system is a 5G communication system. Claim 13 A receiving device in a first system comprises: a transmitting and receiving unit; and a control unit connected to the transmitting and receiving unit, wherein the control unit receives a signal, checks a TBS (transport block size), checks a base matrix based on the TBS and the code rate, checks a lifting size, checks a parity check matrix based on the lifting size and the base matrix, and performs decoding on the signal based on the parity check matrix, wherein the maximum value of the lifting size is determined based on the product of the maximum value of the lifting size in a second system and an expansion factor. Claim 14 In paragraph 13, the above parity check matrix is It is determined based on, is the exponential value associated with the above parity check matrix, is the index value of the second system above, is the maximum value within the lifting size set in the second system above, is the expansion factor for each set index, A receiving device characterized by being set to 0 or 1. Claim 15 A receiving device according to claim 13, characterized in that a code block is identified based on decoding of the above signal, and the number of said code blocks is determined based on the maximum value of the lifting size. Claim 16 A receiving device according to claim 13, characterized in that the first system is a 6G communication system and the second system is a 5G communication system.

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