Semiconductor device and method for manufacturing semiconductor device

Abstract

A semiconductor device according to one embodiment of the present invention comprises: a substrate; a first p-type layer and an n-type epitaxial layer located on the substrate; an n+ type layer and a second p-type layer located on the n-type epitaxial layer; a protection layer located on the n+ type layer and the second p-type layer; and a gate located on the protection layer and on the second p-type layer.

Description

Technology Field

[0001] One embodiment of the present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. More specifically, it relates to a semiconductor device and a method for manufacturing a semiconductor device that increases the breakdown voltage by mitigating the electric field concentration concentrated in the P-type layer at the gate end or below the gate. Background Technology

[0002] Transistor devices (MOSFET, JFET, MESFET, IGBT, etc.) are three-terminal devices capable of conducting current through the control of the gate terminal, and in particular, transistors for power semiconductors used for switching require high voltage and high current.

[0003] Transistor devices possess different electrical characteristics depending on their structure, and appropriate devices are used for specific applications. However, they commonly require high current density, low turn-on voltage, high breakdown voltage, low leakage current, and fast switching speed, and these electrical characteristics involve a trade-off relationship. Therefore, structures are continuously being researched to weaken this trade-off relationship and improve one or more characteristics while maintaining other properties. In particular, for Ultra Wide Band-Gap (UWB) materials such as Ga2O3, AlN, and diamond, horizontal structures are being studied instead of vertical ones due to the high critical electric field, unlike conventional methods, and research to improve the characteristics of horizontal power semiconductors is actively underway. The problem to be solved

[0004] One embodiment of the present invention aims to provide a semiconductor device and a method for manufacturing a semiconductor device. More specifically, it aims to provide a semiconductor device and a method for manufacturing a semiconductor device that increases the breakdown voltage by mitigating the electric field concentration concentrated in the P-type layer at the gate end or below the gate. means of solving the problem

[0005] A semiconductor device according to one embodiment of the present invention comprises: a substrate; a first p-type layer and an n-type epitaxial layer located on the substrate; an n+ type layer and a second p-type layer located on the n-type epitaxial layer; a protection layer located on the n+ type layer and the second p-type layer; and a gate located on the protection layer and the second p-type layer.

[0006] A semiconductor device according to one embodiment of the present invention further comprises an insulating layer, and the insulating layer may be located between the second p-type layer and the gate and between the protection layer and the gate.

[0007] Some of the lower surface of the insulating layer may be in contact with the upper surface of the second p-type layer, other parts of the lower surface of the insulating layer may be in contact with the upper surface of the protective layer, and some parts of the upper surface of the insulating layer may be in contact with the lower surface of the gate.

[0008] The lower surface of the first p-type layer is in contact with the upper surface of the substrate, and the upper surface of the first p-type layer may be in contact with a part of the lower surface of the n-type epitaxial layer.

[0009] The first p-type layer may be positioned below the second p-type layer in the thickness direction of the semiconductor device with respect to it, with an n-type epitaxial layer in between.

[0010] The protection layer can be divided by the gate.

[0011] The device further includes a source electrode located on a protective layer and an n+ type layer, wherein a portion of the lower surface of the source electrode is in contact with the upper surface of the protective layer, and another portion of the lower surface of the source electrode is in contact with the upper surface of the n+ type layer.

[0012] The device further includes a drain electrode located on a protective layer and an n+ type layer, wherein a portion of the lower surface of the drain electrode is in contact with the upper surface of the protective layer, and another portion of the lower surface of the drain electrode is in contact with the upper surface of the n+ type layer.

[0013] It further includes a buffer layer located between the substrate and the n-type epitaxial layer, and a portion of the lower surface of the first p-type layer and the upper surface of the buffer layer may be in contact.

[0014] A method for manufacturing a semiconductor device according to one embodiment of the present invention comprises the steps of: providing a substrate; forming an n-type epitaxial layer and a first p-type layer on the substrate; forming an n+ type layer and a second p-type layer on the n-type epitaxial layer; forming a protective layer on the n+ type layer and the second p-type layer; and partially removing the protective layer located on the second p-type layer and forming a gate on the second p-type layer and the protective layer.

[0015] The step of forming an n-type epitaxial layer and a first p-type layer on a substrate may include: growing an epitaxial layer on the substrate to form the n-type epitaxial layer; implanting ions into a portion of the n-type epitaxial layer to form the first p-type layer; and regrowth an epitaxial layer on the n-type epitaxial layer and the first p-type layer.

[0016] The step of forming an n-type epitaxial layer and a first p-type layer on a substrate may include: forming a first p-type layer on a substrate; removing a portion of the first p-type layer; and growing an epitaxial layer on the remaining first p-type layer and the substrate to form an n-type epitaxial layer.

[0017] The step of forming an n-type epitaxial layer and a first p-type layer on a substrate may include: forming a first p-type layer on a substrate; implanting ions into a portion of the first p-type layer to convert it into an n-type epitaxial layer; and growing an epitaxial layer on the remaining first p-type layer and the n-type epitaxial layer to form the n-type epitaxial layer.

[0018] Prior to the step of forming a gate, the method further includes the step of forming an insulating layer on the second p-type layer and on the protective layer, and the step of forming a gate may form a gate on the insulating layer.

[0019] A method for manufacturing a semiconductor device according to one embodiment of the present invention may further include the steps of forming a source electrode on a protective layer and an n+ type layer and forming a drain electrode on the protective layer and the n+ type layer.

[0020] After the step of providing a substrate, the method may further include the step of forming a buffer layer on the substrate. Effects of the invention

[0021] A semiconductor device according to one embodiment of the present invention can improve breakdown voltage by mitigating electric field concentration.

[0022] A semiconductor device according to one embodiment of the present invention can increase the design freedom of the epitaxial region. Brief explanation of the drawing

[0023] FIG. 1 is a schematic diagram showing a semiconductor device according to one embodiment. Figure 2 is a schematic diagram showing a semiconductor device in the ON state. Figure 3 is a schematic diagram showing a semiconductor device in the device off state. FIG. 4 is a schematic diagram illustrating the step of forming an n-type epitaxial layer and a first p-type layer in a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 5 is a schematic diagram illustrating the step of forming an n-type epitaxial layer and a first p-type layer in a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 6 is a schematic diagram illustrating the step of forming an n-type epitaxial layer and a first p-type layer in a method for manufacturing a semiconductor device according to another embodiment of the present invention. FIG. 7 is a schematic diagram showing the steps after forming an n-type epitaxial layer and a first p-type layer in a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 8 is a schematic diagram illustrating the step of forming a second p-type layer in a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 9 is a schematic diagram illustrating the step of forming an n+ type layer in a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 10 is a schematic diagram illustrating the step of forming a protective layer in a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 11 is a schematic diagram illustrating the step of forming an insulating layer in a method for manufacturing a semiconductor device according to one embodiment of the present invention. FIG. 12 is a schematic diagram illustrating the step of forming a gate, a drain electrode, and a source electrode in a method for manufacturing a semiconductor device according to one embodiment of the present invention. Figure 13 shows the measurement results of the state current (a), threshold voltage (b), and breakdown voltage (c) in the example. Specific details for implementing the invention

[0024] Embodiments of the present invention are described below with reference to the attached drawings so that those skilled in the art can easily implement them. However, the present invention may be embodied in various different forms and is not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification are denoted by similar reference numerals.

[0025] Throughout the specification and claims, when a part is described as "comprising" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. Terms including ordinal numbers, such as first, second, etc., may be used to describe various components, but said components are not limited by said terms. Such terms are used solely for the purpose of distinguishing one component from another.

[0026] FIG. 1 is a drawing for explaining a semiconductor device according to one embodiment.

[0027] Referring to FIG. 1, a semiconductor device (100) according to one embodiment comprises: a substrate (10); a first p-type layer (31) and an n-type epitaxial layer (30) located on the substrate (10); an n+ type layer (40) and a second p-type layer (41) located on the n-type epitaxial layer (30); a protection layer (50) located on the n+ type layer (40) and the second p-type layer (41); and a gate (71) located on the protection layer (50) and the second p-type layer (41).

[0028] The substrate (10) may be a semi-insulating substrate or an insulating substrate. A semi-insulating substrate is a semiconductor material having high electrical resistance and may have characteristics between a conductive semiconductor and a completely insulated insulator. Meanwhile, an insulating substrate may have electrical insulating properties. In some embodiments, the semi-insulating substrate may be made of gallium arsenide (GaAs), silicon carbide (SiC), etc., and the insulating substrate may be made of sapphire, glass, SOI (Silicon-On-Insulator) substrate, etc.

[0029] As disclosed in FIG. 1, a buffer layer (20) may be additionally included on the substrate (10). The buffer layer (20) may inevitably be formed during the process of forming an n-type epitaxial layer (30) on the substrate (10).

[0030] As disclosed in FIG. 1, an n-type epitaxial layer (30) is located on a substrate (10). If a buffer layer (20) is present, a first n-type epitaxial layer (30) is located on the buffer layer (20). The buffer layer (20) may include Ga2O3.

[0031] The n-type epitaxial layer (30) is the main path for electron movement when the semiconductor device (100) is in the On state. It is also a channel region depletion layer formation region, and through this, a region that determines the On / Off state.

[0032] The doping elements of the n-type epitaxial layer (30) may include one or more of Si, Sn, and Ge. In this case, the concentration range is 1.0 × 10⁻⁶ 16 Up to 1.0×10 19 cm -3 It could be. More specifically, 0.5×10 17 Up to 0.5×10 19 cm -3 It could be. The base material could be Ga2O3.

[0033] As shown in FIG. 1, a first p-type layer (31) exists on the substrate (10). As shown in FIG. 1, the first p-type layer (31) exists on a part of the upper surface of the substrate (10), and an n-type epitaxial layer (30) exists on the remaining part.

[0034] More specifically, the lower surface of the first p-type layer (31) is in contact with the upper surface of the substrate (10), and the upper surface of the first p-type layer (31) is in contact with a part of the lower surface of the n-type epitaxial layer (30).

[0035] The doping elements of the first p-type layer (31) may include one or more of N, Mg, Fe, Ir, and As. In this case, the concentration range is 1.0 × 10 16 Up to 1.0 × 10 20 cm -3 It could be. More specifically, 0.5 × 10 17 Up to 0.5 × 10 20 cm -3 It could be. The base material could be Ga2O3. Or p-type NiO x It could be.

[0036] The first p-type layer (31) can increase the breakdown voltage by forming a buried P region at the bottom of the epitaxial layer where no voltage is directly applied (floating) to mitigate the electric field concentrated at the second p-type layer (41) at the bottom of the gate (71) and at the end of the gate (71). Additionally, the design freedom of the device can be increased through the buried P region that does not affect the second p-type layer (41) at the bottom of the gate (71) which controls the on-off of the device.

[0037] In addition, the semiconductor device (100) proposed in one embodiment of the present invention does not require the development of new process technology because it utilizes an ion implantation process and an epitaxial process.

[0038] As disclosed in FIG. 1, the first p-type layer (31) may be positioned with respect to the second p-type layer (41) with respect to the lower portion in the thickness direction of the semiconductor device (100) with respect to the n-type epitaxial layer (30) in between.

[0039] Additionally, the first p-type layer (31) is positioned between the n-type epitaxial layers (30) separated in the horizontal direction, so that the first p-type layer (31) is positioned to divide the n-type epitaxial layers (30) in the horizontal direction. Eventually, one end of the first p-type layer (31) and the other end of the first p-type layer (31) can be positioned to be in contact with the n-type epitaxial layers (30).

[0040] As disclosed in FIG. 1, an n+ type layer (40) and a second p type layer (41) are located on the n- type epitaxial layer (30).

[0041] The n+ type layer (40) is located at corresponding positions on both sides of the n- type epitaxial layer (30). The doping elements of the n+ type layer (40) may include one or more of Si, Sn, and Ge. In this case, the concentration range is 1.0 × 10⁻⁶ 18 Up to 1.0×10 20 cm -3 It could be. More specifically, 0.5×10 19 Up to 0.5×10 20 cm -3 It could be. The base material could be Ga2O3.

[0042] The second p-type layer (41) is positioned on the n-type epitaxial layer (30). Additionally, the second p-type layer (41) is positioned between the n-type epitaxial layers (30) separated in the horizontal direction so as to divide the n-type epitaxial layer (30) in the horizontal direction. Ultimately, one end of the second p-type layer (41) and the other end of the second p-type layer (41) can be positioned to be in contact with the n-type epitaxial layer (30).

[0043] The doping element of the second p-type layer (41) may be the same as that of the first p-type layer (31). Specifically, the doping element may include one or more of N, Mg, Fe, Ir, and As. In this case, the concentration range is 1.0 × 10⁻⁶ 16 Up to 1.0 × 10 20 cm -3 It could be. More specifically, 0.5 × 10 17 Up to 0.5 × 10 20 cm -3 It could be. The base material could be Ga2O3. Or p-type NiO x It could be.

[0044] The protective layer (50) is located on the n+ type layer (40) and the second p-type layer (41). The protective layer (50) may include one or more of SiO2 and Si2N3.

[0045] As shown in FIG. 1, a semiconductor device (100) according to one embodiment of the present invention may further include an insulating layer (60). The insulating layer (60) may be located between the second p-type layer (41) and the gate (71) and between the protection layer (50) and the gate (71).

[0046] More specifically, a portion of the lower surface of the insulating layer (60) is in contact with the upper surface of the second p-type layer (41), another portion of the lower surface of the insulating layer (60) is in contact with the upper surface of the protective layer (50), and the upper surface of the insulating layer (60) can be in contact with the lower surface of the gate (71).

[0047] The insulating layer (60) may include one or more of Al2O3, SiO2, HfO2, and Si2N3, and may be a material different from the aforementioned protective layer (50).

[0048] In FIG. 1, the insulating layer (60) is depicted as being formed only on a part of the upper surface of the protective layer (50), but it is not limited thereto and may be included on the entire upper surface of the protective layer (50).

[0049] The gate (71) is located on the protection layer (50) and on the second p-type layer (41). The protection layer (50) is divided by the gate (71), and each side of the divided protection layer (50) may come into contact with the gate (71). If an insulating layer (60) is further included, the insulating layer (60) may exist between each side of the divided protection layer (50) and the gate (71).

[0050] As shown in FIG. 1, it further includes a source electrode (72) located on the protective layer (50) and the n+ type layer (40). Specifically, a portion of the lower surface of the source electrode (72) is in contact with the upper surface of the protective layer (50), and another portion of the lower surface of the source electrode (72) is in contact with the upper surface of the n+ type layer (40).

[0051] As shown in FIG. 1, it further includes a drain electrode (73) located on the protective layer (50) and the n+ type layer (40). Specifically, a portion of the lower surface of the drain electrode (73) is in contact with the upper surface of the protective layer (50), and another portion of the lower surface of the drain electrode (73) is in contact with the upper surface of the n+ type layer (40).

[0052] FIG. 2 schematically shows a semiconductor device (100) in the ON state. The ON state is 0 ≤ V DS and V th ≤ V GS It means the state of V. DS is the voltage applied between the Drain and Source terminals, V GS ε is the voltage applied between the Gate and Source terminals, V th represents the minimum VGS voltage required for a channel to be formed.

[0053] In this state, the depletion layer (32) between the channel-controlled P region and the N-epi region is reduced by the gate voltage. Accordingly, electron movement is made possible between the depletion layer (32) and the second p-type layer (41) existing around the first p-type layer (31).

[0054] Additionally, a depletion layer (32) is formed around the first p-type layer (31) by the drain voltage. This depletion layer (32) is independent of the gate voltage and the depth and concentration of the second p-type layer (41), and the channel thickness can be controlled by controlling the thickness and concentration of the first p-type layer (31). In other words, this results in an increased degree of design freedom for the semiconductor device (100).

[0055] FIG. 3 schematically shows a semiconductor device (100) in an off state. An off state is defined as 0 ≤ V DS and V th ≥ V GS It means the state of being.

[0056] In the off state, the depletion layer (32) between the channel control P region and the N-epi region is increased by the drain voltage.

[0057] A depletion layer (32) is formed around the first p-type layer (31) and the second p-type layer (41) by the drain voltage, and the depletion layer (32) between the PN junctions increases by the high drain voltage. Accordingly, the depletion layer (32) formed around the first p-type layer (31) and the second p-type layer (41) blocks the electron transport path in the channel.

[0058] The electric field of the gate (71) terminal adjacent to the drain electrode (73) and the second p-type layer (31) is dispersed due to the presence of the first p-type layer (31), thereby mitigating the electric field.

[0060] A method for manufacturing a semiconductor device (100) according to one embodiment of the present invention comprises the steps of: providing a substrate (10); forming an n-type epitaxial layer (30) and a first p-type layer (31) on the substrate (10); forming an n+ type layer (40) and a second p-type layer (41) on the n-type epitaxial layer (30); forming a protective layer (50) on the n+ type layer (40) and the second p-type layer (41); and partially removing the protective layer (50) located on the second p-type layer (41) and forming a gate (71) on the second p-type layer (41) and the protective layer (50).

[0061] Each step is explained in detail below.

[0062] First, a substrate (10) is provided. Since the substrate (10) has been described above, a detailed description is omitted.

[0063] Next, a first n-type epitaxial layer (30) and a first p-type layer (31) are formed on the substrate (10). The first n-type epitaxial layer (30) can be formed by implanting ions such as Si, Sn, and Ge. At this time, a buffer layer (20) may inevitably be formed on the substrate (10).

[0064] The step of forming the first n-type epitaxial layer (30) and the first p-type layer (31) can be performed through various methods and is not particularly limited.

[0065] FIG. 4 schematically illustrates one example thereof. As shown in FIG. 4, the step of forming an n-type epitaxial layer (30) and a first p-type layer (31) on a substrate (10) may include: growing an epitaxial layer on the substrate (10) to form an n-type epitaxial layer (30); implanting ions into a portion of the n-type epitaxial layer (30) to form a first p-type layer (31); and growing an epitaxial layer on the n-type epitaxial layer (30) and the first p-type layer (31).

[0066] As shown in FIG. 4, when ions are implanted into a portion of the n-type epitaxial layer (30), a pattern can be formed with a photosensitive film (80) to form a first p-type layer (31) only at specific locations.

[0067] FIG. 5 schematically illustrates another example thereof. As shown in FIG. 5, the step of forming an n-type epitaxial layer (30) and a first p-type layer (31) on a substrate (10) may include: forming a first p-type layer (31) on the substrate (10); removing a portion of the first p-type layer (31); and growing an epitaxial layer on the remaining first p-type layer (31) and the substrate (10) to form an n-type epitaxial layer (30).

[0068] As shown in FIG. 5, a first p-type layer (31) can be formed on the entire upper surface of a substrate (10) and then partially removed to form a first p-type layer (31).

[0069] FIG. 6 schematically illustrates another example thereof. As shown in FIG. 6, the step of forming an n-type epitaxial layer (30) and a first p-type layer (31) on a substrate (10) comprises: forming a first p-type layer (31) on the substrate (10); implanting ions into a portion of the first p-type layer (31) to convert it into an n-type epitaxial layer (30); and growing an epitaxial layer on the remaining first p-type layer (31) and n-type epitaxial layer (30) to form an n-type epitaxial layer (30).

[0070] As shown in FIG. 6, when ions are implanted into a portion of the first p-type layer (31), a pattern is formed with a photosensitive film (80), and the n-type epitaxial layer (30) can be converted only at specific locations.

[0071] FIG. 7 is a schematic diagram showing the steps after forming an n-type epitaxial layer (30) and a first p-type layer (31) in a method for manufacturing a semiconductor device according to one embodiment of the present invention.

[0072] Next, an n+ type layer (40) and a second p-type layer (41) are formed on the n-type epitaxial layer. As shown in FIGS. 8 and 9, the n+ type layer (40) can be formed after the second p-type layer (41) is formed, but is not limited thereto, and it is also possible to form the n+ type layer (40) first or simultaneously.

[0073] As shown in FIGS. 8 and 9, a pattern can be formed with a photosensitive film (80) to form an n+ type layer (40) and a second p-type layer (41) at appropriate locations. The n+ type layer (40) and the second p-type layer can be formed through appropriate ion implantation.

[0074] Next, a protective layer (50) is formed on the n+ type layer (40) and the second p type layer (41).

[0075] Figure 10 shows a drawing after the formation of the protective layer (50).

[0076] The method may further include the step of forming a protective layer (50) and forming an insulating layer (60) on the second p-type layer (41) and on the protective layer (50).

[0077] If the step of forming an insulating layer (60) is further included, the gate (71) is formed on the insulating layer (60). FIG. 11 shows a drawing after the formation of the insulating layer (60).

[0078] Next, a portion of the protective layer (50) located on the second p-type layer (41) is removed, and a gate (71) is formed on the second p-type layer (41) and the protective layer (50).

[0079] The gate (71) can be formed of polysilicon, and a metal material may be used as needed.

[0080] There are two ways to form the gate (71).

[0081] One method further includes the step of forming an insulating layer (60) on the second p-type layer (41) and the protective layer (50) prior to the step of forming the gate (71), and the step of forming the gate (71) may form the gate (71) on the insulating layer (60).

[0082] Another method further includes the step of forming a photosensitive film, an insulating layer, and a metal layer on a protective layer (50) prior to the step of forming a gate (71), and the step of forming the gate (71) can be performed by patterning and removing the photosensitive film and the insulating layer and metal layer on the photosensitive film. In this process, a desired gate area can be precisely patterned using photolithography technology.

[0083] In one embodiment of the present invention, the steps of forming a source electrode (72) on the protective layer (50) and the n+ type layer (40) and forming a drain electrode (73) on the protective layer (50) and the n+ type layer (40) may be further included. Specific formation methods are as follows.

[0084] First, a photosensitive film is applied to the protective layer (50) and the gate (71), patterned, and the protective layer (50) is partially etched. At this time, the protective layer (50) being etched is located at both ends of the protective layer (50) and becomes the location where the source electrode (72) and the drain electrode (73) are to be formed, respectively.

[0085] FIG. 12 shows a drawing after the gate (71), source electrode (72) and drain electrode (73) have been formed.

[0087] Figure 13 shows the measurement results of the state current (a), threshold voltage (b), and breakdown voltage (c) in the embodiment.

[0088] Unlike the semiconductor device according to one embodiment of the present invention, the semiconductor device labeled as conventional (comparative example) in FIG. 13 does not have a first p-type layer (31) formed separately, and the corresponding location exists as an n-type epitaxial layer (30).

[0089] The proposal (example) in FIG. 13 is a semiconductor device having the structure shown in FIG. 1.

[0090] In addition, in Table 1 below, conventional (comparative example) and proposed (example) semiconductor devices were used, and the current density, threshold voltage, breakdown voltage, and figure of merit were measured for the semiconductor device of the example.

[0091] The results were displayed using Synopsys’ Sentaurus TCAD.

[0092] division Examples Comparative example Current density [mA / mm] 100.54 102.15 Threshold voltage [V] 8.61 -3.23 Breakdown voltage [V] 457.9 387.2 Figure of Merits [MW / mm] 8.43 6.13

[0093] As shown in Table 1 and Figure 13, it can be seen that the breakdown voltage increases by adding the first p-type layer (31). Specifically, the breakdown voltage increased by 18.3%.

[0094] In addition, it was confirmed that the current density decreased slightly. Specifically, the current density decreased by 1.58%. However, due to the breakdown voltage-current density trade-off relationship, the current increased at the equivalent breakdown voltage. Nevertheless, it was confirmed that the power semiconductor performance index improved by 37.6%.

[0095] Finally, by adding the first p-type layer (31), it can be confirmed that the threshold voltage is increased. It was confirmed that the threshold voltage increased by 366.5% and that normally-off operation can be implemented.

[0096] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art to which the present invention belongs, utilizing the basic concept of the present invention as defined in the following claims, also fall within the scope of the present invention. Explanation of the symbols

[0097] 100: Semiconductor device, 10: Substrate, 20: Buffer layer, 30: n-type epitaxial layer, 31: 1st p-type layer, 32: Deprived layer, 40: n+ type layer, 41: Second p-type layer, 50: Protective layer, 60: Insulating layer, 71: Gate, 72: Source electrode, 73: Drain electrode, 80: Photosensitive film

Claims

Claim 1 A semiconductor device comprising: a substrate; a first p-type layer and an n-type epitaxial layer located on the substrate; an n+ type layer and a second p-type layer located on the n-type epitaxial layer; a protection layer located on the n+ type layer and the second p-type layer; and a gate located on the protection layer and on the second p-type layer. Claim 2 A semiconductor device according to claim 1, further comprising an insulating layer, wherein the insulating layer is located between the second p-type layer and the gate and between the protection layer and the gate. Claim 3 A semiconductor device according to paragraph 2, wherein a portion of the lower surface of the insulating layer is in contact with the upper surface of the second p-type layer, another portion of the lower surface of the insulating layer is in contact with the upper surface of the protective layer, and a portion of the upper surface of the insulating layer is in contact with the lower surface of the gate. Claim 4 A semiconductor device according to claim 1, wherein the lower surface of the first p-type layer is in contact with the upper surface of the substrate, and the upper surface of the first p-type layer is in contact with a part of the lower surface of the n-type epitaxial layer. Claim 5 A semiconductor device according to claim 1, wherein the first p-type layer is positioned below the second p-type layer in the thickness direction of the semiconductor device with the n-type epitaxial layer in between. Claim 6 In claim 1, the protective layer is a semiconductor device divided by the gate. Claim 7 A semiconductor device according to claim 1, further comprising a source electrode located on the protective layer and the n+ type layer, wherein a portion of the lower surface of the source electrode contacts the upper surface of the protective layer and another portion of the lower surface of the source electrode contacts the upper surface of the n+ type layer. Claim 8 A semiconductor device according to claim 1, further comprising a drain electrode located on the protective layer and the n+ type layer, wherein a portion of the lower surface of the drain electrode is in contact with the upper surface of the protective layer and another portion of the lower surface of the drain electrode is in contact with the upper surface of the n+ type layer. Claim 9 A semiconductor device according to claim 1, further comprising a buffer layer located between the substrate and the n-type epitaxial layer, wherein a portion of the lower surface of the first p-type layer and the upper surface of the buffer layer are in contact. Claim 10 A method for manufacturing a semiconductor device comprising the steps of: providing a substrate; forming an n-type epitaxial layer and a first p-type layer on the substrate; forming an n+ type layer and a second p-type layer on the n-type epitaxial layer; forming a protective layer on the n+ type layer and the second p-type layer; and partially removing the protective layer located on the second p-type layer and forming a gate on the second p-type layer and the protective layer. Claim 11 A method for manufacturing a semiconductor device according to claim 10, wherein the step of forming an n-type epitaxial layer and a first p-type layer on the substrate comprises: growing an epitaxial layer on the substrate to form the n-type epitaxial layer; implanting ions into a portion of the n-type epitaxial layer to form the first p-type layer; and regrowing an epitaxial layer on the n-type epitaxial layer and the first p-type layer. Claim 12 A method for manufacturing a semiconductor device according to claim 10, wherein the step of forming an n-type epitaxial layer and a first p-type layer on the substrate comprises: a step of forming a first p-type layer on the substrate; a step of partially removing the first p-type layer; and a step of growing an epitaxial layer on the remaining first p-type layer and the substrate to form the n-type epitaxial layer. Claim 13 A method for manufacturing a semiconductor device according to claim 10, wherein the step of forming an n-type epitaxial layer and a first p-type layer on the substrate comprises: a step of forming a first p-type layer on the substrate; a step of implanting ions into a portion of the first p-type layer to convert it into an n-type epitaxial layer; and a step of growing an epitaxial layer on the remaining first p-type layer and the n-type epitaxial layer to form the n-type epitaxial layer. Claim 14 A method for manufacturing a semiconductor device according to claim 10, further comprising, prior to the step of forming the gate, the step of forming the gate, the step of forming the gate, wherein the gate is formed on the insulating layer. Claim 15 A method for manufacturing a semiconductor device according to claim 10, further comprising the steps of forming a source electrode on the protective layer and the n+ type layer and forming a drain electrode on the protective layer and the n+ type layer. Claim 16 A method for manufacturing a semiconductor device according to claim 10, further comprising the step of forming a buffer layer on the substrate after the step of providing the substrate.

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