Electronic apparatus and computing system

Abstract

The present disclosure discloses an electronic device. The electronic device includes a memory comprising a first region and a second region associated with a host memory, and a controller configured to be connected to the memory, wherein the controller may be configured to access the first region based on a physical addressing method and to access the second region based on a virtual addressing method.

Description

Technology Field

[0001] The present invention relates to an electronic device and a computing system including the same. Background Technology

[0002] With the advancement of artificial intelligence, big data, and blockchain-based technologies, accelerators—hardware designed to assist CPU (Central Processing Unit) computations or process specific tasks quickly—are being widely used.

[0003] PCIe (Peripheral Component Interconnect Express) based accelerators use independent memory, so copy overhead occurs when data is transferred between the host device and the accelerator. This causes performance degradation and results in bottlenecks in workloads such as deep learning and big data analysis.

[0004] To overcome these limitations, accelerators containing CXL (Compute Express Link) memory have emerged. Since these accelerators can include both Device Private Memory (DPM) and host memory (HDM, CXL Host Attached Device Memory), copy overhead can be prevented during data transfer between the host device and the accelerator. However, the following additional processes are required.

[0005] First, even though the host memory (HDM) is placed in the accelerator, it remains within the control range of the host device; therefore, permission from the host device is required whenever the accelerator uses the host memory (HDM).

[0006] Secondly, since the host device uses a virtual address-based memory address allocation method, when the accelerator accesses the host memory (HDM), it must access it based on the virtual addressing method to smoothly utilize pointer-based data structures (Linked Lists, Trees, etc.) or cases where the contiguous address space in the virtual address is physically discontinuous.

[0007] The information described above disclosed in the background technology of this invention is intended only to enhance understanding of the background of the present invention and may therefore include information that does not constitute prior art. The problem to be solved

[0008] The present disclosure provides an electronic device and a computing system that use the memory of an electronic device by dividing it into a device-dedicated memory area and a host memory area to solve the aforementioned problems. means of solving the problem

[0009] The present disclosure may be implemented in various ways, including a method, an apparatus (system), or a computer program stored on a readable storage medium.

[0010] An electronic device according to one embodiment of the present disclosure for solving a technical problem comprises a memory including a first region and a second region associated with a host memory, and a controller configured to be connected to the memory, wherein the controller may be configured to access the first region based on a physical addressing method and access the second region based on a virtual addressing method.

[0011] According to one embodiment of the present disclosure, the first region is a device-specific memory region of an electronic device and may include data associated with at least one of Code, Stack, or Heap at runtime of a specific program.

[0012] According to one embodiment of the present disclosure, the second region is a host memory region and may include data that satisfies cache coherence with the host memory.

[0013] According to one embodiment of the present disclosure, a controller may be configured to determine whether to access a first region based on a physical addressing method or to access a second region based on a virtual addressing method, based on the value of a specific address bit received from a host processor.

[0014] According to one embodiment of the present disclosure, the controller includes a Memory Management (MM) unit and a Snoop unit, wherein the MM unit converts a virtual address space allocated in host memory into a physical address space, the Snoop unit satisfies cache consistency between the physical address space and a second area, and the controller may be configured to access the second area when the value of a specific address bit received from a host processor is a first value.

[0015] According to one embodiment of the present disclosure, the controller may be configured to access a first region when the value of a specific address bit received from a host processor is a second value.

[0016] According to one embodiment of the present disclosure, a computing system comprises a host device including a host processor and a host memory, and an electronic device, wherein the electronic device comprises a memory including a first region and a second region associated with the host memory, and a controller configured to be connected to the memory and the host processor, and the controller may be configured to access the first region based on a physical addressing method and to access the second region based on a virtual addressing method.

[0017] According to one embodiment of the present disclosure, the first region is a device-specific memory region of an electronic device and may include data associated with at least one of Code, Stack, or Heap at runtime of a specific program.

[0018] According to one embodiment of the present disclosure, the second region is a host memory region and may include data that satisfies cache coherence with the host memory.

[0019] According to one embodiment of the present disclosure, a controller may be configured to determine whether to access a first region based on a physical addressing method or to access a second region based on a virtual addressing method, based on the value of a specific address bit received from a host processor.

[0020] According to one embodiment of the present disclosure, the controller includes a Memory Management (MM) unit and a Snoop unit, wherein the MM unit converts a virtual address space allocated in host memory into a physical address space, the Snoop unit satisfies cache consistency between the physical address space and a second area, and the controller may be configured to access the second area when the value of a specific address bit received from a host processor is a first value.

[0021] According to one embodiment of the present disclosure, the controller may be configured to access a first region when the value of a specific address bit received from a host processor is a second value.

[0022] According to one embodiment of the present disclosure, the runtime of a host processor and a controller may be configured to allocate an area associated with at least one of code, stack, or heap at runtime of a specific program. Effects of the invention

[0023] According to various embodiments of the present disclosure, an electronic device is provided that uses the memory of an electronic device by dividing it into a device-dedicated memory area and a host memory area, thereby enabling effective memory management and improving processing speed.

[0024] The effects of the present disclosure are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art to which the present disclosure pertains (referred to as "person skilled in the art") from the description in the claims. Brief explanation of the drawing

[0025] Embodiments of the present disclosure will be described with reference to the accompanying drawings described below, wherein similar reference numerals indicate similar elements, but are not limited thereto. FIG. 1 is a diagram for schematically illustrating a computing system according to one embodiment of the present disclosure. FIG. 2 is a diagram illustrating a communication method of a computing system according to one embodiment of the present disclosure. FIG. 3 is a drawing for explaining the configuration of a controller according to one embodiment of the present disclosure. FIG. 4 is a diagram illustrating a method for a controller and a host processor of an electronic device to access device memory according to one embodiment of the present disclosure. FIG. 5 is a diagram illustrating a method for a host program and a device program to access device memory according to one embodiment of the present disclosure. FIG. 6 is a diagram illustrating a process for accessing a host memory area of ​​a device memory according to one embodiment of the present disclosure. FIG. 7 is a diagram illustrating the process of a controller accessing a host memory area according to one embodiment of the present disclosure. FIG. 8 is a diagram illustrating the process of accessing a device-dedicated memory area according to one embodiment of the present disclosure. Embodiments of the present disclosure will be described with reference to the accompanying drawings described below, wherein similar reference numerals indicate similar elements, but are not limited thereto. Specific details for implementing the invention

[0026] Hereinafter, specific details for implementing the present disclosure will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding widely known functions or configurations will be omitted if there is a risk that the gist of the present disclosure may be unnecessarily obscured.

[0027] In the attached drawings, identical or corresponding components are assigned the same reference numerals. Additionally, in the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0028] The advantages and features of the disclosed embodiments and the methods for achieving them will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below but may be implemented in various different forms, and the embodiments provided are merely to make the present disclosure complete and to fully inform those skilled in the art of the scope of the invention.

[0029] The terms used in this specification will be briefly explained, and the disclosed embodiments will be described in detail. The terms used in this specification have been selected to be as generally used as possible, taking into account their functions in this disclosure; however, these terms may vary depending on the intent of those skilled in the art, case law, the emergence of new technologies, etc. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this disclosure should be defined not merely by their names, but based on their meanings and the content throughout this disclosure.

[0030] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0031] Additionally, the terms 'module' or 'part' as used in the specification refer to software or hardware components, and the 'module' or 'part' performs certain roles. However, the meaning of 'module' or 'part' is not limited to software or hardware. The 'module' or 'part' may be configured to reside in an addressable storage medium or configured to run on one or more processors. Thus, as an example, the 'module' or 'part' may include components such as software components, object-oriented software components, class components, and task components, and at least one of processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, or variables. The components and the functions provided within the 'module' or 'part' may be combined into a smaller number of components and 'modules' or 'parts', or further separated into additional components and 'modules' or 'parts'.

[0032] According to one embodiment of the present disclosure, a ‘module’ or ‘part’ may be implemented as a processor and memory. The term ‘processor’ should be broadly interpreted to include a general-purpose processor, a central processing unit (CPU), a microprocessor, a digital signal processor (DSP), a controller, a microcontroller, a state machine, etc. In some environments, the term ‘processor’ may refer to an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a field programmable gate array (FPGA), etc. The term ‘processor’ may also refer to a combination of processing devices, such as, for example, a combination of a DSP and a microprocessor, a combination of multiple microprocessors, a combination of one or more microprocessors combined with a DSP core, or any other combination of such configurations. Additionally, the term ‘memory’ should be broadly interpreted to include any electronic component capable of storing electronic information. 'Memory' may refer to various types of processor-readable media, such as Random Access Memory (RAM), Read-Only Memory (ROM), Non-Volatile Random Access Memory (NVRAM), Programmable Read-Only Memory (PROM), Erasable-Programmable Read-Only Memory (EPROM), Electrically Erasable PROM (EEPROM), Flash Memory, Magnetic or Optical Data Storage Devices, Registers, etc. If a processor can read information from memory and / or write information to memory, the memory is said to be in an electronic communication state with the processor. Memory integrated into a processor is in an electronic communication state with the processor.

[0033] In the present disclosure, the 'system' may include at least one of a server device and a cloud device, but is not limited thereto. For example, the system may be composed of one or more server devices. As another example, the system may be composed of one or more cloud devices. As yet another example, the system may be configured and operated with both a server device and a cloud device.

[0034] In the present disclosure, 'display' may refer to any display device associated with a computing device, for example, any display device capable of displaying any information / data controlled by or provided by the computing device.

[0035] In the present disclosure, 'each of a plurality of A' or 'each of a plurality of A' may refer to each of all components included in a plurality of A, or each of some components included in a plurality of A.

[0036] Various embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The size or location of display screens, images, buttons, etc., as illustrated and described in the drawings are exemplary and are not limited thereto. For example, some buttons may be added or omitted, or configured with sizes and locations different from those illustrated. Furthermore, the flowcharts and descriptions illustrated in the drawings are merely examples and may be implemented differently in some embodiments. For example, one or more steps may be omitted, the order of each step may be changed, one or more steps may be performed in overlap, or one or more steps may be performed repeatedly.

[0037] FIG. 1 is a diagram for schematically illustrating a computing system (1) according to one embodiment of the present disclosure.

[0038] Referring to FIG. 1, the computing system (1) may include a combination of hardware and software capable of processing data and performing operations. The computing system (1) may include a storage server or other types of server that can be used in a data center, and may include an electronic device (100) and a host device (200).

[0039] The host device (200) may include a host memory (210) and a host processor (220). The host memory (210) is memory primarily used by the host processor (220) and may include at least one of RAM (Random Access Memory), Cache Memory, Non-Volatile Memory, and Unified Memory, but is not limited thereto.

[0040] The host processor (220) may include a set of one or more processors. The host processor (220) may control at least one component of a device or terminal (e.g., electronic device (100)) connected to the host processor (220) by running software (e.g., instructions, programs, etc.). Additionally, the host processor (220) may perform various operations such as computation, processing, data generation, or processing. Furthermore, the host processor (220) may load data, etc. from various memory devices or storage devices, or store data, etc., in memory devices or storage devices.

[0041] The electronic device (100) may be configured to perform specific tasks according to the instructions of the host processor (220). That is, the electronic device (100) may be a device for performing offloading (distributed processing) including at least one of artificial intelligence inference, image processing, or data analysis. As an example, the electronic device (100) may include a GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), NPU (Neural Processing Unit), FPGA (Field-Programmable Gate Array), ASIC (Application-Specific Integrated Circuit), etc., but the present disclosure is not limited thereto.

[0042] The electronic device (100) may include a device memory (110) and a controller (120). The device memory (110) may be a Compute Express Link (CXL) memory and may be divided into a plurality of regions (112, 114). The first region (112) is a device-dedicated memory (DPM) region of the electronic device (100), and the second region (114) is a host memory (HDM) region located within the device memory (110) of the electronic device (100) but associated with the host memory (210) and may be included within the control range of the host processor (220).

[0043] The first region (112) may be a device-dedicated memory (DPM) of an electronic device that supports the CXL.io protocol. CXL.io may include an input / output interface compatible with existing PCIe. The first region (112) may include data associated with at least one of the Code, Stack, or Heap at runtime of a specific program. Additionally, the first region (112) may store at least one of predefined data, data for which access is restricted by a controller (120), or data for which user modification is restricted, but the present disclosure is not limited thereto.

[0044] The second region (114) may support the CXL.mem protocol, which provides extended memory by utilizing shared memory. It is a host memory (HDM) region located in the electronic device (100) and may contain data that satisfies cache coherence with the host memory (210) within the host device (200). The host processor (220) may manage the host memory (210) and the second region (114) included in the host device (200). For example, the host processor (220) may manage the second region (114) based on a virtual addressing method, which is the addressing method of the host device (200).

[0045] The second area (114) can address or store at least one of the data associated with shared data, frequent input or output.

[0046] The controller (120) may have one or more memory channels and may communicate with individual components or memory devices through these memory channels. The memory channels may be volatile, non-volatile, or address-region-based memory channels connected to a Solid State Drive (SSD), but the present disclosure is not limited thereto. The controller (120) may access the first region (112) according to the memory address allocation method of the electronic device (100). For example, the controller (120) may access the first region (112) based on a physical addressing method, but is not limited thereto.

[0047] The controller (120) can access the second area (114) according to the memory address allocation method of the host device (200). For example, the controller (120) can access the second area (114) based on a virtual addressing (Physical Addressing) method, but is not limited thereto.

[0048] FIG. 2 is a diagram for explaining a communication method of a computing system (1) according to one embodiment of the present disclosure.

[0049] Referring to FIG. 2, the electronic device (100) includes a device memory (110) and a controller (120), and the host device (200) may include a host memory (210) and a host processor (220).

[0050] The controller (120) can communicate with the host processor (220) through the device communication interface (122). The device communication interface (122) may be a serial communication-based interface and may include one or more communication ports. The device communication interface (122) may be an interface using the PCIe (Peripheral Component Interconnect Express) or CXL (Compute Express Link) protocols, but the present disclosure is not limited thereto.

[0051] The host processor (220) can communicate with the controller (120) through the host communication interface (222). The host communication interface (222) may be a serial communication-based interface, but the present disclosure is not limited thereto.

[0052] The host processor (220) can send a command for offloading to the controller (120). The host processor (220) can copy data based on DMA to access the device-dedicated memory area of ​​the device memory (110). Additionally, the host processor (220) can access the host memory area of ​​the device memory (110) and load or store data based on a virtual addressing method.

[0053] The controller (120) can access the device-only memory area and the host memory area of ​​the device memory (110) according to the command of the host processor (220) to load or store data.

[0054] FIG. 3 is a drawing for explaining the configuration of a controller (120) according to one embodiment of the present disclosure.

[0055] Referring to FIG. 3, the controller (120) may include at least one of a device communication interface (122), a core unit (124), an MM unit (126), and a snoop unit (128).

[0056] The device communication interface (122) is a module for communicating with a host processor and may include a serial communication interface and one or more communication ports.

[0057] The core unit (124) may include a processor core that processes specific tasks within the controller. The core unit (124) may be one or more and may perform at least one of matrix or vector operations, hashing operations, encoding or decoding, deep learning-based training or inference, but is not limited thereto.

[0058] The core unit (124) can determine whether to access the first area (112) or the second area (114) of the device memory (110) based on information transmitted from the host processor.

[0059] The MM (Memory Management) unit (126) can convert a virtual address space allocated to a host memory or host memory area into a physical address space. The MM unit (126) can convert an address space mapped to a host virtual address space by a host process into a physical addressing method, which is the addressing method of an electronic device (100), and map it to a host physical address space.

[0060] The snoop unit (128) may be a unit for satisfying cache consistency between the physical address space of the host and the host memory area (second area) within the device memory (110). The snoop unit (128) may store host caching information indicating the state in which data stored in the device memory (110) is cached in the host cache memory. The host caching information may include the time when data stored at a specific address in the device memory (110) is registered in the host cache memory and the time when it is removed from the host cache memory.

[0061] The core unit (124) can access the host memory area of ​​the device memory (110) through the MM unit (126) and the snoop unit (128) to perform load or store operations.

[0062] FIG. 4 is a diagram illustrating a method for a controller (120) and a host processor (220) of an electronic device to access a device memory (110) according to one embodiment of the present disclosure.

[0063] Referring to FIG. 4, the device memory (110) of the electronic device (100) may be divided into a first area (112) and a second area (114). The first area (112) is an area within the control range of the controller (120) and may be a device-dedicated memory (DPM) area. The second area (114) may be an area included in the electronic device (100) but associated with the host processor (220) and may be a host memory (HDM) area. In one embodiment, the controller (120) may divide the device memory (110) into the first area (112) and the second area (114) before use or during the manufacture of the electronic device (100), but the present disclosure is not limited thereto.

[0064] The first area (112) may include data associated with at least one of the Code, Stack, or Heap at runtime of a specific program. Additionally, the first area (112) may store at least one of predefined data, data for which access restriction rights are set by the controller (120), or data for which user modification is restricted, but the present disclosure is not limited thereto.

[0065] The controller (120) can freely access (S22) the first area (112) and can access the first area (112) based on the addressing method of the electronic device (100). For example, the controller (120) can access the first area (112) based on the physical addressing method.

[0066] The host processor (220) can access (S26) the first area (112) through a memory copy method to copy data in the first area (112) or store data in the first area (112).

[0067] The second region (114) is a region associated with the host memory and the host processor (220), and may be a host memory (HDM) that is not placed in the host device and is under the control of the host processor (220). The host processor (220) may freely access (S28) the second region (114) through a load or store command.

[0068] The controller (120) can convert the virtual address to a physical address basis to access (S24) the host memory and the second region (114) where the Coherence process is performed. To access (S24) the second region (114), the controller (120) needs to obtain permission from the host processor (220), but the present disclosure is not limited thereto.

[0069] FIG. 5 is a diagram illustrating a method (500) for a host program (HP) and a device program (DP) to access a device memory according to one embodiment of the present disclosure.

[0070] Referring to FIG. 5, the host program (HP) may be an OS (Operation System) program executed by the host processor, and the device program (DP) may be a specific program executed by the electronic device (100) and may be a program executed in the core unit (124) of the electronic device (100).

[0071] First, the host program (HP) can configure a runtime memory area corresponding to the device program (DP) through a runtime configuration process. The host program (HP) can configure a first area (112), which may include at least one of a DMA area (510), a code area, a heap area (520), or a stack area (530).

[0072] The DMA area (510) is an area where data can be transferred without the intervention of a host processor, and data can be transferred quickly by efficiently utilizing the bus bandwidth. The DMA area (510) can be used for network packet processing, disk I / O, or graphics operations. The DMA area (510) may be an area that can be accessed (S540, S560) by a host program (HP) and a device program (DP).

[0073] The heap area (520) may have a heap base set at the time of initialization of the device program (DP). The heap base may be set to '(0x1<<48) | HEAP_OFFSET', but the present disclosure is not limited thereto. The heap area (520) may be an area that the device program (DP) can access (S560).

[0074] The stack area (530) may have a stack base set at the time of initialization of the device program (DP). The stack base may be set to '(0x1<<48) | STACK_OFFSET', but the present disclosure is not limited thereto. The stack area (530) may be an area that the device program (DP) can access (S560).

[0075] After the host program (HP) sets up the runtime memory (first area, 112), the device runtime can allocate an address associated with at least one of Code, Stack, or Heap to the first area (112). The device runtime can be configured to allocate an area associated with at least one of Code, Stack, or Heap at runtime of a specific program. That is, the area can be allocated by the host runtime and the device runtime performed by the host processor and controller.

[0076] Here, the device runtime is a program that provides an environment for computational offloading and may be a program that transmits at least one of code, data, or the result of an execution command to the host device (200). For example, the device runtime may store the result or completion signal of an execution command of the host device (200) at a location in a DMA-based agreed-upon first region (112) or at a designated location in the host device (200) to transmit the result or completion signal of an execution command of the host device (200) to the host device (200). Additionally, a host runtime may also be placed in the host device (200) to transmit code, data, or execution commands to the electronic device (100).

[0077] At this time, the host program may set the value of a specific address bit (e.g., the 48th bit, 582) of a specific address (580) to '1' to set the runtime memory of the device program (DP) to the first area (112), but the present disclosure is not limited thereto.

[0078] The host processor can perform memory allocation of the second area (114). When the host processor allocates memory to the second area (114), it can allocate memory based on virtual addressing. The host processor can transmit the address allocated to the second area to the controller (120) through the argument of the command descriptor. The offloading runtime of the electronic device can set the value of a specific address bit (582) received from the host processor (220) to a first value (e.g., '0') (or, if the first value is set by default, the setting may be omitted). If the value of the specific address bit (582) is the first value, the controller (120) can determine whether to access the second area (114) based on the virtual addressing method.

[0079] Additionally, the controller (120) can determine whether to access the first area (112) based on a physical addressing method based on the value of a specific address bit (582) of a specific address (580) received from the host processor (220). For example, if the value of the specific address bit (582) is a second value (e.g., '1'), the controller (120) can access the first area (112) based on a physical addressing method.

[0080] The address covering the first area (112) and the second area (114) of the device memory (110) is a separate address space called the "device physical address." The controller (120) can access the first area (112) based on the device physical addressing method and access the second area (114) by converting the host address into the device physical address based on the host virtual addressing method.

[0081] FIG. 6 is a diagram illustrating a process for accessing a host memory area (114) of a device memory (110) according to one embodiment of the present disclosure.

[0082] Referring to FIG. 6, the device memory (110) may include a first region (112) which is a device-only memory region and a second region (114) which is a host memory region. The controller (120) may include a device communication interface (122), a core unit (124), an MM unit (126), and a snoop unit (128).

[0083] The core unit (124) can attempt to access the second area (114) (610) when the value of a preset specific address bit is the first value (e.g., '0').

[0084] The MM unit (126) can convert a virtual address space allocated in host memory into a physical address space. That is, the MM unit (126) can convert the virtual address space into a physical address space to access a second area (114) allocated in memory according to the address scheme of the host memory.

[0085] The snoop unit (128) can satisfy cache consistency between the physical address space and the second area (114). Accordingly, the controller (120) can access a specific address in the second area (114) when the value of a specific address bit received from the host processor is a first value (e.g., '0').

[0086] FIG. 7 is a diagram illustrating the process (700) of a controller accessing a host memory area according to one embodiment of the present disclosure.

[0087] Referring to FIG. 7, the core unit (124) can determine whether to access the second area (114), which is a host memory area, based on the value of a specific address bit (e.g., '0') set by the offloading runtime.

[0088] When the MM unit (126) receives a command to access the second area (114) by the core unit (124), it can convert a specific space (722) of the host virtual address (720) set (S712) by the host processor (710) into the address space of the second area (114) of the device memory (110).

[0089] The host processor (710) can convert the host virtual address (722) into a host physical address (732) (S724A) by the host OS and the host's MM unit, and then transmit the host physical address (732) to the electronic device (100). The electronic device (100) can convert the host physical address (732) into a second area (114) address according to the address mapping method (740) defined by the CXL standard. That is, the host virtual address can be converted into a second area (114) address by passing through the MM unit (126) from the core unit (124). Accordingly, the controller (120) can directly access the second area (114).

[0090] The snoop unit (128) can satisfy the coherence of the second area (114) and a specific space (732) of the host physical address (730), and the controller (120) can access the second area (114) to read or store specific data.

[0091] FIG. 8 is a diagram illustrating the process of accessing a device-dedicated memory area according to one embodiment of the present disclosure.

[0092] The core unit (124) can immediately access the first area (112) when the value of a specific address bit that has been pre-set is set to a second value (e.g., '1'). The MM unit (126) and the snoop unit (128) can skip operations when the value of a specific address bit is set to a second value. Accordingly, the core unit (124) can immediately access the first area (112) based on a physical address.

[0093] Although the present disclosure has been described in relation to some embodiments, various modifications and changes may be made without departing from the scope of the present disclosure as understood by a person skilled in the art to which the invention of the present disclosure pertains. Furthermore, such modifications and changes should be considered to fall within the scope of the claims appended to this specification. Explanation of the symbols

[0094] 1: Computing System 100: Electronic device 200: Host device 110: Device memory 120: Controller 210: Host Memory 220: Host processor

Claims

Claim 1 An electronic device comprising: a memory including a first region and a second region associated with a host memory; and a controller configured to be connected to said memory, wherein the controller is configured to access said first region based on a physical addressing method and to access said second region based on a virtual addressing method. Claim 2 An electronic device according to claim 1, wherein the first region is a device-dedicated memory region of the electronic device and includes data associated with at least one of Code, Stack, or Heap at runtime of a specific program. Claim 3 An electronic device according to claim 1, wherein the second region is a host memory region and includes data that satisfies cache coherence with the host memory. Claim 4 An electronic device according to claim 1, wherein the controller is configured to determine whether to access the first region based on the physical addressing method or the second region based on the virtual addressing method, based on the value of a specific address bit received from a host processor. Claim 5 An electronic device according to claim 4, wherein the controller comprises a Memory Management (MM) unit and a Snoop unit, wherein the MM unit converts a virtual address space allocated to the host memory into a physical address space, the Snoop unit satisfies cache consistency between the physical address space and the second region, and the controller is configured to access the second region when the value of a specific address bit received from the host processor is a first value. Claim 6 In paragraph 5, the electronic device is configured such that the controller accesses the first region when the value of a specific address bit received from the host processor is a second value. Claim 7 A computing system comprising: a host device including a host processor and a host memory; and an electronic device, wherein the electronic device comprises: a memory including a first region and a second region associated with the host memory; and a controller configured to be connected to the memory and the host processor, wherein the controller is configured to access the first region based on a physical addressing method and access the second region based on a virtual addressing method. Claim 8 In claim 7, the first region is a device-dedicated memory region of the electronic device and includes data associated with at least one of Code, Stack, or Heap at runtime of a specific program, in a computing system. Claim 9 In claim 7, the second region is a host memory region and is a computing system containing data that satisfies cache coherence with said host memory. Claim 10 A computing system according to claim 7, wherein the controller is configured to determine, based on the value of a specific address bit received from the host processor, whether to access the first region based on the physical addressing method or to access the second region based on the virtual addressing method. Claim 11 A computing system according to claim 10, wherein the controller comprises a Memory Management (MM) unit and a Snoop unit, wherein the MM unit converts a virtual address space allocated to the host memory into a physical address space, the Snoop unit satisfies cache consistency between the physical address space and the second region, and the controller is configured to access the second region when the value of a specific address bit received from the host processor is a first value. Claim 12 In paragraph 11, the computing system is configured such that the controller accesses the first region when the value of a specific address bit received from the host processor is the second value. Claim 13 In claim 8, the computing system, wherein the runtime running on the host processor and the controller is configured to allocate an area associated with at least one of the code, stack, or heap at runtime of the specific program.

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