semiconductor device

Abstract

A semiconductor device having a novel configuration is provided. It includes a first memory cell, a sensing amplifier, a second memory cell, and an operation block. The first memory cell, the sensing amplifier, and the operation block are provided in a first device layer. The second memory cell is provided in a second device layer. The second device layer is provided on an upper layer of the first device layer. The second memory cell is electrically connected to the sensing amplifier and the first memory cell through a first bit line. The first memory cell is electrically connected to the operation block through a second bit line. The data transmitted to the operation block is data maintained in the second memory cell that is activated in the sensing amplifier and recorded in the first memory cell.

Description

Technology Field

[0001] In this specification, semiconductor devices, etc. are described.

[0002] Furthermore, one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification, etc. include semiconductor devices, imaging devices, display devices, light-emitting devices, capacitor devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, methods for driving the same, or methods for manufacturing the same. Background Technology

[0003] In recent years, the importance of measures against global warming has been increasing. Energy consumption continues to rise, yet carbon dioxide emissions, one of the causes of global warming, have not yet been reduced. Simply reducing energy consumption alone can sometimes lead to a decrease in convenience. To reduce energy consumption without compromising convenience, low-energy conversion technologies are becoming critical.

[0004] As performance improves in AI (Artificial Intelligence) technology, power consumption increases; therefore, active development of technologies for low power consumption is underway. In AI technology, the operation of sequentially reading data stored in memory circuits, performing calculations using said data with calculation circuits, and storing the data obtained from these calculations in memory is repeated. Consequently, the power required for data transfer between memory circuits and calculation circuits accounts for a large proportion of power consumption. As a countermeasure, a technology called so-called in-memory computing or near-memory computing has been proposed, which integrates memory circuits and calculation circuits using, for example, a transistor containing an oxide semiconductor (also called an OS transistor) (e.g., Patent Document 1). Prior art literature

[0005] U.S. Patent Application Publication US2021 / 0024083 The problem to be solved

[0006] When executing a series of computational processes required for AI technology in computational circuits, memory circuits capable of reading or writing large amounts of data at high speeds are necessary. While SRAM (Static Random Access Memory) memory cells are desirable for such memory circuits, they are disadvantageous in that, for example, the area per memory cell is large or power consumption during data retention is high. On the other hand, memory cells in memory circuits using OS transistors are advantageous in that, for example, power consumption during data retention is low and the number of memory cells per unit area can be increased by stacking them due to the high degree of freedom in placement; however, data reading or writing is slower than that of SRAM.

[0007] One embodiment of the present invention has as its objective to provide a semiconductor device capable of operating at high speed, consuming low power, and maintaining a large amount of data, while simultaneously executing a series of computational processes required for AI technology. Alternatively, one embodiment of the present invention has as its objective to provide a miniaturized semiconductor device. Alternatively, one embodiment has as its objective to provide a semiconductor device having a novel configuration.

[0008] Furthermore, one embodiment of the present invention does not necessarily need to solve all of the above problems, and it is sufficient if it can solve at least one problem. Also, the description of the above problems does not interfere with the existence of other problems. Problems other than these become naturally apparent from the description in the specification, claims, drawings, etc., and problems other than these can be derived from the description in the specification, claims, drawings, etc. means of solving the problem

[0009] One embodiment of the present invention is a semiconductor device comprising a first memory cell, a sensing amplifier, a second memory cell, and an operation block, wherein the first memory cell, the sensing amplifier, and the operation block are provided in a first element layer, the second memory cell is provided in a second element layer, the second element layer is provided in an upper layer of the first element layer, the second memory cell is electrically connected to the sensing amplifier and the first memory cell through a first bit line, the first memory cell is electrically connected to the operation block through a second bit line, and the data transmitted to the operation block is data maintained in the second memory cell that is activated in the sensing amplifier and recorded in the first memory cell.

[0010] One embodiment of the present invention is a semiconductor device comprising a first memory cell, a sensing amplifier, a second memory cell, and an operation block, wherein the first memory cell, the sensing amplifier, and the operation block are provided in a first element layer, the second memory cell is provided in a second element layer, the second element layer is provided in an upper layer of the first element layer, the second memory cell is electrically connected to the sensing amplifier and the first memory cell through a first bit line, the first memory cell is electrically connected to the operation block through a second bit line, and the data transmitted to the operation block is data maintained in the second memory cell that is activated in the sensing amplifier and recorded in the first memory cell, and the operation block is a product-sum operation unit, an activation function operation unit, a data conversion unit, a load / store unit, and a controller unit.

[0011] In a semiconductor device of one embodiment of the present invention, the first memory cell includes a first transistor, and the first transistor preferably includes a first semiconductor layer including silicon in a channel forming region.

[0012] In a semiconductor device of one embodiment of the present invention, the second memory cell includes a second transistor, and the second transistor preferably includes a second semiconductor layer including an oxide semiconductor in a channel forming region.

[0013] In a semiconductor device of one embodiment of the present invention, the first memory cell is preferably a memory cell of static random access memory.

[0014] In a semiconductor device of one embodiment of the present invention, the first bit line preferably includes a portion provided parallel to a direction perpendicular to the surface of a substrate provided with a first element layer between the second memory cell and the sensing amplifier and between the second memory cell and the first memory cell.

[0015] In a semiconductor device of one embodiment of the present invention, the redundancy operation unit includes an operation circuit and an analog-to-digital conversion circuit, wherein the operation circuit includes a cell array that performs redundancy operations and an input circuit that converts an input digital signal into an analog signal and inputs it to the cell array, and the analog-to-digital conversion circuit has the function of converting an analog signal output by the operation circuit into a digital signal, and the input circuit and the analog-to-digital conversion circuit are provided in a first device layer, and the cell array is preferably provided in a second device layer.

[0016] In addition, other embodiments of the present invention are described in the following embodiments and drawings. Effects of the invention

[0017] One embodiment of the present invention may provide a semiconductor device capable of operating at high speed, consuming low power, and maintaining a large amount of data, while simultaneously executing a series of computational processes required for AI technology. Alternatively, one embodiment of the present invention may provide a miniaturized semiconductor device. Alternatively, a semiconductor device having a novel configuration may be provided.

[0018] The description of multiple effects does not impede the existence of other effects. Furthermore, one embodiment of the present invention is not required to possess all of the exemplified effects. Additionally, in one embodiment of the present invention, problems, effects, and novel features other than those mentioned above become self-evident from the description and drawings of this specification. Brief explanation of the drawing

[0019] Figures 1 (A) and (B) are drawings illustrating examples of the configuration of a semiconductor device. Figure 2 is a diagram illustrating an example of the operation of a semiconductor device. Figures 3 (A) and (B) are drawings illustrating examples of the configuration of a semiconductor device. Figures 4 (A) and (B) are drawings illustrating examples of the configuration of a semiconductor device. Figures 5 (A) and (B) are drawings illustrating examples of the configuration of a semiconductor device. Figures 6 (A) to (C) are drawings illustrating examples of configurations of a semiconductor device. Figures 7 (A) to (G) are drawings illustrating examples of configurations of a semiconductor device. Figures 8 (A) to (C) are drawings illustrating examples of configurations of a semiconductor device. Figures 9 (A) and (B) are drawings illustrating examples of the configuration of a semiconductor device. Figures 10 (A) and (B) are drawings illustrating examples of the configuration of a semiconductor device. Figure 11 is a diagram illustrating an example of the configuration of a semiconductor device. Figures 12 (A) to (C) are drawings illustrating examples of configurations of a semiconductor device. Figures 13 (A) to (D) are drawings illustrating examples of configurations of a semiconductor device. Figure 14 is a timing chart illustrating an example of operation of a semiconductor device. FIG. 15 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. Figure 16 (A) is a diagram illustrating an example of the configuration of a transistor included in a semiconductor device. Figure 16 (B) is a diagram illustrating an equivalent circuit of a memory cell. Figures 17 (A) to (C) are cross-sectional views illustrating examples of the configuration of a transistor included in a semiconductor device. FIG. 18 (A) is a plan view illustrating an example of a transistor configuration included in a semiconductor device. FIG. 18 (B) to (D) are cross-sectional views illustrating examples of a transistor configuration included in a semiconductor device. Figure 19 (A) is a plan view illustrating an example configuration of a transistor included in a semiconductor device. Figures 19 (B) to (D) are cross-sectional views illustrating examples configurations of a transistor included in a semiconductor device. FIG. 20 is a cross-sectional view illustrating an example of the configuration of a semiconductor device. Figure 21 (A) is a diagram illustrating an example of the configuration of a transistor included in a semiconductor device. Figure 21 (B) is a diagram illustrating an equivalent circuit of a memory cell. Figures 22 (A) and (B) are plan views showing examples of the configuration of a transistor included in a semiconductor device, and Figure 22 (C) is a cross-sectional view showing examples of the configuration of a transistor included in a semiconductor device. Figures 23 (A) and (B) are cross-sectional views showing examples of the configuration of a transistor included in a semiconductor device. FIG. 24 is a cross-sectional view showing an example of the configuration of a transistor included in a semiconductor device. Figures 25 (A) and (B) are schematic diagrams showing examples of the configuration of a transistor included in a semiconductor device. Figures 26 (A) and (B) are plan views showing examples of the configuration of a transistor included in a semiconductor device, and Figures 26 (C) and (D) are cross-sectional views showing examples of the configuration of a transistor included in a semiconductor device. Figures 27 (A) to (D) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Figures 28 (A) to (D) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. Figures 29 (A) and (B) are drawings showing examples of electronic components. Figures 30 (A) to (D) are drawings illustrating examples of electronic components. Figures 31 (A) and (B) are drawings showing an example of an electronic device. Figures 32 (A) to (C) are drawings showing examples of electronic devices. Figure 33 is a diagram showing an example of a large computer. Specific details for implementing the invention

[0020] Embodiments of the present invention are described below. However, it is readily understood by those skilled in the art that one embodiment of the present invention is not limited to the description below, and that various changes to its form and details can be made without departing from the spirit and scope of the present invention. Therefore, one embodiment of the present invention is not to be interpreted as being limited to the description of the embodiments below.

[0021] In addition, the ordinal numbers 'first', 'second', and 'third' in this specification, etc. are attached to avoid confusion of components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of components. Also, for example, a component referred to as 'first' in one of the embodiments of this specification, etc. may become a component referred to as 'second' in another embodiment or claim. Also, for example, a component referred to as 'first' in one of the embodiments of this specification, etc. may be omitted in another embodiment or claim.

[0022] In drawings, the same reference numeral is assigned to identical elements, elements with the same function, elements of the same material, or elements formed simultaneously, and their repetitive descriptions are sometimes omitted.

[0023] In this specification, for example, the power potential VDD may be abbreviated as potential VDD, VDD, etc. The same applies to other components (e.g., signals, voltages, circuits, devices, electrodes, wiring, etc.).

[0024] In addition, when the same symbol is used for multiple elements and it is particularly necessary to distinguish them, identification symbols such as '_1', '_2', '[n]', or '[m, n]' are attached to the symbol. For example, the second wiring (GL) is written as wiring (GL[2]).

[0025] (Embodiment 1)

[0026] The configuration and operation of a semiconductor device, which is one embodiment of the present invention, will be described.

[0027] In addition, the term "semiconductor device" in this specification and others refers to any device capable of functioning by utilizing semiconductor characteristics. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are forms of semiconductor devices. Display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, capacitor devices, memory devices, semiconductor circuits, imaging devices, electronic devices, etc., may be said to include semiconductor devices.

[0028] (Example configuration of a semiconductor device (100))

[0029] FIG. 1 (A) is a schematic diagram for explaining a semiconductor device (100) which is one embodiment of the present invention. The semiconductor device (100) has the function of executing computational processing, such as redundancy processing, used in AI technology. A semiconductor device (100) capable of executing a series of computational processing required for AI technology is called an NPU (Neural-network Processing Unit or Neural Processing Unit). The semiconductor device (100) executes processing according to computational processing of a neural network using data maintained in a memory circuit. Specifically, it performs parallel processing of redundancy processing, computational processing of activation functions, computational processing of data conversion, and loading and storing of data according to various computational processing.

[0030] A semiconductor device (100) includes a device layer (10) and a device layer (40) provided by stacking on the device layer (10). In the schematic diagram shown in (A) of FIG. 1, the device layer (10) and the device layer (40) are shown separately to easily understand the arrangement of each element constituting the semiconductor device (100). Also, a device layer refers to a layer on which a device such as a transistor or a capacitor is provided.

[0031] The device layer (10) includes an interface section (12), a memory circuit section (11), and an operation block (14). The memory circuit section (11) includes a sensing amplifier section (20) and a memory circuit (30). The operation block (14) includes a controller section (15), a redundancy operation section (16), an activation function operation section (17), a data conversion section (18), and a load / store section (19).

[0032] In the schematic diagram shown in FIG. 1 (A), to explain the arrangement of each component, the direction perpendicular to the surface of the device layer (10) (e.g., the surface where the interlayer insulating layer is provided) or the direction substantially perpendicular is defined as the Z-axis direction. Additionally, for ease of understanding, the Z-axis direction may be referred to in the specification as the direction perpendicular to the surface of the device layer (10). Furthermore, "substantially perpendicular" refers to a state in which the components are arranged at an angle of 85° or greater and 95° or less.

[0033] In addition, the X direction, Y direction, and Z direction may be defined in the specification and drawings to explain the arrangement of each element. For example, in the schematic diagram shown in (A) of FIG. 1, the X direction, Y direction, and Z direction are defined to explain the arrangement of each element constituting the semiconductor device (100). Each of the X direction, Y direction, and Z direction is perpendicular to or substantially perpendicular to each other.

[0034] The device layer (10) includes a silicon transistor (Si transistor) in a semiconductor layer that includes a channel forming region. The device layer (10) is a device layer in which a semiconductor layer including a channel forming region is provided within a silicon substrate, or a device layer in which a silicon semiconductor layer including a channel forming region is bonded to a silicon substrate.

[0035] Additionally, the substrate provided to the device layer (10) is described as a silicon substrate, but the present embodiment is not limited thereto. Furthermore, a silicon substrate refers to a substrate made of silicon as a semiconductor material, for example, a single-crystal silicon substrate. In addition, the substrate may not be limited to silicon, and may use materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), etc.

[0036] In particular, highly crystalline silicon, such as single-crystal silicon or polycrystalline silicon, is used for the Si transistor included in the device layer (10). By including highly crystalline silicon in the device layer (10), high field-effect mobility can be realized, allowing for higher speed operation. Therefore, the device layer (10) can be provided with an interface section (12), a sensing amplifier section (20) and a memory circuit (30) included in the memory circuit section (11), and a controller section (15), a redundancy operation section (16), an activation function operation section (17), a data conversion section (18), and a load / store section (19) included in the operation block (14) by integrating them.

[0037] The device layer (40) includes a plurality of memory cells (41). In addition, although the device layer (40) in (A) of FIG. 1 is shown only above the memory circuit portion (11) included in the device layer (10), it can be provided at a position that overlaps with the device layer (10).

[0038] The memory cell (41) functions as a memory circuit that retains data. The memory cell (41) is connected to the sensing amplifier section (20) and the memory circuit (30) included in the memory circuit section (11). The memory cell (41) retains data used in the operation block (14) through the sensing amplifier section (20) and the memory circuit (30). The data stored (retained) in the memory cell (41) is data (weight data) corresponding to the weight parameters used in the integration operation of the neural network. By making the weight data digital data, it is possible to create a semiconductor device that is resistant to noise and capable of high-speed operation. Additionally, the weight data may be analog data.

[0039] The device layer (40) includes a transistor (OS transistor) including an oxide semiconductor in a semiconductor layer including a channel forming region. The device layer (40) including the OS transistor can be provided by stacking it on the device layer (10). By providing the device layer (40) on the device layer (10), the transistor density per unit area can be increased. Therefore, the memory capacity in a memory circuit including a memory cell (41) provided in the device layer (40) can be increased.

[0040] Examples of metal oxides applied to OS transistors include indium oxide (In oxide), gallium oxide (Ga oxide), and zinc oxide (Zn oxide). Additionally, In-Zn oxide may be used as a metal oxide applied to OS transistors. Furthermore, it is preferable that the metal oxide comprises one or more selected from indium, element M, and zinc. Additionally, element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, and tin.

[0041] FIG. 1 (B) is a block diagram for explaining the sensing amplifier unit (20) and the memory circuit (30) included in the memory circuit unit (11). FIG. 1 (B) also shows a driving circuit (71) that outputs a signal (WEN) and a driving circuit (72) that outputs a signal (REN). The signal (WEN) is a signal that controls the recording of data in the sensing amplifier unit (20) and the memory circuit (30) included in the memory circuit unit (11). The signal (REN) is a signal that controls the reading of data in the sensing amplifier unit (20) and the memory circuit (30) included in the memory circuit unit (11).

[0042] In the memory circuit section (11), the sensing amplifier section (20) includes a plurality of sensing amplifiers (21). The memory circuit (30) includes a plurality of memory cells (31). The memory cell (31) may be referred to as the first memory cell. The memory cell (41) provided in the above-described device layer (40) may be referred to as the second memory cell.

[0043] The interface section (12) is the input record data (W DATA The potential of the bit line (OBL) is controlled according to ). The interface unit (12) amplifies the potential of the bit line (OBL) and reads the data (R DATA Outputs as ). Record data (W DATA In addition to weight data, there is input data that is input to the operation block (14) and used for processing operations with the weight data.

[0044] The bit line (OBL) is a wire for bidirectional input and output of data between the interface unit (12) and the detection amplifier (21). For example, by supplying data from the interface unit (12) to the bit line (OBL) to activate a bit line pair (bit line (BL)) connecting the detection amplifier (21) and the memory cell (41), weight data can be written to the memory cell (41). Additionally, the bit line (OBL) can read output data through the interface unit (12) by selecting a memory cell (31) that holds output data obtained from the operation block (14).

[0045] The bit line (SBL) is a wire for bidirectional input and output of data between the memory cell (31) and the operation block (14). For example, by selecting the memory cell (31) in which weight data is maintained, data can be output to the operation block (14) through the bit line (SBL). Additionally, the output data obtained from the operation block (14) can be maintained in the memory cell by selecting the selected memory cell (31).

[0046] When the data input / output via the bit line (OBL, SBL) is multi-bit, there are multiple wires. Also, the bit line (BL) connected to the memory cell (41) may be referred to as the first bit line. The bit line (OBL) connected to the memory cell (31) may be referred to as the second bit line.

[0047] The sensing amplifier (21) is connected to the memory cell (41) through a bit line pair (bit line (BL) and inverted bit line (BLB)) provided in the Z direction. The sensing amplifier (21) is positioned in close proximity to the memory cell (31). The recording and reading of data by the sensing amplifier (21) is controlled by the driving circuit (71) and the driving circuit (72). The bit line (BL) and the inverted bit line (BLB) are sometimes referred to as a bit line pair (BL-BLB). Similarly, the bit line (OBL) and the inverted bit line (OBLB), and the bit line (SBL) and the inverted bit line (SBLB) are sometimes referred to as a bit line pair (OBL-OBLB) and a bit line pair (SBL-SBLB), respectively.

[0048] The memory cell (31) can update the data by selecting weight data maintained in the memory cell (41). Additionally, the memory cell (31) can update the data by selecting output data obtained from the operation block (14). The memory cell (31) is connected to the memory cell (41) through a bit line pair (BL-BLB) provided in the Z direction (a direction parallel to the direction perpendicular to the surface of the substrate). The memory cell (31) is positioned in close proximity to the sensing amplifier (21). The memory cell (31) is connected to the sensing amplifier (21). The recording and reading of data in the memory cell (31) are controlled by the driving circuit (71) and the driving circuit (72).

[0049] A memory cell with a fast access speed is applied to the memory cell (31). For example, as the memory cell (31), a memory cell of static random access memory (hereinafter SRAM) is preferred. A memory cell (31) placed near the operation block (14) may be referred to as a scratchpad memory. Although the memory capacity of the memory circuit (30) containing the memory cell (31) is smaller than the memory capacity of the memory circuit containing the memory cell (41), it is preferred as a memory for maintaining weight data in the operation block (14) because the access speed is fast.

[0050] The controller unit (15) included in the operation block (14) is a circuit for controlling the operation processing performed in the operation block (14). The redundancy operation unit (16) included in the operation block (14) is a circuit for performing redundancy operation processing used on weight data input to the operation block (14). The activation function operation unit (17) included in the operation block (14) is a circuit for performing processing by an activation function, such as a rectified linear function, based on the operation result obtained from the redundancy operation unit (16) within the operation block (14). The data conversion unit (18) included in the operation block (14) is a circuit for performing data conversion for preprocessing based on the operation result obtained from the activation function operation unit (17) within the operation block (14). The load store unit (19) included in the operation block (14) is a circuit for performing the input or output of data for the operation processing performed within the operation block (14).

[0051] In this way, the semiconductor device (100) is configured with a circuit specialized for the computational processing of a neural network within the computational block (14). By configuring it as described above, the power consumption required to perform computational processing can be reduced compared to when the same computational processing is performed using general-purpose computational circuits such as CPUs and GPUs.

[0052] FIG. 2 is a schematic diagram for explaining the operation of a semiconductor device (100) of one form of the present invention described using (A) and (B) of FIG. 1. FIG. 2 shows data maintained in a memory cell (41) that is transferred according to a clock cycle, data maintained in a memory cell (31), processing of operations in a redundancy operation unit (16), processing of operations in an activation function operation unit (17), processing of operations in a data conversion unit (18), and processing of input or output of data in a load store unit (19).

[0053] As described above, the memory circuit including the memory cell (41) has a large memory capacity. The memory cell (41) can store more data than the amount of data maintained in the memory cell (31). As such data, data (OS_1 to OS_N) (N is an integer greater than or equal to 2) is shown in FIG. 2. The data (OS_1 to OS_N) is data that is stored in the memory cell (41) in advance before performing operations in the semiconductor device (100). The data maintained in the memory cell (41) also functions as a cache for the data maintained in the memory cell (31).

[0054] Data is transferred from memory cell (41) to memory cell (31) at the timing of time T01. In FIG. 2, data (SR1) is shown as the data transferred to memory cell (31). Data (SR1) is data corresponding to the weight data used in the operation block (14). Afterwards, the integration operation unit (16) performs an operation processing (MAC1) to perform integration operations on the input data and data (SR1) that are input to the operation block (14). Afterwards, the activation function operation unit (17) performs an operation processing (AF1) on the data obtained from the operation processing (MAC1). Afterwards, the data conversion unit (18) performs an operation processing (DC1) on the data obtained from the operation processing (AF1). Afterwards, the load store unit (19) performs an input or output processing (LS1) on the data obtained from the operation processing (DC1).

[0055] After time T01, the data required from the operation block (14) in the memory cell (31) is read from the memory cell (41) to the memory cell (31). Below, as shown in FIG. 2, operation processing (MAC2 to MAC8), operation processing (AF2 to AF7), operation processing (DC2 to DC6), and processing (LS2 to LS5) are executed by pipeline processing.

[0056] In the memory cell (41), a large amount of data corresponding to weight data can be maintained. Therefore, it is possible to store the data required in the memory cell (31) in the memory cell (41). The memory cell (31) can update the data (SR1 to SR9) required by the operation block (14) based on the data maintained in the memory cell (41) without accessing an external memory circuit. Therefore, it is possible to provide a semiconductor device that operates at high speed, has low power consumption, can maintain a large amount of data, and can simultaneously execute a series of computational processes required for AI technology.

[0057] Additionally, data maintained in the memory cell (41) can be rewritten separately from the data maintained in the memory cell (31). For example, as shown in FIG. 2, data maintained at the timing of time T02 can be rewritten from data (OS_2) to data (OS_2x). Also, as shown in FIG. 2, for example, data maintained at the timing of time T03 can be rewritten from data (OS_1) to data (OS_1x). Also, as shown in FIG. 2, for example, data (OS_N) can be maintained for a certain period without performing rewriting.

[0058] A semiconductor device according to one embodiment of the present invention is configured to have a plurality of sensing amplifiers (21) and memory cells (31) arranged directly below a memory cell (41). Therefore, by arranging the memory cell (41), the sensing amplifier (21), and the memory cell (31) in close proximity, the updating of data maintained in the memory cell (31) can be performed at high speed without accessing an external memory circuit. In addition, the memory cell (31), which has excellent access speed, is arranged near the operation block (14) so ​​that data can be input and output bidirectionally between it and the operation block (14). Therefore, near-memory computing can be realized, and the power consumption required for data transmission between circuits can be reduced.

[0059] FIG. 3 (A) is a schematic diagram illustrating an example configuration of a memory cell (41), a sensing amplifier (21), and a memory cell (31). FIG. 3 (A) shows a configuration in which a device layer (40) containing a memory cell (41) is provided above the area where the sensing amplifier (21) and the memory cell (31) described using FIG. 1 (B) are provided. Additionally, to improve visibility, the memory cell (41) above the sensing amplifier (21) is omitted in FIG. 3 (A).

[0060] The memory cell (41) is connected to the detection amplifier (21) and the memory cell (31) via a bit line pair (BL-BLB). The detection amplifier (21) is connected to the bit line (OBL) (bit line pair). The memory cell (31) is connected to the bit line (SBL) (bit line pair).

[0061] FIG. 3 (B) is a schematic diagram for explaining the transistor (53) provided to the device layer (10) and the transistor (51) provided to the device layer (40) in the schematic diagram in which the device layer (10) and the device layer (40) shown in FIG. 1 (A) are stacked. Also, FIG. 3 (B) shows a bit line pair (BL-BLB) connecting the memory cell (41), the sensing amplifier (21), and the memory cell (31) shown in FIG. 3 (A).

[0062] By using an oxide semiconductor (metal oxide) in the semiconductor layer (52) included in the transistor (51), it is possible to make a memory cell (41) composed of the above-described OS transistor.

[0063] By using silicon in the semiconductor layer (54) included in the transistor (53), a sensing amplifier (21) and a memory cell (31) can be provided in the device layer (10) composed of the above-described Si transistor.

[0064] By providing a device layer (40) on which a memory cell (41) is provided on a device layer on which a sensing amplifier (21) and a memory cell (31) are provided, the number of memory circuits per unit area, i.e., the memory capacity, can be increased compared to the case where the memory cell (41), the sensing amplifier (21), and the memory cell (31) are placed on the same layer. When the memory capacity is increased, power consumption can be reduced because the number of data transfers required for computational processing on the semiconductor device from an external memory device can be reduced.

[0065] In the case where the memory circuit, such as the memory cell (41), and the memory circuit, such as the memory cell (31), are different chips, the bus width is limited according to the number of pins of the chip. Meanwhile, in a configuration in which the memory cell (41) and the memory cell (31) are stacked as in one embodiment of the present invention, the number of parallel data required for computation processing can be increased according to the opening providing bit line pairs (BL-BLB), so efficient computation processing can be performed.

[0066] In FIG. 4 (A), a sensing amplifier (21_P, 21_Q) is shown as the sensing amplifier (21) of the schematic diagram shown in FIG. 3 (A), and a memory cell (31_P, 31_Q) is shown as the memory cell (31) of the schematic diagram shown in FIG. 3 (A). Additionally, a device layer (40) including memory cells (41P, 41Q) is shown as the memory cell (41) of the schematic diagram shown in FIG. 3 (A).

[0067] The sensing amplifiers (21_P, 21_Q) are each connected to bit lines (OBL_P, OBL_Q). By connecting the interface unit (12) and the sensing amplifiers (21_P, 21_Q) through multiple bit lines (OBL_P, OBL_Q), it is possible to configure the system to record or read different data at the same timing.

[0068] Memory cells (31_P, 31_Q) are each connected to bit lines (SBL_P, SBL_Q). By connecting the operation block (14) and memory cells (31_P, 31_Q) through multiple bit lines (SBL_P, SBL_Q), it is possible to configure the system to write or read different data at the same time.

[0069] The memory cell (41P) is connected to the bit line pair (BL_P, BLB_P). The memory cell (41Q) is connected to the bit line pair (BL_Q, BLB_Q). It is preferable that the bit line pair (BL_P, BLB_P) and the bit line pair (BL_Q, BLB_Q) are not connected. By configuring it as above, it is possible to perform the recording and reading of different weight data in the sensing amplifier (21_P), the sensing amplifier (21_Q), the memory cell (31_P), and the memory cell (31_Q), or to perform computation processing using the weight data.

[0070] FIG. 4(B) is a diagram illustrating a bit line (BL_V) connecting the sensing amplifier (21_P) and memory cell (31_P) and memory cell (41P) shown in FIG. 4(A), and the sensing amplifier (21_Q) and memory cell (31_Q) and memory cell (41Q). As shown in FIG. 4(A) and (B), the bit line (BL_V) is a bit line provided in the Z direction (a direction parallel to the direction perpendicular to the surface of the substrate).

[0071] Also, FIG. 4 (B) is a diagram showing bit lines (BL_LD, BL_RD) connected to a bit line (BL_V) and provided to a device layer (40). It is preferable that the lengths of the bit lines (BL_LD, BL_RD) be the same. That is, it is preferable that the opening for providing the bit line (BL_V) be provided near the center of the bit line (BL) provided to the device layer (40). By configuring it as above, the distance between the sensing amplifier (21) and the memory cell (31) and the memory cell (41) can be made equal, and thus the parasitic capacitance between the bit line pairs (BL-BLB) can be made equal.

[0072] The semiconductor device (100A) shown in FIG. 5 (A) is a modified example of the semiconductor device (100) shown in FIG. 3 (A). FIG. 5 (A) is a schematic diagram showing a case where the device layer (40) of FIG. 3 (A) is provided by stacking a plurality of device layers (40_1, 40_2).

[0073] The semiconductor device (100A) shown in (A) of FIG. 5 includes device layers (40_1, 40_2) in which a plurality of memory cells (41) are respectively arranged. By adopting the above configuration, a manufacturing process using the same photomask can be employed in the plurality of device layers (40_1, 40_2). Therefore, memory cells (41) can be manufactured in a vertical direction by repeatedly using the same manufacturing process, thereby realizing a reduction in manufacturing costs.

[0074] FIG. 5(B) is a schematic diagram showing device layers (40_1 to 40_n) (where n is an integer greater than or equal to 2) including the device layers (40_1, 40_2) shown in FIG. 5(A). FIG. 5(B) also shows a bit line pair (BL-BLB) connecting the memory cell (41), the sensing amplifier (21), and the memory cell (31) shown in FIG. 5(A). As shown in FIG. 5(B), in the semiconductor device (100A), a plurality of device layers (40_1 to 40_n) are provided stacked in a direction perpendicular to the surface of the device layer (10) or substantially perpendicular to it. By making the above configuration, the number of memory cells (41) arranged per unit area can be increased. Therefore, the memory capacity of the memory circuit composed of memory cells (41) can be increased.

[0075] The configuration of (B) in FIG. 5 can increase the number of memory cells (41) connected to the bit line pair (BL-BLB) and shorten the bit line pair (BL-BLB) connecting the memory cell (41), the sensing amplifier (21), and the memory cell (31). Since the wiring distance can be shortened by stacking the device layer (40), the parasitic capacitance between the bit line pairs (BL-BLB) can be reduced, thereby reducing power consumption. In addition, the number of bits of the weight data can be increased while reading weight data from the memory cell (41) to the sensing amplifier (21) at high speed.

[0076] (Example of configuration of memory cell (41))

[0077] The circuit configuration of a memory cell that can be applied to a memory cell (41) is described. Additionally, the memory cell (41) is a memory cell that includes an OS transistor. A memory that includes a memory cell that includes an OS transistor is sometimes referred to as an 'OS memory'.

[0078] The OS transistor has a very small off-current. Therefore, the charge corresponding to the data recorded in the memory cell (41) can be maintained for a long time. That is, data recorded once in the memory cell (41) can be maintained for a long time. Therefore, the power consumption of a semiconductor device of one form of the present invention can be reduced by lowering the data refresh frequency.

[0079] FIG. 6 (A) is a diagram illustrating a memory cell array (42) including a plurality of memory cells (41). FIG. 6 (A) shows word lines (WL_1 to WL_m) and bit lines (BL_1 to BL_n) arranged side by side in the direction of an m row n column matrix (m, n is a natural number greater than or equal to 2). Also, memory cells (41) connected to each word line (WL) and bit line (BL) are shown. Additionally, a signal for driving the memory cells (41) supplied to the word lines and bit lines can be output from the driving circuit (71) and driving circuit (72) shown in FIG. 1 (B).

[0080] FIG. 6 (B) is a circuit diagram illustrating an example of a circuit configuration applicable to a memory cell (41). The memory cell (41) includes a transistor (M1) and a capacitor (C1) (also called a capacitive element). The transistor (M1) is connected to a word line (WL), a bit line (BL), and a capacitor (C1). Additionally, the capacitor (C1) is connected to a wire (PL) that functions as a capacitive line. For example, a ground potential GND (low-level power supply potential) is input to the wire (PL). Also, FIG. 6 (C) is a circuit block corresponding to the circuit diagram of FIG. 6 (B).

[0081] The memory cell (41) shown in Fig. 6 (B) can be a memory cell of a 1T1C type DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM refers to a RAM containing a 1T (transistor) 1C (capacitance element) type memory cell. DOSRAM is a DRAM formed using an OS transistor and is a memory that temporarily stores information transmitted from the outside. DOSRAM is a memory that utilizes the fact that the off-current of the OS transistor is small. Since DOSRAM is a 1T1C type memory cell, a large storage capacity can be realized in the memory cell array (42). In addition, by using an OS transistor, the data retention period can be extended compared to a DRAM containing a Si transistor.

[0082] The circuit configuration applicable to the memory cell (41) is not limited to the 1T1C type DOSRAM of FIG. 6 (B). For example, FIG. 7 (A) shows another configuration example of a 1T1C type memory cell applicable to a DOSRAM. The memory cell (41A) shown in FIG. 7 (A) is different from the memory cell (41) shown in FIG. 6 (B) in that the transistor (M1) is an OS transistor including a back gate, and the back gate is connected to a wiring (BGL). By making the configuration including a wiring (BGL), the transistor (M1) can be made into a transistor with improved electrical characteristics.

[0083] The memory cell (41) containing the OS transistor can be a NOSRAM (Nonvolatile Oxide Semiconductor Random Access Memory). The NOSRAM is a memory cell that is a 2-transistor type (2T) or 3-transistor type (3T) gain cell. Since the NOSRAM rewrites data by charging and discharging a capacitor, in principle there is no limit to the number of rewrite cycles and energy consumption is low. Therefore, the NOSRAM is a memory capable of high-speed operation, low power consumption, and high rewrite resistance. In addition, the NOSRAM is suitable for long-term data retention because it enables non-destructive reading of recorded data.

[0084] The memory cell (41B) shown in (B) of FIG. 7 is a circuit corresponding to a 2T type NOSRAM. The memory cell (41B) includes a transistor (M1), a transistor (M2), and a capacitor (C1). The transistors (M1, M2) are a write transistor and a read transistor, respectively. The transistors (M1) and (M2) may be OS transistors with semiconductor layers placed on different layers, or OS transistors with semiconductor layers placed on the same layer. The memory cell (41B) is an example of being connected to a write bit line (WBL), a read bit line (RBL), a write word line (WWL), a read word line (RWL), and a wire (SL).

[0085] The memory cell (41C) shown in (C) of FIG. 7 is a circuit corresponding to a 3T-type NOSRAM. The memory cell (41C) includes a transistor (M1), a transistor (M2), a transistor (M3), and a capacitor (C1). The transistors (M1, M2, M3) are a write transistor, a read transistor, and a select transistor, respectively. By configuring the circuit to include the transistor (M3), the current flowing between the source line and the read bit line (RBL) can be more reliably blocked regardless of the conduction state of the transistor (M2). The transistors (M1), M2, and M3 may be OS transistors with semiconductor layers placed on different layers, or OS transistors with semiconductor layers placed on the same layer.

[0086] Since the write transistor is configured with an OS transistor, the charge corresponding to the data can be continuously maintained by turning off the write transistor. Therefore, the memory cells (41B, 41C) do not consume power to maintain the data. Thus, the memory cells (41B, 41C) can maintain data for a long period and function as memory cells with low power consumption. In addition, the gate of the read transistor functions as a node that maintains the charge corresponding to the data. The read transistor has the function of flowing current according to the potential of the node that maintains the charge corresponding to the data. The select transistor controls the current flowing through the read transistor.

[0087] Another configuration example of a 2T type gain cell is shown in FIG. 7 (D). The memory cell (41D) shown in FIG. 7 (D) is different from the memory cell (41B) shown in FIG. 7 (B) in that the transistors (M1, M2) are each OS transistors including a back gate, and the back gate is connected to the wiring (BGL). For example, a ground potential GND (low-level side power potential) is input to the wiring (BGL). By configuring it to include the wiring (BGL), the transistors (M1, M2) can be transistors with improved electrical characteristics.

[0088] Another configuration example of a 3T-type gain cell is shown in FIG. 7 (E). The memory cell (41E) shown in FIG. 7 (E) is different from the memory cell (41C) shown in FIG. 7 (C) in that the transistors (M1, M2, M3) are each OS transistors including a back gate, and the back gate is connected to the wiring (BGL). For example, a ground potential GND (low-level side power potential) is input to the wiring (BGL). By configuring it to include the wiring (BGL), the transistors (M1, M2, M3) can be transistors with improved electrical characteristics.

[0089] Another configuration example of a 2T type gain cell is shown in (F) of FIG. 7. The memory cell (41F) shown in (F) of FIG. 7 differs from the memory cell (41B) shown in (B) of FIG. 7 in that the capacitor (C1) and wiring (SL) are omitted by using the gate capacitance of the read transistor. By omitting the capacitor (C1), the semiconductor device can be miniaturized.

[0090] The transistors (M1, M2) included in the 2T type gain cell shown in (F) of FIG. 7 are preferably vertical transistors in which the source electrode and the drain electrode are located at different heights. In a vertical transistor, current flows in the height direction (Z direction) in the channel formation region of the semiconductor layer. That is, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, the above-described vertical transistor may be called a VFET (Vertical Field Effect Transistor), a vertical channel transistor, a vertical channel type transistor, or a vertical transistor.

[0091] Since vertical transistors have a configuration in which at least a portion of the source region, channel formation region, and drain region overlap when viewed in a plane, they can reduce the occupied area (also known as footprint) compared to horizontal transistors (also called planar transistors) where the source and drain electrodes are located at the same height. Additionally, because they have a structure that allows for a shorter channel length and a larger channel width, they can reduce the on-resistance (increase the on-current).

[0092] Another configuration example of a 3T-type gain cell is shown in FIG. 7 (G). The memory cell (41G) shown in FIG. 7 (G) differs from the memory cell (41C) shown in FIG. 7 (C) in that the capacitor (C1) and wiring (PL) are omitted by using the gate capacitance of the read transistor. By making the transistors (M1, M2, M3) included in the 3T-type gain cell shown in FIG. 7 (G) into vertical transistors in which the source electrode and the drain electrode are located at different heights, the occupied area (also called footprint) can be reduced and the on-resistance can be reduced (the on-current can be increased).

[0093] (Example of configuration of the detection amplifier (21))

[0094] An example of a circuit configuration of a sensing amplifier (21) is described. Figure 8 (A) is a circuit diagram of a sensing amplifier (21). Figure 8 (B) is a circuit block corresponding to the circuit diagram. In addition, Figure 8 (C) shows an example of a configuration combining the circuit block of the memory cell (41) shown in Figure 6 (C) and the circuit block of the sensing amplifier (21) shown in Figure 8 (B).

[0095] The sensing amplifier (21) shown in (A) of FIG. 8 includes an amplification circuit (61), a precharge circuit (62), a precharge circuit (63), and a switch circuit (64). The amplification circuit (61), the precharge circuit (62), the precharge circuit (63), and the switch circuit (64) are each connected to a bit line pair (BL-BLB). Additionally, a signal for driving the sensing amplifier (21) can be output from the driving circuit (71) and the driving circuit (72) shown in (B) of FIG. 1.

[0096] The amplifier circuit (61) has the function of outputting a potential corresponding to one of the two levels of data to the bit line (BL) and outputting a potential corresponding to the other of the two levels of data to the inverted bit line (BLB) by applying a predetermined potential to each of the wiring (SAP) and wiring (SAN). The amplifier circuit (61) includes a transistor (61_1), a transistor (61_2), a transistor (61_3), and a transistor (61_4). Each of the transistors (61_1) and (61_2) is a p-channel type transistor. Each of the transistors (61_3) and (61_4) is an n-channel type transistor. The transistors (61_1) and (61_3) form an inverter circuit that takes the inverted bit line (BLB) as an input, takes the bit line (BL) as an output, uses the wiring (SAP) as a high-potential power line, and uses the wiring (SAN) as a low-potential power line. Transistors (61_2) and (61_4) form an inverter circuit that takes a bit line (BL) as an input, an inverted bit line (BLB) as an output, uses a wire (SAP) as a high-potential power line, and uses a wire (SAN) as a low-potential power line.

[0097] The precharge circuit (62) has the function of precharging a bit line pair (BL-BLB) to a potential VPRE according to a signal (EQB). Specifically, the precharge circuit (62) includes a transistor (62_1), a transistor (62_2), and a transistor (62_3). Each of the transistors (62_1), (62_2), and (62_3) is a p-channel type transistor. The transistor (62_1) has the function of making the bit line pair (BL-BLB) conduct or non-conduct depending on the signal (EQB). The transistor (62_2) has the function of precharging a bit line (BL) to a potential VPRE according to the signal (EQB). The transistor (62_3) has the function of precharging an inverted bit line (BLB) to a potential VPRE according to the signal (EQB).

[0098] The precharge circuit (63) has the function of precharging bit line pairs (BL-BLB) to a potential VPRE according to a signal (EQ). Specifically, the precharge circuit (63) includes a transistor (63_1), a transistor (63_2), and a transistor (63_3). Each of the transistors (63_1), (63_2), and (63_3) is an n-channel type transistor. The transistor (63_1) has the function of making the bit line pairs (BL-BLB) conduct or non-conduct depending on the signal (EQ). The transistor (63_2) has the function of precharging bit line (BL) to a potential VPRE according to the signal (EQ). The transistor (63_3) has the function of precharging inverted bit line (BLB) to a potential VPRE according to the signal (EQ).

[0099] The switch circuit (64) has the function of making the bit line pair (BL-BLB) and the bit line (OBL) (bit line pair (OBL-OBLB)) conduct or non-conduct depending on the column selection signal (CSE). Specifically, the switch circuit (64) includes a transistor (64_1) and a transistor (64_2). Each of the transistors (64_1) and (64_2) is an n-channel type transistor. The transistor (64_1) has the function of making the bit line pair (BL-BLB) and the bit line (BL) and bit line (OBL) conduct or non-conduct depending on the column selection signal (CSE). The transistor (64_2) has the function of making the bit line pair (BL-BLB) and the bit line pair (OBL-OBLB) conduct or non-conduct depending on the column selection signal (CSE).

[0100] Fig. 8 (B) is a circuit block corresponding to the circuit diagram of the sensing amplifier (21) described using Fig. 8 (A). In addition, Fig. 8 (C) shows an example configuration combining the circuit block of the sensing amplifier (21) shown in Fig. 8 (B) and the circuit block of the memory cell (41) shown in Fig. 6 (C).

[0101] In the configuration of the sensing amplifier (21) shown in (A) to (C) of FIG. 8, the potential difference between the bit line (BL) and the inverted bit line (BLB), which fluctuates according to the charge maintained in the memory cell (41) by the data reading operation from the memory cell (41), can be amplified and output to the bit line pair (OBL-OBLB) according to the column selection signal (CSE). In addition, in the configuration of the sensing amplifier (21) shown in (A) to (C) of FIG. 8, the potential difference of the bit line pair (OBL-OBLB) can be applied to the bit line pair (BL-BLB) according to the column selection signal (CSE), and the amplified potential difference can be recorded as data in the memory cell (41) connected to the bit line pair (BL-BLB).

[0102] (Example of configuration of memory cell (31))

[0103] The circuit configuration of a memory cell applicable to a memory cell (31) is described. Additionally, the memory cell (31) is a memory cell including a Si transistor. As described above, the memory cell (31) is a memory cell applicable to an SRAM with a fast access speed. In particular, a memory cell of a multi-port SRAM is preferred.

[0104] Figure 9 (A) shows an example of a memory cell of a multi-port SRAM that can be applied to a memory cell (31).

[0105] Figure 9 (A) shows a memory cell (31A) including transistors (M1A, M1B, M6A, M6B), inverters (INV1, INV2), bit lines (BL, SBL), inverted bit lines (BLB, SBLB), and word lines (WL1, WL2). Additionally, a signal for driving the memory cell (31A) can be output from the driving circuit (71) and driving circuit (72) shown in Figure 1 (B).

[0106] The bit line (BL) and inverted bit line (BLB) shown in (A) of FIG. 9 correspond to a bit line pair (BL-BLB) connected to the memory cell (41) and detection amplifier (21) described above. Additionally, the bit line (SBL, SBLB) corresponds to a bit line pair of the bit line (SBL) connected to the operation block (14) described above. The word line (WL1) is a word line for controlling the recording of data supplied to the bit line pair (BL-BLB) to the memory cell (31A) and the reading of the bit line pair (BL-BLB) of data maintained in the memory cell (31A). The word line (WL2) is a word line for controlling the recording of data supplied to the bit line pair of the bit line (SBL) connected to the operation block (14) to the memory cell (31A) and the reading of the bit line pair of the bit line (SBL) connected to the operation block (14) of data maintained in the memory cell (31A).

[0107] Also, (B) of FIG. 9 shows an example of a memory cell of a multi-port SRAM that can be applied to a memory cell (31). Additionally, a signal for driving the memory cell (31B) can be output from the driving circuit (71) and the driving circuit (72) shown in (B) of FIG. 1.

[0108] Figure 9 (B) shows a memory cell (31B) including transistors (M1A, M6A, M7, M8), inverters (INV1, INV2), bit line (BL), inverted bit line (BLB), bit line (SBL), and word line (WL1, WL2).

[0109] The bit line (BL) and inverted bit line (BLB) shown in (B) of FIG. 9 correspond to the bit line pair (BL-BLB) connected to the memory cell (41) and detection amplifier (21) described above. Additionally, the bit line (SBL) corresponds to the bit line (SBL) connected to the operation block (14) described above. The word line (WL1) is a word line for controlling the writing of data supplied to the bit line pair (BL-BLB) to the memory cell (31B) and the reading of the bit line pair (BL-BLB) of data maintained in the memory cell (31B). The word line (WL2) is a word line for controlling the reading of the bit line (SBL) connected to the operation block (14) of data maintained in the memory cell (31B).

[0110] In one embodiment of the present invention, it is preferable that the recording and reading of data for the memory cell (31) be controlled separately, such as the memory cell of the multiport SRAM shown in (A) of FIG. 9. By making the above configuration, it is possible to achieve both an improvement in the speed at which the operation block (14) accesses the data maintained in the memory cell (31) and the rewriting of the data of the memory cell (31) based on the large amount of data maintained in the memory cell (41).

[0111] As described above, a semiconductor device according to one embodiment of the present invention is configured to have a plurality of sensing amplifiers (21) and memory cells (31) arranged directly below a memory cell (41). Therefore, by arranging the memory cell (41), the sensing amplifier (21), and the memory cell (31) in close proximity, the updating of data maintained in the memory cell (31) can be performed at high speed. In addition, the memory cell (31), which has excellent access speed, is arranged close to the operation block (14). Therefore, near-memory computing can be realized, and the power consumption required for data transmission between circuits can be reduced.

[0112] The configurations, structures, methods, etc. described in this embodiment may be used in appropriate combination with the configurations, structures, methods, etc. described in other embodiments, etc.

[0113] (Embodiment 2)

[0114] In this embodiment, an example of a redundancy operation unit applicable to a semiconductor device of one form of the present invention is described.

[0115] <Example of configuration for redundancy operation unit>

[0116] Figure 10 (A) is a block diagram illustrating an example of the configuration of a redundancy operation unit (16A) that can be applied to a redundancy operation unit (16) included in a semiconductor device (100) described using Figure 1 (A) of the preceding embodiment 1.

[0117] The red-coding operation unit (16A) includes an operation circuit (MAC1) and an analog-to-digital conversion circuit (79).

[0118] The operation circuit (MAC1) is a digital signal (D IND By converting ) into an analog signal and executing an integration operation between the first data (e.g., weight data) and the second data (e.g., input data), an analog signal (D) according to the integration operation is obtained. MACA It has the function of outputting ).

[0119] The analog-to-digital conversion circuit (79) is an analog signal (D) output by the operation circuit (MAC1). MACA ) digital signal (D MACD It converts into ) and has the function of transmitting and receiving signals with other circuits included in the operation block (14) in addition to the memory circuit (11) (controller (15), activation function operation unit (17), data conversion unit (18), and load store unit (19)).

[0120] The operation circuit (MAC1) includes an input circuit (WCS), an input circuit (XCS), a control circuit (WSD), and a cell array (CA).

[0121] The operation circuit (MAC1) is a circuit that performs an operation of combining the first data (weighted data) and the second data (input data) based on the potential maintained in each cell. In addition, the first data and the second data can be analog data or multi-level data (discrete data), for example.

[0122] The input circuit (WCS) and the input circuit (XCS) have the function of converting the first data and second data of a digital signal supplied from the outside into the first data and second data of an analog signal and supplying them to a cell for performing a redundancy operation included in the operation circuit (MAC1). In addition, the control circuit (WSD) has the function of outputting a signal to control the cell for performing a redundancy operation included in the operation circuit (MAC1).

[0123] Figure 10 (B) is a block diagram of a semiconductor device (100A) in which the red-setting operation unit (16) in the configuration of the semiconductor device (100) described using Figure 1 (A) of the preceding embodiment 1 is changed to the red-setting operation unit (16A) described using Figure 10 (A).

[0124] The analog-to-digital conversion circuit (79), input circuit (WCS), input circuit (XCS), and control circuit (WSD) are circuits provided in the device layer (10).

[0125] The cell array (CA) is a circuit that can be provided to a device layer (40) that includes the memory cell (41) described in the previous embodiment 1 (shown as device layer (40A) in the drawing). That is, the transistors included in the plurality of cells included in the cell array (CA) can be OS transistors. Therefore, the cell array (CA) can be provided by overlapping it on the upper layer of the area where the analog-to-digital conversion circuit (79), input circuit (WCS), input circuit (XCS), and control circuit (WSD) included in the device layer (10) are provided. As a result, the cell array (CA) and the analog-to-digital conversion circuit (79), input circuit (WCS), input circuit (XCS), and control circuit (WSD) can be placed in close proximity, thereby reducing the power consumption required for signal input and output.

[0126] OS transistors have a very small off-current. Therefore, a cell using an OS transistor can be used as a cell to hold the first data of analog data. A cell array (CA) can hold multi-bit digital data as an analog value. In addition, power consumption can be reduced in the cell array (CA) by performing a subthreshold operation using subthreshold current.

[0127] <Configuration Example of Operational Circuit (MAC1)>

[0128] FIG. 11 shows an example configuration of an operation circuit (MAC1) that performs a combination operation of first data and second data. In addition to the input circuit (WCS), input circuit (XCS), control circuit (WSD), and cell array (CA) described above, the operation circuit (MAC1) includes circuit (SWS1) and circuit (SWS2).

[0129] <<Cell Array (CA)>>

[0130] Here, a specific example of a cell array (CA) is described.

[0131] The cell array (CA) includes cells (91_1,1) to cells (91_m,n) and cells (81_1) to cells (81_m). Each of the cells (91_1,1) to cells (91_m,n) includes, for example, a transistor (92), a transistor (93), a transistor (94), and a capacitor (95). Each of the cells (81_1) to cells (81_m) includes, for example, a transistor (82), a transistor (83), a transistor (84), and a capacitor (85). In addition, in the following description, 'one of the source and drain' may be described as the 'first terminal' and 'the other of the source and drain' as the 'second terminal'. In addition, in the following description, 'one electrode' of the capacitor may be described as the 'first terminal' and 'the other electrode' as the 'second terminal'.

[0132] As shown in FIG. 11, the transistor and capacitance elements included in cells (91_1,1) to cells (91_m,n) and cells (81_1) to cells (81_m) are connected to at least one of the wiring (WSL_1 to WSL_m) (wiring (WSL)), wiring (XCL_1 to XCL_m) (wiring (XCL)), wiring (VBL), wiring (WCL_1 to WCL_n) (wiring (WCL)), and wiring that applies a ground potential.

[0133] In FIG. 11, in cell (91_1,1), the connection portion between the first terminal of transistor (92), the gate of transistor (94), and the first terminal of capacitor (95) is designated as node (NN_11). Likewise, in FIG. 11, in cell (91_1,n), cell (91_m,1), and cell (91_m,n), the same connection portion is designated as node (NN_1n), node (NN_m1), and node (NN_mn). Likewise, in FIG. 11, in cell (81_1) and cell (81_m), the same connection portion is designated as node (NN_ref1) and node (NNref_m). Additionally, nodes (NN_11) to (NN_mn) and nodes (NNref_1) to (NNref_m) function as maintenance nodes (node ​​(NN), node (NNref)) of each cell.

[0134] Cell (81) (cell (81_1,1) to cell (81_m)) has the function of executing operation in cell (91) (cell (91_1,1) to cell (91_m, n)) by flowing a set current during data recording and data reading. Specifically, cell (81) has the function of maintaining a reference voltage within cell (81) by flowing a reference current during data recording, and then flowing a current according to the input data (X) supplied to cell (91) during data reading, and controlling the current flowing in cell (91).

[0135] Explain the connection relationships within the cell (81).

[0136] The gate of the transistor (82) is connected to the wiring (WSL). One of the source and drain of the transistor (82) is connected to one of the source and drain of the transistor (83) and to the wiring (XCL). The other of the source and drain of the transistor (82) is connected to the gate of the transistor (84) and one electrode of the capacitor (85). When writing data, the transistor (82) is turned on to record a reference voltage to the maintenance node (gate of the transistor (84)) within the cell (81), and by turning it off, the reference voltage can be maintained within the cell (81).

[0137] The gate of transistor (83) is connected to the wiring (VBL). The back gate of transistor (83) is connected to the other side of the source and drain of transistor (84). One side of the source and drain of transistor (83) is connected to one side of the source and drain of transistor (82) and to the wiring (XCL). The other side of the source and drain of transistor (83) is connected to one side of the source and drain of transistor (84). Transistor (83) sets the potential of one side of the source and drain of transistor (84) to the potential corresponding to the potential of the gate of transistor (83).

[0138] The gate of the transistor (84) is connected to the other side of the source and drain of the transistor (82) and to one electrode of the capacitor (85). Additionally, the holding node to which the gate of the transistor (84), the other side of the source and drain of the transistor (82), and one electrode of the capacitor (85) are connected can be set to a potential according to the current flowing through the transistor (84). The back gate of the transistor (84) is connected to the other side of the source and drain of the transistor (84). The other side of the source and drain of the transistor (84) is connected to a wiring that applies a low power potential (e.g., ground potential). The wiring that applies the ground potential functions as wiring for flowing current between the source and drain of the transistor (84). The other side of the source and drain of the transistor (84) is connected to the back gate of the transistor (83) and the back gate of the transistor (84). Since a fixed potential is applied to the back gate of transistor (83) and the back gate of transistor (84), the transistor characteristics of transistor (83) and transistor (84) are stabilized. Transistor (84) flows an output current according to the potential of the gate of transistor (84) to the other side between the source and the drain.

[0139] One electrode of the capacitor (85) is connected to the other of the source and drain of the transistor (82) and to the gate of the transistor (84). The other electrode of the capacitor (85) is connected to the wiring (XCL). The capacitor (85) has the function of changing the potential of one electrode according to the change in potential of the other electrode when one electrode is in a floating state.

[0140] The cell (91) has the function of maintaining a voltage according to the current inside by flowing a current according to the weight data (W) maintained in the cell (91) during data recording. Additionally, the cell (91) has the function of flowing a current according to the operation of the weight data and input data by increasing the voltage maintained during data recording according to the current flowing through the cell (81) during data reading. There are cases where the weight data is referred to as the first data and the input data as the second data. Furthermore, the weight data is, for example, data (weight data) corresponding to the weight parameters used in the integration operation of an artificial neural network.

[0141] Explain the connection relationships within the cell (91).

[0142] The gate of the transistor (92) is connected to the wiring (WSL). One of the source and drain of the transistor (92) is connected to one of the source and drain of the transistor (93) and to the wiring (WCL). The other of the source and drain of the transistor (92) is connected to the gate of the transistor (94) and one electrode of the capacitor (95). The transistor (92) is turned on to record the voltage according to the weight data in the cell (91) when data is recorded, and is turned off to maintain the voltage according to the weight data in the cell (91).

[0143] The gate of the transistor (93) is connected to the wiring (VBL). The back gate of the transistor (93) is connected to the other side of the source and drain of the transistor (94). One side of the source and drain of the transistor (93) is connected to one side of the source and drain of the transistor (92) and to the wiring (WCL). The other side of the source and drain of the transistor (93) is connected to one side of the source and drain of the transistor (94). The transistor (93) sets the potential of one side of the source and drain of the transistor (94) to the potential corresponding to the potential of the gate of the transistor (93).

[0144] The gate of the transistor (94) is connected to the other side of the source and drain of the transistor (92) and to one electrode of the capacitor (95). The back gate of the transistor (94) is connected to the other side of the source and drain of the transistor (94). The other side of the source and drain of the transistor (94) is connected to wiring that applies a low power potential (e.g., ground potential). The wiring that applies the ground potential functions as wiring for flowing current between the source and drain of the transistor (94). The other side of the source and drain of the transistor (94) is connected to the back gate of the transistor (93) and the back gate of the transistor (94). Since a fixed potential is applied to the back gate of the transistor (93) and the back gate of the transistor (94), the transistor characteristics of the transistor (93) and the transistor (94) are stabilized. The transistor (94) flows an output current according to the potential of the gate of the transistor (94) to the other side of the source and drain.

[0145] One electrode of the capacitor (95) is connected to the other of the source and drain of the transistor (92) and to the gate of the transistor (94). The other electrode of the capacitor (95) is connected to the wiring (XCL). When one electrode of the capacitor (95) is in a floating state, the potential of one electrode changes according to the change in potential of the other electrode.

[0146] Next, the transistors included in the cell (81) and the cell (91) will be described.

[0147] Transistors (84) and (94) operate in the subthreshold region unless specifically mentioned otherwise. The drain current Id of the transistors operating in the subthreshold region can be expressed by Equation (1).

[0148] [Mathematical Formula 1]

[0149]

[0150] In equation (1), I0 is V g =Vth When , the drain current is q, the electric charge is V g is the gate voltage, V th ε is the threshold voltage, η is a coefficient determined by the device structure, etc., k B ε is the Boltzmann constant, and T is the temperature. As shown in Equation (1), the drain current Id of a transistor operating in the subthreshold region does not depend on the drain voltage. The current flowing through transistors (84) and (94) is the current flowing when operating in the subthreshold region. The current in the subthreshold region of transistors (84) and (94) can reduce the influence of deviations in the drain voltage. Therefore, the precision of the data obtained by calculation can be increased.

[0151] Furthermore, in this specification and others, the term "sub-threshold region" refers to the region in a graph representing the gate voltage (Vg)-drain current (Id) characteristics of a transistor where the gate voltage is lower than the threshold voltage. Alternatively, the term "sub-threshold region" refers to a region where current flows due to carrier diffusion, deviating from the gradual channel approximation (a model that considers only drift current). Alternatively, the term "sub-threshold region" refers to a region where the drain current increases exponentially with increasing gate voltage. Alternatively, the term "sub-threshold region" is considered to include a region that can be regarded as the region described above.

[0152] In addition, the drain current when a transistor operates in the subthreshold region is called the subthreshold current. The subthreshold current increases exponentially with respect to the gate voltage, regardless of the drain voltage. Circuit operation using the subthreshold current can reduce the influence of drain voltage deviations.

[0153] Additionally, transistors (92) and (82) have the function of maintaining the potential of the gate of transistor (84) and the gate of transistor (94) by turning them off. Specifically, they have the function of maintaining the potential according to the data supplied to the gate of transistor (94) through transistor (92). As an example, transistors (92) and (82) are preferably OS transistors.

[0154] The OS transistor has a very small current flowing between the source and drain in the off state, i.e., leakage current. By using the OS transistor as the transistor (92) and / or transistor (82), the leakage current of the transistor (92) and / or transistor (82) can be suppressed, thereby reducing the power consumption of the semiconductor device (100). Specifically, the potential fluctuation maintained at each of the gate of the transistor (84) and the gate of the transistor (94) can be made very small, thereby reducing the refresh operation of the potential. In addition, by reducing the refresh operation, the power consumption of the semiconductor device (100) can be reduced. Furthermore, by making the leakage current from the maintenance node to the wiring (WCL) or wiring (XCL) very small, the cell can maintain the potential of the maintenance node for a long time.

[0155] In addition, for OS transistors, when the gate voltage is lower than the transistor's threshold voltage, the drain current per 1 μm of channel width is very small, for example, 1 × 10⁻⁶ -20 Less than A, 1×10 -22 Less than A, or 1×10 -24 It can flow a current of less than A. In addition, for an OS transistor, when the gate voltage is the transistor's threshold voltage, the drain current per 1 μm of channel width is, for example, 1.0 × 10⁻⁶ -8 A or less, 1.0×10 -12 A or less, or 1.0×10 -15A current of less than or equal to A can be flowed. Therefore, in an OS transistor, subthreshold currents of different magnitudes can be flowed within the range of gate voltages operating in the subthreshold region. In other words, the OS transistor can widen the range of gate voltages operating in the subthreshold region. Specifically, the threshold voltage of the OS transistor is V th In the case of , in the subthreshold region (V th -1.0V) or higher V th Below, or (V th -0.5V) or higher V th Circuit operation using gate voltages in the voltage range below is possible.

[0156] On the other hand, Si transistors have a large off-current and a narrow range of gate voltages operating in the sub-threshold region. When utilizing sub-threshold current, OS transistors can perform circuit operation over a wider range of gate voltages than Si transistors.

[0157] OS transistors are accumulation-type transistors that use electrons as majority carriers. Therefore, compared to inversion-type transistors with pn junctions, they are less affected by Drain-Induced Barrier Lowering (DIBL), a type of short-channel effect. In other words, OS transistors have higher resistance to short-channel effects than Si transistors.

[0158] In addition, by using OS transistors for transistors (93, 94) and transistors (83, 84), current consumption can be reduced because they can be operated over a wide current range in the subthreshold region. Also, by using OS transistors for transistors (93, 94) and transistors (83, 84), the manufacturing process of the computational circuit can be shortened because they can be manufactured simultaneously with transistor (82) and transistor (92). In addition, transistors (93, 94) and transistors (83, 84) can be Si transistors containing silicon in the channel forming region, other than OS transistors. As for silicon, examples include amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, single-crystal silicon, etc.

[0159] When using Si transistors as transistors (93, 94) and transistors (83, 84), it is preferable to provide a configuration that functions as a back gate of the transistor, for example, an electrode or a body electrode, and to set the potential applied to the back gate to a ground potential applied to the other side of the source and drain of the transistor (94, 84). By doing so, the electrical characteristics of the transistors (93, 94) and transistors (83, 84) can be stabilized.

[0160] Next, wiring (WSL), wiring (XCL), wiring (VBL), and wiring (WCL) connected to cell (81) and cell (91) will be described.

[0161] A signal is supplied to the wiring (WSL) to control the on or off of the transistor (82) and transistor (92), which function as switches. The wiring (WSL) functions as a recording word line when recording data in the cell (81) and cell (91). Data is recorded in the cell (81) and cell (91) by applying a current or voltage corresponding to the data to be recorded in the wiring (XCL) or wiring (WCL). The data is recorded by turning on the transistor (82) and transistor (92). In this case, the wiring (WCL) is set to an H level (high level potential). Additionally, data is maintained in the cell (81) and cell (91) by controlling the transistor (82) and transistor (92) to turn off. In this case, the wiring (WCL) is set to an L level (low level potential).

[0162] The wiring (WCL) is a current (weighted current or constant current I) according to weighted data (also called first data, first input data) with respect to the operation cell (91). Wut It has the function of flowing current, or the function of applying a drain voltage Vd to flow current according to the potential maintained in the operating cell.

[0163] The wiring (XCL) for the cell (81) and cell (91) is a current according to reference data (reference current or constant current I Xut ) or current (input current or current I) according to input data (also called second data, second input data) X It has the function of flowing ).

[0164] The wiring (VBL) is a wiring to which a positive potential Vb is applied. The positive potential Vb is a potential to fix the potential of the respective drain terminals of the transistor (84) and transistor (94) in the cell (81) and cell (91). By applying the positive potential Vb to the gates of the transistor (83) and transistor (93), transistor characteristics such as the threshold voltage of the transistor (84) and transistor (94) can be stabilized according to the fluctuation of the potential of the wiring (WCL).

[0165] In particular, when transistors (94) and (84) are single-channel transistors with short channel lengths, the threshold voltage is lowered due to DIBL, so the drain current Id depends on the drain voltage Vd. Therefore, a configuration is effective in which a positive potential Vb is applied to the gates of transistors (83) and (93) and the drain voltage of transistors (84) and (94) changes are minimized. With the above configuration, the precision of the data obtained by calculation can be increased.

[0166] Additionally, the transistor (82) and transistor (92) shown in FIG. 11 include a back gate, but may be configured in other ways. For example, the transistor (82) and transistor (92) shown in FIG. 11 may be configured not to include a back gate, i.e., as a transistor having a single gate structure. Also, the potential or signal applied to the back gate may be a fixed potential, such as ground potential, or a signal supplied to the gate.

[0167] In addition, the transistors (92 to 94) and transistors (82 to 84) shown in FIG. 11 are n-channel type transistors, but they may be configured differently. For example, some or all of the transistors (92 to 94) and transistors (82 to 84) may be changed to p-channel type transistors. Also, when some or all of the transistors (92 to 94) and transistors (82 to 84) are changed to p-channel type transistors, the voltage applied to the wiring, etc., may be changed as needed so that the transistors (92 to 94) and transistors (82 to 84) perform the desired operation.

[0168] In addition, it is desirable that the sizes of the transistors included in each cell of the cell array (CA) (e.g., channel length, channel width, transistor configuration, etc.) be the same. For example, it is desirable that the sizes of transistor (82) and transistor (92) be the same. For example, it is desirable that the sizes of transistor (83) and transistor (93) be the same. For example, it is desirable that the sizes of transistor (84) and transistor (94) be the same.

[0169] By making the sizes of the transistors equal to each other, the electrical characteristics of each transistor can be made nearly identical. Therefore, by making the transistor (92) included in each of the cells (91_1,1) to (91_m,n) the same size, the transistor (93) included in each of the cells (91_1,1) to (91_m,n) the same size, and the transistor (94) included in each of the cells (91_1,1) to (91_m,n) the same size, each of the cells (91_1,1) to (91_m,n) can perform nearly identical operations under identical conditions. Here, identical conditions refer, for example, to the input potential to the source, drain, gate, etc. of the transistor (92), the input potential to the source, drain, gate, etc. of the transistor (93), the input potential to the source, drain, gate, etc. of the transistor (94), and the voltage maintained in each of the cells (91_1,1) to cells (91_m,n). In addition, by making the transistor (82) included in each of the cells (81_1) to cells (81_m) the same size, making the transistor (83) included in each of the cells (81_1) to cells (81_m) the same size, and making the transistor (84) included in each of the cells (81_1) to cells (81_m) the same size, for example, the operation and the result of the operation of the cells (81_1) to cells (81_m) can be made almost identical. When the conditions are identical, almost identical operations can be performed. Here, the same conditions refer, for example, to the input potential to the source, drain, gate, etc. of the transistor (82), the input potential to the source, drain, gate, etc. of the transistor (83), the input potential to the source, drain, gate, etc. of the transistor (84), and the voltage maintained in each of the cells (81_1) to (81_m).

[0170] <<Circuit (SWS1), Circuit (SWS2)>>

[0171] Here, specific examples of circuits (SWS1) and (SWS2) are described.

[0172] The circuit (SWS1) includes, for example, transistors (F3_1) to transistor (F3_n). The first terminal of transistor (F3_1) is connected to the wire (WCL_1), the second terminal of transistor (F3_1) is connected to the input circuit (WCS), and the gate of transistor (F3_1) is connected to the wire (SWL1). The first terminal of transistor (F3_n) is connected to the wire (WCL_n), the second terminal of transistor (F3_n) is connected to the input circuit (WCS), and the gate of transistor (F3_n) is connected to the wire (SWL1).

[0173] For each of the transistors (F3_1) to (F3_n), a transistor applicable to a transistor included in a cell array (CA), for example, may be used. In particular, it is preferable to use an OS transistor for each of the transistors (F3_1) to (F3_n).

[0174] The circuit (SWS1) functions as a circuit that turns the input circuit (WCS) and each of the wires (WCL_1) to (WCL_n) on or off.

[0175] The circuit (SWS2) includes, for example, transistors (F4_1) to transistor (F4_n). The first terminal of transistor (F4_1) is connected to wiring (WCL_1), the second terminal of transistor (F4_1) is connected to wiring (OL_1), and the gate of transistor (F4_1) is connected to wiring (SWL2). The first terminal of transistor (F4_n) is connected to wiring (WCL_n), the second terminal of transistor (F4_n) is connected to wiring (OL_n), and the gate of transistor (F4_n) is connected to wiring (SWL2).

[0176] For each of the transistors (F4_1) to (F4_n), a transistor applicable to a transistor included in a cell array (CA), for example, may be used. In particular, it is preferable to use an OS transistor for each of the transistors (F4_1) to (F4_n).

[0177] The circuit (SWS2) has the function of turning on or off the wiring (WCL_1) and wiring (OL_1) and wiring (WCL_n) and wiring (OL_n).

[0178] The input circuit (WCS) has the function of supplying data to be stored in each cell included in the cell array (CA).

[0179] The input circuit (XCS) is connected to wiring (XCL_1) to wiring (XCL_m). The input circuit (XCS) has the function of flowing current according to reference data or current according to second data for each of the cells (81_1) to cells (81_m) included in the cell array (CA).

[0180] The control circuit (WSD) is connected to wiring (WSL_1) to wiring (WSL_m). When recording first data to cells (91_1,1) to cells (91_m,n), the control circuit (WSD) has the function of selecting a row of the cell array (CA) to be recorded with the first data by supplying a predetermined signal to wiring (WSL_1) to wiring (WSL_m). That is, wiring (WSL_1) to wiring (WSL_m) functions as a recording word line.

[0181] Additionally, the control circuit (WSD) is connected to wiring (SWL1) and wiring (SWL2) as an example. The control circuit (WSD) has the function of turning the input circuit (WCS) and the cell array (CA) into an ON or OFF state by supplying a predetermined signal to wiring (SWL1), and the function of turning the wiring (OL_1) to wiring (OL_n) and the cell array (CA) into an ON or OFF state by supplying a predetermined signal to wiring (SWL2).

[0182] <<Input Circuit (WCS), Input Circuit (XCS)>>

[0183] Here, specific examples of the input circuit (WCS) and input circuit (XCS) are described.

[0184] First, the input circuit (WCS) will be described. Fig. 12 (A) is a block diagram showing an example of the input circuit (WCS). In addition, Fig. 12 (A) also shows the circuit (SWS1), transistor (F3), wiring (SWL1), and wiring (WCL) to show the electrical connection between the input circuit (WCS) and surrounding circuits. In addition, transistor (F3) is any one of transistors (F3_1) to transistor (F3_n) included in the operation circuit (MAC1) of Fig. 11, and wiring (WCL) is any one of wirings (WCL_1) to wiring (WCL_n) included in the operation circuit (MAC1) of Fig. 11.

[0185] The input circuit (WCS) shown in (A) of FIG. 12 includes a switch (SWW) as an example. The first terminal of the switch (SWW) is connected to the second terminal of the transistor (F3), and the second terminal of the switch (SWW) is connected to the wiring (VINIL1). The wiring (VINIL1) functions as a wiring that applies an initialization potential to the wiring (WCL), and the initialization potential can be a ground potential GND, a low-level potential, a high-level potential, etc. In addition, the switch (SWW) is turned on only when an initialization potential is applied to the wiring (WCL), and is turned off otherwise.

[0186] As the switch (SWW), electrical switches such as analog switches or transistors may be applied. Furthermore, when a transistor is applied as the switch (SWW), the transistor may be a transistor applicable to a cell array (CA), for example. In addition, mechanical switches may be applied in addition to electrical switches.

[0187] In addition, the input circuit (WCS) of (A) in FIG. 12 has a plurality of current sources (CS) as an example. Specifically, the input circuit (WCS) has K bits (2 K It has the function of outputting the first data of a level (K is an integer greater than or equal to 1) as current, and in this case, the input circuit (WCS) is 2 K - It has one current source (CS). In addition, the input circuit (WCS) has one current source (CS) that outputs information corresponding to the value of the first bit as current, two current sources (CS) that output information corresponding to the value of the second bit as current, and two current sources (CS) that output information corresponding to the value of the K-th bit as current. K-1 I have a dog.

[0188] In (A) of FIG. 12, each current source (CS) includes a terminal (T1) and a terminal (T2). The terminal (T1) of each current source (CS) is connected to the second terminal of a transistor (F3) included in the circuit (SWS1). Additionally, the terminal (T2) of one current source (CS) is connected to wiring (DW_1), and each of the terminals (T2) of two current sources (CS) is connected to wiring (DW_2), and 2 K-1 Each terminal (T2) of the current source (CS) is connected to the wiring (DW_K).

[0189] Multiple current sources (CS) included in the input circuit (WCS) each have the same constant current I Wut It has the function of outputting constant current I from terminal (T1). Wut is the normalized current I Wut It is equivalent to. In addition, in practice, errors may occur during the fabrication stage of the operation circuit (MAC1) due to deviations in the electrical characteristics of the transistors included in each current source (CS). Therefore, the constant current I output from each terminal (T1) of the multiple current sources (CS) Wut The error is preferably within 10%, more preferably within 5%, and more preferably within 1%. In addition, in this embodiment, the constant current I output from the terminal (T1) of a plurality of current sources (CS) included in the input circuit (WCS) Wut The explanation assumes that there is no error.

[0190] Wiring (DW_1) to wiring (DW_K) receives a constant current I from a connected current source (CS). Wut It functions as a wiring that transmits a control signal to output. Specifically, for example, when a high-level potential is applied to the wiring (DW_1), the current source (CS) connected to the wiring (DW_1) is a constant current I Wut When the current flows to the second terminal of the transistor (F3) and a low-level potential is applied to the wiring (DW_1), the current source (CS) connected to the wiring (DW_1) is IWut It does not print.

[0191] The current flowing from one current source (CS) connected to wiring (DW_1) corresponds to the value of the first bit, the current flowing from two current sources (CS) connected to wiring (DW_2) corresponds to the value of the second bit, and the current flowing from K current sources (CS) connected to wiring (DW_K) corresponds to the value of the Kth bit.

[0192] In addition, Figure 12 (A) shows an input circuit (WCS) where K is an integer greater than or equal to 3, but when K is 1, the input circuit (WCS) of Figure 12 (A) may be configured to not provide a current source (CS) connected to wiring (DW_2) to wiring (DW_K). Also, when K is 2, the input circuit (WCS) of Figure 12 (A) may be configured to not provide a current source (CS) connected to wiring (DW_3) to wiring (DW_K).

[0193] Next, a specific configuration example of the current source (CS) will be described.

[0194] The current source (CS1) shown in (A) of FIG. 13 is a circuit that can be applied to the current source (CS) included in the input circuit (WCS) of (A) of FIG. 12, and the current source (CS1) includes transistors (Tr1) and (Tr2).

[0195] The first terminal of transistor (Tr1) is connected to the wiring (VDDL), and the second terminal of transistor (Tr1) is connected to the gate of transistor (Tr1), the back gate of transistor (Tr1), and the first terminal of transistor (Tr2). The second terminal of transistor (Tr2) is connected to terminal (T1), and the gate of transistor (Tr2) is connected to terminal (T2). Also, terminal (T2) is connected to the wiring (DW).

[0196] The wiring (DW) is any one of the wiring (DW_1) to wiring (DW_K) of (A) in FIG. 12.

[0197] The wiring (VDDL) functions as wiring that applies a constant voltage. The constant voltage can be, for example, a high-level potential.

[0198] When the constant voltage applied by the wiring (VDDL) is set to a high-level potential, a high-level potential is input to the first terminal of the transistor (Tr1). Additionally, the potential of the second terminal of the transistor (Tr1) is set to a potential lower than the above high-level potential. At this time, the first terminal of the transistor (Tr1) functions as a drain, and the second terminal of the transistor (Tr1) functions as a source. Furthermore, since the gate of the transistor (Tr1) and the second terminal of the transistor (Tr1) are connected, the gate-source voltage of the transistor (Tr1) becomes 0V. Therefore, when the threshold voltage of the transistor (Tr1) is within an appropriate range, a current (drain current) within the current range of the sub-threshold region flows between the first terminal and the second terminal of the transistor (Tr1). As for the amount of the above current, for example, 1.0 × 10⁻⁶ -8 It is desirable that it be A or less, and also 1.0×10 -12 It is more desirable that it be less than or equal to A, and also 1.0×10 -15 It is more desirable that it be less than A. Additionally, for example, it is more desirable that the above current is within a range that increases exponentially with respect to the gate-source voltage. That is, the transistor (Tr1) functions as a current source to flow a current within the current range when operating in the sub-threshold region. Furthermore, the above current is the aforementioned I Wut Or I described below Xut It is equivalent to.

[0199] The transistor (Tr2) functions as a switching element. Also, when the potential of the first terminal of the transistor (Tr2) is higher than the potential of the second terminal of the transistor (Tr2), the first terminal of the transistor (Tr2) functions as a drain, and the second terminal of the transistor (Tr2) functions as a source. Also, since the back gate of the transistor (Tr2) and the second terminal of the transistor (Tr2) are connected, the back gate-source voltage becomes 0V. Therefore, when the threshold voltage of the transistor (Tr2) is within an appropriate range, the transistor (Tr2) is turned on by inputting a high-level potential to the gate of the transistor (Tr2), and the transistor (Tr2) is turned off by inputting a low-level potential to the gate of the transistor (Tr2). Specifically, when the transistor (Tr2) is in the ON state, the current in the current range of the subthreshold region described above flows from the second terminal of the transistor (Tr1) to the terminal (T1), and when the transistor (Tr2) is in the OFF state, the current does not flow from the second terminal of the transistor (Tr1) to the terminal (T1).

[0200] In addition, the circuit applicable to the current source (CS) included in the input circuit (A) of FIG. 12 is not limited to the current source (CS1) of FIG. 13 (A). For example, the current source (CS1) is configured such that the back gate of the transistor (Tr2) and the second terminal of the transistor (Tr2) are connected, but the back gate of the transistor (Tr2) may be configured such that it is connected to a different wiring. An example of such a configuration is shown in FIG. 13 (B). The current source (CS2) shown in FIG. 13 (B) has a configuration in which the back gate of the transistor (Tr2) is connected to wiring (VTHL). Since the wiring (VTHL) of the current source (CS2) is connected to an external circuit, etc., a predetermined potential can be applied to the wiring (VTHL) by the external circuit, etc., thereby applying the predetermined potential to the back gate of the transistor (Tr2). By doing so, the threshold voltage of the transistor (Tr2) can be varied. In particular, by increasing the threshold voltage of the transistor (Tr2), the off-current of the transistor (Tr2) can be reduced.

[0201] In addition, for example, the current source (CS1) is configured such that the back gate of transistor (Tr1) and the second terminal of transistor (Tr1) are connected, but the voltage between the back gate of transistor (Tr2) and the second terminal may be maintained by a capacitive element. An example of such a configuration is shown in (C) of FIG. 13. The current source (CS3) shown in (C) of FIG. 13 includes transistor (Tr1) and transistor (Tr2), in addition to transistor (Tr3) and transistor (Tr2), transistor (Tr3) and a capacitive element (C6). The current source (CS3) differs from the current source (CS1) in that the second terminal of transistor (Tr1) and the back gate of transistor (Tr1) are connected through the capacitive element (C6), and the back gate of transistor (Tr1) and the first terminal of transistor (Tr3) are connected. In addition, the current source (CS3) has a configuration in which the second terminal of the transistor (Tr3) is connected to the wiring (VTL) and the gate of the transistor (Tr3) is connected to the wiring (VWL). The current source (CS3) can turn on the transistor (Tr3) by applying a high-level potential to the wiring (VWL), thereby turning on the circuit between the wiring (VTL) and the back gate of the transistor (Tr1). At this time, a predetermined potential can be input from the wiring (VTL) to the back gate of the transistor (Tr1). Then, by applying a low-level potential to the wiring (VWL) to turn off the transistor (Tr3), the voltage between the second terminal of the transistor (Tr1) and the back gate of the transistor (Tr1) can be maintained by the capacitance element (C6). That is, the threshold voltage of the transistor (Tr1) can be varied by determining the voltage that the wiring (VTL) applies to the back gate of the transistor (Tr1), and the threshold voltage of the transistor (Tr1) can also be fixed by the transistor (Tr3) and the capacitance element (C6).

[0202] In addition, for example, the current source (CS) included in the input circuit (WCS) of FIG. 12 (A) may be the current source (CS4) shown in FIG. 13 (D). The current source (CS4) has a configuration in which the back gate of the transistor (Tr2) in the current source (CS3) of FIG. 13 (C) is connected to the wiring (VTHL) instead of the second terminal of the transistor (Tr2). That is, the current source (CS4), like the current source (CS2) of FIG. 13 (B), can vary the threshold voltage of the transistor (Tr2) according to the potential applied by the wiring (VTHL).

[0203] In the case where a large current flows between the first terminal and the second terminal of the transistor (Tr1) in the current source (CS4), it is necessary to increase the ON current of the transistor (Tr2) in order to flow the current from the terminal (T1) to the outside of the current source (CS4). In this case, the current source (CS4) can flow the large current flowing between the first terminal and the second terminal of the transistor (Tr1) from the terminal (T1) to the outside of the current source (CS4) by applying a high-level potential to the wiring (VTHL), lowering the threshold voltage of the transistor (Tr2), and increasing the ON current of the transistor (Tr2).

[0204] As a current source (CS) included in the input circuit (WCS) of FIG. 12 (A), by applying the current sources (CS1) to (CS4) shown in FIG. 13 (A) to (D), the input circuit (WCS) can output a current according to the first data of K bits. In addition, the amount of the current can be, for example, the current flowing between the first terminal and the second terminal within the range in which the transistor (94) operates in the subthreshold region.

[0205] In addition, the input circuit (WCS) shown in FIG. 12 (B) may be applied as the input circuit (WCS) of FIG. 12 (A). The input circuit (WCS) of FIG. 12 (B) has a configuration in which one current source (CS) of FIG. 13 (A) is connected to each of the wires (DW_1) to (DW_K). Furthermore, when the channel width of transistor (Tr1_1) is w_1, the channel width of transistor (Tr1_2) is w_2, and the channel width of transistor (Tr1_K) is w_K, the ratio of each channel width is w_1:w_2:w_K = 1:2:2 K-1 Since the current flowing between the source and drain of a transistor operating in the subthreshold region is proportional to the channel width, the input circuit (WCS) shown in (B) of FIG. 12 can output a current according to the first data of K bits, just like the input circuit (WCS) of (A) of FIG. 12.

[0206] In addition, transistors (Tr1) (including transistors (Tr1_1) to (Tr1_K)), transistor (Tr2) (including transistors (Tr2_1) to (Tr2_K)), and transistor (Tr3) may be transistors applicable to, for example, transistors included in a cell array (CA). In particular, it is preferable to use OS transistors as transistors (Tr1) (including transistors (Tr1_1) to (Tr1_K)), transistor (Tr2) (including transistors (Tr2_1) to (Tr2_K)), and transistor (Tr3).

[0207] Next, a specific example of the input circuit (XCS) will be described.

[0208] Fig. 12 (C) is a block diagram showing an example of an input circuit (XCS). In Fig. 12 (C), wiring (XCL) is also shown to indicate the electrical connection between the input circuit (XCS) and surrounding circuits. In addition, wiring (XCL) is any one of wiring (XCL_1) to wiring (XCL_m) included in the operation circuit (MAC1) of Fig. 11.

[0209] The input circuit (XCS) shown in (C) of FIG. 12 includes a switch (SWX) as an example. The first terminal of the switch (SWX) is connected to a wiring (XCL) and a plurality of current sources (CS), and the second terminal of the switch (SWX) is connected to a wiring (VINIL2). The wiring (VINIL2) functions as a wiring that applies an initialization potential to the wiring (XCL), and the initialization potential can be a ground potential GND, a low-level potential, a high-level potential, etc. In addition, the initialization potential applied by the wiring (VINIL2) may be equal to the potential applied by the wiring (VINIL1). In addition, the switch (SWX) is turned on only when an initialization potential is applied to the wiring (XCL), and is turned off otherwise.

[0210] Switch (SWX) can be a switch that can be applied to, for example, Switch (SWW).

[0211] In addition, the circuit configuration of the input circuit (XCS) of (C) in FIG. 12 can be almost the same as the configuration of the input circuit (WCS) of (A) in FIG. 12. Specifically, the input circuit (XCS) has a function of outputting reference data as current and an L-bit (2 L It has the function of outputting second data of level)(L is an integer greater than or equal to 1) as current, and in this case, the input circuit (XCS) is 2 LIt has one current source (CS). Additionally, the input circuit (XCS) has one current source (CS) that outputs information corresponding to the value of the first bit as current, two current sources (CS) that output information corresponding to the value of the second bit as current, and two current sources (CS) that output information corresponding to the value of the L-th bit as current. L-1 I have a dog.

[0212] In addition, the reference data output as current by the input circuit (XCS) can be, for example, information where the value of the first bit is '1' and the value of the second bit and subsequent bits is '0'.

[0213] In (C) of FIG. 12, the terminal (T2) of one current source (CS) is connected to wiring (DX_1), and each of the terminals (T2) of two current sources (CS) is connected to wiring (DX_2), and 2 L-1 Each terminal (T2) of the current source (CS) is connected to the wiring (DX_L).

[0214] Multiple current sources (CS) included in the input circuit (XCS) are each I as the same constant current Xut It has the function of outputting from terminal (T1). In addition, wiring (DX_1) to wiring (DX_L) receives I from the connected current source (CS). Xut It functions as a wire that transmits a control signal for outputting. That is, the input circuit (XCS) has the function of flowing current to the wire (XCL) according to the information of L bits transmitted from the wire (DX_1) to the wire (DX_L).

[0215] In addition, if an error occurs due to a deviation in the electrical characteristics of the transistors included in each current source (CS) included in the input circuit (XCS), the constant current I output from each terminal (T1) of the plurality of current sources (CS) XutThe error is preferably within 10%, more preferably within 5%, and more preferably within 1%. In addition, in this embodiment, the constant current I output from the terminal (T1) of a plurality of current sources (CS) included in the input circuit (XCS) Xut The explanation assumes that there is no error.

[0216] In addition, as the current source (CS) of the input circuit (XCS), any of the current sources (CS1) to (CS4) of FIG. 13 (A) to (D) can be applied, just like the current source (CS) of the input circuit (WCS). In this case, it is preferable to change the wiring (DW) shown in FIG. 13 (A) to (D) to wiring (DX). By doing so, the input circuit (XCS) can flow a current in the subthreshold region's current range into the wiring (XCL) as reference data or second data of L bits.

[0217] In addition, the same circuit configuration as the input circuit (WCS) shown in (B) of Fig. 12 can be applied to the input circuit (XCS) of (C) of Fig. 12. In this case, it is recommended to consider changing the input circuit (WCS) shown in (B) of Fig. 12 to the input circuit (XCS), changing the wiring (DW_1) to the wiring (DX_1), changing the wiring (DW_2) to the wiring (DX_2), changing the wiring (DW_K) to the wiring (DX_L), changing the switch (SWW) to the switch (SWX), and changing the wiring (VINIL1) to the wiring (VINIL2).

[0218] <Example of Operation of Operational Circuit>

[0219] Next, an example of the operation of the operation circuit (MAC1) will be explained.

[0220] FIG. 14 shows a timing chart of an example of operation of the operation circuit (MAC1). The timing chart of FIG. 14 shows the fluctuations in potential of wiring (SWL1), wiring (SWL2), wiring (WSL_i) (where i is an integer between 1 and m-1), wiring (WSL_i+1), wiring (XCL_i), wiring (XCL_i+1), node (NN_i,j) (where j is an integer between 1 and n-1), node (NN_i+1,j), node (NNref_i), and node (NNref_i+1) between time T11 and time T23 and in their vicinity. In addition, the timing chart of FIG. 14 shows the current I flowing between the first terminal and the second terminal of the transistors (93, 94) included in the cell (91_i,j). 94 Current I flowing between the first terminal and the second terminal of the transistor (83, 84) included in the cell (81_i) and _i,j 84 _i and current I flowing between the first and second terminals of the transistor (93, 94) included in the cell (91_i+1,j). 94 _i+1,j and the current I flowing between the first and second terminals of the transistors (83, 84) included in the cell (81_i+1). 84 The variation for each _i+1 was also shown.

[0221] In addition, the input circuit (WCS) of FIG. 12 (A) is applied as the input circuit (WCS) of the operation circuit (MAC1), and the input circuit (XCS) of FIG. 12 (C) is applied as the input circuit (XCS) of the operation circuit (MAC1).

[0222] In addition, in this example of operation, the source potential of the transistor (84) and the transistor (94) is set to the ground potential GND. Also, prior to time T11, as an initial setting, the potential of each of the nodes (NN_i,j), (NN_i+1,j), (NNref_i), and (NNref_i+1) is set to the ground potential GND. Specifically, for example, the initialization potential of the wiring (VINIL1) of FIG. 12 (A) is set to the ground potential GND, and each transistor (92) included in the switch (SWW), transistor (F3), and cell (91_i,j), cell (91_i+1,j) is turned on, thereby making the potential of the nodes (NN_i,j) and (NN_i+1,j) the ground potential GND. In addition, for example, the initialization potential of the wiring (VINIL2) in (C) of FIG. 12 can be set to the ground potential GND, and each transistor (82) included in the switch (SWX) and cell (91_i,j) and cell (91_i+1,j) can be turned on, thereby making the potential of node (NNref_i,j) and node (NNref_i+1,j) the ground potential GND.

[0223] In addition, in this example of operation, the gate potential of transistors (83) and (93) is set to a positive potential Vb. By setting the gate potential of transistors (83) and (93) to a positive potential Vb, the first terminal of each transistor (83) and transistor (93) can be lowered to a voltage Vb-Vth, which is lowered by a threshold voltage from the positive potential Vb. Therefore, the rise of the second terminal (drain side) of transistors (84, 94) can be suppressed.

[0224] <<Time T11 to Time T12>>

[0225] At time T11 to time T12, a high-level potential (labeled High in FIG. 14) is applied to the wire (SWL1), and a low-level potential (labeled Low in FIG. 14) is applied to the wire (SWL2). As a result, a high-level potential is applied to the gates of each of transistors (F3_1) to (F3_n), so that each of transistors (F3_1) to (F3_n) turns on, and a low-level potential is applied to the gates of each of transistors (F4_1) to (F4_n), so that each of transistors (F4_1) to (F4_n) turns off.

[0226] Additionally, between time T11 and time T12, a low-level potential is applied to the wiring (WSL_i) and wiring (WSL_i+1). As a result, a low-level potential is applied to the gate of the transistor (92) included in the cell (91_i,1) to cell (91_i,n) of the i-th row of the cell array (CA) and the gate of the transistor (82) included in cell (81_i), causing each transistor (92) and transistor (82) to turn off. Additionally, a low-level potential is applied to the gate of the transistor (92) included in the cell (91_i+1,1) to cell (91_i+1,n) of the i+1-th row of the cell array (CA) and the gate of the transistor (82) included in cell (81_i+1), causing each transistor (92) and transistor (82) to turn off.

[0227] In addition, between time T11 and time T12, ground potential GND is applied to wiring (XCL_i) and wiring (XCL_i+1). Specifically, for example, in the case where the wiring (XCL) described in (C) of FIG. 12 is wiring (XCL_i) and wiring (XCL_i+1) respectively, the initialization potential of wiring (VINIL2) can be set to ground potential GND, and by turning on the switch (SWX), the potential of wiring (XCL_i) and wiring (XCL_i+1) can be set to ground potential GND.

[0228] In addition, between time T11 and time T12, when the wiring (WCL) described in (A) of FIG. 12 is each wiring (WCL_1) to wiring (WCL_K), the first data is not input to wiring (DW_1) to wiring (DW_K). In addition, when the wiring (XCL) described in (C) of FIG. 12 is each wiring (XCL_1) to wiring (XCL_K), the second data is not input to wiring (DX_1) to wiring (DX_L). Here, in the input circuit (WCS) of FIG. 12 (A), a low-level potential is input to each wiring (DW_1) to wiring (DW_K), and in the input circuit (XCS) of FIG. 12 (C), a low-level potential is input to each wiring (DX_1) to wiring (DX_L).

[0229] Also, between time T11 and time T12, no current flows in wiring (WCL_j), wiring (XCL_i), and wiring (XCL_i+1). Therefore, I 94 _i,j, I 84 _i, I 94 _i+1,j, I 84 _i+1 is 0.

[0230] <<Time T12 to Time T13>>

[0231] Between time T12 and time T13, a high-level potential is applied to the wiring (WSL_i). As a result, a high-level potential is applied to the gate of the transistor (92) included in the cells (91_i,1) to (91_i,n) of the i-th row of the cell array (CA) and the gate of the transistor (82) included in the cell (81_i), so that each transistor (92) and transistor (82) are turned on. Additionally, between time T12 and time T13, a low-level potential is applied to the wiring (WSL_1) to (WSL_m) excluding the wiring (WSL_i), and the transistor (92) included in the cells (91_1,1) to (91_m,n) other than the i-th row of the cell array (CA) and the transistor (82) included in the cells (81_1) to (81_m) other than the i-th row are turned off.

[0232] In addition, the ground potential GND has been continuously applied to the wiring (XCL_1) to wiring (XCL_m) since before time T12.

[0233] <<Time T13 to Time T14>>

[0234] Between time T13 and time T14, a current I0_i,j flows from the input circuit (WCS) through the transistor (F3_j) to the cell array (CA) as the first data. Specifically, when the wiring (WCL) described in (A) of FIG. 12 is wiring (WCL_j), a signal corresponding to the first data is input to each of wirings (DW_1) to wiring (DW_K), thereby causing a current I0_i,j to flow from the input circuit (WCS) to the second terminal of the transistor (F3_j). That is, the value of the K-bit signal input as the first data is w_i,j (w_i,j is 0 or greater than 2 K When set to an integer less than or equal to -1, I0_i,j=w_i,j×I Wut It becomes.

[0235] Also, when w_i,j is 0, I0_i,j=0, so strictly speaking, no current flows from the input circuit (WCS) to the cell array (CA) through the transistor (F3_j), but in the present specification, etc., it may be stated that 'current flows with I0_i,j=0'.

[0236] Between time T13 and time T14, the transistor (92) contained in the cell (91_i,j) of the i-th row of the cell array (CA) is in the ON state, and the transistor (92) contained in the cells (91_1,j) to (91_m,j) other than the i-th row of the cell array (CA) is in the OFF state, so current I0_i,j flows from the wiring (WCL_j) to the cell (91_i,j).

[0237] When the transistor (92) included in the cell (91_i,j) is in the ON state, current I0_i,j flows through the transistor (94). Current I0_i,j is set as the current flowing between the first terminal and the second terminal of the transistor (94). The gate-source voltage of the transistor (94) is V so that current I0_i,j flows. g _i,j-GND becomes.

[0238] Also, between time T13 and time T14, current I from the input circuit (XCS) to the wiring (XCL_i) as reference data. ref0 This flows. Specifically, in the case where the wiring (XCL) described in (C) of FIG. 12 is wiring (XCL_i), a high-level potential is input to wiring (DX_1) and a low-level potential is input to wirings (DX_2) through (DX_K), respectively, and current I flows from the input circuit (XCS) to wiring (XCL_i). ref0 =I Xut It flows.

[0239] During the period between time T13 and time T14, since the transistor (82) included in the cell (81_i) is in the ON state, current I from wiring (XCL_i) to the cell (81_i)ref0 It flows. 84 _i is I ref0 is. ref0 =I Xut Because of this, I 94 _i,j is I0_i,j=w_i,j×I ref0 This becomes ('j×I' in the specification ref0 ' is 'j*I in the drawing ref0 (It was described as ').

[0240] When the transistor (82) included in cell (81_i) is in the ON state, just like in cell (91_i,j), current I in the transistor (84) ref0 This flows. As a current flowing between the first terminal and the second terminal of the transistor (84), current I ref0 This is set. Current I ref0 The gate-source voltage of the transistor (84) V is set so that this flows. gm It becomes _i-GND.

[0241] <<Time T14 to Time T15>>

[0242] Between time T14 and time T15, a low-level potential is applied to the wiring (WSL_i). As a result, a low-level potential is applied to the gate of the transistor (92) included in the cell (91_i,1) to cell (91_i,n) of the i-th row of the cell array (CA) and the gate of the transistor (82) included in cell (81_i), so that each transistor (92) and transistor (82) are turned off.

[0243] As the transistor (92) included in the cell (91_i,j) is turned off, the capacitor (95) receives V, which is the difference between the potential of the gate (node ​​(NN_i,j)) of the transistor (94) and the potential of the wiring (XCL_i). g _i,jV gm_i is maintained. Also, as the transistor (92) included in the cell (91_i) is turned off, the capacitor (95) maintains a value of 0, which is the difference between the potential of the gate (node ​​(NNref_i)) of the transistor (84) and the potential of the wiring (XCL_i).

[0244] <<Time T15 to Time T16>>

[0245] Between time T15 and time T16, GND is applied to the wiring (XCL_i). Specifically, for example, when the wiring (XCL) described in (C) of FIG. 12 is wiring (XCL_i), the initialization potential of wiring (VINIL2) can be set to the ground potential GND, and the potential of wiring (XCL_i) can be set to the ground potential GND by turning on the switch (SWX).

[0246] Therefore, the potential of nodes (NN_i,1) to (NN_i,n) is changed by the capacitive coupling of the capacitor (95) included in each of the cells (91_i,1) to (91_i,n) of the i-th row, and the potential of node (NNref_i) is changed by the capacitive coupling of the capacitor (85) included in cell (81_i).

[0247] The change in potential of nodes (NN_i,1) to (NN_i,n) is the potential obtained by multiplying the change in potential of the wiring (XCL_i) by a capacitance coupling coefficient determined according to the configuration of each cell (91_i,1) to (91_i,n) included in the cell array (CA). The above capacitance coupling coefficient is calculated based on the capacitance of the capacitor (95), the gate capacitance of the transistor (94), parasitic capacitance, etc. For each cell (91_i,1) to cell (91_i,n), when the capacitance coupling coefficient due to the capacitor (95) is p, the potential of node (NN_i,j) of cell (91_i,j) is p(V) from the potential at the time point between time T14 and time T15. gm It decreases by _i-GND).

[0248] Likewise, as the potential of the wiring (XCL_i) changes, the potential of the node (NNref_i) also changes due to capacitive coupling by the capacitor (85) included in the reference cell (81_i). When the capacitive coupling coefficient by the capacitor (85) is set to p, as with the capacitor (95), the potential of the node (NNref_i) of the cell (81_i) is p(V) from the potential between time T14 and time T15. gm It decreases by _i-GND). Also, in the timing chart of FIG. 14, p=1 as an example. Therefore, the potential of the node (NNref_i) between time T15 and time T16 becomes GND.

[0249] Accordingly, as the potential of the node (NN_i,j) of the cell (91_i,j) decreases, the transistor (94) becomes off, and likewise, as the potential of the node (NNref_i) of the cell (81_i) decreases, the transistor (84) also becomes off. Therefore, between time T15 and time T16, I 94 _i,j, I 84 Each _i becomes 0.

[0250] <<Time T16 to Time T17>>

[0251] Between time T16 and time T17, a high-level potential is applied to the wiring (WSL_i+1). As a result, a high-level potential is applied to the gate of the transistor (92) included in the cell (91_i+1,1) to cell (91_i+1,n) of the i+1th row of the cell array (CA) and the gate of the transistor (82) included in cell (81_i+1), so that each transistor (92) and transistor (82) are turned on. In addition, between time T16 and time T17, a low-level potential is applied to wiring (WSL_1) to wiring (WSL_m) excluding wiring (WSL_i+1), and transistors (92) included in cells (91_1,1) to cells (91_m,n) other than the i+1th row of the cell array (CA) and transistors (82) included in cells (81_1) to cells (81_m) other than the i+1th row are in an off state.

[0252] In addition, the ground potential GND has been continuously applied to the wiring (XCL_1) to wiring (XCL_m) since before time T16.

[0253] <<Time T17 to Time T18>>

[0254] Between time T17 and time T18, a current I0_i+1,j flows from the input circuit (WCS) through the transistor (F3_j) to the cell array (CA) as the first data. Specifically, when the wiring (WCL) described in (A) of FIG. 12 is wiring (WCL_j+1), a signal corresponding to the first data is input to each of wirings (DW_1) to wiring (DW_K), thereby causing a current I0_i+1,j to flow from the input circuit (WCS) to the second terminal of the transistor (F3_j). That is, the value of the K-bit signal input as the first data is w_i+1,j (w_i+1,j is 0 or greater than or equal to 2 K When set to an integer less than or equal to -1, I0_i+1,j=w_i+1,j×I Wut It becomes.

[0255] Also, when w_i+1,j is 0, I0_i+1,j=0, so strictly speaking, no current flows from the input circuit (WCS) to the cell array (CA) through the transistor (F3_j), but in the present specification, etc., it is sometimes stated that 'current flows when I0_i+1,j=0', just as in the case when I0_i,j=0.

[0256] At this time, since the transistor (92) included in the cell (91_i+1,j) of the i+1th row of the cell array (CA) is in the ON state and the transistor (92) included in the cell (91_1,j) to the cell (91_m,j) other than the i+1th row of the cell array (CA) is in the OFF state, current I0_i+1,j flows from the wiring (WCL_j) to the cell (91_i+1,j).

[0257] When the transistor (92) included in the cell (91_i+1,j) is in the ON state, current I0_i+1,j flows through the transistor (94). Current I0_i+1,j is set as the current flowing between the first terminal and the second terminal of the transistor (94). The gate-source voltage of the transistor (94) V is set so that current I0_i+1,j flows. g _i+1,j-GND becomes.

[0258] Also, between time T17 and time T18, current I from the input circuit (XCS) to the wiring (XCL_i+1) as reference data. ref0 This flows. Specifically, as in the case between time T13 and time T14, when the wiring (XCL) described in (C) of FIG. 12 is wiring (XCL_i+1), a high-level potential is input to wiring (DX_1) and a low-level potential is input to wirings (DX_2) through (DX_K) respectively, and current I flows from the input circuit (XCS) to wiring (XCL_i+1). ref0 =I Xut It flows.

[0259] During the period between time T17 and time T18, since the transistor (82) included in the cell (81_i+1) is in the ON state, current I from the wiring (XCL_i+1) to the cell (81_i+1) ref0 It flows. 84 _i+1 is I ref0 It becomes. ref0 =I Xut Because of this, I 94 _i+1,j is I0_i+1,j=w_i+1,j×I ref0 This becomes (in the drawing, '×' is shown as '*').

[0260] When the transistor (82) included in cell (81_i+1) is in the ON state, just like cell (91_i+1,j), current I in the transistor (84) ref0 This flows. As a current flowing between the first terminal and the second terminal of the transistor (84), current I ref0 This is set. Current I ref0 The gate-source voltage of the transistor (84) V is set so that this flows. gm It becomes _i+1-GND.

[0261] <<Time T18 to Time T19>>

[0262] Between time T18 and time T19, a low-level potential is applied to the wiring (WSL_i+1). As a result, a low-level potential is applied to the gate of the transistor (92) included in the cell (91_i+1,1) to cell (91_i+1,n) of the i+1th row of the cell array (CA) and the gate of the transistor (82) included in cell (81_i+1), causing each transistor (92) and transistor (82) to turn off.

[0263] As the transistor (92) included in the cell (91_i+1,j) is turned off, the capacitor (95) receives V, which is the difference between the potential of the gate (node ​​(NN_i+1,j)) of the transistor (94) and the potential of the wiring (XCL_i+1). g _i+1,jV gm_i+1 is maintained. Additionally, as the transistor (92) included in the cell (81_i+1) is turned off, the capacitor (85) maintains a voltage of 0, which is the difference between the potential of the gate (node ​​(NNref_i+1)) of the transistor (84) and the potential of the wiring (XCL_i+1). Furthermore, the voltage maintained by the capacitor (85) is a non-zero voltage (here, for example, V) depending on the transistor characteristics of the transistor (82) and transistor (84) during operation from time T18 to time T19. ds There are also cases where it becomes (as). In this case, the potential of node (NNref_i+1) is V relative to the potential of wiring (XCL_i+1). ds It is good to think of it as the potential with added.

[0264] <<Time T19 to Time T20>>

[0265] Between time T19 and time T20, a ground potential GND is applied to the wiring (XCL_i+1). Specifically, for example, when the wiring (XCL) described in (C) of FIG. 12 is wiring (XCL_i+1), the initialization potential of wiring (VINIL2) is set to a ground potential GND, and by turning on the switch (SWX), the potential of wiring (XCL_i+1) can be set to a ground potential GND.

[0266] Therefore, the potential of nodes (NN_i,1) to (NN_i+1,n) is changed by the capacitive coupling of the capacitor (95) included in each of the cells (91_i+1,1) to (91_i+1,n) of the i+1th row, and the potential of node (NNref_i+1) is changed by the capacitive coupling of the capacitor (85) included in the cell (81_i+1).

[0267] The change in potential of nodes (NN_i+1,1) to (NN_i+1,n) is the change in potential of wiring (XCL_i+1) multiplied by a capacitance coupling coefficient determined according to the configuration of each cell (91_i+1,1) to cell (91_i+1,n) included in the cell array (CA). The capacitance coupling coefficient is calculated based on the capacitance of the capacitor (95), the gate capacitance of the transistor (94), parasitic capacitance, etc. In each of cells (91_i+1,1) to cells (91_i+1,n), when the capacitance coupling coefficient due to the capacitor (95) is set to p, which is the same as the capacitance coupling coefficient due to the capacitor (95) in each of cells (91_i,1) to cells (91_i,n), the potential of the node (NN_i+1,j) of cell (91_i+1,j) is p(V) from the potential at the time point between time T18 and time T19. gm It decreases by _i+1-GND).

[0268] Likewise, as the potential of the wiring (XCL_i+1) changes, the potential of the node (NNref_i+1) also changes due to capacitive coupling by the capacitor (85) included in the cell (81_i+1). When the capacitive coupling coefficient by the capacitor (85) is set to p, as with the capacitor (95), the potential of the node (NNref_i+1) of the cell (81_i+1) is p(V) from the potential between time T18 and time T19. gm It decreases by _i+1-GND). Also, in the timing chart of FIG. 14, p=1 as an example. Therefore, the potential of the node (NNref_i+1) between time T20 and time T21 becomes GND.

[0269] Accordingly, as the potential of the node (NN_i+1,j) of the cell (91_i+1,j) decreases, the transistor (94) becomes off, and likewise, as the potential of the node (NNref_i+1) of the cell (81_i+1) decreases, the transistor (84) also becomes off. Therefore, between time T19 and time T20, I 94_i+1,j, I 84 Each _i+1 becomes 0.

[0270] <<Time T20 to Time T21>>

[0271] Between time T20 and time T21, a low-level potential is applied to the wiring (SWL1). As a result, a low-level potential is applied to the gates of each of transistors (F3_1) to transistor (F3_n), and each of transistors (F3_1) to transistor (F3_n) is turned off.

[0272] <<Time T21 to Time T22>>

[0273] Between time T21 and time T22, a high-level potential is applied to the wiring (SWL2). As a result, a high-level potential is applied to the gates of each of transistors (F4_1) to transistor (F4_n), and each of transistors (F4_1) to transistor (F4_n) is turned on.

[0274] <<Time T22 to Time T23>>

[0275] Between time T22 and time T23, current I from the input circuit (XCS) to the wiring (XCL_i) as the second data ref0 x_iI which is x_i times of ref0 A current flows. Specifically, for example, in the case where the wiring (XCL) described in (C) of FIG. 12 is wiring (XCL_i), a high-level potential or a low-level potential is input to each of wirings (DX_1) to (DX_K) according to the value of x_i, and x_iI flows from the input circuit (XCS) to wiring (XCL_i) as a current. ref0 =x_iI Xut flows. Also, in this operation example, x_i corresponds to the value of the second data. At this time, the potential of the wiring (XCL_i) is from 0 to V gm It is assumed to change to _i+ΔV_i.

[0276] As the potential of the wiring (XCL_i) changes, the potential of nodes (NN_i,1) to (NN_i,n) also changes due to capacitive coupling by the capacitor (95) included in each of the cells (91_i,1) to (91_i,n) of the i-th row of the cell array (CA). Therefore, the potential of node (NN_i,j) of cell (91_i,j) is V g It becomes _i,j+pΔV_i.

[0277] Likewise, as the potential of the wiring (XCL_i) changes, the potential of the node (NNref_i) also changes due to capacitive coupling by the capacitor (85) included in the reference cell (81_i). Therefore, the potential of the node (NNref_i) of the cell (81_i) is V gm It becomes _i+pΔV_i.

[0278] Therefore, the current flowing between the first terminal and the second terminal of the transistor (94) included in the cell (91_i,j) is a current proportional to the product of the first data (w_i,j) and the second data (x_i).

[0279] Also, between time T22 and time T23, current I from the input circuit (XCS) to the wiring (XCL_i+1) as the second data. ref0 x_i+1, which is x_i+1 times x_i. ref0 A current flows. Specifically, for example, in the case where the wiring (XCL) described in (C) of FIG. 12 is wiring (XCL_i+1), a high-level potential or a low-level potential is input to each of wirings (DX_1) to (DX_K) according to the value of x_i+1, and x_i+1I flows from the input circuit (XCS) to wiring (XCL_i+1) as a current. ref0 = x_i+1I Xut flows. Also, in this operation example, x_i+1 corresponds to the value of the second data. At this time, the potential of the wiring (XCL_i+1) is from 0 to V gm It is assumed that it changes to _i+1+ΔV_i+1.

[0280] As the potential of the wiring (XCL_i+1) changes, the potential of nodes (NN_i+1,1) to (NN_i+1,n) also changes due to capacitive coupling by the capacitor (95) included in each of the cells (91_i+1,1) to (91_i+1,n) of the i+1th row of the cell array (CA). Therefore, the potential of the node (NN_i+1,j) of cell (91_i+1,j) is V g _i+1,j+pΔV_i+1 becomes.

[0281] Likewise, as the potential of the wiring (XCL_i+1) changes, the potential of the node (NNref_i+1) also changes due to capacitive coupling by the capacitor (85) included in the cell (81_i+1). Therefore, the potential of the node (NNref_i+1) of the cell (81_i+1) is V gm _i+1+pΔV_i+1 becomes.

[0282] Therefore, the current flowing between the first terminal and the second terminal of the transistor (94) included in the cell (91_i+1,j) is a current proportional to the product of the first data w_i+1,j and the second data x_i+1.

[0283] Accordingly, the current output from the wiring (OL_j) can be a current proportional to the sum of the first data, the weighting coefficients (w_i,j and w_i+1,j), and the second data, the input signal values ​​x_i and x_i+1. The above current is an analog signal (D) having an analog voltage value by means of a current-voltage conversion circuit, etc. MACA It can be converted into ) and output to an analog-to-digital conversion circuit (79).

[0284] Therefore, even in the case of an operation circuit (MAC1) including a cell array (CA) having three or more rows and two or more columns, redundancy operations can be performed as described above. In this case, the operation circuit (MAC1) uses one of the multiple columns as current I ref0 and xI ref0By maintaining the cell, redundancy processing can be executed simultaneously for as many columns as the number of remaining columns among multiple columns. That is, by increasing the number of columns of the memory cell array, a semiconductor device capable of realizing high-speed redundancy processing can be provided. Therefore, a redundancy processing unit with excellent computational processing capability per unit power can be provided.

[0285] In addition, although the present embodiment describes a case where the transistor included in the operation circuit (MAC1) is an OS transistor or a Si transistor, the present invention is not limited thereto. As for the transistor included in the operation circuit (MAC1), for example, a transistor in which Ge or the like is included in the channel forming region, a transistor in which a compound semiconductor such as ZnSe, CdS, GaAs, InP, GaN, or SiGe is included in the channel forming region, a transistor in which a carbon nanotube is included in the channel forming region, or a transistor in which an organic semiconductor is included in the channel forming region may be used.

[0286] In addition, this embodiment can be appropriately combined with other embodiments in this specification.

[0287] (Embodiment 3)

[0288] In this embodiment, an example of a cross-sectional configuration of a device layer including stacked OS transistors applicable to semiconductor devices, etc. is described. In this embodiment, an example of a cross-sectional schematic diagram applicable to circuit configurations such as NOSRAM and DOSRAM is described.

[0289] <NOSRAM의 구성예 1>

[0290] FIG. 15 shows an example of a cross-sectional configuration using a circuit configuration of a 3-transistor type NOSRAM. FIG. 15 illustrates a case where device layers (UF[1]) to device layers (UF[3]) are stacked on a device layer (LF). FIG. 16 (A) also shows an example of a cross-sectional structure of a device layer (UF[k]). FIG. 16 (B) also shows an equivalent circuit diagram of FIG. 16 (A).

[0291] The device layer (LF) is the device layer (10) described in the preceding embodiment 1. A device such as a Si transistor is provided in the device layer (LF). The device layer (UF) is the device layer (40) described in the preceding embodiment 1. A device such as an OS transistor is provided in the device layer (UF).

[0292] Also, FIG. 15 shows a transistor (550) included in a device layer (LF). The transistor (550) is provided on a substrate (311) and includes a conductive layer (316) that functions as a gate electrode, an insulating layer (315), a semiconductor region (313) formed as part of the substrate (311), and a low-resistance region (314a) and a low-resistance region (314b) that function as a source region or a drain region.

[0293] In addition, the transistor (550) may be either a p-channel type or an n-channel type.

[0294] The low resistance region (314a) and the low resistance region (314b) include, in addition to the semiconductor material applied to the semiconductor region (313), an element that imparts n-type conductivity such as arsenic and phosphorus, or an element that imparts p-type conductivity such as boron.

[0295] In addition, the transistor (550) shown in FIG. 15 is an example and is not limited to that structure; it is acceptable to use an appropriate transistor depending on the circuit configuration or driving method.

[0296] Between the device layer (LF) and the device layer (UF), or between the device layer (UF) of the k-th layer and the device layer (UF) of the k+1-th layer, a wiring layer provided with an interlayer film, wiring, and plug, etc. may be provided. In addition, in the present embodiment, the device layer (UF) of the k-th layer may be denoted as the device layer (UF[k]), and the device layer (UF) of the k+1-th layer may be denoted as the device layer (UF[k+1]). Here, k is an integer greater than or equal to N. In addition, in the present embodiment, etc., when 'k+α (α is an integer greater than or equal to 1)' or 'k-α' is denoted, the solution of 'k+α' and 'k-α', respectively, shall be an integer greater than or equal to N.

[0297] In addition, multiple wiring layers may be provided depending on the design. Furthermore, the wiring and the plug connected to the wiring described in this specification and others may be integral. That is, there may be cases where a portion of the conductive layer functions as wiring and cases where a portion of the conductive layer functions as a plug.

[0298] For example, an insulating layer (320), an insulating layer (322), an insulating layer (324), and an insulating layer (326) are provided stacked in this order as an interlayer film on the transistor (550). Additionally, a conductive layer (328), etc., is embedded in the insulating layer (320) and the insulating layer (322). Additionally, a conductive layer (330), etc., is embedded in the insulating layer (324) and the insulating layer (326). Furthermore, the conductive layer (328) and the conductive layer (330) function as contact plugs or wiring.

[0299] A wiring layer may be provided on the insulating layer (326) and the conductive layer (330). For example, in FIG. 15, an insulating layer (350), an insulating layer (357), an insulating layer (352), and an insulating layer (354) are provided stacked in this order on the insulating layer (326) and the conductive layer (330). A conductive layer (356) is formed on the insulating layer (350), the insulating layer (357), and the insulating layer (352). The conductive layer (356) functions as a contact plug or wiring.

[0300] An insulating layer (514) included in the device layer (UF) is provided on top of the insulating layer (354). Additionally, a conductive layer (358) is embedded in the insulating layer (514) and the insulating layer (354). The conductive layer (358) functions as a contact plug or wiring. For example, wiring functioning as a bit line and a transistor (550) are connected through the conductive layer (358), the conductive layer (356), and the conductive layer (330), etc.

[0301] As shown in (A) of FIG. 16, in the memory cell (41E) shown in FIG. 15, transistors (M2), transistor (M3), and transistor (M1) are provided on an insulating layer (514).

[0302] The transistor (M2) and transistor (M3) shown in (A) of FIGS. 15 and 16 share a single island-shaped semiconductor layer (530). In other words, a part of the single island-shaped semiconductor layer (530) functions as a channel forming region of transistor (M2), and another part functions as a channel forming region of transistor (M3). Additionally, the source of transistor (M2) and the drain of transistor (M3), or the drain of transistor (M2) and the source of transistor (M3) are shared. Therefore, the occupied area of ​​the transistor is smaller than when transistors (M2) and transistor (M3) are provided independently.

[0303] In addition, the memory cell (41E) shown in (A) of FIGS. 15 and 16 can be configured without a transistor (M1). The memory cell (41E) having a configuration without a transistor (M1) can be a 2-transistor type NOSRAM and corresponds to the memory cell (41D) shown in (D) of FIG. 17.

[0304] Here, the OS transistor is described with reference to (A) to (C) of FIG. 17. FIG. 17 (A) and (B) are cross-sectional schematic diagrams of a transistor (500) that can be applied as transistors (M1 to M3).

[0305] As shown in (A) and (B) of FIG. 17, an insulating layer (516) is disposed on an insulating layer (514). The transistor (500) includes a conductive layer (503) disposed to be embedded in the insulating layer (516), an insulating layer (522) disposed on the insulating layer (516) and the conductive layer (503), an insulating layer (524) disposed on the insulating layer (522), a semiconductor layer (530) disposed on the insulating layer (524), conductive layers (542a) and (542b) disposed apart from each other on the semiconductor layer (530), an insulating layer (580) disposed on the conductive layer (542a) and the conductive layer (542b) and overlapped between them to form an opening, an insulating layer (545) disposed on the bottom and side of the opening, and a conductive layer (560) disposed on the insulating layer (545). The conductive layer (560) includes a conductive layer (560a) provided on the inner side of the insulating layer (545) and a conductive layer (560b) provided to be embedded in the opening on the conductive layer (560a).

[0306] Also, as shown in (A) and (B) of FIG. 17, an insulating layer (544) is disposed between the semiconductor layer (530), the conductive layer (542a), and the conductive layer (542b) and the insulating layer (580). Additionally, an insulating layer (574) is disposed on the insulating layer (580), the conductive layer (560), and the insulating layer (545), and an insulating layer (581) is disposed on the insulating layer (574).

[0307] In the transistor (500), the conductive layer (560) functions as a gate electrode, the insulating layer (545) functions as a gate insulating film, and the conductive layer (542a) and the conductive layer (542b) each function as a source electrode or a drain electrode. The conductive layer (560) may function as a first gate electrode. Additionally, the conductive layer (503) may function as a second gate electrode. The insulating layer (522) and the insulating layer (524) function as a second gate insulating film.

[0308] In addition, in the transistor (500) shown in (A) and (B) of FIG. 17, insulating layer (522) and insulating layer (524) are shown as a second gate insulating film having a two-layer stacked structure, but the second gate insulating film may have a single-layer structure or a stacked structure of three or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials.

[0309] It is preferable for the transistor (500) to use an oxide semiconductor layer as the semiconductor layer (530) including a channel forming region. An oxide semiconductor layer that can be used as the semiconductor layer (530) will be described in Embodiment 4 below.

[0310] In transistors using oxide semiconductors in the semiconductor layer, the channel formation region has more oxygen vacancies (V) than the source and drain regions. O It is desirable that ) is low or that the concentration of impurities such as hydrogen, nitrogen, and metallic elements is low. In addition, hydrogen near the oxygen vacancy is a defect in which hydrogen enters the oxygen vacancy (hereinafter, V O Since it forms (sometimes referred to as H) and generates electrons that become carriers, V in the channel formation region O It is desirable that H is also reduced. As such, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be described as i-type (intrinsic) or substantially i-type.

[0311] In addition, the source and drain regions of transistors using oxide semiconductors in the semiconductor layer have more oxygen vacancies than the channel formation region, or V O It is a region where the carrier concentration increases and resistance is reduced due to a high concentration of H or impurities such as hydrogen, nitrogen, and metal elements. In other words, the source and drain regions of a transistor are n-type regions with a higher carrier concentration and lower resistance than the channel-forming region.

[0312] It is preferable that the band gap of the oxide semiconductor be 2 eV or larger, and more preferable that it be 2.5 eV or larger. By using an oxide semiconductor with a large band gap in the semiconductor layer, the off-current of the transistor can be reduced. By using a transistor with a small off-current in the memory cell, the memory contents can be retained over a long period of time. In other words, since refresh operations are unnecessary or the frequency of refresh operations is very low, the power consumption of the semiconductor device can be sufficiently reduced.

[0313] In FIG. 17 (A) and (B), the semiconductor layer (530) is shown as a single-layer structure, but the present invention is not limited thereto. For example, the semiconductor layer (530) may have a stacked structure of two or more layers.

[0314] When an oxide semiconductor is used in the semiconductor layer (530), as shown in (A) of FIG. 17, a region (543a) may be formed as a low-resistance region at the interface with the conductive layer (542a) in the semiconductor layer (530) and in the vicinity thereof. Similarly, a region (543b) may be formed as a low-resistance region at the interface with the conductive layer (542b) in the semiconductor layer (530) and in the vicinity thereof. In this case, the region (543a) and the region (543b) each function as a source region or a drain region. Additionally, a channel forming region is formed in the region between the region (543a) and the region (543b).

[0315] In addition, the semiconductor material that can be used for the semiconductor layer (530) is not limited to oxide semiconductors. Semiconductor materials other than oxide semiconductors may be used for the semiconductor layer (530). Other semiconductor materials that can be used for the semiconductor layer (530) will be described in [Other Semiconductor Materials] below.

[0316] In FIG. 17 (A), the conductive layer (542a) and the conductive layer (542b) are each shown as single-layer structures, but the present invention is not limited thereto. For example, the conductive layer (542a) and the conductive layer (542b) may each have a stacked structure of two or more layers.

[0317] In FIG. 17 (A) and (B), the conductive layer (560) and the conductive layer (503) are each shown as having a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductive layer (560) and the conductive layer (503) may each have a single-layer structure or a stacked structure of three or more layers.

[0318] An insulating layer (580) is provided over a conductive layer (542a) and a conductive layer (542b) with an insulating layer (544) interposed therein. An opening in the insulating layer (580) is formed to overlap with the region between the conductive layer (542a) and the conductive layer (542b). Thus, the conductive layer (560) is formed to be embedded in the opening of the insulating layer (580) and the region between the conductive layer (542a) and the conductive layer (542b).

[0319] When an oxide semiconductor is used in the semiconductor layer (530), it is preferable to use an insulator in the insulating layer (580) that contains oxygen that is released by heating (hereinafter referred to as excess oxygen). By performing heat treatment on the insulating layer (580) containing excess oxygen, oxygen is supplied from the insulating layer (580) to the channel forming region of the semiconductor layer (530), thereby reducing oxygen deficiency and V O H can be reduced. This stabilizes the electrical characteristics of the transistor (500) and improves reliability.

[0320] In FIG. 17 (A) and (B), the insulating layer (545) is shown as a single-layer structure, but the present invention is not limited thereto. For example, the insulating layer (545) may have a stacked structure of two or more layers.

[0321] An insulating layer (544) is provided to cover the conductive layer (542a) and the conductive layer (542b). It is preferable that the insulating layer (544) has a barrier property against oxygen. By making this configuration, oxidation of the conductive layer (542a) and the conductive layer (542b) can be suppressed.

[0322] An insulating layer (571a) is disposed on a conductive layer (542a), and an insulating layer (571b) is disposed on a conductive layer (542b). By providing the insulating layer (571a) and the insulating layer (571b), when the semiconductor film that becomes the semiconductor layer (530) and the conductive film that becomes the conductive layer (542a) and the conductive layer (542b) are processed collectively into an island shape, it is possible to prevent the ends of each of the conductive layer (542a) and the conductive layer (542b) from being excessively etched. Therefore, fine transistors can be processed with high precision.

[0323] It is preferable that the insulating layer (574) has a function of suppressing the diffusion of impurities such as hydrogen. It is also preferable that the insulating layer (574) has a function of capturing or fixing impurities such as hydrogen. By having this configuration, the diffusion of hydrogen into the semiconductor layer (530) can be suppressed. In addition, the hydrogen concentration within the semiconductor layer (530) can be reduced.

[0324] A conductive layer (540a) is disposed in an opening formed in an insulating layer (581), an insulating layer (574), an insulating layer (580), an insulating layer (544), and an insulating layer (571a), and a conductive layer (540b) is disposed in an opening formed in an insulating layer (581), an insulating layer (574), an insulating layer (580), an insulating layer (544), and an insulating layer (571b). The conductive layer (540a) and the conductive layer (540b) are provided facing each other with a conductive layer (560) in between. The conductive layer (540a) and the conductive layer (540b) function as a via, a contact plug, or wiring.

[0325] In FIG. 17 (A), the conductive layer (540a) and the conductive layer (540b) are each shown as having a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductive layer (540a) and the conductive layer (540b) may each have a single-layer structure or a stacked structure of three or more layers.

[0326] The transistor (500) shown in (A) and (B) of FIG. 17 is an example and is not limited to that configuration; it is acceptable to use an appropriate transistor depending on the circuit configuration, driving method, etc.

[0327] In addition, the transistors that can be used in the present invention are not limited to the transistors (500) shown in (A) and (B) of FIG. 17. For example, a transistor (500) having the structure shown in (C) of FIG. 17 may be used. The transistor (500) shown in (C) of FIG. 17 differs from the transistors (500) shown in (A) and (B) of FIG. 17 in that the conductive layer (542a) and the conductive layer (542b) each have a stacked structure, and the insulating layer (520) and the insulating layer (555) are provided.

[0328] In the transistor (500) shown in (C) of FIG. 17, the conductive layer (542a) has a stacked structure of a conductive layer (542a1) and a conductive layer (542a2) on top of the conductive layer (542a1), and the conductive layer (542b) has a stacked structure of a conductive layer (542b1) and a conductive layer (542b2) on top of the conductive layer (542b1). It is preferable to use a conductor that is difficult to oxidize, such as a metal nitride, for the conductive layer (542a1) and the conductive layer (542b1) that are in contact with the semiconductor layer (530). This prevents the conductive layer (542a) and the conductive layer (542b) from being excessively oxidized due to oxygen contained in the semiconductor layer (530). Additionally, it is preferable to use a conductor with higher conductivity than the conductive layer (542a1) and the conductive layer (542b1) for the conductive layer (542a2) and the conductive layer (542b2). Thus, the conductive layer (542a) and the conductive layer (542b) can be made to function as highly conductive wiring or electrodes. In this way, a semiconductor device can be provided that has the conductive layer (542a) and the conductive layer (542b) in contact with the upper surface of the semiconductor layer (530) and function as wiring or electrodes.

[0329] As shown in (C) of FIG. 17, when the transistor (500) is viewed in a cross-section along the channel length, the distance between the conductive layer (542a1) and the conductive layer (542b1) is shorter than the distance between the conductive layer (542a2) and the conductive layer (542b2). By configuring it this way, the distance between the source and the drain can be made shorter, and accordingly, the channel length can be shortened. In addition, by configuring the stacked structure of the conductive layer (542a2) and the conductive layer (542a2) and the stacked structure of the conductive layer (542b1) and the conductive layer (542b2), the deviation in the manufacturing process of the transistor (500) can be reduced. More specifically, by processing the conductive layer (542a1) and the conductive layer (542b1) after processing the conductive layer (542a2) and the conductive layer (542b2), the deviation in the manufacturing process of the transistor (500) can be reduced. Therefore, the frequency characteristics of the transistor (500) can be improved, and a semiconductor device with a high yield can be realized. By miniaturizing the semiconductor device in this way, a semiconductor device with improved operating speed can be provided.

[0330] An insulating layer (555) is provided in contact with the side of the conductive layer (542a2) and the side of the conductive layer (542b2). It is preferable that the insulating layer (555) has the function of inhibiting the diffusion of oxygen. By making this configuration, oxidation of the side of the conductive layer (542a2) and the side of the conductive layer (542b2) can be inhibited.

[0331] It is desirable that the insulating layer (520) has a barrier property against hydrogen. This suppresses the diffusion of hydrogen into the semiconductor layer (530), thereby reducing the hydrogen concentration within the semiconductor layer (530).

[0332] By using this configuration, it is possible to miniaturize or highly integrate semiconductor devices using transistors including oxide semiconductors.

[0333] Furthermore, the transistors that can be used in the present invention are not limited to the transistors (500) shown in (A) and (C) of FIG. 17. Using FIG. 18 (A) to (D), configurations different from the transistors shown in FIG. 17 (A) to (C) will be described. FIG. 18 (A) is a plan view of a transistor (500A) that can be applied to the transistors (M1 to M3). FIG. 18 (B) to (D) are cross-sectional views of the transistor (500A).

[0334] FIG. 18 (B) is a cross-sectional view of the portion indicated by the dotted line A1-A2 in FIG. 18 (A), and is also a cross-sectional view in the channel width direction of the transistor (500A). FIG. 18 (C) is a cross-sectional view of the portion indicated by the dotted line A3-A4 in FIG. 18 (A), and is also a cross-sectional view in the channel width direction of the transistor (500A). FIG. 18 (D) is a cross-sectional view of the portion indicated by the dotted line A5-A6 in FIG. 18 (A), and is also a cross-sectional view in the channel length direction of the transistor (500A). Here, the dotted line A5-A6 is orthogonal to the dotted line A1-A2 and the dotted line A3-A4, and the dotted line A1-A2 and the dotted line A3-A4 are parallel to each other. In addition, in the plan view of (A) in Fig. 18, some elements were omitted and some elements were shown transparently for clarity of the drawing.

[0335] A transistor (500A) comprises an insulating layer (516) on a substrate (not shown), an insulator (521) on the insulating layer (516), an insulating layer (522) on the insulator (521), a semiconductor layer (530) on the insulating layer (522), a conductive layer (542a) and a conductive layer (542b) on the semiconductor layer (530) and the insulating layer (522), an insulating layer (545) on the semiconductor layer (530), and a conductive layer (560) (conductive layer (560a) and a conductive layer (560b)) on the insulating layer (545). Additionally, the conductive layer (542a) and the conductive layer (542b) may be collectively referred to as the conductive layer (542) below.

[0336] An insulator (575) is provided on the conductive layer (542), and an insulating layer (580) is provided on the insulator (575). The insulating layer (545) and the conductive layer (560) are positioned within an opening provided in the insulating layer (580) and the insulator (575). The opening reaches the semiconductor layer (530), and within the opening, the insulating layer (545) is in contact with the semiconductor layer (530). Additionally, an insulating layer (574) is provided on the insulating layer (580) and on the conductive layer (560). Additionally, an insulator (583) is provided on the insulating layer (574). Additionally, an insulator (515) is provided below the insulating layer (516).

[0337] An insulator (541a) is provided in contact with the inner wall of an opening such as an insulating layer (580), and a conductive layer (540a) is provided in contact with the side of the insulator (541a). The lower surface of the conductive layer (540a) is in contact with the upper surface of the conductive layer (542a). Additionally, an insulator (541b) is provided in contact with the inner wall of an opening such as an insulating layer (580), and a conductive layer (540b) is provided in contact with the side of the insulator (541b). The lower surface of the conductive layer (540b) is in contact with the upper surface of the conductive layer (542b). Furthermore, in the following, the conductive layer (540a) and the conductive layer (540b) may be collectively referred to as the conductive layer (540). Additionally, the insulator (541a) and the insulator (541b) may be collectively referred to as the insulator (541).

[0338] The semiconductor layer (530) includes a region that functions as a channel forming region of the transistor (500A). Additionally, the conductive layer (560) includes a region that functions as a first gate electrode (upper gate electrode) of the transistor (500A). The insulating layer (545) includes a region that functions as a first gate insulator of the transistor (500A).

[0339] The conductive layer (542a) includes a region that functions as one of the source electrode and drain electrode of the transistor (500A). The conductive layer (540a) functions as a plug connected to the conductive layer (542a). The conductive layer (542b) includes a region that functions as the other of the source electrode and drain electrode of the transistor (500A). The conductive layer (540b) functions as a plug connected to the conductive layer (542b).

[0340] The semiconductor layer (530) is formed in contact with the insulating layer (522). The semiconductor layer (530) has a shape with a high aspect ratio when viewed from a cross-section in the channel width direction (a shape where the length H in the height direction is greater than or equal to the length W of the base (H≥W)). The semiconductor layer (530) having a shape with a high aspect ratio may be said to have a fin shape.

[0341] Here, when viewed from a cross-section in the channel width direction, the aspect ratio of the semiconductor layer (530) refers to the ratio of the width L of the semiconductor layer (530) to the height H of the semiconductor layer (530). The aspect ratio of the semiconductor layer (530) is preferably as large as possible within a range where the semiconductor layer (530) does not collapse during the manufacturing process of the transistor (500A). In the semiconductor layer (530), the height H of the semiconductor layer (530) is at least longer than the width L of the semiconductor layer (530). The height H of the semiconductor layer (530) is preferably greater than 1 time and less than 400 times the width L of the semiconductor layer (530), preferably more than 2 times and less than 100 times, more preferably more than 5 times and less than 40 times, and more preferably more than 10 times and less than 20 times. Additionally, for example, the height H may be more than 2 times and less than 10 times the width L. For example, the width L may be 5 nm or more and 100 nm or less, preferably 5 nm or more and 50 nm or less, and more preferably 10 nm or more and 30 nm or less. Also, for example, the height H may be 50 nm or more and 2000 nm or less, preferably 100 nm or more and 1000 nm or less. Also, for example, the height H may be 50 nm or more and 100 nm or less.

[0342] In addition, when viewed in a cross-section in the channel width direction, it is preferable that the angle formed by the side of the semiconductor layer (530) and the upper surface of the insulating layer (522) be a right angle or substantially a right angle. For example, it is preferable that the angle formed by the side of the semiconductor layer (530) and the upper surface of the insulating layer (522) be 80° or more and 100° or less, and more preferable that it be 85° or more and 95° or less.

[0343] An insulating layer (545), a conductive layer (560), and a conductive layer (542) are provided over the semiconductor layer (530) with a high aspect ratio. In the transistor (500A), a portion of the insulating layer (545) and the conductive layer (560) is provided so that they are folded in half with the semiconductor layer (530) in between. Thus, when viewed from a cross-section in the channel width direction, the semiconductor layer (530) and the conductive layer (560) are provided facing each other with the insulating layer (545) in between at the top of the semiconductor layer (530), the side of the A1 side, and the side of the A2 side, respectively. That is, the top of the semiconductor layer (530), the side of the A1 side, and the side of the A2 side, respectively, function as channel forming regions. Therefore, compared to the case where the semiconductor layer (530) is formed in a planar shape, the channel width of the transistor (500A) is larger by the side of the A1 side and the side of the A2 side of the semiconductor layer (530).

[0344] As described above, if the channel width increases, the on-current, mutual conductance, frequency characteristics, etc. of the transistor (500A) can be improved. This allows for the provision of a transistor with a fast operating speed. Additionally, the operating speed of a memory device using the transistor can be improved. Furthermore, in the above structure, by providing a semiconductor layer (530), the channel width can be increased without expanding the occupied area of ​​the transistor (500A). This enables the miniaturization or high integration of the transistor. Additionally, by making the structure as described above, the area where the sides of the conductive layer (560) and the semiconductor layer (530) face each other increases, so the transistor (500A) can be normally turned off by controlling the threshold value.

[0345] Additionally, the upper portion of the semiconductor layer (530) may have a curved shape. By having such a curved shape, it is possible to prevent defects such as voids from forming in the insulating layer (545) and the conductive layer (542) near the upper portion of the semiconductor layer (530).

[0346] Since the semiconductor layer (530) has a shape with a high aspect ratio, it is desirable to form a sidewall shape on the side of the filler composed of an insulator. Therefore, it is desirable to form the semiconductor layer (530) using an ALD method with good coverage properties. In addition, when the semiconductor layer (530) has a stacked structure, it is desirable to form at least one layer, preferably the layer in contact with the filler, using an ALD method.

[0347] By forming a semiconductor layer (530) in a sidewall shape in contact with the sides of multiple fillers, multiple semiconductor layers (530) can be formed simultaneously as shown in (A) of FIG. 18. By forming multiple semiconductor layers (530) in this way, the distance between each semiconductor layer (530) can be set according to the size and shape of the fillers. Therefore, by shortening the distance between each semiconductor layer (530), the occupied area of ​​the transistor (500A) can be reduced and the transistor can be highly integrated.

[0348] Since the semiconductor layer (530) is formed in a sidewall shape in contact with the filler, as shown in FIG. 18 (A), the upper surface shape of the semiconductor layer (530) becomes a perimeter shape (which may also be called a border shape, ring shape, donut shape, or closed curve shape) with both ends aligned. Additionally, the semiconductor layer (530) may be a shape having an opening in the center. Furthermore, in FIG. 18 (A), the upper surface shape of the semiconductor layer (530) is shown as a line-symmetric shape centered on A1-A2, but the present invention is not limited thereto. For example, the upper surface shape of the semiconductor layer (530) may be an asymmetric shape.

[0349] The structure shown in FIG. 18 (A) is a structure in which two pillars are arranged in the A1-A2 direction, and a periphery-shaped semiconductor layer (530) is formed in contact with the side of each pillar. As shown in FIG. 18 (A), it is preferable that the semiconductor layer (530) overlaps with the conductive layer (560) at two or more locations when viewed from a planar view. That is, it includes two or more regions where the semiconductor layer (530) and the conductive layer (560) overlap. By making the structure this way, as shown in FIG. 18 (B), multiple fin-shaped semiconductor layers (530) are formed when viewed from a cross-section in the channel width direction. Each of the multiple fin-shaped semiconductor layers (530) functions as a channel forming region. That is, the transistor (500A) functions as a multi-channel type transistor. Therefore, the channel width in the transistor (500A) can be made larger.

[0350] In addition, the configuration of the transistor (500A) applicable to the transistors (M1 to M3) described using (A) to (D) of FIG. 18 may include a conductive layer (503) under an insulator (521), as in the transistor (500B) shown in (A) to (D) of FIG. 19. The conductive layer (503) includes a region that functions as the second gate electrode (lower gate electrode) of the transistor (500B). In addition, the insulating layer (522) and the insulator (521) each include a region that functions as the second gate insulator of the transistor (500B). Here, since FIG. 19 (A) to (D) corresponds to FIG. 18 (A) to (D), the above description may be used for detailed configurations.

[0351] In the transistor (500B), the conductive layer (503) is arranged to overlap with the semiconductor layer (530) and the conductive layer (560). Here, it is preferable that the conductive layer (503) be provided by being embedded in an opening formed in the insulating layer (516). Additionally, as shown in (A) and (B) of FIG. 19, it is preferable that the conductive layer (503) be provided extending in the channel width direction. By having this configuration, when providing a plurality of transistors, the conductive layer (503) functions as wiring.

[0352] As shown in (B) and (D) of FIG. 19, the conductive layer (503) preferably comprises a conductive layer (503a) and a conductive layer (503b). The conductive layer (503a) is provided in contact with the bottom surface and side wall of the opening. The conductive layer (503b) is provided to fill the recess of the conductive layer (503a) formed along the opening. Here, the height of the upper surface of the conductive layer (503) matches or substantially matches the height of the upper surface of the insulating layer (516).

[0353] Here, the conductive layer (503a) preferably comprises a conductive material having a function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms. Alternatively, it is preferable to comprise a conductive material having a function of inhibiting the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0354] By using a conductive material having a function to reduce the diffusion of hydrogen in the conductive layer (503a), impurities such as hydrogen contained in the conductive layer (503b) can be prevented from diffusing into the semiconductor layer (530) through the insulating layer (516), etc. Additionally, by using a conductive material having a function to suppress the diffusion of oxygen in the conductive layer (503a), the oxidation of the conductive layer (503b) and the resulting decrease in conductivity can be prevented. Examples of conductive materials having a function to suppress the diffusion of oxygen include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The conductive layer (503a) may have a single-layer structure or a stacked structure of the above conductive material. For example, it is preferable that the conductive layer (503a) includes titanium nitride.

[0355] In addition, it is preferable to use a conductive material with tungsten, copper, or aluminum as the main component for the conductive layer (503b). For example, it is preferable that the conductive layer (503b) contains tungsten.

[0356] The conductive layer (503) can function as a second gate electrode. In this case, the threshold voltage Vth of the transistor (500B) can be controlled by changing the potential applied to the conductive layer (503) independently without linking it with the potential applied to the conductive layer (560). In particular, by applying a negative potential to the conductive layer (503), the Vth of the transistor (500B) can be made larger to reduce the off-current. Therefore, when a negative potential is applied to the conductive layer (503), the drain current when the potential applied to the conductive layer (560) is 0V can be reduced compared to when it is not applied.

[0357] In addition, the electrical resistivity of the conductive layer (503) is designed considering the potential applied to the conductive layer (503), and the film thickness of the conductive layer (503) is set according to the electrical resistivity. Also, the film thickness of the insulating layer (516) is almost the same as that of the conductive layer (503). Here, it is desirable to thin the film thickness of the conductive layer (503) and the insulating layer (516) within the design allowable range of the conductive layer (503). By thinning the film thickness of the insulating layer (516), the absolute amount of impurities such as hydrogen contained in the insulating layer (516) can be reduced, and thus the diffusion of said impurities into the semiconductor layer (530) can be suppressed.

[0358] In addition, although the stacked structure of the conductive layer (503a) and the conductive layer (503b) has been described above, the present invention is not limited thereto, and the conductive layer (503) may have a single-layer structure or a stacked structure of three or more layers. For example, if the conductive layer (503) has a three-layer stacked structure, a conductor including a material similar to that of the conductive layer (503a) may be further provided on the conductive layer (503b) in the stacked structure of the conductive layer (503a) and the conductive layer (503b). In this case, the upper surface of the conductive layer (503b) may be lower than the uppermost part of the conductive layer (503a), and the conductor may be formed to fill the concave portion formed by the conductive layer (503a) and the conductive layer (503b).

[0359] <DOSRAM의 구성예>

[0360] FIG. 20 shows an example of a cross-sectional configuration using a DOSRAM circuit configuration. FIG. 20 illustrates a case where device layers (UF[1]) to device layers (UF[3]) are stacked on a device layer (LF). FIG. 21 (A) also shows an example of a cross-sectional structure of a device layer (UF[k]). FIG. 21 (B) also shows an equivalent circuit diagram of FIG. 21 (A).

[0361] In FIG. 20, each of the plurality of device layers (UF) includes a plurality of memory cells (41). In each of the device layers (UF[1]) to (UF[3]) shown in FIG. 20, an example is shown in which two memory cells (41) are connected to one bit line (BL). The memory cell (41) shown in FIG. 20 includes a transistor (M1) and a capacitor (C1). In the memory cell (41) shown in FIG. 20, the capacitor (C1) is provided below the transistor (M1). An OS transistor can be used as the transistor (M1).

[0362] Additionally, a conductive layer (363a), a conductive layer (363b), and a conductive layer (363c) are embedded in the interlayer film between the device layer (LF) and the device layer (UF[1]). Furthermore, in each of the plurality of device layers (UF), a conductive layer (365) is embedded in the insulating layer (180) described later. Additionally, in each of the plurality of device layers (UF), a conductive layer (366) is embedded in the insulating layer (180) and the insulating layer (280) described later. Furthermore, in each of the plurality of device layers (UF), a conductive layer (367) is embedded in the semiconductor layer (270), the insulating layer (250), and the insulating layer (285) described later. The conductive layer (363a), the conductive layer (363b), the conductive layer (363c), the conductive layer (365), the conductive layer (366), and the conductive layer (367) function as vias, contact plugs, or wiring.

[0363] Next, an example of the configuration of a memory cell (41) included in a plurality of element layers (UF) shown in FIG. 20 will be described.

[0364] FIG. 22 (A) is a plan view showing a configuration example of a memory cell (41) included in each of a plurality of element layers (UF) and its surroundings. FIG. 22 (B) is a plan view with some of the components shown in FIG. 22 (A) omitted. FIG. 22 (C) is a cross-sectional view along the dotted line A1-A2 shown in FIG. 22 (A). In FIG. 22 (A), some of the components of the transistor (VM1), such as an insulating layer (250), for example, have been omitted. In addition, some of the components, such as the insulating layer, have also been omitted in the subsequent plan view of the transistor.

[0365] In (A) to (C) of FIG. 22, the transistor (VM1) corresponds to the transistor (M1) in FIG. 20, and the capacitor (VC1) corresponds to the capacitor (C1) in FIG. 20.

[0366] In (C) of FIG. 22, an insulating layer (160) is placed on a substrate (not shown), an insulating layer (180) is placed on the insulating layer (160), an insulating layer (280) is placed on the insulating layer (180), and an insulating layer (285) is placed on the insulating layer (280).

[0367] A conductive layer (110) is provided on the insulating layer (160). The conductive layer (110) can be, for example, a wiring (PL) extending in the Y direction.

[0368] An opening (601) is provided in the region of the insulating layer (180) that overlaps with the conductive layer (110). A conductive layer (115) is provided to be in contact with the bottom surface and side wall of the opening (601). That is, the conductive layer (115) includes a region in contact with the upper surface of the conductive layer (110) and a region in contact with the side of the insulating layer (180) at the opening (601). Also, in (C) of FIG. 22, the conductive layer (115) includes a region in contact with the upper surface of the insulating layer (180).

[0369] An insulating layer (130) is provided on the insulating layer (180) and on the conductive layer (115). Additionally, a conductive layer (220) is provided on the insulating layer (130). The conductive layer (220) is provided to fill the opening (601).

[0370] The capacitor (VC1) includes a conductive layer (115), a conductive layer (220), and an insulating layer (130).

[0371] In the capacitor (VC1), the conductive layer (115) functions as one of a pair of electrodes, the conductive layer (220) functions as the other of a pair of electrodes, and the insulating layer (130) functions as a dielectric layer fitted between the pair of electrodes.

[0372] A transistor (VM1) is provided on the upper side of the capacitor (VC1). The transistor (VM1) includes a conductive layer (220), a conductive layer (240), a semiconductor layer (270), an insulating layer (250), and a conductive layer (260).

[0373] In the transistor (VM1), the conductive layer (260) functions as a gate electrode, and the insulating layer (250) functions as a gate insulating film. The conductive layer (220) and the conductive layer (240) each function as a source electrode or a drain electrode. Additionally, as described above, the conductive layer (220) also functions as the other side of a pair of electrodes of the capacitor (VC1).

[0374] In the semiconductor layer (270), the entire region facing the gate electrode, with a gate insulating film in between the source electrode and the drain electrode, functions as a channel forming region. Additionally, in the semiconductor layer (270), the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0375] The insulating layer (280) can function as an interlayer insulating layer. Here, the interlayer insulating layer can be an interlayer film for separating the source electrode and the drain electrode in the transistor (VM1).

[0376] A conductive layer (240) is provided on top of an insulating layer (280). An opening (602) reaching the conductive layer (220) is provided in the insulating layer (280). An opening (603) reaching the opening (602) is provided in the conductive layer (240). That is, the opening (603) includes an area that overlaps with the opening (602).

[0377] FIG. 22 (A) shows a conductive layer (220), a conductive layer (240), a conductive layer (260), an opening (602), and an opening (603). FIG. 22 (B) shows an example of a configuration in which the conductive layer (260) is omitted from the components shown in FIG. 22 (A). That is, FIG. 22 (B) shows a conductive layer (220), a conductive layer (240), an opening (602), and an opening (603).

[0378] Figures 22 (A) and (B) illustrate examples in which the shapes of the opening (602) and the opening (603) are circular when viewed from a planar perspective. By making the planar shape (shape and contour of the object when viewed from a planar perspective) of the opening (602) and the opening (603) circular, the processing precision when forming the opening (602) and the opening (603) can be increased, thereby enabling the formation of openings (602) and the opening (603) of a small size. Thus, miniaturization or high integration of memory cells is possible. Furthermore, in this specification, the circular shape is not limited to a perfect circle. For example, the planar shape of the opening (602) and the opening (603) may be elliptical, or may be a shape including curves. Alternatively, it may be polygonal, or may be a shape with rounded corners of a polygon.

[0379] The description of the shape of the opening (602) and the opening (603) can also be applied to the opening (601).

[0380] It is preferable that the conductive layer (240) is not provided inside the opening (602). That is, it is preferable that the conductive layer (240) does not come into contact with the side of the insulating layer (280) on the side of the opening (602). By making this configuration, the opening (603) and the opening (602) can be formed together, thereby simplifying the process.

[0381] Figure 22 (C) shows an example in which the lower end of the conductive layer (240) at the opening (603) coincides with or substantially coincides with the upper end of the insulating layer (280) at the opening (602). Also, in this specification, the lower end of the conductive layer (240) refers to the surface on the side of the insulating layer (280). The upper surface of the insulating layer (280) refers to the surface on the side of the conductive layer (240).

[0382] Furthermore, "the ends coincide or substantially coincide" can also be described as "the ends are aligned or substantially aligned." When the ends are aligned or substantially aligned, and when the planar shapes coincide or substantially coincide, it can be said that at least a portion of the contours overlap between the stacked layers when viewed from a plane. For example, this category includes cases where the upper and lower layers are processed using the same mask pattern or partially the same mask pattern. However, strictly speaking, there are cases where the contours do not overlap and the upper layer is located inside or outside the lower layer; in such cases, it is also referred to as "the ends are substantially aligned" or "the planar shapes substantially coincide."

[0383] In the following description, an opening including an opening (602) and an opening (603) may be referred to as an opening (290). That is, an opening (290) reaching the conductive layer (220) is provided in the insulating layer (280) and the conductive layer (240). Additionally, the opening (602) is part of the opening (290), and the opening (603) is another part of the opening (290).

[0384] At least a portion of the semiconductor layer (270) is disposed in the opening (290). The semiconductor layer (270) includes an area in contact with the side of the conductive layer (240) at the opening (290), an area in contact with the side of the insulating layer (280), and an area in contact with the upper surface of the conductive layer (220). The semiconductor layer (270) includes an area in contact with the upper surface of the conductive layer (240).

[0385] At least a portion of the insulating layer (250) is disposed in the opening (290). The insulating layer (250) is provided over the semiconductor layer (270) and over the insulating layer (280). The insulating layer (250) includes an area in contact with the upper surface of the semiconductor layer (270), an area in contact with the side of the semiconductor layer (270), an area in contact with the side of the conductive layer (240), and an area in contact with the upper surface of the insulating layer (280).

[0386] A conductive layer (260) is provided on an insulating layer (250) and includes an area in contact with the upper surface of the insulating layer (250). The conductive layer (260) is provided to fill an opening (290). The conductive layer (260) is provided to fill a recess of the insulating layer (250) that reflects the shape of the opening (290). The conductive layer (260) includes an area that overlaps with the semiconductor layer (270) through the insulating layer (250).

[0387] In FIG. 22 (C), an example is shown in which the conductive layer (260) includes an area overlapping with the conductive layer (240) through an insulating layer (250) and a semiconductor layer (270), but the present invention is not limited thereto. For example, the conductive layer (260) may be provided so as not to overlap with the conductive layer (240). By making such a configuration, the parasitic capacitance between the conductive layer (260) and the conductive layer (240) can be reduced. Thus, the operating speed of the memory cell can be improved.

[0388] The transistor (VM1) has a configuration in which the channel length direction is not substantially parallel to the substrate (not shown) and follows the sidewall of the opening (602) provided in the insulating layer (280). Thus, the transistor (VM1) is a vertical transistor.

[0389] Figure 22 (A) shows an example in which a conductive layer (240) extends in a direction perpendicular to the conductive layer (110) and the conductive layer (260).

[0390] Here, an enlarged view of the semiconductor layer (270) and its vicinity in (C) of FIG. 22 is shown in (A) of FIG. 23. Additionally, a cross-sectional view in the XY plane including the conductive layer (240) is shown in (B) of FIG. 23.

[0391] As shown in (A) of FIG. 23, the semiconductor layer (270) includes a region (270i), a region (270na) and a region (270nb) provided to interpose the region (270i).

[0392] Region (270na) is a region in the semiconductor layer (270) that is in contact with the conductive layer (220). Region (270nb) is a region in the semiconductor layer (270) that is in contact with the conductive layer (240). Regions (270na) and (270nb) each function as a source region or a drain region of the transistor (VM1). As shown in (B) of FIG. 23, the conductive layer (240) is in contact with the entire outer periphery of the semiconductor layer (270). Therefore, the source region or drain region of the transistor (VM1) can be formed on the entire outer periphery of the portion formed in the same layer as the conductive layer (240) in the semiconductor layer (270).

[0393] Region (270i) is a region sandwiched between region (270na) and region (270nb) in the semiconductor layer (270). Region (270i) functions as a channel forming region of the transistor (VM1). That is, the channel forming region of the transistor (VM1) is formed in a part of the semiconductor layer (270) located in the region between the conductive layer (220) and the conductive layer (240). Additionally, the channel forming region of the transistor (VM1) may be located in the region in contact with the insulating layer (280) in the semiconductor layer (270) or in a region near it.

[0394] The channel length of the transistor (VM1) is the distance between the source region and the drain region. That is, the channel length of the transistor (VM1) can be said to be determined by the thickness of the insulating layer (280) on the conductive layer (220). In FIG. 23 (A), the channel length L of the transistor (VM1) is indicated by a dashed double-sided arrow. The channel length L is the distance between the end of the region where the semiconductor layer (270) and the conductive layer (220) meet and the end of the region where the semiconductor layer (270) and the conductive layer (240) meet when viewed from a cross-section. That is, the channel length L corresponds to the length of the side of the opening (602) of the insulating layer (280) when viewed from a cross-section.

[0395] In a planar type transistor, the channel length is set to the exposure limit of photolithography, but in the present invention, it can be set to the film thickness of the insulating layer (280). Therefore, the channel length of the transistor (VM1) can be made into a very fine structure below the exposure limit of photolithography. This increases the on-current of the transistor (VM1), thereby improving frequency characteristics. Thus, a semiconductor device with a fast operating speed can be provided.

[0396] In addition, as described above, a channel forming region, a source region, and a drain region can be formed in the opening (290). This allows the occupied area of ​​the transistor (VM1) to be reduced compared to a planar transistor in which the channel forming region, the source region, and the drain region are provided separately on the XY plane. Since this allows for high integration of the semiconductor device, the memory capacity per unit area can be increased.

[0397] In addition, in the XY plane including the channel formation region of the semiconductor layer (270), the semiconductor layer (270), the insulating layer (250), and the conductive layer (260) are provided concentrically as in (B) of FIG. 23. Thus, the side of the conductive layer (260) provided at the center faces the side of the semiconductor layer (270) with the insulating layer (250) in between. That is, when viewed from a plane, the entire perimeter of the semiconductor layer (270) becomes the channel formation region. At this time, for example, the channel width of the transistor (VM1) is determined according to the length of the outer circumference of the semiconductor layer (270). That is, the channel width of the transistor (VM1) can be said to be determined according to the size of the maximum width of the opening (602). In FIG. 23 (A) and (B), the maximum width D of the opening (602) is indicated by a dotted double-sided arrow. In FIG. 23 (B), the channel width W of the transistor (VM1) is indicated by a dotted double-sided arrow. By increasing the size of the maximum width D of the opening (602), the channel width per unit area can be increased, thereby increasing the on current.

[0398] When the opening (602) is formed using a photolithography method, the maximum width D of the opening (602) is set to the exposure limit of the photolithography. Additionally, the maximum width D of the opening (602) is set according to the film thickness of each of the semiconductor layer (270), insulating layer (250), and conductive layer (260) provided to the opening (602). Furthermore, if the opening (602) is circular when viewed from a plane, the maximum width D of the opening (602) corresponds to the diameter of the opening (602), and the channel width W can be calculated as 'D × π'.

[0399] Additionally, the maximum width D of the opening (602) should be appropriately calculated according to the shape of the opening (602) when viewed in a planar view. For example, if the opening (602) is a rectangle when viewed in a planar view, the maximum width of the opening (602) should be the length of the diagonal of the rectangle. Or, for example, if the opening (602) is an ellipse, a polygon, or a polygon with rounded corners when viewed in a planar view, the maximum width of the opening (602) should be the diameter of the minimum bounding circle that encompasses the shape of the opening (602) when viewed in a planar view.

[0400] In addition, in a semiconductor device of one embodiment of the present invention, it is preferable that the channel length L of the transistor (VM1) is at least smaller than the channel width W of the transistor (VM1). According to one embodiment of the present invention, the channel length L of the transistor (VM1) is 0.1 times or more and 0.99 times or less with respect to the channel width W of the transistor (VM1), preferably 0.5 times or more and 0.8 times or less. By making such a configuration, a transistor having good electrical characteristics and high reliability can be realized.

[0401] In addition, by forming an opening (602) that is substantially circular when viewed from a plane, the semiconductor layer (270), the insulating layer (250), and the conductive layer (260) are provided concentrically. As a result, the distance between the conductive layer (260) and the semiconductor layer (270) becomes substantially uniform, so that a gate electric field can be applied substantially uniformly to the semiconductor layer (270).

[0402] In addition, in Fig. 23 (A), etc., the opening (602) is provided such that the side of the opening (602) is perpendicular to the upper surface of the conductive layer (220), but the present invention is not limited thereto. For example, the side of the opening (602) may be tapered.

[0403] In addition, the term "tapered shape" in this specification and others refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface. For example, it is preferable to include a region in which the angle formed between the inclined side and the substrate surface (also called the taper angle) is less than 90°.

[0404] As shown in (C) of FIG. 22, a portion of the insulating layer (250) is located outside the opening (603), that is, on the insulating layer (280). At this time, it is preferable that the insulating layer (250) covers the side end of the conductive layer (240). This prevents the conductive layer (260) and the conductive layer (240) from being short-circuited.

[0405] In the semiconductor layer (270), a semiconductor that can be applied to the semiconductor layer (530) described above may be used as a single layer or in a stacked manner. Additionally, regarding the configuration of the semiconductor layer (270), the configuration of the semiconductor layer (530) described above may also be referenced.

[0406] It is preferable that the semiconductor layer (270) includes a layered crystal substantially parallel to the side of the insulating layer (280) at the opening (602). By making this configuration, the layered crystal of the semiconductor layer (270) is formed substantially parallel to the channel length direction of the transistor (VM1), so the on-current of the transistor can be increased.

[0407] By contacting the semiconductor layer (270) and the conductive layer (220), a metal compound or oxygen vacancy is formed, and the region (270na) of the semiconductor layer (270) becomes low resistance. By making the semiconductor layer (270) in contact with the conductive layer (220) low resistance, the contact resistance between the semiconductor layer (270) and the conductive layer (220) can be reduced. Similarly, by contacting the semiconductor layer (270) and the conductive layer (240), the region (270nb) of the semiconductor layer (270) becomes low resistance. Therefore, the contact resistance between the semiconductor layer (270) and the conductive layer (240) can be reduced.

[0408] The conductive layer (240) may have a stacked structure of a first conductive layer and a second conductive layer on top of the first conductive layer. In this case, the first conductive layer may be formed using a highly conductive material, and the second conductive layer may be formed using a conductive material containing oxygen. When an oxide semiconductor is used in the semiconductor layer (270), by using a conductive material containing oxygen in the second conductive layer of the conductive layer (240) that contacts the semiconductor layer (270), the contact resistance between the second conductive layer of the conductive layer (240) and the semiconductor layer (270) can be reduced, thereby suppressing the decrease in the on-current of the transistor (VM1) caused by contact resistance. For example, it is preferable to use tungsten in the first conductive layer of the conductive layer (240) and indium tin oxide containing silicon in the second conductive layer of the conductive layer (240).

[0409] The conductive layer (220) is provided with a recess at a position overlapping with the opening (602). The semiconductor layer (270) contacts the bottom and side surfaces of the recess included in the conductive layer (220). Additionally, the recess included in the conductive layer (220) may be considered as part of the opening (290).

[0410] By including a recess at a position where the conductive layer (220) overlaps with the opening (602), the height of the lower surface of the insulating layer (250) and the lower surface of the conductive layer (260) at the opening (290) can each be lowered compared to the height of the upper surface of the conductive layer (220) in contact with the insulating layer (280) relative to the upper surface of the insulating layer (160) compared to the case where the recess is not included. Here, the height of each surface can be determined based on the surface to be formed of the memory cell or transistor. Here, the upper surface of the insulating layer (160) is used as the reference. The surface used as the reference is not particularly limited, and, for example, may be used as the reference for the upper surface of the substrate on which the memory cell or transistor is provided.

[0411] This allows the contact area between the conductive layer (220) and the semiconductor layer (270) to be increased, thereby reducing the contact resistance between the conductive layer (220) and the semiconductor layer (270). Consequently, the decrease in the on-current of the transistor (VM1) caused by the contact resistance between the conductive layer (220) and the semiconductor layer (270) can be suppressed. Additionally, since the gate electric field becomes easier to apply to the channel formation region of the semiconductor layer (270), the electrical characteristics of the transistor (VM1) can be improved. Furthermore, since the gate electric field becomes easier to apply to the region in contact with the conductive layer (220) in the semiconductor layer (270), the on-current of the transistor (VM1) can be increased. Additionally, the electrical characteristics of the transistor (VM1) can be improved even if either the conductive layer (220) or the conductive layer (240) is used as the drain electrode.

[0412] In addition, it is preferable to use a conductive material containing oxygen in the conductive layer (220). When an oxide semiconductor is used in the semiconductor layer (270), the contact resistance between the semiconductor layer (270) and the conductive layer (220) can be reduced by using a conductive material containing oxygen in the conductive layer (220).

[0413] In addition, the conductive layer (220) may use a structure in which tungsten is laminated under a conductive material containing oxygen. By providing tungsten laminated in this way, the conductivity of the conductive layer (220) can be improved.

[0414] Since the insulating layer (280) and the insulating layer (285) function as interlayer films, it is desirable that they have a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the capacitance value of the parasitic capacitance generated between the wires can be reduced.

[0415] In addition, it is desirable that the concentration of impurities such as water and hydrogen within the insulating layer (280) be reduced. This prevents impurities such as water and hydrogen from being mixed into the channel forming region of the semiconductor layer (270).

[0416] In addition, it is preferable to use an insulator containing excess oxygen in the insulating layer (280). By performing heat treatment on the insulating layer (280) containing excess oxygen, oxygen is supplied from the insulating layer (280) to the channel forming region of the semiconductor layer (270), thereby reducing oxygen deficiency and V O H can be reduced. This stabilizes the electrical characteristics of the transistor (VM1) and improves reliability.

[0417] In addition, the transistor that can be used in the present invention is not limited to the transistor (VM1) shown in (C) of FIG. 22. For example, a transistor (VM2) having the structure shown in FIG. 24 may be used. The transistor (VM2) shown in FIG. 24 is different from the transistor (VM1) shown in (C) of FIG. 22 in that it is provided with a conductive layer (215) and an insulating layer (225).

[0418] The configuration shown in FIG. 24 corresponds to the memory cell (41A) shown in FIG. 7 (A). In the memory cell (41A) shown in FIG. 24, a transistor (VM2) is provided above the capacitor (VC1).

[0419] As shown in FIG. 24, a conductive layer (215) is provided on an insulating layer (280). Additionally, an insulating layer (281) is disposed on the insulating layer (280) and on the conductive layer (215). Additionally, a conductive layer (240) is provided on the insulating layer (281).

[0420] An opening (604) reaching the conductive layer (220) is provided in the insulating layer (280), the conductive layer (215), the insulating layer (281), and the conductive layer (240). The opening (604) includes an opening contained in the insulating layer (280), an opening contained in the conductive layer (215), an opening contained in the insulating layer (281), and an opening contained in the conductive layer (240). The side walls of the opening (604) include the side of the insulating layer (280), the side of the conductive layer (215), the side of the insulating layer (281), and the side of the conductive layer (240).

[0421] Each of the insulating layer (225), semiconductor layer (270), insulating layer (250), and conductive layer (260) is provided such that at least a portion thereof is located in the opening (604). Specifically, the insulating layer (225) is provided to cover a portion of the bottom part of the opening (604) and the side wall, the semiconductor layer (270) is provided to cover another portion of the bottom part of the opening (604) and the insulating layer (225), and the insulating layer (250) is provided to cover the semiconductor layer (270). Additionally, the conductive layer (260) is provided to fill the concave portion of the insulating layer (250) that reflects the shape of the opening (604).

[0422] The insulating layer (225) is in contact with a portion of the upper surface of the conductive layer (220), the side of the insulating layer (280), the side of the conductive layer (215), the side of the insulating layer (281), and the side of the conductive layer (240) at the opening (604).

[0423] In the transistor (VM2) shown in FIG. 24, the semiconductor layer (270) functions as a semiconductor layer, the conductive layer (260) functions as a first gate electrode, the insulating layer (250) functions as a first gate insulating film, the conductive layer (215) functions as a second gate electrode, the insulating layer (225) functions as a second gate insulating film, and the conductive layer (220) and the conductive layer (240) each function as a source electrode or a drain electrode.

[0424] By changing the potential applied to the conductive layer (215) independently without linking it with the potential applied to the conductive layer (260), the threshold voltage V of the transistor th It can be controlled. In particular, by applying a negative potential to the conductive layer (215), the V of the transistor thThe off-current can be reduced by making it larger. Therefore, when a negative potential is applied to the conductive layer (215), the drain current when the potential applied to the conductive layer (260) is 0V can be reduced compared to when it is not applied. Additionally, the conductive layer (260) may be made to function as a second gate electrode and the conductive layer (215) may be made to function as a first gate electrode.

[0425] Alternatively, the conductive layer (215) may be connected to the conductive layer (260). By connecting the conductive layer (215) and the conductive layer (260) and applying the same potential, it is possible to increase the on-current, reduce the initial characteristic deviation, suppress the deterioration of electrical characteristics in the -GBT (Gate Bias-Temperature) stress test, and suppress fluctuations in the rise voltage of the on-current at different drain voltages.

[0426] As described above, since the transistor (VM2) shown in FIG. 24 includes a first gate electrode and a second gate electrode, the electrical characteristics of the transistor included in the semiconductor device can be improved.

[0427] <NOSRAM의 구성예 2>

[0428] Figures 25 (A) and (B) show examples of transistor configurations applicable to the circuit configuration of a two-transistor type NOSRAM. Figure 25 (A) is an example of a perspective view of a semiconductor device in which a plurality of memory cells (41F), including a transistor (VT1) and a transistor (VT2) provided in a stacked manner, are arranged side by side. The transistors (VT1) and (VT2) are vertical transistors. The memory cells (41F) are connected to a conductive layer (220a), a conductive layer (240a), a conductive layer (240b), and a conductive layer (210). In addition, for clarity, insulating layers such as interlayer films are not shown in Figure 25 (A), and the conductive layer (210) located at the top is shown as a dashed line.

[0429] The conductive layer (220a) shown in FIG. 25 (A) functions as a readable bit line (RBL) shown in FIG. 7 (F), etc. The conductive layer (240a) shown in FIG. 25 (A) functions as a readable word line (RWL) shown in FIG. 7 (F), etc. The conductive layer (240b) shown in FIG. 25 (A) functions as a recordable bit line (WBL) shown in FIG. 7 (F), etc. The conductive layer (210) shown in FIG. 25 (A) functions as a recordable word line (WWL) shown in FIG. 7 (F), etc.

[0430] In the memory cell (41F) shown in FIG. 25 (A), a transistor (VT2) is provided above the transistor (VT1). The transistor (VT2) shown in FIG. 25 (A) corresponds to the transistor (M1) of the memory cell (41F) shown in FIG. 7 (F). The transistor (VT1) shown in FIG. 25 (A) corresponds to the transistor (M2) of the memory cell (41F) shown in FIG. 7 (F).

[0431] In addition, Figure 25 (A) shows an example in which memory cells (41F) are arranged at equal intervals in the X and Y directions, but memory cells (41F) may be arranged in a staggered pattern in which they are arranged alternately one by one.

[0432] The transistor (VT1) includes a conductive layer (220a), a conductive layer (240a), and a conductive layer (260a) as components. The transistor (VT2) includes a conductive layer (260a), a conductive layer (240b), and a conductive layer (260b) as components.

[0433] Next, an example of the configuration of the memory cell (41F) will be described. Figure 25 (B) is a perspective view illustrating an example of the configuration of the memory cell (41F). Additionally, for clarity, insulating layers such as interlayer films are not shown, and a portion of the conductive layer (220a), the conductive layer (240a), and the conductive layer (240b), and the conductive layer (210) are shown with dashed lines.

[0434] The memory cell (41F) shown in (B) of FIG. 25 has a configuration in which a semiconductor layer (270a) is provided in an opening provided in the conductive layer (240a) of the transistor (VT1), and the side of the conductive layer (240a) at the opening is in contact with the semiconductor layer (270a).

[0435] Figure 26 (A) is a plan view illustrating a transistor (VT1), and Figure 26 (B) is a plan view illustrating a transistor (VT2). In addition, some elements have been omitted in the plan views for clarity.

[0436] Figure 26 (C) is a drawing corresponding to the cross-section of line segment A1-A2 shown in Figures 26 (A) and (B). Figure 26 (D) is a drawing corresponding to the cross-section of line segment B1-B2 shown in Figures 26 (A) and (B).

[0437] The memory cell (41F) includes an insulating layer (160) on a substrate (not shown), a transistor (VT1) provided on the insulating layer (160), and a transistor (VT2) provided on the transistor (VT1). Additionally, insulating layers (280a), insulating layers (280b), and insulating layers (285), which function as interlayer films, may be provided between the transistors and between various wirings.

[0438] The transistor (VT1) includes a conductive layer (220a), a conductive layer (240a), a semiconductor layer (270a), an insulating layer (250a), and a conductive layer (260a). In the transistor (VT1), the semiconductor layer (270a) functions as a semiconductor layer, the conductive layer (260a) functions as a gate electrode, and the insulating layer (250a) functions as a gate insulating film. Additionally, the conductive layer (220a) and the conductive layer (240a) each function as a source electrode or a drain electrode.

[0439] That is, the transistor (VT1) has a structure corresponding to the structure of the transistor (VM1) shown in (C) of FIG. 22. Therefore, in the drawings, the corresponding configurations of the transistor (VM1) and the transistor (VT1) are basically assigned the same three-digit number as a symbol. Also, unless otherwise specifically mentioned, the description of the transistor (VM1) may be referred to for the transistor (VT1).

[0440] The transistor (VT2) includes a conductive layer (260a), a conductive layer (240b), a semiconductor layer (270b), an insulating layer (250b), and a conductive layer (260b). In the transistor (VT2), the semiconductor layer (270b) functions as a semiconductor layer, the conductive layer (260b) functions as a gate electrode, and the insulating layer (250b) functions as a gate insulating film. Additionally, the conductive layer (260a) and the conductive layer (240b) function as a source electrode or a drain electrode.

[0441] That is, the transistor (VT2) has a structure corresponding to the structure of the transistor (VM1) shown in (C) of FIG. 22. Therefore, in the drawings, the corresponding configurations of the transistor (VM1) and the transistor (VT2) are basically assigned the same three-digit number as a symbol. Also, unless specifically mentioned otherwise below, the description of the transistor (VM1) may be referred to for the transistor (VT2). In addition, the conductive layer (260a) corresponds to the conductive layer (220) in the transistor (VM1). Therefore, the description of the conductive layer (220) described above may be referred to for the conductive layer (260a).

[0442] In addition, the transistor (VM2) shown in FIG. 24 may be applied to one or both of the transistors (VT1) and (VT2).

[0443] It can also be said that the conductive layer (260a) includes a region that shares one of the gate electrode of the transistor (VT1) and the source electrode and drain electrode of the transistor (VT2).

[0444] The conductive layer (260b) is connected to the conductive layer (210) formed on the conductive layer (260b). Additionally, the conductive layer (260b) and the conductive layer (210) may be formed as the same element.

[0445] It is preferable that the upper surface shape of the conductive layer (260a) and the conductive layer (260b) be substantially circular. By making this configuration, the integration density of the memory cell (41F) can be increased. Additionally, regarding the upper surface shape of the conductive layer (260a) and the conductive layer (260b), one can refer to the description of the shape of the opening (602) and the above-described shape.

[0446] In order to increase the overlap area between the transistor (VT2) and the transistor (VT1), it is preferable to make the upper surface shape of the opening (290b) and the upper surface shape of the opening (290a) where the transistor (VT1) is formed have the same or similar shape.

[0447] <Constituent materials of semiconductor devices>

[0448] The following describes the constituent materials that can be used in semiconductor devices.

[0449] [Circuit board]

[0450] As substrates suitable for use in semiconductor devices, it is preferable to use, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttria-stabilized zirconia substrates), and resin substrates. Additionally, examples of semiconductor substrates include semiconductor substrates using silicon or germanium as materials, or compound semiconductor substrates composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, there are semiconductor substrates containing an insulating region within the aforementioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates containing metal nitrides or substrates containing metal oxides. Additionally, there are substrates in which a conductor or semiconductor is provided on an insulating substrate, substrates in which a conductor or insulator is provided on a semiconductor substrate, and substrates in which a semiconductor or insulator is provided on a conductive substrate. Alternatively, it is also acceptable to use substrates in which a device is provided on these substrates. Components provided on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0451] [Insulator]

[0452] Insulators include oxides, nitrides, nitride oxides, nitrate oxides, metal oxides, metal nitride oxides, and metal nitrate oxides that possess insulating properties.

[0453] For example, as transistors become more miniaturized and highly integrated, problems such as leakage current may arise due to the thinning of the gate insulator. By using high-k materials for the insulator functioning as the gate insulator, the voltage during transistor operation can be reduced while maintaining the physical film thickness. Furthermore, it is possible to thin the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator. On the other hand, by using materials with a low dielectric constant for the insulator functioning as an interlayer film, the capacitance of parasitic capacitance generated between wirings can be reduced. Therefore, it is advisable to select materials based on the function of the insulator. Additionally, materials with a low dielectric constant are also materials with high dielectric strength.

[0454] Examples of high-k materials include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides containing aluminum and hafnium, nitrides containing aluminum and hafnium, oxides containing silicon and hafnium, nitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0455] Materials with low dielectric constant include, for example, inorganic insulating materials such as silicon oxide, silicon nitride, and silicon nitride, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic. In addition, other inorganic insulating materials with low dielectric constant include, for example, silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. There are also, for example, silicon oxide having vacancies. Furthermore, these silicon oxides may contain nitrogen.

[0456] In addition, the electrical characteristics of a transistor using an oxide semiconductor can be stabilized by surrounding it with an insulator that has the function of suppressing the permeation of impurities and oxygen. As an insulator that has the function of suppressing the permeation of impurities and oxygen, an insulator including, for example, boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used as a single layer or in a stack. Specifically, as an insulator that has the function of suppressing the permeation of impurities and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon nitride, and silicon nitride can be used.

[0457] In addition, it is desirable for an insulating layer in contact with a semiconductor layer, such as a gate insulating film, or an insulating layer provided near the semiconductor layer, to include a region containing excess oxygen. For example, oxygen deficiency within the semiconductor layer can be reduced by having a structure in which an insulating layer containing a region containing excess oxygen is in contact with or provided near the semiconductor layer. Examples of insulators that are easy to form a region containing excess oxygen include silicon oxide, silicon nitride, or silicon oxide having vacancies.

[0458] In addition, insulators having barrier properties against oxygen may include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, or gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide. In addition, oxides containing one or both of aluminum and hafnium may include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).

[0459] In addition, insulators that have barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, or silicon nitride oxide.

[0460] An insulator having barrier properties against oxygen and an insulator having barrier properties against hydrogen can be described as an insulator having barrier properties against one or both of oxygen and hydrogen.

[0461] In addition, oxides containing magnesium, or oxides containing one or both of aluminum and hafnium, may be used as insulators having the function of capturing or fixing hydrogen. Furthermore, it is more preferable for these oxides to have an amorphous structure. In oxides having an amorphous structure, oxygen atoms may have dangling bonds and possess the property of capturing or fixing hydrogen through said dangling bonds. Additionally, while it is preferable for these metal oxides to have an amorphous structure, it is also acceptable for crystalline regions to be formed in some parts.

[0462] Furthermore, in this specification and others, the term "barrier insulating film" refers to an insulating film having barrier properties. Additionally, barrier properties refer to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult to pass through a corresponding substance, a property with low permeability to a corresponding substance, or a function that inhibits the diffusion of a corresponding substance). Furthermore, the function of capturing or fixing a corresponding substance (also referred to as gettering) can be interchangeably called barrier properties. Additionally, when hydrogen is described as a corresponding substance, it refers, for example, to hydrogen atoms, hydrogen molecules, water molecules, and OH. -It refers to at least one of the substances combined with hydrogen, etc. Furthermore, when described as a corresponding substance, the impurity refers to an impurity in the channel-forming region or the semiconductor layer unless specifically stated otherwise, and refers to at least one of, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Additionally, when described as a corresponding substance, oxygen refers to at least one of, for example, oxygen atoms, oxygen molecules, etc. Specifically, barrier properties against oxygen refer to the property that at least one of oxygen atoms, oxygen molecules, etc. is difficult to diffuse.

[0463] [Challenge]

[0464] For the conductor, it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the aforementioned metal element as a component, or an alloy combining the aforementioned metal element. As an alloy containing the aforementioned metal element as a component, a nitride of the alloy or an oxide of the alloy may be used. For example, it is preferable to use tantalum nitride, titanium nitride, tungsten nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc. In addition, highly electrically conductive semiconductors, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0465] In addition, conductive materials containing nitrogen, such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum; conductive materials containing oxygen, such as oxides containing ruthenium oxide, strontium and ruthenium, or oxides containing lanthanum and nickel; and materials containing metallic elements such as titanium, tantalum, or ruthenium are desirable because they are conductive materials that are difficult to oxidize, conductive materials that have the function of inhibiting the diffusion of oxygen, or materials that maintain conductivity even when absorbing oxygen. In addition, examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide containing silicon, indium zinc oxide, and indium zinc oxide containing tungsten oxide. In the present specification and other sources, a conductive film formed using an oxygen-containing conductive material may be referred to as an oxide conductive film.

[0466] In addition, conductive materials containing tungsten, copper, or aluminum as main components are desirable because they have high conductivity.

[0467] In addition, multiple conductive layers formed from the above-mentioned material may be stacked and used. For example, a stacked structure may be formed by combining a material containing the metal element described above with a conductive material containing oxygen. Alternatively, a stacked structure may be formed by combining a material containing the metal element described above with a conductive material containing nitrogen. Furthermore, a stacked structure may be formed by combining a material containing the metal element described above, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0468] In addition, when an oxide semiconductor is used in the channel formation region of a transistor, it is preferable to use a stacked structure in which a material containing the aforementioned metal element and a conductive material containing oxygen are combined for the conductor functioning as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material becomes easier to supply to the channel formation region.

[0469] In particular, as a conductor functioning as a gate electrode, it is preferable to use a conductive material containing a metal element and oxygen included in the oxide semiconductor where the channel is formed. Additionally, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, a conductive material containing nitrogen, such as titanium nitride or tantalum nitride, may be used. Furthermore, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide containing silicon may be used. Additionally, indium gallium zinc oxide containing nitrogen may be used. By using such materials, hydrogen included in the oxide semiconductor where the channel is formed may be captured. Alternatively, hydrogen introduced from an external insulator may be captured.

[0470] [Other Semiconductor Materials]

[0471] The semiconductor material that can be used in the semiconductor layer is not limited to oxide semiconductors. Semiconductor materials having a band gap (semiconductor materials that are not zero-gap semiconductors) may be used in the semiconductor layer. For example, it is desirable to use semiconductors of elemental types, compound semiconductors, or layered materials (also called atomic layer materials, two-dimensional materials, etc.) as semiconductor materials.

[0472] In this specification and other contexts, the term "layered material" refers to a group of materials having a layered crystal structure. In a layered crystal structure, layers formed by covalent or ionic bonds are stacked by bonds weaker than covalent or ionic bonds, such as Van der Waals forces. Layered materials have high electrical conductivity within a monolayer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0473] Examples of elemental semiconductors that can be used in semiconductor materials include silicon and germanium. Examples of silicon that can be used in semiconductor layers include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0474] Examples of compound semiconductors that can be used as semiconductor materials include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide. It is preferable that boron nitride that can be used in the semiconductor layer has an amorphous structure. It is preferable that boron arsenide that can be used in the semiconductor layer includes crystals with a cubic structure.

[0475] Layered materials include graphene, silicene, boron carbonitride, and chalcogenides. In the case of boron carbonitride, a layered material, carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane. Chalcogenides are compounds containing chalcogens. Furthermore, chalcogen is a general term for elements belonging to Group 16, including oxygen, sulfur, selenium, tellurium, polonium, and livermorium. Additionally, examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.

[0476] For the semiconductor layer, it is preferable to use, for example, a transition metal chalcogenide that functions as a semiconductor. Specifically, examples of transition metal chalcogenides applicable to the semiconductor layer include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2). By applying the above-described transition metal chalcogenides to the semiconductor layer, a semiconductor device with a large on-current can be provided.

[0477] According to one embodiment of the present invention, a novel transistor and a novel semiconductor device may be provided. Alternatively, a semiconductor device capable of miniaturization or high integration may be provided. Alternatively, a semiconductor device with good frequency characteristics may be provided. Alternatively, a semiconductor device with a fast operating speed may be provided. Alternatively, a semiconductor device with good reliability may be provided. Alternatively, a semiconductor device with low power consumption may be provided. Alternatively, a semiconductor device including a transistor with a large on-current may be provided. Alternatively, a semiconductor device with low variation in transistor characteristics may be provided. Alternatively, a semiconductor device with good electrical characteristics may be provided.

[0478] The configurations, structures, methods, etc. described in this embodiment may be used in appropriate combination with the configurations, structures, methods, etc. described in other embodiments, etc.

[0479] (Embodiment 4)

[0480] In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor is described.

[0481] [Oxide semiconductor layer]

[0482] In one embodiment of the present invention, the oxide semiconductor layer preferably comprises a crystalline metal oxide. Examples of structures of the crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide in the oxide semiconductor layer, the defect level density within the oxide semiconductor layer can be reduced. Accordingly, the reliability of a transistor using the oxide semiconductor layer of one embodiment of the present invention can be increased, and the reliability of a semiconductor device equipped with the transistor can be increased.

[0483] In one embodiment of the present invention, the oxide semiconductor layer preferably comprises a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically microcrystals having a plurality of hexagonal crystal structures) have a c-axis orientation, and in the ab plane, the plurality of microcrystals are connected without orientation. Furthermore, when observing a cross-section of the oxide semiconductor layer having a CAAC structure using high-resolution transmission electron microscope (TEM) images, it can be confirmed that metal atoms are arranged in a layered manner in the crystal region. Therefore, the oxide semiconductor layer having a CAAC structure can also be described as a structure comprising a layered crystal region.

[0484] The crystallinity of the oxide semiconductor layer can be analyzed using, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, analysis may be performed by combining multiple of these methods.

[0485] Furthermore, the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), and a semiconductor having crystallinity other than a single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor containing a crystalline region in part). In some cases, the degradation of transistor characteristics can be suppressed by the oxide semiconductor layer having crystallinity.

[0486] Examples of metal oxides included in the oxide semiconductor layer of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide. The metal oxide according to one embodiment of the present invention preferably comprises at least indium (In) or zinc (Zn). In addition, the metal oxide preferably comprises two or three elements selected from indium, element M, and zinc. In addition, element M is a metal element or metalloid element with a high binding energy with oxygen, for example, a metal element or metalloid element with a binding energy with oxygen higher than that of indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M included in the metal oxide is preferably one or more of the above elements, more preferably one or more of selected from aluminum, gallium, tin, and yttrium, and more preferably gallium. When the element M included in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention is preferably one or more of selected from indium, gallium, and zinc. In addition, in this specification and other documents, metal elements and metalloid elements are collectively referred to as "metal elements," and metalloid elements may be included in the "metal elements" described in this specification and other documents.

[0487] According to one embodiment of the present invention, metal oxides include, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also denoted as IGTO), gallium zinc oxide (Ga-Zn oxide, also denoted as GZO), aluminum zinc oxide (Al-Zn oxide, also denoted as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also denoted as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also denoted as ITO), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also denoted as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also denoted as IGZTO), and indium gallium aluminum zinc. Oxides (also denoted as In-Ga-Al-Zn oxide, IGAZO, or IAGZO) can be used. Alternatively, examples include silicon-containing indium tin oxide (also known as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0488] By increasing the ratio of the number of indium atoms to the sum of the number of atoms of all metal elements included in the metal oxide, the transistor can obtain large on-current and high frequency characteristics.

[0489] In addition, the metal oxide may contain one or more types of metal elements with large period numbers in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more types of metal elements with large period numbers in the periodic table in addition to indium. The carrier conductivity in the metal oxide tends to increase as the overlap of the orbitals of the metal elements increases. Therefore, by including metal elements with large period numbers in the periodic table, the field-effect mobility of the transistor can be increased. Examples of metal elements with large period numbers in the periodic table include metal elements belonging to the 5th period and metal elements belonging to the 6th period. Specifically, examples of the above metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Also, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0490] In addition, the metal oxide may contain one or more types of non-metal elements. In some cases, the field-effect mobility of the transistor can be increased by the metal oxide containing non-metal elements. Examples of non-metal elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0491] In addition, by increasing the ratio of the number of zinc atoms to the sum of the number of atoms of all metal elements contained in the metal oxide, the crystallinity of the metal oxide is increased, which can suppress the diffusion of impurities in the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby increasing reliability.

[0492] In addition, by increasing the ratio of the number of atoms of element M to the sum of the number of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation caused by oxygen vacancies is suppressed, allowing for a transistor with a small off-current. Furthermore, fluctuations in the electrical characteristics of the transistor are suppressed, thereby increasing reliability.

[0493] In this embodiment, In-Ga-Zn oxide may be used as an example to describe the metal oxide.

[0494] An oxide semiconductor layer of one embodiment of the present invention has crystallinity. Additionally, an oxide semiconductor layer of one embodiment of the present invention preferably has a CAAC structure.

[0495] An oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide using at least two types of film deposition methods. For example, an oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide using a first film deposition method and a second film deposition method. Additionally, an oxide semiconductor layer formed using at least two types of film deposition methods may be referred to as a Hybrid OS.

[0496] An oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer using a first film deposition method, and then forming a metal oxide as a second layer on the first layer using a second film deposition method. At this time, it is preferable to use a film deposition method as the first film deposition method that causes less damage to the surface to be formed compared to the second film deposition method. By using a film deposition method as the first film deposition method that causes less damage to the surface to be formed, the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer that is the surface to be formed of the oxide semiconductor layer can be suppressed. In addition, since the incorporation of impurities such as silicon into the second layer can be suppressed, the crystallinity of the oxide semiconductor layer can be increased.

[0497] Examples of the first film deposition methods include Atomic Layer Deposition (ALD), Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE), and wet methods. Examples of CVD methods include Plasma Enhanced CVD (PECVD), Thermal CVD, Photo-CVD, and Metal Organic CVD (MOCVD). Examples of wet methods include spray coating. Since the ALD and CVD methods can suppress damage to the surface to be formed compared to the sputtering method described later, they are suitable as the first film deposition methods.

[0498] Examples of ALD methods include the Thermal ALD method, which induces the reaction between a precursor and a reactant using only thermal energy, and the Plasma Enhanced ALD (PEALD) method, which uses a plasma-excited reactant.

[0499] Since the ALD method allows for the deposition of atoms layer by layer, it offers several advantages, such as the ability to form very thin films, deposit films on structures with high aspect ratios or surfaces with large step heights, produce films with fewer defects like pinholes, achieve excellent coverage, and deposit at low temperatures. Additionally, the PEALD method utilizes plasma, which enables film deposition at even lower temperatures, making it a desirable option in some cases. Furthermore, the precursors used in the ALD method may contain elements such as carbon or chlorine. Consequently, films produced by the ALD method may contain higher levels of these elements than films produced by other deposition methods. Additionally, the quantification of these elements can be performed using X-ray Photoelectron Spectroscopy (XPS) or Secondary Ion Mass Spectrometry (SIMS). In addition, as a method for depositing a metal oxide film in one embodiment of the present invention, the ALD method is used. However, since one or both of high substrate temperature and impurity removal treatment are applied as conditions during film deposition, the amount of carbon and chlorine contained in the film may be lower than when the ALD method is used without applying these conditions.

[0500] Unlike film deposition methods where particles emitted from a target are deposited, the ALD method forms a film through a reaction on the surface of the workpiece. Therefore, it is a film deposition method that is less affected by the shape of the workpiece and offers excellent step coverage. In particular, because the ALD method provides excellent step coverage and thickness uniformity, it is suitable for applications such as covering the surfaces of openings with high aspect ratios.

[0501] Using the plasma CVD method, high-quality films can be obtained at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is a film deposition method that can reduce plasma damage to the workpiece. Additionally, because plasma damage does not occur during film deposition in the thermal CVD method, films with fewer defects can be obtained.

[0502] Examples of the second film deposition method include sputtering and pulsed laser deposition (PLD). Metal oxides formed using the second film deposition method tend to have a CAAC structure.

[0503] In addition, as the first layer, a metal oxide having a microcrystalline or amorphous structure with lower crystallinity than the CAAC structure may be formed. By forming a second layer with high crystallinity on the first layer with low crystallinity, or by performing heat treatment after forming it, the crystallinity of the first layer may be increased using the second layer as a nucleus. This allows for increased crystallinity throughout the entire oxide semiconductor layer, including the area near the interface with the surface to be formed.

[0504] In addition, a third layer may be formed on top of the second layer. Since the second layer has high crystallinity, crystal growth of the third layer is possible using the crystals of the second layer as nuclei or seeds. Therefore, the third layer can be crystallized even if a film deposition method that is prone to crystallinity is not used as the film deposition method for the third layer. Here, for example, by forming the third layer using a film deposition method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0505] For example, an oxide semiconductor layer of one embodiment of the present invention can be fabricated by forming a metal oxide as a first layer using a first film deposition method, forming a metal oxide as a second layer using a second film deposition method, and forming a metal oxide as a third layer using the first film deposition method. Specifically, an ALD method can be used as the first film deposition method, and a sputtering method can be used as the second film deposition method. The ALD method is a film deposition method with superior coverage properties compared to the sputtering method, and by using the ALD method as the film deposition method for the first and third layers, the coverage properties of the oxide semiconductor layer can be improved. Therefore, the oxide semiconductor layer can be well coated on steps, openings, etc., with a high aspect ratio.

[0506] [Method for fabricating oxide semiconductor layers]

[0507] The oxide semiconductor layer (230) can be manufactured, for example, by forming an oxide semiconductor (230a) on a layer (229) that is a surface to be formed using an ALD method, forming an oxide semiconductor (230b) on the oxide semiconductor (230a) using a sputtering method, and forming an oxide semiconductor (230c) on the oxide semiconductor (230b) using an ALD method. Additionally, it is preferable to perform heat treatment after forming the oxide semiconductor (230). By performing heat treatment, the crystallinity of the oxide semiconductor (230) can be increased. Here, the heat treatment is not limited to heating treatment. For example, it may be heat applied during the manufacturing process.

[0508] The oxide semiconductor (230) can be used in the semiconductor layer (530) and semiconductor layer (270), etc., described in the previous embodiment. Additionally, the layer (229) corresponds to the insulating layer (524), insulating layer (280), insulating layer (225), or conductive layer (220), etc., described in the previous embodiment.

[0509] The layer (229) does not have to be crystalline. Also, if the layer (229) is crystalline, it may have a crystal structure with low lattice compatibility with the metal oxide included in the oxide semiconductor (230).

[0510] An example of a method for fabricating an oxide semiconductor (230) using FIG. 27 (A) to FIG. 28 (D) will be described.

[0511] First, an oxide semiconductor (230a) is formed on the layer (229) using the ALD method (Fig. 27 (A)). Then, an oxide semiconductor (230b) is formed on the oxide semiconductor (230a) using the sputtering method (Fig. 27 (B)).

[0512] When a metal oxide film is formed by sputtering, damage to the surface to be formed may cause alloying between the components contained in the metal oxide film and the components contained in the layer that is the surface to be formed. Once alloying occurs, it is difficult to increase the crystallinity of the alloyed region even if the heat treatment described later is performed. Furthermore, using an oxide semiconductor layer containing alloyed regions in a transistor may adversely affect the initial characteristics or reliability of the transistor. Therefore, it is desirable to suppress alloying between the components contained in the metal oxide film and the components contained in the layer that is the surface to be formed.

[0513] In a method for fabricating an oxide semiconductor layer of one embodiment of the present invention, an oxide semiconductor (230a) is formed between the oxide semiconductor (230b) and the layer (229) using a film formation method that causes less damage to the surface to be formed. This suppresses the alloying of the components included in the oxide semiconductor (230) and the components included in the layer (229), thereby increasing the crystallinity of the oxide semiconductor (230).

[0514] By the above configuration, the thickness of the alloyed region can be made thin, or thin enough so that the alloyed region cannot be observed. For example, the thickness of the alloyed region can be made to be 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and more preferably 0 nm or more and less than 0.3 nm. In addition, FIG. 27 (A) and (B) show an example in which no alloyed region is formed between the layer (229) and the oxide semiconductor (230a).

[0515] In addition, the thickness of the alloyed region can sometimes be calculated by performing a line analysis of the composition using SIMS or Energy Dispersive X-ray Spectroscopy (EDX) on the said region and its surroundings.

[0516] For example, the direction perpendicular to the surface to be formed of the oxide semiconductor (230a) is defined as the depth direction, and line analysis of EDX is performed on the said region and its periphery. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained from the said analysis, the depth at which the quantitative value of the metal (in the case where the oxide semiconductor (230a) contains In) that is the main component of the oxide semiconductor (230a) and not the main component of the layer to be formed (here, layer (229)) is halved is defined as the depth (location) of the interface between the said region and the oxide semiconductor (230a). In addition, the depth at which the quantitative value of the element (e.g., Si) that is the main component of the layer to be formed and not the main component of the oxide semiconductor (230a) is halved is defined as the depth (location) of the interface between the said region and the layer to be formed. Thus, the thickness of the alloyed region can be calculated.

[0517] When observing the thickness of the alloyed region in an oxide semiconductor layer of one embodiment of the present invention by EDX analysis, for example, the thickness is preferably 0 nm or more and 3 nm or less, more preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and more preferably 0 nm or more and less than 0.3 nm.

[0518] Also, for example, when using a silicon oxide layer as the layer (229) and performing SIMS analysis of an oxide semiconductor (230) formed on the layer (229), the depth at which the silicon concentration becomes 50% of the maximum concentration of the layer (229) is set as the interface, and the silicon concentration is 1.0×10 21 atoms / cm 3 , preferably 5.0×10 20 atoms / cm 3 , more preferably 1.0×10 20 atoms / cm 3 The distance between the depth at which it decreases and the interface is defined as the thickness t_s2. The thickness t_s2 is preferably 3 nm or less, and more preferably 2 nm or less.

[0519] By making the thickness of the alloyed region thin, the thickness t_s2 can be made within the above range.

[0520] In addition, by reducing the alloyed region, a CAAC structure can be formed near the surface to be formed. Here, the area near the surface to be formed refers to, for example, a region of 0 nm greater than 3 nm less than or equal to, preferably 0 nm greater than 2 nm less than or equal to, and more preferably 1 nm greater than or equal to 2 nm less than or equal to, substantially perpendicular from the surface to be formed of the oxide semiconductor (230).

[0521] In addition, the CAAC structure near the surface to be formed can sometimes be confirmed through observation using TEM. For example, in cross-sectional observation of an oxide semiconductor (230) using high-resolution TEM, bright spots arranged in layers parallel to the surface to be formed are confirmed near the surface to be formed.

[0522] In addition, when forming an oxide semiconductor (230a) using the ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure with lower crystallinity than the CAAC structure may be formed. That is, in the fabrication step shown in (A) of FIG. 27, the oxide semiconductor (230a) may include a region with lower crystallinity than the oxide semiconductor (230b).

[0523] It is preferable that the oxide semiconductor (230b) be of a composition suitable for forming a CAAC structure.

[0524] When forming an oxide semiconductor (230b) using a sputtering method, a mixed layer (231) is formed on or near the surface of the oxide semiconductor (230a). Additionally, when forming the oxide semiconductor (230b), a fine crystalline region may be formed in the mixed layer (231) by energy supplied to the substrate side from the sputtering particles or the like. In a subsequent heat treatment process, the fine crystalline region formed in the mixed layer (231) or the mixed layer (231) may act as a nucleus, causing at least a portion of the oxide semiconductor (230a) to crystallize.

[0525] In the deposition of an oxide semiconductor (230b) using the sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, by increasing the substrate temperature (stage temperature) during the formation of the metal oxide, it is possible to form a metal oxide with high crystallinity.

[0526] Next, an oxide semiconductor (230c) is formed on the oxide semiconductor (230b) using the ALD method ((C) of FIG. 27). For the formation of the oxide semiconductor (230c) using the ALD method, the method for forming the oxide semiconductor (230a) can be referenced.

[0527] When an oxide semiconductor (230c) is formed on an oxide semiconductor (230b) having a CAAC structure using an ALD method, the oxide semiconductor (230c) may grow epitaxially with the oxide semiconductor (230b) as a nucleus. Therefore, when forming the oxide semiconductor (230c), the oxide semiconductor (230c) may include a region having a CAAC structure. Furthermore, it is preferable that the region having a CAAC structure be formed over the entire oxide semiconductor (230c).

[0528] Next, a heat treatment process may be performed. Through the heat treatment process, the crystallinity of the region having a CAAC structure in the oxide semiconductor (230c) may be increased. In addition, if the region is formed only on the lower side of the oxide semiconductor (230c) after film formation by the ALD method, the region may be expanded upward through the heat treatment process ((D) of FIG. 27). That is, by performing the heat treatment, the region having a CAAC structure in the oxide semiconductor (230c) may be formed over the entire layer.

[0529] In addition, it is desirable that at least a portion of the oxide semiconductor (230a) be CAACed by the above heat treatment process (Fig. 27 (D)). Since the mixed layer (231) formed within the oxide semiconductor (230a) in the deposition of the oxide semiconductor (230b) acts as a nucleus or seed, it is expected that CAACing will occur more easily. It is desirable that the region of the oxide semiconductor (230a) that is CAACed be wide, and it is desirable that the CAACing extends to the vicinity of the layer (229).

[0530] In addition, since CAAC is performed from the top to the bottom of the oxide semiconductor (230a), CAAC can be performed up to the vicinity of the layer (229) without limitation on the material or crystallinity of the layer (229). For example, even if the layer (229) has an amorphous structure, a highly crystallin oxide semiconductor (230a) can be formed. Therefore, a method for fabricating an oxide semiconductor layer of one embodiment of the present invention is particularly suitable when the layer to be formed has an amorphous structure.

[0531] Additionally, FIGS. 27 (A) to (D) are cross-sectional views illustrating a method for forming a metal oxide film according to one embodiment of the present invention. FIGS. 27 (A) to (D) may also be considered as conceptual diagrams representing a model of forming a metal oxide film according to one embodiment of the present invention. As shown in FIGS. 27 (A) to (D), the oxide semiconductor (230a) and the oxide semiconductor (230c) each have increased crystallinity by using a highly crystalline oxide semiconductor (230b) as a nucleus or seed. Specifically, the crystallinity of the oxide semiconductor (230a) may be increased by heat treatment during the formation of the oxide semiconductor (230b) or after the formation of the oxide semiconductor (230c). Additionally, the crystallinity of the oxide semiconductor (230c) may be increased by heat treatment during the formation of the oxide semiconductor (230c) or after the formation of the oxide semiconductor (230c). Furthermore, the above heat treatment has an auxiliary function to increase crystallinity.

[0532] In this way, in a method for forming a metal oxide film of one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (here, oxide semiconductor (230a) and oxide semiconductor (230c)) can be increased by using a highly crystalline oxide semiconductor (230b) (i.e., CAAC) as a nucleus or seed. This can increase the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be solid-state grown using the oxide semiconductor (230b) as a nucleus or seed to form a highly crystalline oxide semiconductor. The oxide semiconductor formed using this film formation method, here, the CAAC film, can be called an Axial Growth CAAC (AG CAAC).

[0533] It is desirable that the region having a CAAC structure in the oxide semiconductor (230) exists widely throughout the entire layer. FIG. 28 (A) shows the state in which the oxide semiconductor (230a), oxide semiconductor (230b), and oxide semiconductor (230c) are each crystallized. In this case, the boundary between the oxide semiconductor (230a) and the oxide semiconductor (230b) may not be observed. Also, the boundary between the oxide semiconductor (230b) and the oxide semiconductor (230c) may not be observed. The oxide semiconductor (230) may be described as a single layer where the interface is not clearly observed. The oxide semiconductor (230) may be described as a single layer. Additionally, FIG. 27 (D) illustrates the oxide semiconductor (230) as a stacked structure of three layers consisting of the oxide semiconductor (230a), the oxide semiconductor (230b), and the oxide semiconductor (230c), but it is not limited thereto. For example, the oxide semiconductor (230) may be made into a two-layer stacked structure of oxide semiconductor (230b) and oxide semiconductor (230c).

[0534] Additionally, there are cases where a portion of the oxide semiconductor (230a) or oxide semiconductor (230c) does not crystallize. Fig. 28 (B) shows an example of a state in which the area near the interface with the layer (229) in the oxide semiconductor (230a) is not crystallized. Fig. 28 (C) shows a state in which the area near the surface of the oxide semiconductor (230c) is not crystallized. Fig. 28 (D) shows a state in which the area near the interface with the layer (229) in the oxide semiconductor (230a) and the area near the surface of the oxide semiconductor (230c) are not crystallized, respectively.

[0535] By increasing the crystallinity of the oxide semiconductor layer, the increase in electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer is suppressed, and the initial characteristics of the transistor (especially the on-current) are improved; therefore, it is expected to become a transistor suitable for high-speed operation. In addition, the reliability of the transistor can be increased, allowing for a larger on-current.

[0536] In one embodiment of the present invention, the oxide semiconductor layer has high crystallinity throughout the layer. Therefore, in the oxide semiconductor (230), the boundaries of the stacked films of oxide semiconductor (230a), oxide semiconductor (230b), and oxide semiconductor (230c) may not be visible. In particular, after heat treatment, it may be difficult to see the boundaries of the stacked films. The presence or absence of boundaries of the stacked films can be confirmed, for example, using cross-sectional TEM, cross-sectional STEM, etc.

[0537] As described above, by using a metal oxide with a high In content in a transistor, the field-effect mobility of the transistor can be increased. Meanwhile, oxide semiconductors with a high In content tend to become polycrystalline. If a metal oxide having a polycrystalline structure is used in a transistor, the initial characteristics or reliability of the transistor are adversely affected. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductor (230a) and the oxide semiconductor (230c), a crystal is formed that reflects the orientation of the crystal included in the oxide semiconductor (230b), thereby suppressing polycrystalline formation.

[0538] In addition, it is desirable that the degree of lattice mismatch between the crystal included in the oxide semiconductor (230b) and the crystal included in the oxide semiconductor (230a) or oxide semiconductor (230c) is small. In this case, the oxide semiconductor (230a) or oxide semiconductor (230c) can form a crystal that reflects the orientation of the crystal included in the oxide semiconductor (230b). At this time, for example, when observing the cross-section of the oxide semiconductor (230) using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the surface to be formed are confirmed in the oxide semiconductor (230a) or oxide semiconductor (230c).

[0539] If the degree of lattice mismatch between the crystal included in the oxide semiconductor (230b) and the crystal included in the oxide semiconductor (230a) or oxide semiconductor (230c) is small, the crystal structure of the oxide semiconductor (230a) or oxide semiconductor (230c) is not particularly limited. The crystal structure of the oxide semiconductor (230a) or oxide semiconductor (230c) may be any of the cubic, tetragonal, or hexagonal, monoclinic, and trigonal systems.

[0540] [Composition of Oxide Semiconductor Layer]

[0541] As described above, it is preferable that the oxide semiconductor (230b) have a composition suitable for forming a CAAC structure. For example, a sputtering method may be used to form the oxide semiconductor (230b). It is preferable that the oxide semiconductor (230b) contains, for example, zinc. By including zinc, it becomes a metal oxide with high crystallinity. In addition, it is preferable that the oxide semiconductor (230b) contains element M in addition to zinc. By including element M in the oxide semiconductor (230b), the formation of oxygen vacancies in, for example, the metal oxide can be suppressed. Thus, the reliability of the transistor to which the oxide semiconductor layer is applied can be increased. Specifically, as the oxide semiconductor (230b), it is preferable to use a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a nearby composition, In:M:Zn=1:1:1.2 [atomic ratio] or a nearby composition, In:M:Zn=1:1:0.5 [atomic ratio] or a nearby composition, In:M:Zn=1:1:2 [atomic ratio] or a nearby composition, In:M:Zn=4:2:3 [atomic ratio] or a nearby composition, In:M:Zn=1:3:2 [atomic ratio] or a nearby composition, or In:M:Zn=1:3:4 [atomic ratio] or a nearby composition. Additionally, a nearby composition is one that includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as element M.

[0542] The oxide semiconductor (230b) does not need to contain element M. For example, it may be an In-Zn oxide. Specifically, it may be an In:Zn=1:1 [atomic ratio] or a composition near that, an In:Zn=2:1 [atomic ratio] or a composition near that, or an In:Zn=4:1 [atomic ratio] or a composition near that. Alternatively, indium oxide may be used. It may also be composed of a trace amount of element M. For example, it may be an In:Ga:Zn=4:0.1:1 [atomic ratio] or a composition near that, or an In:Ga:Zn=2:0.1:1 [atomic ratio] or a composition near that. Also, for example, it may be an In:Sn:Zn=4:0.1:1 [atomic ratio] or a composition near that, or an In:Sn:Zn=2:0.1:1 [atomic ratio] or a composition near that.

[0543] The oxide semiconductor (230a) and oxide semiconductor (230c) can be metal oxides with a high proportion of In. For example, the ALD method can be used to form the oxide semiconductor (230a) and oxide semiconductor (230c). In addition, it is particularly desirable to use a metal oxide with a higher proportion of In than of element M. By using a metal oxide with a high proportion of In, the on-current can be increased and frequency characteristics can be improved when the oxide semiconductor layer is applied to a transistor.

[0544] Alternatively, the oxide semiconductor (230a) and the oxide semiconductor (230c) do not need to contain element M. For example, they may be In-Zn oxide. Specifically, they may have a composition of In:Zn=1:1 [atomic ratio] or a nearby composition, In:Zn=2:1 [atomic ratio] or a nearby composition, or In:Zn=4:1 [atomic ratio] or a nearby composition. Alternatively, indium oxide may be used. Furthermore, the oxide semiconductor (230a) and the oxide semiconductor (230c) may be configured to contain a trace amount of element M. Specifically, it can be In:Ga:Zn=4:0.1:1 [atomic ratio] or a nearby composition, In:Ga:Zn=2:0.1:1 [atomic ratio] or a nearby composition, In:Sn:Zn=4:0.1:1 [atomic ratio] or a nearby composition, or In:Sn:Zn=2:0.1:1 [atomic ratio] or a nearby composition.

[0545] In addition, oxide semiconductors (230a) and (230c) can be metal oxides with a higher proportion of In than oxide semiconductor (230b).

[0546] In addition, for example, metal oxides with a higher proportion of Ga than oxide semiconductor (230b) may be used as oxide semiconductors (230a) and (230c). For example, it is preferable to use metal oxides with a composition of In:Ga:Zn=1:1:1 [atomic ratio] or a similar composition, In:Ga:Zn=1:3:2 [atomic ratio] or a similar composition, or In:Ga:Zn=1:3:4 [atomic ratio] or a similar composition, respectively, as oxide semiconductors (230a) and (230c). By increasing the proportion of Ga, for example, the band gaps of oxide semiconductors (230a) and (230c) may be made larger than those of oxide semiconductors (230b). As a result, oxide semiconductors (230b) are sandwiched between oxide semiconductors (230a) and (230c) with large band gaps, and primarily function as current paths (channels). By sandwiching the oxide semiconductor (230b) between the oxide semiconductor (230a) and the oxide semiconductor (230c), the trap level at the interface of the oxide semiconductor (230b) and its vicinity can be reduced. This enables the realization of a buried channel type transistor in which the channel is located far from the interface of the insulating layer, thereby increasing the field-effect mobility.

[0547] In addition, in one embodiment of the present invention, even if oxide semiconductors (230a) and (230c) of a composition that makes it difficult to form a CAAC structure when formed as a single layer are used, crystal growth occurs with the oxide semiconductor (230b) as a nucleus, so the entire oxide semiconductor layer including the oxide semiconductor (230a) and the oxide semiconductor (230c) can have a CAAC structure. Alternatively, the structure can be configured to have a CAAC structure in a region that includes at least a portion of each of the oxide semiconductor (230a) and the oxide semiconductor (230c) and a region extending to the oxide semiconductor (230b).

[0548] In particular, even in compositions with a high proportion of In in oxide semiconductors (230a) and oxide semiconductors (230c), it can have crystallinity suitable for use as a semiconductor layer of a transistor. In one embodiment of the present invention, an oxide semiconductor layer can achieve both improved on-characteristics of a transistor by increasing the proportion of In and improved reliability by having a CAAC structure with high crystallinity.

[0549] In addition, the composition of the oxide semiconductor (230a) and the oxide semiconductor (230c) may be different.

[0550] In addition, as oxide semiconductors (230a) and (230c), metal oxides having the same composition as oxide semiconductor (230b) may be used.

[0551] By using an oxide semiconductor layer having a CAAC structure formed using the two types of film deposition methods described above in the channel formation region of a transistor, it is possible to realize a transistor with excellent characteristics (e.g., a transistor with a large on-current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also called f characteristics), a transistor with high reliability, etc.).

[0552] For the analysis of the composition of the metal oxide used in the oxide semiconductor (230), for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES) may be used. Alternatively, analysis may be performed by combining multiple of these methods. In addition, for elements with low content, the content obtained by analysis may differ from the actual content due to the influence of analysis precision. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0553] [c-axis orientation rate]

[0554] An oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The degree of crystallinity of an oxide semiconductor layer of one embodiment of the present invention can be evaluated, for example, using crystal orientation.

[0555] Crystal orientation can be obtained from the FFT pattern obtained by performing a Fast Fourier Transform (FFT) on a TEM image. Specifically, the direction of the crystal axes can be obtained using the FFT pattern. The FFT pattern obtained by the FFT processing reflects reciprocal lattice space information, such as electron diffraction patterns.

[0556] By performing FFT processing on each region within a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area range, a map representing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region containing a layered crystal portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0557] In a map representing crystal orientation, the c-axis orientation rate can be calculated by calculating the ratio of the c-axis oriented region. In addition, the c-axis oriented region here is defined as a region where the orientation coincides with the c-axis and a region where the difference from the c-axis is within 20°.

[0558] In an oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate can be calculated, for example, by performing TEM observation of a cross-section or planar surface of the oxide semiconductor layer. In addition, the area for performing FFT (also called the FFT window) can be, for example, circular with a diameter of 1.0 nm. In addition, the area for performing FFT is not limited to a circular shape.

[0559] In an oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and more preferably 95% or more.

[0560] In addition, the c-axis orientation rates of the region formed as an oxide semiconductor (230a), the region formed as an oxide semiconductor (230b), and the region formed as an oxide semiconductor (230c) are respectively set to Rc1, Rc2, and Rc3. Rc2 and Rc3 are each 60% or more, preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and more preferably 95% or more. It is preferable that Rc3 / Rc1 be greater than 1. In addition, it is preferable that Rc2 / Rc1 be greater than 1.

[0561] In addition, there are cases where the boundaries of the oxide semiconductors (230a, 230b, and 230c) are not clearly observed after fabrication in the oxide semiconductor (230).

[0562] An oxide semiconductor (230) of one form of the present invention can be divided into three regions sequentially from the layer (229): a first region, a second region, and a third region. Each region is a layered region.

[0563] The first region, the second region, and the third region each have a CAAC structure. Additionally, it is preferable that the c-axis orientation rate of the third region is higher than the c-axis orientation rate of the first region. Additionally, it is preferable that the c-axis orientation rate of the second region is higher than the c-axis orientation rate of the first region. Furthermore, the c-axis orientation rates of the second region and the third region are each 80% or more, more preferably 90% or more, and even more preferably 95% or more.

[0564] The first region is located at 0 nm or more and 3 nm or less from the upper surface of the layer (229), and the third region is located at 0 nm or more and 3 nm or less from the upper surface of the oxide semiconductor (230).

[0565] Or the layer thickness of each region is substantially the same, for example.

[0566] The present embodiment may be appropriately combined with other embodiments. In addition, where multiple configuration examples are presented in one embodiment in this specification, the configuration examples may be appropriately combined.

[0567] (Embodiment 5)

[0568] In this embodiment, electronic components, electronic devices, and large computers capable of using the semiconductor device described in the previous embodiment are described. Electronic components, electronic devices, and large computers using a semiconductor device of one form of the present invention are effective for achieving high performance, such as low power consumption.

[0569] [Electronic Components]

[0570] FIG. 29 (A) is a perspective view of a substrate (mounting substrate (704)) on which an electronic component (709) is mounted. The electronic component (709) shown in FIG. 29 (A) includes a semiconductor device (710) within a mold (711). In FIG. 29 (A), some parts of the illustration are omitted to show the interior of the electronic component (709). The electronic component (709) includes a land (712) on the outside of the mold (711). The land (712) is connected to an electrode pad (713), and the electrode pad (713) is connected to the semiconductor device (710) through a wire (714). The electronic component (709) is mounted, for example, on a printed circuit board (702). A plurality of such electronic components are combined and each is connected on the printed circuit board (702) to complete the mounting substrate (704).

[0571] Additionally, the semiconductor device (710) includes a layer (715) containing an arithmetic core and a layer (716) containing memory. Additionally, the layer (716) containing memory has a configuration in which a plurality of memory cell arrays are stacked. The stacked configuration of the layer (715) containing the arithmetic core and the layer (716) containing memory can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as TSV (Through Silicon Via) or bonding technology such as Cu-Cu direct bonding. By configuring the layer (715) containing the arithmetic core and the layer (716) containing memory as a monolithic stacked configuration, it can be configured as a so-called on-chip memory, for example, in which memory is formed directly on a processor. By configuring as an on-chip memory, the operation of the interface portion between the processor and the memory can be performed at high speed.

[0572] In addition, by configuring it as an on-chip memory, the size of the connection wiring can be reduced compared to technologies using through-electrodes such as TSVs, and thus the number of connection pins can be increased. Since parallel operation becomes possible by increasing the number of connection pins, the memory bandwidth (also called memory bandwidth) can be improved.

[0573] In addition, it is preferable to form a plurality of memory cell arrays included in the layer (716) containing memory using OS transistors and stack them monolithically. By configuring the plurality of memory cell arrays in a monolithic stack, either or both of the memory bandwidth and memory access latency can be improved. In addition, bandwidth refers to the amount of data transferred per unit time, and access latency refers to the time from access until the transmission and reception of data begins. Furthermore, when using Si transistors in the layer (716) containing memory, it is difficult to form a monolithic stack configuration compared to OS transistors. Therefore, in a monolithic stack configuration, OS transistors can be said to have a superior structure compared to Si transistors.

[0574] In addition, the semiconductor device (710) may also be referred to as a die. Furthermore, in the present specification and other documents, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disc-shaped substrate (also called a wafer) in the semiconductor chip manufacturing process and cutting it into a die shape. In addition, semiconductor materials that can be used for a die include, for example, silicon (Si), silicon carbide (SiC), or gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be referred to as a silicon die.

[0575] Figure 29 (B) is a perspective view of an electronic component (730). The electronic component (730) is an example of a System in Package (SiP) or Multi Chip Module (MCM). In the electronic component (730), an interposer (731) is provided on a package substrate (732) (printed substrate), and a semiconductor device (735) and a plurality of semiconductor devices (710) are provided on the interposer (731).

[0576] As the package substrate (732), for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate may be used. As the interposer (731), for example, a silicon interposer or a resin interposer may be used.

[0577] The interposer (731) includes multiple wires and has the function of connecting multiple integrated circuits with different terminal pitches. The multiple wires are provided in a single layer or in multiple layers. Additionally, the interposer (731) has the function of connecting an integrated circuit provided on the interposer (731) to an electrode provided on a package substrate (732). Therefore, the interposer is sometimes referred to as a 're-wiring substrate' or 'intermediate substrate'. Additionally, a through-electrode is provided on the interposer (731), and the integrated circuit and the package substrate (732) are connected using the through-electrode. Furthermore, in a silicon interposer, a TSV may be used as the through-electrode.

[0578] In HBM, it is necessary to connect a large number of wires to realize a wide memory bandwidth. Therefore, the interposer mounting HBM requires the formation of fine and high-density wiring. Accordingly, it is desirable to use a silicon interposer for mounting HBM.

[0579] In addition, in SiPs and MCMs using silicon interposers, it is difficult for reliability degradation to occur due to the difference in expansion coefficients between the integrated circuit and the interposer. Furthermore, since silicon interposers have high surface flatness, it is difficult for connection failures to occur between the integrated circuit provided on the silicon interposer and the silicon interposer. In particular, it is desirable to use silicon interposers in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are placed side by side on an interposer.

[0580] Meanwhile, when connecting multiple integrated circuits with different terminal pitches using silicon interposers and TSVs, space such as the width of the terminal pitch is required. Therefore, when attempting to reduce the size of the electronic component (730), the width of the terminal pitch becomes a problem, and it may be difficult to provide many wires required to realize a wide memory bandwidth. Therefore, as described above, a monolithic stacking configuration using OS transistors is suitable. It may also be a composite structure combining a memory cell array stacked using TSVs and a monolithic stacked memory cell array.

[0581] Additionally, a heat sink may be provided by overlapping with the electronic component (730). When providing a heat sink, it is desirable to match the height of the integrated circuit provided on the interposer (731). For example, in the electronic component (730) described in this embodiment, it is desirable to match the height of the semiconductor device (710) and the semiconductor device (735).

[0582] In order to mount an electronic component (730) on another substrate, an electrode (733) may be provided on the bottom portion of the package substrate (732). An example in FIG. 29 (B) shows the electrode (733) being formed as a solder ball. By providing the solder ball as a matrix on the bottom portion of the package substrate (732), a Ball Grid Array (BGA) mounting can be realized. Additionally, the electrode (733) may be formed as a conductive pin. By providing the conductive pin as a matrix on the bottom portion of the package substrate (732), a Pin Grid Array (PGA) mounting can be realized.

[0583] The electronic component (730) is not limited to BGA and PGA and can be mounted on other substrates using various mounting methods. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0584] FIGS. 30 (A) to (D) is a drawing illustrating a configuration example different from the electronic component (709, 730) described using FIGS. 29 (A) and (B) above. The electronic component (730A to 730D) shown in FIGS. 30 (A) to (D) has a configuration in which a layer (715) including a computational core and a layer (716) including a memory are provided within a mold (711) on an interposer (731) provided with the electrode (733) described above.

[0585] In the configuration of the electronic component (730A) shown in (A) of FIG. 30, the layer (715) containing the computational core is provided on the interposer (731) and connected to an electrode pad (not shown) via a wire (714). The layer (716) containing the memory formed on the layer (715) containing the computational core has the configuration of the monolithic stacking described above. In the monolithic stacking configuration, the layer (716) containing the memory and the layer (715) containing the computational core are connected. Therefore, since the wire (714) connecting the interposer (731) and the layer (715) containing the computational core can also serve as wiring connecting the layer (716) containing the memory of each layer and the interposer (731), the number of wires can be reduced.

[0586] In addition, although the configuration example of FIG. 30 (A) describes a case where the monolithic stacking configuration is a single unit, the configuration may also be one in which the electronic components of the monolithic stacking configuration are provided by overlapping with other electronic components. For example, as shown in FIG. 30 (B), the configuration may be one in which a layer (716A) containing memory and a layer (715A) containing a computational core, and a layer (716B) containing memory and a layer (715B) containing a computational core are stacked in multiple units. In the monolithic stacking configuration provided by overlapping with other electronic components, it is fixed to a resin sheet (744) by an adhesive layer (743). By making the above configuration, multiple memory cell arrays having different circuit configurations can be stacked. By having different circuit configurations, the semiconductor device can have different memory bandwidths and memory access latencies, and is suitable for application to configurations having a hierarchical structure such as cache memory.

[0587] In addition, in the configuration example of (A) of FIG. 30, it can be provided by stacking with other electronic components. For example, as shown in (C) of FIG. 30, the electronic component (730C) can be formed by stacking the electronic component (730A) with the layer (715C) containing a computational core such as a processor, provided within the mold (711) between the interposer (731A) and the interposer (731B). Each circuit layer can be connected through a conductor such as an electrode (733). By making the above configuration, the operation of the interface portion between the processor and the memory can be performed at high speed. Furthermore, since a gap (space) can be provided between the mold containing the layer (715C) containing the computational core and the electronic component (730A) and the mold, it can be made difficult to transfer heat generated from the layer (715C) containing the computational core to the electronic component (730A).

[0588] In addition, in the configuration example of (C) of FIG. 30, a memory layer including an OS transistor may be provided on a layer (715C) including an operation core such as a processor. For example, as shown in (D) of FIG. 30, a layer (716C) including memory may be provided on a layer (715C) including an operation core and provided in a stacked configuration with an electronic component (730A). By making the above configuration, the operation of the interface portion between the configuration of a so-called on-chip memory, in which memory is directly formed on a processor, and the configuration of a semiconductor device including a stacked memory layer can be performed at high speed.

[0589] [Electronic devices]

[0590] FIG. 31 (A) is an external view showing an example of a portable electronic device. FIG. 31 (B) is a simplified drawing showing data transmission and reception within the portable electronic device. The portable electronic device (595) includes a printed circuit board (596), a speaker (597), a camera (598), a microphone (599), etc.

[0591] The electronic component (709) can be provided on a printed circuit board (596) in a portable electronic device (595). The portable electronic device (595) can improve user convenience by processing and interpreting multiple data obtained from a speaker (597), camera (598), microphone (599), etc., using the electronic component (709). It can also be used in a system that performs voice guidance, image search, etc.

[0592] In the electronic component (709), by performing computational processing such as a neural network on the obtained image data, processing such as improving image resolution, reducing image noise, face recognition (for security purposes, etc.), object recognition (for automatic driving purposes, etc.), image compression, image correction (wide dynamic range), image restoration of a lensless image sensor, positioning, character recognition, and reduction of reflection can be performed.

[0593] The portable game device (1100) shown in FIG. 32 (A) includes a housing (1101), a housing (1102), a housing (1103), a display unit (1104), a connection unit (1105), an operation key (1107), etc. The housing (1101), the housing (1102), and the housing (1103) can be separated. By mounting the connection unit (1105) provided in the housing (1101) onto the housing (1108), the image output from the display unit (1104) can be output to another video device. Additionally, by mounting the housing (1102) and the housing (1103) onto the housing (1109), the housing (1102) and the housing (1103) are integrated and function as an operation unit. The electronic component (709) can be provided on a chip, etc., provided on the substrate of the housing (1102) and the housing (1103).

[0594] Figure 32 (B) shows a stick-type electronic device (1120) with a USB connection. The electronic device (1120) includes a housing (1121), a cap (1122), a USB connector (1123), and a substrate (1124). The substrate (1124) is housed in the housing (1121). For example, a memory chip (1125) and a controller chip (1126) are mounted on the substrate (1124). The electronic components (709) can be provided on the controller chip (1126) of the substrate (1124), etc.

[0595] Figure 32 (C) shows a humanoid robot (1130). The robot (1130) includes sensors (2101 to 2106) and a control circuit (2110). For example, the control circuit (2110) may be provided with the electronic component (709).

[0596] [Large Computer]

[0597] The above electronic component (709) may be used in a system (3000) including a large computer that communicates with the electronic device, instead of being embedded in the electronic device. In this case, the computing system is configured with the electronic device and the large computer. An example of the configuration of the system (3000) is shown in FIG. 33.

[0598] The system (3000) consists of an electronic device (3001) and a large computer (3002). Communication between the electronic device (3001) and the large computer (3002) can be performed via an internet line (3003).

[0599] The large computer (3002) includes a plurality of racks (3004). A plurality of substrates (3005) are provided in the plurality of racks, and electronic components (709) described in the previous embodiment can be mounted on the substrates (3005). Thus, a neural network is configured in the large computer (3002). The large computer (3002) can perform neural network operations using data input from the electronic device (3001) via the internet line (3003). The results of the operations performed by the large computer (3002) can be transmitted to the electronic device (3001) via the internet line (3003) as needed. This reduces the burden of operations on the electronic device (3001).

[0600] This embodiment can be appropriately combined with the description of other embodiments.

[0601] <Notes on the Description in this Specification, etc.>

[0602] The description of the preceding embodiment and each component in the embodiment is appended below.

[0603] The configurations described in each embodiment can be appropriately combined with the configurations described in other embodiments to form one form of the present invention. In addition, if multiple configuration examples are described in one embodiment, the configuration examples can be appropriately combined.

[0604] In addition, the contents described in any one embodiment (may be partial contents) may be applied, combined, or substituted, etc. with other contents described in that embodiment (may be partial contents) and / or contents described in one or more other embodiments (may be partial contents).

[0605] In addition, the content described in the embodiments refers to the content described using various drawings in each embodiment or the content described using sentences written in the specification.

[0606] In addition, the drawings described in any one embodiment (may be part of them) may be combined with other parts of the drawings, other drawings described in that embodiment (may be part of them), and / or drawings described in one or more other embodiments (may be part of them) to form more drawings.

[0607] Furthermore, in the block diagrams described in this specification and others, components are classified by function and represented as independent blocks. However, in actual circuits, it is difficult to classify components by function, and there may be cases where multiple functions are involved in a single circuit or a single function is involved in multiple circuits. Therefore, the blocks in the block diagram are not limited to the components described in the specification and can be appropriately rephrased.

[0608] In addition, the size, layer thickness, or area in the drawings is shown as an arbitrary size for the convenience of explanation. Therefore, it is not necessarily limited to that scale. Furthermore, the drawings are schematically represented for clarity and are not limited to the shapes or values ​​shown in the drawings. For example, it may include deviations in signal, voltage, or current caused by noise, or deviations in signal, voltage, or current caused by timing misalignment.

[0609] When describing the connection relationships of a transistor in the present specification, etc., notations such as "one of the source and drain" (or the first electrode or the first terminal) and "the other of the source and drain" (or the second electrode or the second terminal) are used. This is because the source and drain of the transistor change depending on the structure or operating conditions of the transistor. In addition, the terms source and drain of the transistor can be appropriately changed to source (drain) terminal or source (drain) electrode.

[0610] Furthermore, the terms "electrode" or "wiring" in this specification and others do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Additionally, the terms "electrode" or "wiring" include cases where multiple "electrodes" or "wiring" are integrally formed.

[0611] In addition, voltage and potential may be appropriately interchanged in this specification and the like. Voltage refers to the potential difference from a reference potential, and for example, if the reference potential is ground voltage, voltage may be interchanged with potential. Ground potential does not necessarily mean 0V. Also, potential is relative, and depending on the reference potential, the potential applied to wiring, etc. may change.

[0612] Additionally, terms such as 'film' and 'layer' in this specification are interchangeable. For example, the term 'conductive layer' may be changed to the term 'conductive film'. Or, for example, the term 'insulating film' may be changed to the term 'insulating layer'.

[0613] In the present specification, etc., the term "switch" refers to a device having the function of controlling whether to conduct (on state) or not conduct (off state) current. Alternatively, the term "switch" refers to a device having the function of selecting and switching the path through which current flows.

[0614] In the present specification and others, the channel length in a planar transistor refers, for example, to the distance between the source and the drain in the region where the semiconductor (or the part within the semiconductor through which current flows when the transistor is in the ON state) and the gate overlap in the planar view of the transistor, or in the region where the channel is formed.

[0615] In the present specification, etc., channel width refers to, for example, the length of the portion where the source and drain face each other in the region where the semiconductor (or the portion where current flows within the semiconductor when the transistor is in the ON state) and the gate electrode overlap, or in the region where the channel is formed.

[0616] Furthermore, in this specification and others, a node may be replaced with a terminal, wiring, electrode, conductive layer, conductor, impurity region, etc., depending on the circuit configuration, device structure, etc. Additionally, a terminal, wiring, etc., may be replaced with a node.

[0617] In the present specification and others, the "on state" of a transistor refers to a state in which, for example, the source and drain of the transistor can be considered to be short-circuited. For example, in an n-channel transistor, the state in which the voltage between the gate and the source is higher than the threshold voltage, or in a p-channel transistor, the state in which the voltage between the gate and the source is lower than the threshold voltage, is referred to as the "on state." Furthermore, the "on state" of a transistor refers to a state in which current can flow between the source and the drain. Therefore, the "on state" of a transistor is sometimes referred to as the "conduction state" of the transistor.

[0618] In the present specification and others, the term "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be blocked. For example, in an n-channel transistor, a state in which the voltage between the gate and the source is lower than the threshold voltage, or in a p-channel transistor, a state in which the voltage between the gate and the source is higher than the threshold voltage, is referred to as the "off state." Additionally, the "off state" of a transistor may be referred to as the "non-conduction state" of the transistor.

[0619] In the present specification, etc., the voltage between the gate and the source (gate-source) may be referred to as the "gate voltage," the voltage between the drain and the source (drain-source) may be referred to as the "drain voltage," and the voltage between the back gate and the source (back gate-source) may be referred to as the "back gate voltage." Additionally, the current flowing from the drain to the source may be referred to as the "drain current."

[0620] In this specification and others, the term "off-current" of a transistor refers to the drain current when the transistor is in the off state, unless otherwise specifically stated. Additionally, in this specification and others, the off-current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may be referred to as leakage current.

[0621] In this specification, "connection" includes, by way of example, "electrical connection." Furthermore, when the term "electrical connection" is used to define the connection relationship of circuit elements as an object, "electrical connection" includes, by way of example, "direct connection" and "indirect connection." "A and B are directly connected" means, by way of example, that A and B are connected without passing through a circuit element (referring, for example, a transistor or switch, etc., but not wiring). On the other hand, "A and B are indirectly connected" means, by way of example, that A and B are connected through one or more circuit elements.

[0622] In cases where it is stipulated here that 'A and B are indirectly connected,' it refers to the connection relationship in the following cases as an example. That is, assuming the circuit is operating, if there is a timing during the circuit's operation period in which the exchange of electrical signals or potential interaction occurs between A and B, such a circuit may be stipulated as having 'A and B indirectly connected.' Furthermore, even if there is a timing in which the exchange of el...

Claims

Claim 1 A semiconductor device comprising a first memory cell, a sensing amplifier, a second memory cell, and an operation block, wherein the first memory cell, the sensing amplifier, and the operation block are provided in a first element layer, the second memory cell is provided in a second element layer, the second element layer is provided in a layer above the first element layer, the second memory cell is electrically connected to the sensing amplifier and the first memory cell through a first bit line, the first memory cell is electrically connected to the operation block through a second bit line, and the data transmitted to the operation block is data maintained in the second memory cell that is activated in the sensing amplifier and recorded in the first memory cell. Claim 2 A semiconductor device according to claim 1, wherein the first memory cell includes a first transistor, and the first transistor includes a first semiconductor layer including silicon in a channel forming region. Claim 3 A semiconductor device according to claim 1 or 2, wherein the second memory cell comprises a second transistor, and the second transistor comprises a second semiconductor layer comprising an oxide semiconductor in a channel forming region. Claim 4 A semiconductor device according to claim 1, wherein the first memory cell is a memory cell of static random access memory. Claim 5 A semiconductor device according to claim 1, wherein the first bit line comprises a portion provided parallel to a direction perpendicular to the surface of a substrate on which the first element layer is provided, between the second memory cell and the sensing amplifier and between the second memory cell and the first memory cell. Claim 6 A semiconductor device comprising a first memory cell, a sensing amplifier, a second memory cell, and an operation block, wherein the first memory cell, the sensing amplifier, and the operation block are provided in a first element layer, the second memory cell is provided in a second element layer, the second element layer is provided in a layer above the first element layer, the second memory cell is electrically connected to the sensing amplifier and the first memory cell through a first bit line, the first memory cell is electrically connected to the operation block through a second bit line, and the data transmitted to the operation block is data maintained in the second memory cell that is activated in the sensing amplifier and recorded in the first memory cell, and the operation block comprises a product-sum operation unit, an activation function operation unit, a data conversion unit, a load-store unit, and a controller unit. Claim 7 A semiconductor device according to claim 6, wherein the first memory cell comprises a first transistor, and the first transistor comprises a first semiconductor layer including silicon in a channel forming region. Claim 8 A semiconductor device according to claim 6 or 7, wherein the second memory cell comprises a second transistor, and the second transistor comprises a second semiconductor layer comprising an oxide semiconductor in a channel forming region. Claim 9 In claim 6, the semiconductor device wherein the first memory cell is a memory cell of static random access memory. Claim 10 A semiconductor device according to claim 6, wherein the first bit line has a portion provided parallel to a direction perpendicular to the surface of a substrate on which the first element layer is provided, between the second memory cell and the sensing amplifier and between the second memory cell and the first memory cell. Claim 11 In claim 6, the above-mentioned operation unit includes an operation circuit and an analog-to-digital conversion circuit, wherein the operation circuit includes a cell array that performs an operation and an input circuit that converts an input digital signal into an analog signal and inputs it to the cell array, and the analog-to-digital conversion circuit has the function of converting an analog signal output by the operation circuit into a digital signal, wherein the input circuit and the analog-to-digital conversion circuit are provided in the first element layer, and the cell array is provided in the second element layer.

Images