Improvement of seam performance for large-area gap fills

Abstract

Methods for filling features on a semiconductor substrate may include the step of performing a process for filling features on a semiconductor substrate by repeatedly performing first operations. The first operations may include providing a silicon-containing precursor. The first operations may include contacting a substrate with a silicon-containing precursor to form a silicon-containing material within a feature defined on the substrate. The first operations may include purging a semiconductor processing chamber. The first operations may include providing an oxygen-containing precursor. The first operations may include contacting a substrate with an oxygen-containing precursor to form silicon and oxygen-containing materials within a feature defined on the substrate. At least some parts of the first operations may be performed as frequency characteristics, power characteristics, and pressure characteristics.

Description

Technology Field Cross-reference regarding related applications

[0001] This application claims the interest and priority of U.S. Regular Application No. 18 / 410,634, filed on January 11, 2024, under the title "SEAM PERFORMANCE IMPROVEMENT FOR LARGE AREA GAPFILL," the contents of which are incorporated herein by reference in their entirety for all purposes. Technology field

[0002] The present technology relates to methods of semiconductor processing. More specifically, the present technology relates to methods of forming materials on semiconductor structures. Background Technology

[0003] Integrated circuits are made possible by processes that generate complexly patterned material layers on substrate surfaces. Generating patterned materials on a substrate requires controlled methods for forming and removing the materials. As device sizes continue to decrease and device complexity continues to increase, creating structures is becoming increasingly complex. Developing structures may require significantly more operations to generate complex patterns and achieve material integration. Additionally, complex patterning and material integration at the intersections of materials containing similar materials may require more operations to prevent potential deformations or unwanted formations.

[0004] Therefore, there is a need for improved systems and methods that can be used to produce high-quality devices and structures. These and other needs are addressed by the present technology.

[0005] In some embodiments, as a method for filling a feature on a semiconductor substrate, the method may include the step of performing a process for filling a feature on a semiconductor substrate in a semiconductor processing chamber, wherein the process includes repeatedly performing first operations, the first operations include providing a silicon-containing precursor; contacting a substrate with the silicon-containing precursor to form a silicon-containing material within a defined feature on the substrate; purging the semiconductor processing chamber; providing an oxygen-containing precursor plasma having power characteristics and pressure characteristics based at least partially on the frequency characteristics of a plasma power source of the semiconductor processing chamber — the power characteristics, pressure characteristics, and frequency characteristics are configured to increase the radical density of the oxygen-containing precursor plasma and provide kinetic energy within a certain range to the ions of the oxygen-containing precursor plasma — and contacting a substrate with the oxygen-containing precursor to form a silicon and oxygen-containing material within a defined feature on the substrate.

[0006] In some embodiments, as a method for filling features on a semiconductor substrate, the method comprises the step of performing a process for filling features on a semiconductor substrate in a semiconductor processing chamber, wherein the process comprises repeatedly performing first operations, the first operations comprising: providing a silicon-containing precursor; contacting a substrate with the silicon-containing precursor to form a silicon-containing material within a feature defined on the substrate; purging the semiconductor processing chamber; providing an oxygen-containing precursor; and contacting the substrate with the oxygen-containing precursor by forming a plasma having frequency characteristics, power characteristics, and pressure characteristics — the power characteristics, pressure characteristics, and frequency characteristics are configured to provide sufficient radical density and kinetic energy, and contacting the substrate with the oxygen-containing precursor forms silicon and oxygen-containing materials within a feature defined on the substrate —.

[0007] In some embodiments, as a method for filling features on a semiconductor substrate, the method comprises the step of performing a process for filling features on a semiconductor substrate in a semiconductor processing chamber, wherein the process comprises repeatedly performing first operations at a first pressure level, the first operations comprising: providing a silicon-containing precursor; contacting a substrate with the silicon-containing precursor to form a silicon-containing material within a defined feature on the substrate; purging the semiconductor processing chamber; providing an oxygen-containing precursor; and providing an oxygen-containing precursor. The process for filling features may further comprise second operations, the second operations comprising applying a silicon-containing and non-oxide-containing material through a conformal application process.

[0008] In any embodiment, any and all of the following features may be implemented in any combination and without limitation. In some embodiments, providing an oxygen-containing precursor having power characteristics, pressure characteristics, and frequency characteristics may cause a gap in the feature to be closed by causing a first side of the silicon and oxygen-containing material in the feature to bond with a second side of the silicon and oxygen-containing material in the feature. In some embodiments, forming the silicon-containing material in the feature may include forming an atomic layer of silicon on an exposed surface of the feature. In some embodiments, forming the silicon and oxygen-containing material in the feature may include providing oxygen to the atomic layer of silicon. In some embodiments, contacting the silicon and oxygen-containing material with the oxygen-containing precursor having frequency characteristics, power characteristics, and pressure characteristics may cause a gap in the feature to be closed by causing a first side of the silicon and oxygen-containing material in the feature to bond with a second side of the silicon and oxygen-containing material in the feature. In some embodiments, the frequency characteristics may be in the range of about 25 MHz to 30 MHz. In some embodiments, the pressure characteristic may be within a second range of about 4 Torr to about 15 Torr. In some embodiments, the power characteristic may be within a third range of about 1500 watts to about 3000 watts. In some embodiments, providing the oxygen-containing precursor plasma may include providing the oxygen-containing precursor plasma at a second frequency characteristic of a second plasma power source of a semiconductor processing chamber, and the second frequency characteristic may be within a fourth range of about 1 kHz to 1 MHz. In some embodiments, the feature may be characterized by an aspect ratio of about 10:1 or greater. In some embodiments, the oxygen-containing precursor may include O2.In some embodiments, power characteristics may be within a range of about 1,000 watts to about 2,000 watts. In some embodiments, pressure characteristics may be within a second range of about 8 Torr to about 15 Torr. In some embodiments, frequency characteristics may be within a third range of about 10 MHz to 15 MHz. In some embodiments, the process may be performed at a temperature of about 400°C or higher. In some embodiments, the conformal application process may be a chemical vapor deposition process. In some embodiments, the conformal application process may be an atomic layer deposition process. In some embodiments, the silicon-containing and non-oxide-containing materials may include at least one of SiC, SiN, and high-purity silicon. In some embodiments, the second operations may be performed in a semiconductor processing chamber. Brief explanation of the drawing

[0009] Further understanding of the nature and advantages of the disclosed technology can be achieved by referring to the drawings and the remainder of this specification.

[0010] FIG. 1 illustrates a schematic cross-sectional view of an exemplary plasma system according to some embodiments of the present technology.

[0011] FIGS. 2a through 2d illustrate exemplary schematic cross-sectional structures in which material layers are formed according to some embodiments of the present technology.

[0012] FIGS. 3a and 3b illustrate exemplary schematic cross-sectional structures in which material layers are formed according to some embodiments of the present technology.

[0013] FIG. 4 illustrates operations in a semiconductor processing method according to some embodiments of the present technology.

[0014] FIGS. 5a and 5b illustrate exemplary schematic cross-sectional structures in which material layers are formed according to some embodiments of the present technology.

[0015] FIG. 6 illustrates operations in a semiconductor processing method according to some embodiments of the present technology.

[0016] Several of the drawings are included as schematics. It should be understood that the drawings are for illustrative purposes only and should not be considered to be of actual scale unless specifically stated otherwise. Additionally, as schematics, the drawings are provided for illustrative purposes and may not include all aspects or information compared to actual representations, and may contain exaggerated data for illustrative purposes.

[0017] In the attached drawings, similar components and / or features may have the same reference label. Additionally, various components of the same type may be distinguished by having a character following the reference label that distinguishes between similar components. Where only the first reference label is used in this specification, the description is applicable to any component among similar components having the same first reference label, regardless of the character. Specific details for implementing the invention

[0018] Silicon materials can be used in the fabrication of semiconductor devices for a variety of structures and processes. In gap-fill operations, some processing may utilize plasma-enhanced deposition under process conditions in an attempt to increase the directionality of deposition, which can allow the deposited material to better fill features on the substrate. However, in some deposition processes, the deposited material in certain types of features may feature seams when the deposited material comes into contact with other deposited materials. For example, if a feature exhibits a significantly large depth-to-width ratio (meaning the feature is deep but the aperture size is relatively narrow in width), the deposited material from the sides of the feature may come into contact and create seams. Seams can indicate that the gap-fill process failed to properly fill the gaps and can lead to structural problems as additional semiconductor manufacturing processes are performed on the substrate.

[0019] As feature sizes continue to shrink, depositions on narrow features that can additionally feature higher aspect ratios may face difficulties. For example, as material is deposited on a feature with a high aspect ratio, seams may form between the deposited material on the first side of the feature and the deposited material on the second side of the feature. Seams may also be referred to as gaps or voids. Seams indicate that the deposited material on the sides of the feature does not bond when the deposited materials on the sides come into contact. These seams may not be visible to tools because they may exist at the atomic level. Nevertheless, the etchant used for the deposited material (e.g., a buffer oxide etchant for silicon oxide deposited material) can reveal and / or demonstrate the presence of seams between the deposited materials on the sides of the feature.

[0020] This technology can overcome these limitations by performing atomic layer deposition of materials having sufficiently high radical density and optimized kinetic energy, which can improve large-scale gap-fill operations by eliminating and / or reducing seams in the gap-fill material. Sufficiently high radical density and optimized kinetic energy can be achieved by carefully adjusting the power supplied to the plasma and the pressure within the semiconductor manufacturing chamber based on the frequencies of the plasma power source. Increasing the radical density in the gap-fill material can provide more bonding sites on both sides to help bond the two sides of the deposited material. Sufficient kinetic energy can provide enough energy for bonding the two sides when there are sufficient radicals. Too much kinetic energy can cause damage within the gap-fill material. Additionally, the gap-fill operation may involve partially filling the gap by forming layers of compression films and then filling the remainder of the gap by applying non-oxide silicon material through a conformal process. In this way, the gap fill can have compressible properties, but a seam is not formed between the two sides of the non-oxide silicon material at the center of the gap fill.

[0021] The remainder of the disclosure will conventionally identify specific deposition processes utilizing the disclosed technology and describe one type of semiconductor processing chamber, but it will be readily understood that the described processes can be performed in any number of semiconductor processing chambers. Additionally, the technology may be applicable to any number of semiconductor processes beyond the exemplary processes described below. Accordingly, the technology should not be considered to be limited to use only in these specific deposition processes or chambers. Before semiconductor processing methods according to embodiments of the technology are described, the disclosure will discuss one possible chamber that can be used to perform the processes according to embodiments of the technology.

[0022] Fig. 1The drawing illustrates a cross-sectional view of an exemplary processing chamber (100) according to some embodiments of the present technology. The drawing may illustrate an overview of a system that may be specifically configured to incorporate one or more aspects of the present technology and / or perform one or more operations according to embodiments of the present technology. Further details of the chamber (100) or the methods performed may be further described below. The chamber (100) may be used to form film layers, etch material layers, form other material layers, or a combination thereof, but it should be understood that deposition and etching methods may similarly be performed in any chamber where deposition and etching processes may occur therein. The processing chamber (100) may include a chamber body (102), a substrate support (104) disposed inside the chamber body (102), and a lid assembly (106) coupled to the chamber body (102) and surrounding the substrate support (104) within the processing volume (120). A substrate (103) may be provided to a processing volume (120) through an opening (126), and the opening (126) may be typically sealed for processing using a slit valve or door. The substrate (103) may be placed on the surface (105) of a substrate support during processing. In some embodiments, the substrate support (104) may be rotatable along a vertical axis where the shaft (144) of the substrate support (104) may be located, or it may be stationary. Alternatively, the substrate support (104) may be lifted to rotate as needed during the deposition process.

[0023] The gas distributor (112) may define apertures (118) for distributing process precursors into a processing volume (120). The gas distributor (112) may be coupled to a first electric power source (142), such as an RF generator, an RF power source, a DC power source, a pulsed DC power source, a pulsed RF power source, or any other power source that can be coupled to the processing chamber. In some embodiments, the first electric power source (142) may be an RF power source.

[0024] The gas distributor (112) may be a conductive gas distributor or a non-conductive gas distributor. The gas distributor (112) may also be formed of conductive and non-conductive components. For example, the body of the gas distributor (112) may be conductive, while the face plate of the gas distributor (112) may be non-conductive. The gas distributor (112) may be powered by a first electric power source (142), for example, as shown in FIG. 1, or the gas distributor (112) may be coupled to ground in some embodiments.

[0025] The first electrode (122) may be coupled to the substrate support (104). The first electrode (122) may be embedded within the substrate support (104) or coupled to the surface of the substrate support (104). The first electrode (122) may be a plate, a perforated plate, a mesh, a wire screen, or any other distributed arrangement of conductive elements. The first electrode (122) may be a tuning electrode and may be coupled to a tuning circuit (136) by a cable having a selected resistance, such as 50 ohms, disposed within a conduit (146), for example, the shaft (144) of the substrate support (104). The tuning circuit (136) may have an electronic sensor (138) and an electronic controller (140), which may be a variable capacitor. The electronic sensor (138) may be a voltage or current sensor and may be coupled with an electronic controller (140) to provide additional control over plasma conditions within the processing volume (120).

[0026] A second electrode (124), which may be a bias electrode and / or an electrostatic chuck electrode, may be coupled to a substrate support (104). The second electrode may be coupled to a second electric power source (150) through a filter (148), which may be an impedance matching circuit. The second electric power source (150) may be DC power, pulsed DC power, RF bias power, pulsed RF source or bias power, or a combination of these or other power sources. In some embodiments, the second electric power source (150) may be RF bias power. The substrate support (104) may also include one or more heating elements configured to heat the substrate to a processing temperature that may be about 25°C to about 800°C or higher.

[0027] The cover assembly (106) and substrate support (104) of FIG. 1 may be used with any processing chamber for plasma or thermal processing. In operation, the processing chamber (100) may provide real-time control of plasma conditions within the processing volume (120) through a system controller (101) that may be included, for example, in a processor (107). A substrate (103) may be placed on the substrate support (104), and process gases may flow through the cover assembly (106) using an inlet (114) according to any desired flow plan. The gases may exit the processing chamber (100) through an outlet (152). Electric power may be coupled with a gas distributor (112) to form plasma within the processing volume (120). In some embodiments, the substrate may be electrically biased using a second electrode (124).

[0028] When the plasma within the processing volume (120) is energized, a potential difference can be established between the plasma and the first electrode (122). Then, an electronic controller (140) can be used to control the flow properties of the ground paths represented by the tuning circuit (136). A set point can be transmitted to the tuning circuit (136) to provide independent control of the deposition rate and the plasma density uniformity from the center to the edge. In embodiments where both electronic controllers may be variable capacitors, the electronic sensors can independently control the variable capacitors to minimize thickness non-uniformity and maximize the deposition rate.

[0029] The tuning circuit (136) may have a variable impedance that can be adjusted using an electronic controller (140). If the electronic controller (140) is a variable capacitor, the capacitance range of each variable capacitor may be selected to provide a constant impedance range. This range may depend on the frequency and voltage characteristics of the plasma, which may have a minimum value at the capacitance range of each variable capacitor. Thus, when the capacitance of the electronic controller (140) is at a minimum or maximum value, the impedance of the tuning circuit (136) may be high, which may cause a plasma shape having minimum aerial or lateral coverage over the substrate support. When the capacitance of the electronic controller (140) approaches a value that minimizes the impedance of the tuning circuit (136), the aerial coverage of the plasma may grow to a maximum, which can effectively cover the entire working area of ​​the substrate support (104). When the capacitance of the electronic controller (140) deviates from the minimum impedance setting, the plasma shape may shrink from the chamber walls and the aerial coverage of the substrate support may be reduced.

[0030] The electronic sensor (138) can be used to tune the tuning circuit (136) in a closed loop. Depending on the type of sensor used, a set point for current or voltage may be installed on each sensor, and the sensor may be provided with control software that determines the adjustment to the electronic controller (140) to minimize deviation from the set point. Consequently, the plasma shape can be selected and dynamically controlled during processing. Although the foregoing discussion is based on the electronic controller (140), which may be a variable capacitor, it should be understood that any electronic component having adjustable characteristics may be used to provide an adjustable impedance to the tuning circuit (136).

[0031] A processing chamber (100) may be used in some embodiments of the present invention for processing methods that may include bottom-up deposition of materials for semiconductor structures. The described chamber should not be considered limiting, and it should be understood that any chamber configured to perform operations as described may be used similarly.

[0032] A processing chamber (100) may be used in some embodiments of the present invention for processing methods that may include forming, etching, or converting materials for semiconductor structures. The described chamber should not be considered limiting, and it should be understood that any chamber configured to perform operations as described may be used similarly. FIGS. 2a to 2d The drawings schematically illustrate exemplary operations in processing methods according to some embodiments of the present technology. The methods may be performed in various processing chambers, including the processing chamber (100) described above, and on one or more mainframes or tools. The processing methods may include a number of optional operations that may or may not be specifically associated with some embodiments of the methods according to the present technology. For example, many of the operations are described to provide a wider range of structural formations, but may be performed by alternative methodologies that are not critical to the technology or are readily recognizable. The drawings illustrate only partial schematics, and it should be understood that the structure (200) or substrate (205) may include any number of additional materials and features having various characteristics and aspects as illustrated in the drawings.

[0033] The substrate (205) may include any number of materials used in semiconductor processing. The substrate material may be dielectric materials including silicon, germanium, silicon oxide or silicon nitride, metal materials, or any number of combinations of these materials, or may include them. The substrate (205) may include one or more substrate features formed within the substrate (205). The substrate (205) may include one or more materials (210) on which one or more features can be formed. The features may feature any shape or configuration according to the present technology. In some embodiments, the features may be or include trench structures (208) or apertures formed within the substrate. In some embodiments, the features may feature any aspect ratios or height-to-width ratios of the structures, but in some embodiments, the materials may feature larger aspect ratios, which may not allow seam-free or void-free deposition using conventional techniques or methodologies. For example, in some embodiments, the aspect ratio of any layer of the exemplary structure may be about 10:1 or more, about 11:1 or more, about 12:1 or more, about 13:1 or more, about 14:1 or more, about 15:1 or more, about 16:1 or more, or greater than that. Additionally, the features are about 2.0 microns or less, about 1.9 microns or less, about 1.8 microns or less, about 1.7 microns or less, about 1.6 microns or less, about 1.5 microns or less, about 1.4 microns or less, about 1.3 microns or less, about 1.2 microns or less, about 1.1 microns or less, about 1.0 microns or less, about 0.9 microns or less, about 0.8 microns or less, about 0.7 microns or less, about 0.6 microns or less, about 0.5 microns or less, about 0.4 microns or less, about 0.3 microns or less, about 0.2 microns or less, about 0.It may be characterized by a reduced width such as 1 micron or less, or less than (including any fraction of any number among the mentioned numbers). As such, features may feature heights such as about 20.0 microns or less, about 19.0 microns or less, about 18.0 microns or less, about 17.0 microns or less, about 16.0 microns or less, about 15.0 microns or less, about 14.0 microns or less, about 13.0 microns or less, about 12.0 microns or less, about 11.0 microns or less, about 10.0 microns or less, about 9.0 microns or less, about 8.0 microns or less, about 7.0 microns or less, about 6.0 microns or less, about 5.0 microns or less, about 4.0 microns or less, about 3.0 microns or less, about 2.0 microns or less, about 1.0 microns or less, about 0.8 microns or less, or less (including any fraction of any of the numbers mentioned). This combination of high aspect ratios and minimum widths can make many conventional deposition operations difficult for bonding the deposited material on one side of a feature with the deposited material on the other side of the feature.

[0034] The methods described herein may include additional operations prior to the initiation of operations for gap-filling the seams. For example, additional processing operations may include forming structures on the semiconductor substrate (205), which may include both forming and removing materials. For example, transistor structures, memory structures, or any other structures may be formed. The prior processing operations may be performed in a chamber where the methods for gap-filling the seams described herein may be performed, or processing may be performed in one or more other processing chambers before transferring the substrate to a semiconductor processing chamber or chambers where the methods for gap-filling the seams described herein may be performed. Regardless of this, the methods for gap-filling the seams described herein may optionally include the step of transferring the semiconductor substrate (205) to a processing area of ​​a semiconductor processing chamber such as the processing chamber (100) described above, or to another chamber that may include components as described above. The substrate (205) may be a pedestal such as the substrate support (104) and may be placed on the substrate support that may reside in a processing area of ​​a semiconductor processing chamber such as a processing volume.

[0035] Embodiments of the present disclosure may form silicon-containing and / or silicon and oxygen-containing materials through atomic layer deposition. The material may be formed by alternately providing precursors so that the material is formed intermittently. To deposit silicon and oxygen-containing materials, the precursors may include silicon and oxygen. A precursor containing silicon may be referred to as a silicon-containing precursor. A precursor containing oxygen may be referred to as an oxygen-containing precursor. In some embodiments, silicon and oxygen-containing materials may be formed through atomic layer deposition. To incorporate oxygen, the precursors may further include oxygen. For example, the oxygen-containing precursor may be provided intermittently during formation. Alternatively, the silicon-containing precursor may further include oxygen. For example, the silicon-containing precursor may be a silicon and oxygen-containing precursor.

[0036] Embodiments of the present disclosure may gap-fill seams formed between sides of silicon and oxygen-containing materials along sides of a feature. In some embodiments, gap-filling seams may be performed via atomic layer deposition. Gap-filling seams may be performed by alternately providing precursors so that the material is formed intermittently. One precursor may include silicon and may be referred to as a silicon-containing precursor. Another precursor may include oxygen and may be referred to as an oxygen-containing precursor.

[0037] In embodiments, the silicon-containing precursor may be any silicon-containing material useful in semiconductor processing, such as in atomic layer deposition processes. Exemplary silicon-containing precursors may be or include any other silicon-containing precursors that can be used to form silicon-containing materials, as well as silanes, disilanes, or other aminosilanes, or cyclohexasilanes, silicon tetrafluoride, silicon tetrachloride, dichlorosilane, tetraethyl orthosilicate (TEOS), tetramethyldisiloxane (TMDSO), hexamethyldisiloxane (HMDSO), hexamethyldisilazane (HMDSN), and silicon tetrakis(ethylmethylamide) (TEMASi), alkylaminosilanes, trisilylamines, alkylaminodisilanes, alkylsilanes, alkyloxysilanes, alkylsilanols, and other organosilanes including alkyloxysilanols (but not limited thereto). In some embodiments, the silicon-containing precursor may contain a halogen, such as chlorine, bromine, iodine, or any other halogen. Additional silicon-containing precursors may be any of the following materials or may include them: In the above materials, each X can be independently selected from chlorine, bromine, iodine, hydrogen, OR, NR2, NCO, NCS, or CN, where R can be an alkyl.

[0038] The oxygen-containing precursor may be any oxygen-containing material useful in semiconductor processing, such as in atomic layer deposition processes. For example, the oxygen-containing precursor may be molecular oxygen (O2), ozone (O3), N2O, and / or other similar materials. In embodiments, to maintain the oxygen content in the formed material, the oxygen-containing precursor may be diluted with another precursor, such as an inert precursor. The oxygen-containing precursor may be about 50% or less based on the oxygen-containing precursor and the inert precursor.

[0039] The methods described herein for gap-filling seams may include the step of providing a first precursor to a semiconductor processing chamber, e.g., a processing area of ​​the semiconductor processing chamber. Optionally, a plasma of the first precursor may be generated. Additionally, it is considered that the plasma of the first precursor may be generated prior to providing the plasma of the first precursor to the semiconductor processing chamber. In some embodiments, the first precursor is a silicon-containing precursor. Referring to FIG. 2a, the first precursor may have at least one reactive group capable of forming bonds with a group attached to a surface of a substrate (205) or one or more materials (210) within the processing area. Molecules of the first precursor (215) (e.g., a silicon-containing precursor) may react with the surface groups to form bonds that link the first precursor molecules to the surface of the substrate (205) or one or more materials (210). Reactions between the molecules of the first precursor (215) and the groups on the surface of the substrate (205) or on one or more materials (210) may continue until most or all of the surface groups are bonded to the reactive groups on the molecules of the first precursor (215). As illustrated in FIG. 2b, a first portion of the silicon-containing material (220) may be formed from the first precursor. The formation of the silicon-containing material (220) may block further reactions between the molecules of the first precursor (215) in the first precursor effluent and the substrate (205) or one or more materials (210).

[0040] The first precursor may remain in the processing area for a certain period of time to form the silicon-containing material (220) almost or completely. According to embodiments of the present technology, to form the silicon-containing material, the precursors may be delivered in alternating pulses to grow the material. In some embodiments, the pulse time of the first precursor may be about 0.5 seconds or more, about 1 second or more, about 2 seconds or more, about 3 seconds or more, about 4 seconds or more, about 5 seconds or more, about 10 seconds or more, about 20 seconds or more, about 40 seconds or more, about 60 seconds or more, about 80 seconds or more, about 100 seconds or more, or more.

[0041] The methods described herein may also include the operation of purging or removing the first precursor from the processing area following the formation of the silicon-containing material (220). The methods described herein may include the step of stopping the flow of the first precursor before purging the first precursor from the semiconductor processing chamber. The first precursor may be removed by pumping the first precursor out of the processing area for a time period ranging from about 10 seconds to about 100 seconds. Additional exemplary time ranges may include about 20 seconds to about 50 seconds, and 25 seconds to about 45 seconds, among other exemplary time ranges. However, in some embodiments, an increased purge time may begin to remove reactive sites, which may reduce uniform formation. Accordingly, in some embodiments, purging may be performed for about 60 seconds or less, about 50 seconds or less, about 40 seconds or less, about 30 seconds or less, or less. In some embodiments, a purge gas may be introduced into the processing area to assist in the removal of effluents. Exemplary purge gases include helium and nitrogen, among other purge gases.

[0042] After the removal of the first precursor, the second precursor may be provided to the semiconductor processing chamber as illustrated in FIG. 2c. Optionally, a plasma of the second precursor may be generated. It is also considered that the plasma of the second precursor may be generated prior to providing the plasma of the second precursor to the semiconductor processing chamber. The second precursor may have at least one reactive group capable of forming bonds with unreacted reactive groups of the first precursor that formed the silicon-containing material (220). In some embodiments, the second precursor is an oxygen-containing precursor. Molecules of the second precursor (225) may react with the unreacted reactive groups of the first precursor to form bonds that link the molecules of the second precursor (225) to the molecules of the first precursor (215). Reactions between the molecules of the second precursor (225) and the molecules of the first precursor (215) may continue until most or all unreacted reactive groups on the molecules of the first precursor (215) react with the molecules of the second precursor (225). As illustrated in FIG. 2d, contact between the second precursor and the silicon-containing material (220) may form a silicon and oxygen-containing material (230), such as silicon oxide (SiO, or SiO2). The formation of the silicon and oxygen-containing material (230) may block further reactions between the molecules of the second precursor (225) and the silicon-containing material (220) within the second precursor effluent.

[0043] Similar to the first precursor, the second precursor may remain in the processing area for a certain period of time to form the silicon and oxygen-containing material (230) almost or completely. As previously discussed, to form the silicon and oxygen-containing material according to embodiments of the present technology, the precursors may be delivered in alternating pulses to grow the material. In some embodiments, the pulse time of the second precursor may be about 0.5 seconds or more, about 1 second or more, about 2 seconds or more, about 3 seconds or more, about 4 seconds or more, about 5 seconds or more, about 10 seconds or more, about 20 seconds or more, about 40 seconds or more, about 60 seconds or more, about 80 seconds or more, about 100 seconds or more, or more.

[0044] In some embodiments, the first precursor may be pulsed for longer periods than the second precursor. By increasing the residence time of the first precursor, improved adhesion across the substrate (205) or one or more materials (210) may be produced. Then, the second precursor may react more readily with the ligands of the first precursor, and thus the second precursor may be pulsed for a shorter period, which can improve throughput. For example, in some embodiments, the second precursor may be pulsed for about 90% or less of the time the first precursor is pulsed. The second precursor may also be pulsed for about 80% or less of the time the first precursor is pulsed, about 70% or less of the time the first precursor is pulsed, about 60% or less of the time the first precursor is pulsed, about 50% or less of the time the first precursor is pulsed, about 40% or less of the time the first precursor is pulsed, about 30% or less of the time the first precursor is pulsed, or less than that.

[0045] The methods described herein may also include the operation of purging or removing second precursor effluents from the processing area following the formation of the silicon and oxygen-containing material (230). The methods described herein may include the step of stopping the flow of the second precursor before purging the second precursor. The second precursor may be removed by pumping it out of the processing area for a time period ranging from about 10 seconds to about 100 seconds. Additional exemplary time ranges may include about 20 seconds to about 50 seconds, and 25 seconds to about 45 seconds, among other exemplary time ranges. In some embodiments, a purge gas may be introduced into the processing area to assist in the removal of the effluents. Exemplary purge gases include helium and nitrogen, among other purge gases.

[0046] In embodiments, following one or more cycles of forming a silicon and oxygen-containing material (230), there may be a determination as to whether the target thickness of the material immediately after deposition (as-deposited) on the substrate (205) or one or more materials (210) has been achieved. If the target thickness of the material immediately after deposition has not been achieved, another cycle of providing the first precursor and the second precursor may be performed. If the target thickness of the material immediately after deposition has been achieved, the other cycle of providing the first precursor and the second precursor may not be started. Exemplary number of cycles for forming the silicon and oxygen-containing material (230) may include one cycle, or more than two cycles, five cycles, ten cycles, twenty-five cycles, fifty cycles, one hundred cycles, one thousand cycles, two thousand cycles, three thousand cycles, four thousand cycles, five thousand cycles, six thousand cycles, seven thousand cycles, eight thousand cycles, nine thousand cycles, ten thousand cycles, or more. Additional exemplary ranges for the number of cycles may include 50 to 2000 cycles, 50 to 1000 cycles, and 100 to 750 cycles, 1000 to 2000 cycles, 2000 to 3000 cycles, 3000 to 4000 cycles, 4000 to 5000 cycles, 5000 to 6000 cycles, 6000 to 7000 cycles, 7000 to 8000 cycles, 8000 to 9000 cycles, 9000 to 10000 cycles, and / or any combination of these ranges. For example, some embodiments may use 6000 to 8000 cycles for a gap structure with a width of 1 μm. Exemplary ranges of target thicknesses for stopping additional cycles of forming silicon and oxygen-containing material (230) are about 1.Includes 0 micron or less. Additional exemplary thickness ranges may include about 1.0 micron or less, about 0.9 micron or less, about 0.8 micron or less, about 0.7 micron or less, about 0.6 micron or less, about 0.5 micron or less, about 0.4 micron or less, about 0.3 micron or less, about 0.2 micron or less, about 0.1 micron or less, or less than (including any fraction of any of the numbers mentioned).

[0047] FIGS. 3a to 3b Figure 3 illustrates schematically how a seam may be formed during processing methods according to some embodiments of the present technology. Sections (302) and (304) schematically illustrate how a seam (350) is formed by a silicon and oxygen-containing material (330) (e.g., the silicon and oxygen-containing material (230) of FIG. 2) deposited into one or more materials (310) (e.g., one or more materials (210) of FIG. 2). In FIG. 3a, a space (340) may be seen between two sides of the silicon and oxygen-containing material (330) deposited into the feature. The silicon and oxygen-containing material (330) may be approximately uniform across the surface of one or more materials (310).

[0048] In FIG. 3b, as more silicon and oxygen-containing material (330) is deposited, a seam (350) may be formed so that the two sides of the silicon and oxygen-containing material (330) are not bonded. The seam (350) may be formed because layers of silicon and oxygen-containing material (330) are stacked from the sides of the feature. As mentioned above, the seam (350) may be inconspicuous because the seam may exist at the atomic and / or molecular level. However, when an etchant (e.g., a buffer oxide etchant that etches the silicon and oxygen-containing material (330)) is applied to the silicon and oxygen-containing material (330) along the seam (350), the seam (350) may become visible as material from the silicon and oxygen-containing material (330) around the seam (350) is etched away.

[0049] Fig. 4 This illustrates an exemplary flowchart (400) of a method for filling features on a semiconductor substrate in a manner that reduces and / or eliminates the seams as described in this specification. This method may be performed by a controller that generates signals for controlling processing chambers and other elements as illustrated above in FIGS. 2a through 2d and FIGS. 3a through 3b. This method may be performed by a controller having processors that execute commands for performing these operations.

[0050] The method may include the step of performing a process for filling a feature on a semiconductor substrate in a semiconductor processing chamber. The process may include repeatedly performing first operations as described herein. For example, the first operations may be repeated for a number of cycles as described herein. Additionally, parts of the first operations may be repeated for a different number of cycles, such that a first part of the first operations may be repeated for a first number of cycles, while a second part of the first operations may be repeated for a second number of cycles. In some embodiments, the feature may feature an aspect ratio of about 10:1 or greater as described herein.

[0051] The first operations may include providing a silicon-containing precursor to a semiconductor processing chamber (e.g., the processing chamber (100) of FIG. 1) as described in connection with at least FIG. 2a to 2d (402). The silicon-containing precursor may be a first precursor as described herein.

[0052] The first operations may include contacting a substrate with a silicon-containing precursor as described herein to form a silicon-containing material (404) within a feature defined on the substrate. Forming the silicon-containing material within the feature may include forming an atomic layer of silicon on an exposed surface of the feature. The exposed surface of the feature may include two or more sides of the feature, for example, sides opposite each other.

[0053] The formation of the silicon-containing material (220) (either one or both of providing a silicon-containing precursor and bringing a substrate into contact with the silicon-containing precursor) can be performed at various temperatures (e.g., the temperature of the substrate (205), the temperature of the processing chamber, and / or the temperature of the precursors flowing into the processing area). Exemplary temperatures for the substrate, processing chamber, and / or precursors during the operations described herein are about 50°C or more, about 75°C or more, about 100°C or more, about 125°C or more, about 150°C or more, about 175°C or more, about 200°C or more, about 250°C or more, about 300°C or more, about 350°C or more, about 400°C or more, about 425°C or more, about 450°C or more, about 475°C or more, about 500°C or more, about 525°C or more, about 550°C or more, about 575°C or more, about 600°C or more, about 625°C or more, about 650°C or more, about 675°C or more, about 700°C or more, about 725°C or more, about 750°C or more, about 775°C or more, about 800°C or more, about 825°C or more, about The temperature may be 850°C or higher, approximately 875°C or higher, approximately 900°C or higher, approximately 925°C or higher, approximately 950°C or higher, approximately 975°C or higher, approximately 1000°C or higher, or higher. In some embodiments, exemplary temperatures may be in the range of 400°C to 1000°C. In some embodiments, exemplary temperatures may be in the range of 400°C to 700°C. In some embodiments, exemplary temperatures may be in the range of 600°C to 1000°C. By maintaining the substrate temperature high, such as at approximately 400°C or higher in some embodiments, a greater number of nucleation sites may be available along the substrate (205), which can improve formation and reduce void formation by improving coverage at each location.

[0054] The formation of the silicon-containing material (220) (either providing a silicon-containing precursor and contacting a substrate with the silicon-containing precursor, or both) can be performed at various pressures within a processing chamber. Exemplary pressures within the processing area may be in the range of about 1 Torr to about 100 Torr. In some embodiments, pressures within the processing area may be in the range of 2 to 20 Torr. In embodiments, the pressure may be about 20 Torr or less, e.g., about 19 Torr or less, about 18 Torr or less, about 17 Torr or less, about 16 Torr or less, about 15 Torr or less, about 14 Torr or less, about 13 Torr or less, about 12 Torr or less, about 11 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. In some embodiments, some of the processes within the processing chamber may be performed at approximately atmospheric pressure as described herein.

[0055] The formation of the silicon-containing material (220) (either providing a silicon-containing precursor and contacting a substrate with the silicon-containing precursor, or both) can be performed at various powers and frequencies of a plasma power source. Exemplary powers may be in the range of about 100 watts to about 5000 watts. In some embodiments, the power may be in the range of 1000 watts to 3000 watts. In embodiments, the power may be about 5000 watts or less, e.g., about 4500 watts or less, about 4000 watts or less, about 3500 watts or less, about 3000 watts or less, about 2500 watts or less, about 2000 watts or less, about 1500 watts or less, about 1000 watts or less, about 500 watts or less, or less. Exemplary frequencies may be in the range of 1 kilohertz (kHz) to 100 megahertz (MHz). In some embodiments, the frequency may be in the range of 1 kHz to 30 MHz. In embodiments, the frequency is about 100 MHz or less, e.g., about 95 MHz or less, about 90 MHz or less, about 85 MHz or less, about 80 MHz or less, about 75 MHz or less, about 70 MHz or less, about 65 MHz or less, about 60 MHz or less, about 55 MHz or less, about 50 MHz or less, about 45 MHz or less, about 40 MHz or less, about 35 MHz or less, about 30 MHz or less, about 27 MHz or less, about 25 MHz or less, about 20 MHz or less, about 15 MHz or less, about 13.56 MHz or less, about 10 MHz or less, about 5 MHz or less, about 1 MHz or less, about 750 kHz or less, about 500 kHz or less, about 350 kHz or less, about 250 kHz or less, about 100 kHz or less, about 10 kHz It may be less than or equal to. In some examples, industry standards may use about 27 MHz, about 13.56 MHz, and / or about 350 kHz.

[0056] The first operations may include purging the semiconductor processing chamber (406) as described in this specification. Purging the silicon-containing precursor from the semiconductor processing chamber may enable the use of other precursors during the process of filling features on the semiconductor substrate.

[0057] The first operations may include providing an oxygen-containing precursor plasma (408) as described herein. Providing the oxygen-containing precursor may cause a gap in the feature to be closed by causing a first side of the silicon and oxygen-containing material in the feature to bond with a second side of the silicon and oxygen-containing material in the feature, as described in connection with at least FIGS. 3a and 3b. In some embodiments, the oxygen-containing precursor may include O2. In some embodiments, the oxygen-containing precursor may include plasma, may include mainly plasma, or may be plasma. In some embodiments, the oxygen-containing precursor may include gas, may include mainly gas, or may be gas.

[0058] The first operations may include contacting a substrate with an oxygen-containing precursor as described herein to form silicon and oxygen-containing materials within features defined on the substrate (410). Forming silicon and oxygen-containing materials within features may include providing oxygen to an atomic layer of silicon.

[0059] In some examples, the oxygen-containing precursor plasma is provided with power characteristics and pressure characteristics. In some examples, the values ​​of the power characteristics and pressure characteristics are based at least partially on the frequency characteristics of the plasma power source of the semiconductor processing chamber. In some examples, the values ​​of the power characteristics and pressure characteristics are based at least partially on the frequency characteristics of the oxygen-containing precursor plasma. The power characteristics, pressure characteristics, and frequency characteristics may be configured to increase the radical density (e.g., the radical density of the oxygen-containing precursor plasma and / or the silicon and oxygen-containing material) to a sufficient threshold value. The power characteristics, pressure characteristics, and frequency characteristics may be configured to provide kinetic energy (e.g., to the oxygen-containing precursor plasma and / or the silicon and oxygen-containing material) within a range having a minimum threshold value and a maximum threshold value.

[0060] As described herein, gap-fill operations minimize seams (and / or precursors and / or formed materials) that may require a minimum amount of radical density and sufficiently optimal (e.g., neither too much nor too little) kinetic energy. As such, power characteristics, pressure characteristics, and frequency characteristics must be within specific ranges to minimize seam formation and / or improve seam performance. In some examples, increasing the frequency characteristics increases the radical density. In some examples, decreasing the frequency characteristics decreases the radical density. In some examples, increasing the frequency characteristics decreases the kinetic energy. In some examples, decreasing the frequency characteristics increases the kinetic energy. In some examples, increasing the pressure characteristics decreases the kinetic energy. In some examples, decreasing the pressure characteristics increases the kinetic energy. In some examples, increasing the power characteristics increases both the radical density and the kinetic energy. In some examples, decreasing the power characteristics decreases both the radical density and the kinetic energy.

[0061] In this way, an increase in power characteristics can be paired with an increase in pressure characteristics, so that the power characteristics provide both increased radical density (above the threshold) and kinetic energy, while the increased pressure characteristics can lower the kinetic energy within the range of the minimum and maximum thresholds. Similarly, an increase in power characteristics can be paired with an increase in frequency characteristics, so that the power characteristics provide both increased radical density (above the threshold) and kinetic energy, while the increased frequency characteristics can lower the kinetic energy within the range of the minimum and maximum thresholds. The increased frequency characteristics can also increase radical density to help raise the radical density above the threshold.

[0062] In some examples, multiple frequency characteristics may be used. For example, a first power source may have a first frequency characteristic, and a second power source may have a second frequency characteristic. The first frequency characteristic may be a higher frequency to increase radical density. The second frequency characteristic may be a lower frequency to increase kinetic energy. A combination of frequency characteristics can provide the benefits of both increased kinetic energy and increased radical density.

[0063] As previously discussed, plasma effluents of silicon-containing precursors and / or oxygen-containing precursors may be generated. In some embodiments, only plasma effluents of oxygen-containing precursors may be generated, whereas silicon-containing precursors may be plasma-free. By generating plasma effluents of one or more precursors, the directionality of the effluents may be increased, which can promote the deposition of seam-free and void-free materials. When the plasma is generated, one or more inert precursors, such as argon, helium, or nitrogen, may be provided along with the precursors to assist in distributing the precursors as well as generating plasma effluents. The plasma of the inert precursors may be a capacitively coupled plasma (CCP) plasma, a plasma formed from a remote plasma source (RPS), or a microwave plasma.

[0064] After forming the silicon and oxygen-containing material (230), the methods described herein may include the step of performing post-formation treatment. Post-formation treatment may include providing an inert precursor to a semiconductor processing chamber, generating plasma effluents of the inert precursor, and bringing the silicon and oxygen-containing material (230) into contact with the plasma effluents of the inert precursor. The inert precursor may be any inert precursor, such as argon, helium, or nitrogen, or may include such. Similar to the optional plasma of the first precursor, the second precursor, and / or the third precursor, the plasma of the inert precursor may be a capacitively coupled plasma (CCP) plasma, a plasma formed from a remote plasma source (RPS), or a microwave plasma. The plasma effluents of the inert precursor may regenerate reactive species on the surfaces of the exposed materials, which may cause continuous growth to occur. The plasma effluents of the inert precursor may densify the material by outgassing hydrogen.

[0065] The formation of the silicon and oxygen-containing material (230) (either one or both of providing an oxygen-containing precursor and bringing a substrate into contact with the oxygen-containing precursor) can be performed at various temperatures (e.g., the temperature of the substrate (205), the temperature of the processing chamber, and / or the temperature of the precursors flowing into the processing area). Exemplary temperatures for the substrate, processing chamber, and / or precursors during the operations described herein are about 50°C or more, about 75°C or more, about 100°C or more, about 125°C or more, about 150°C or more, about 175°C or more, about 200°C or more, about 250°C or more, about 300°C or more, about 350°C or more, about 400°C or more, about 425°C or more, about 450°C or more, about 475°C or more, about 500°C or more, about 525°C or more, about 550°C or more, about 575°C or more, about 600°C or more, about 625°C or more, about 650°C or more, about 675°C or more, about 700°C or more, about 725°C or more, about 750°C or more, about 775°C or more, about 800°C or more, about 825°C or more, about The temperature may be 850°C or higher, approximately 875°C or higher, approximately 900°C or higher, approximately 925°C or higher, approximately 950°C or higher, approximately 975°C or higher, approximately 1000°C or higher, or higher. In some embodiments, exemplary temperatures may be in the range of 400°C to 1000°C. In some embodiments, exemplary temperatures may be in the range of 400°C to 700°C. In some embodiments, exemplary temperatures may be in the range of 600°C to 1000°C. In some embodiments, exemplary temperatures may be in the range of 500°C to 600°C. In some embodiments, an exemplary temperature may be 550°C. By maintaining a high substrate temperature, such as approximately 400°C or higher in some embodiments, a greater number of nucleation sites may be available along the substrate (205), which can improve formation and reduce void formation by improving coverage at each location.

[0066] The formation of the silicon and oxygen-containing material (230) (either one or both of providing an oxygen-containing precursor and contacting a substrate with the oxygen-containing precursor) can be performed at various pressures within the processing chamber. The formation rate of the silicon and oxygen-containing material (230) may also vary depending on the pressure within the processing chamber. Exemplary pressures within the processing zone may be in the range of about 1 Torr to about 100 Torr. In some embodiments, pressures within the processing zone may be in the range of 2 to 20 Torr. In embodiments, the pressure may be about 20 Torr or less, e.g. about 19 Torr or less, about 18 Torr or less, about 17 Torr or less, about 16 Torr or less, about 15 Torr or less, about 14 Torr or less, about 13 Torr or less, about 12 Torr or less, about 11 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. In some embodiments, some of the processes within the processing chamber may be performed at approximately atmospheric pressure as described herein. In some embodiments, some of the processes within the processing chamber may be performed at approximately atmospheric pressure as described herein.

[0067] The formation of the silicon and oxygen-containing material (230) (either providing a silicon-containing precursor and contacting a substrate with the silicon-containing precursor, or both) can be performed at various powers and frequencies of a plasma power source. Exemplary powers may be in the range of about 100 watts to about 5000 watts. In some embodiments, the power may be in the range of 1000 watts to 3000 watts. In embodiments, the power may be about 5000 watts or less, e.g., about 4500 watts or less, about 4000 watts or less, about 3500 watts or less, about 3000 watts or less, about 2500 watts or less, about 2000 watts or less, about 1500 watts or less, about 1000 watts or less, about 500 watts or less, or less. Exemplary frequencies may be in the range of 1 kilohertz (kHz) to 100 megahertz (MHz). In some embodiments, the frequency may be in the range of 1 kHz to 30 MHz. In embodiments, the frequency is about 100 MHz or less, e.g., about 95 MHz or less, about 90 MHz or less, about 85 MHz or less, about 80 MHz or less, about 75 MHz or less, about 70 MHz or less, about 65 MHz or less, about 60 MHz or less, about 55 MHz or less, about 50 MHz or less, about 45 MHz or less, about 40 MHz or less, about 35 MHz or less, about 30 MHz or less, about 27 MHz or less, about 25 MHz or less, about 20 MHz or less, about 15 MHz or less, about 13.56 MHz or less, about 10 MHz or less, about 5 MHz or less, about 1 MHz or less, about 750 kHz or less, about 500 kHz or less, about 350 kHz or less, about 250 kHz or less, about 100 kHz or less, about 10 kHz It may be less than or equal to. In some examples, industry standards may use about 27 MHz, about 13.56 MHz, and / or about 350 kHz.

[0068] In some examples, the frequency characteristic may be 10 MHz to 15 MHz (e.g., 13.56 MHz). In these examples where the frequency characteristic is 10 MHz to 15 MHz, the power characteristic may be 1000 watts to 2000 watts. In these examples where the frequency characteristic is 10 MHz to 15 MHz, the pressure characteristic may be 8 Torr to 15 Torr. In some examples, the frequency characteristic is about 13.56 MHz, the power characteristic is about 1000 W, and the pressure characteristic is about 10 Torr. In some examples, the frequency characteristic may be 25 MHz to 30 MHz (e.g., 27 MHz). In these examples where the frequency characteristic is 25 MHz to 30 MHz, the power characteristic may be 1500 watts to 3000 watts. In these examples where the frequency characteristic is 25 MHz to 30 MHz, the pressure characteristic may be 4 Torr to 15 Torr. In some examples, the frequency characteristic is about 27 MHz, the power characteristic is about 2000 watts, and the pressure characteristic is 4 Torr to 10 Torr.

[0069] In some examples, the first frequency characteristic may be 25 MHz to 30 MHz (e.g., 27 MHz), and the second frequency characteristic may be 1 kHz to 1 MHz (e.g., 350 kHz). The first power associated with the first power source having the first frequency characteristic and the second power associated with the second power source having the second frequency characteristic may be the same or different. For example, the first power may be greater than the second power. Alternatively, the second power may be greater than the first power. In some examples, the total power (any operation of adding the first power and the second power, such as summing the powers) may be equal to 1,000 to 5,000 watts. In some examples, each power (the first power and the second power) may be equal to 1,000 to 5,000 watts.

[0070] In some examples, the final series of cycles for forming the silicon and oxygen-containing material (230) (specifically, either or both of providing a silicon-containing precursor and contacting a substrate with the silicon-containing precursor) may be performed with specific pressure, power, and frequency characteristics described herein (e.g., frequency characteristics of 10 MHz to 15 MHz, power characteristics of 1000 watts to 2000 watts, and pressure characteristics of 8 Torr to 15 Torr). For example, if the total number of cycles for forming the silicon and oxygen-containing material is 1000 cycles, the first 900 cycles may be performed without the specific pressure, power, and frequency characteristics described herein, but the last 100 cycles may be performed with the specific pressure, power, and frequency characteristics described herein. In some examples, the last 50% or less of the cycles are performed with specific pressure, power, and frequency characteristics. In some examples, the proportion of cycles performed with specific pressure, power, and frequency characteristics may be the last 50% or less of cycles, the last 45% or less of cycles, the last 40% or less of cycles, the last 35% or less of cycles, the last 30% or less of cycles, the last 25% or less of cycles, the last 20% or less of cycles, the last 15% or less of cycles, the last 10% or less of cycles, or the last 5% or less of cycles, or less. In some examples, the number of cycles performed with specific pressure, power, and frequency characteristics may be the last 1,000 or less of cycles.In some examples, the number of cycles performed with specific pressure, power, and frequency characteristics may be less than 1,000 cycles, less than 900 cycles, less than 900 cycles, less than 800 cycles, less than 700 cycles, less than 600 cycles, less than 500 cycles, less than 400 cycles, less than 300 cycles, less than 200 cycles, less than 100 cycles, less than 50 cycles, or fewer.

[0071] FIGS. 5a to 5b Figure 5 illustrates schematically the processing methods for improving seam performance according to some embodiments of the present technology. The cross-section (502) illustrates the formation of a silicon and oxygen-containing material (530) (e.g., the silicon and oxygen-containing material (230) of Figure 2) deposited into one or more materials (510) (e.g., one or more materials (210) of Figure 2). In Figure 5a, a space (540) may be seen between two sides of the silicon and oxygen-containing material (530) deposited into the feature. The silicon and oxygen-containing material (530) may be approximately uniform across the surface of one or more materials (510).

[0072] In FIG. 5b, a silicon-containing non-oxide-containing material (550) may be co-deposited to fill the space (540). The silicon-containing non-oxide-containing material (550) may not contain oxygen. The silicon-containing non-oxide-containing material (550) may be deposited via any conformal process, e.g., atomic layer deposition or chemical vapor deposition. The silicon-containing non-oxide-containing material (550) may be silicon (e.g., high-purity silicon), silicon carbide, or silicon nitride. When an etchant (e.g., a buffer oxide etchant for etching the silicon and oxygen-containing material (530)) is applied to the silicon and oxygen-containing material (530) and the silicon-containing non-oxide-containing material (550), the seam may not be visible. Atomic layer deposition of the silicon and oxygen-containing material (530) may be used to form a sufficiently compressible gap fill. Conformal deposition of silicon-containing non-oxide-containing material (550) can be used to ensure that a sufficiently compressible gap fill has high seam performance by not forming a seam.

[0073] Fig. 6 This illustrates an exemplary flowchart (600) of a method for filling features on a semiconductor substrate as described in this specification. This method may be performed by a controller that generates signals for controlling a processing chamber and other elements as illustrated above in FIGS. 2a through 2d and FIGS. 5a through 5b. This method may be performed by a controller having processors that execute commands for performing these operations.

[0074] The method may include the step of performing a process for filling a feature on a semiconductor substrate in a semiconductor processing chamber. The process may include repeatedly performing second operations (601) as described herein. For example, the second operations may be repeated for a number of cycles as described herein. Additionally, parts of the second operations may be repeated for a different number of cycles, so that a first part of the second operations may be repeated for a first number of cycles, while a second part of the second operations may be repeated for a second number of cycles. In some embodiments, the feature may feature an aspect ratio of about 10:1 or greater as described herein.

[0075] In some embodiments, the second operations may be performed at a first pressure level. In some embodiments, the first pressure level may be about 100 Torr or less, as described herein. Exemplary pressures within the processing area may be in the range of about 1 Torr to about 100 Torr. In some embodiments, pressures within the processing area may be in the range of 2 to 20 Torr. In embodiments, the pressure may be about 20 Torr or less, e.g., about 19 Torr or less, about 18 Torr or less, about 17 Torr or less, about 16 Torr or less, about 15 Torr or less, about 14 Torr or less, about 13 Torr or less, about 12 Torr or less, about 11 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. In some embodiments, some of the processes within the processing chamber may be performed at approximately atmospheric pressure as described herein.

[0076] In some embodiments, the second operations may be performed at a first temperature. In some embodiments, the first temperature may be a temperature of about 400°C or higher as described herein. In some embodiments, the second operations may be performed at a temperature of about 400°C or higher as described herein. Exemplary temperatures for the substrate, processing chamber, and / or precursors during the operations described herein may be about 400°C or higher, about 425°C or higher, about 450°C or higher, about 475°C or higher, about 500°C or higher, about 525°C or higher, about 550°C or higher, about 575°C or higher, about 600°C or higher, about 625°C or higher, about 650°C or higher, about 675°C or higher, about 700°C or higher, about 725°C or higher, about 750°C or higher, about 775°C or higher, about 800°C or higher, about 825°C or higher, about 850°C or higher, about 875°C or higher, about 900°C or higher, about 925°C or higher, about 950°C or higher, about 975°C or higher, about 1000°C or higher, or higher. In some embodiments, exemplary temperatures may be in the range of 400°C to 1000°C. In some embodiments, exemplary temperatures may be in the range of 400°C to 700°C. In some embodiments, exemplary temperatures may be in the range of 600°C to 1000°C.

[0077] The second operations may include providing (602) a silicon-containing precursor to a semiconductor processing chamber (e.g., the processing chamber (100) of FIG. 1) as described in connection with at least FIG. 2a to 2d. The silicon-containing precursor may be a first precursor as described herein.

[0078] Second operations may include contacting a substrate with a silicon-containing precursor as described herein to form a silicon-containing material (604) within a feature defined on the substrate. Forming the silicon-containing material within the feature may include forming an atomic layer of silicon on an exposed surface of the feature. The exposed surface of the feature may include two or more sides of the feature, for example, sides opposite each other.

[0079] Second operations may include purging the semiconductor processing chamber (606) as described in this specification. Purging the silicon-containing precursor from the semiconductor processing chamber may enable the use of other precursors during the process of filling features on the semiconductor substrate.

[0080] Second operations may include providing an oxygen-containing precursor (608) as described herein. In some embodiments, the oxygen-containing precursor may include plasma, primarily plasma, or exclusively plasma. In some embodiments, the oxygen-containing precursor may include gas, primarily gas, or exclusively gas.

[0081] Second operations may include contacting a substrate with an oxygen-containing precursor as described herein to form silicon and oxygen-containing materials within features defined on the substrate (610). Forming silicon and oxygen-containing materials within features may include providing oxygen to an atomic layer of silicon.

[0082] The process may also include repeatedly performing third operations (613) as described herein. For example, the third operations may be repeated for a number of cycles as described herein. Additionally, parts of the third operations may be repeated for a different number of cycles, so that a first part of the third operations may be repeated for a first number of cycles, while a second part of the second operations may be repeated for a second number of cycles. In some embodiments, the feature may feature an aspect ratio of about 10:1 or greater as described herein. The third operations may be performed in the same semiconductor processing chamber as the second operations.

[0083] In some embodiments, the third operations may be performed at a second pressure level. In some embodiments, the second pressure level may be 100 Torr or less. Exemplary pressures within the processing area may be in the range of about 1 Torr to about 100 Torr. In some embodiments, pressures within the processing area may be in the range of 2 to 20 Torr. In embodiments, the pressure may be about 20 Torr or less, e.g., about 19 Torr or less, about 18 Torr or less, about 17 Torr or less, about 16 Torr or less, about 15 Torr or less, about 14 Torr or less, about 13 Torr or less, about 12 Torr or less, about 11 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. In some embodiments, some of the processes within the processing chamber may be performed at approximately atmospheric pressure as described herein.

[0084] In some embodiments, the third operations may be performed at a second temperature. In some embodiments, the second temperature may be a temperature of about 400°C or higher as described herein. In some embodiments, the first temperature and the second temperature may be different. In some embodiments, the third operations may be performed at a temperature of about 400°C or higher as described herein. Exemplary temperatures for the substrate, processing chamber, and / or precursors during the operations described herein may be about 400°C or higher, about 425°C or higher, about 450°C or higher, about 475°C or higher, about 500°C or higher, about 525°C or higher, about 550°C or higher, about 575°C or higher, about 600°C or higher, about 625°C or higher, about 650°C or higher, about 675°C or higher, about 700°C or higher, about 725°C or higher, about 750°C or higher, about 775°C or higher, about 800°C or higher, about 825°C or higher, about 850°C or higher, about 875°C or higher, about 900°C or higher, about 925°C or higher, about 950°C or higher, about 975°C or higher, about 1000°C or higher, or higher. In some embodiments, exemplary temperatures may be in the range of 400°C to 1000°C. In some embodiments, exemplary temperatures may be in the range of 400°C to 700°C. In some embodiments, exemplary temperatures may be in the range of 600°C to 1000°C.

[0085] Third operations may include applying a silicon-containing non-oxide-containing material through a conformal process as described herein (614). For example, the silicon-containing non-oxide-containing material may be the silicon-containing non-oxide-containing material (550) of FIG. 5B. In some embodiments, the silicon-containing non-oxide-containing material (550) may contain silicon (Si), such as high-purity silicon or single-crystal silicon. In some embodiments, the silicon-containing non-oxide-containing material (550) may contain silicon carbide (SiC). In some embodiments, the silicon-containing non-oxide-containing material (550) may contain silicon nitride (SiN). In some embodiments, the oxygen-containing precursor may contain plasma, may contain mainly plasma, or may be solely plasma. In some embodiments, the oxygen-containing precursor may contain gas, may contain mainly gas, or may be solely gas.

[0086] Silicon-containing non-oxide-containing materials can be applied through any conformal process. In some examples, silicon-containing non-oxide-containing materials can be applied via chemical vapor deposition. In some examples, silicon-containing non-oxide-containing materials can be applied by atomic layer deposition. For example, atomic layer deposition of silicon-containing non-oxide-containing materials may involve the alternating provision and contact of different precursors as described herein. In some embodiments, as described herein, the second actions may precede the third actions. For example, the second actions may be performed repeatedly before the third actions are performed repeatedly. In some embodiments, the ratio of the total cycles for the second actions and the third actions may be distributed such that the second actions occur for about 90% of the total cycles, for about 80% of the total cycles, for about 70% of the total cycles, for about 60% of the total cycles, for about 50% of the total cycles, for about 40% of the total cycles, for about 30% of the total cycles, for about 20% of the total cycles, for about 10% of the total cycles, or for less than that.

[0087] In some embodiments, there may be a determination of the target thickness of the silicon and oxygen-containing material and / or the target thickness of the silicon-containing non-oxide-containing material. If the target thickness of the silicon and oxygen-containing material is not achieved, another cycle of the second operation may occur. If the target thickness of the silicon and oxygen-containing material is achieved, a cycle of the third operation may be performed. If the target thickness of the silicon-containing non-oxide-containing material is achieved, the third operation may be discontinued. Exemplary cycle numbers for the second operations may include one cycle, or more than two cycles, five cycles, ten cycles, twenty-five cycles, fifty cycles, one hundred cycles, one thousand cycles, two thousand cycles, three thousand cycles, four thousand cycles, five thousand cycles, six thousand cycles, seven thousand cycles, eight thousand cycles, nine thousand cycles, ten thousand cycles, or more. Additional exemplary ranges for the number of cycles may include 50 to 2000 cycles, 50 to 1000 cycles, and 100 to 750 cycles, 1000 to 2000 cycles, 2000 to 3000 cycles, 3000 to 4000 cycles, 4000 to 5000 cycles, 5000 to 6000 cycles, 6000 to 7000 cycles, 7000 to 8000 cycles, 8000 to 9000 cycles, 9000 to 10000 cycles, and / or any combination of these ranges. For example, some embodiments may use 6000 to 8000 cycles for a gap structure with a width of 1 μm. Exemplary ranges of target thicknesses for stopping additional cycles forming silicon and oxygen-containing materials include about 1.0 micron or less. Additional exemplary thickness ranges include about 1.0 micron or less, about 0.9 micron or less, and about 0.It may include 8 microns or less, about 0.7 microns or less, about 0.6 microns or less, about 0.5 microns or less, about 0.4 microns or less, about 0.3 microns or less, about 0.2 microns or less, about 0.1 microns or less, or less than (including any fraction of any of the numbers mentioned). Exemplary cycle numbers for the third operations may include one cycle, or more than two cycles, five cycles, ten cycles, twenty-five cycles, fifty cycles, one hundred cycles, one thousand cycles, two thousand cycles, three thousand cycles, four thousand cycles, five thousand cycles, six thousand cycles, seven thousand cycles, eight thousand cycles, nine thousand cycles, ten thousand cycles, or more. Additional exemplary ranges for the number of cycles may include 50 to 2000 cycles, 50 to 1000 cycles, and 100 to 750 cycles, 1000 to 2000 cycles, 2000 to 3000 cycles, 3000 to 4000 cycles, 4000 to 5000 cycles, 5000 to 6000 cycles, 6000 to 7000 cycles, 7000 to 8000 cycles, 8000 to 9000 cycles, 9000 to 10000 cycles, and / or any combination of these ranges. For example, some embodiments may use 6000 to 8000 cycles for a gap structure with a width of 1 μm. Exemplary ranges of target thicknesses for stopping additional cycles forming silicon-containing non-oxide-containing materials include about 1.0 micron or less. Additional exemplary thickness ranges include about 1.0 micron or less, about 0.9 micron or less, about 0.8 micron or less, about 0.7 micron or less, about 0.6 micron or less, about 0.5 micron or less, about 0.4 micron or less, about 0.It may include 3 microns or less, about 0.2 microns or less, about 0.1 microns or less, or less than (including any fraction of any of the numbers mentioned).

[0088] In the preceding description, many details have been presented for the purpose of explanation and to provide an understanding of various embodiments of the present technology. However, it will be obvious to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0089] Although various embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative configurations, and equivalents may be used without departing from the spirit of the embodiments. Additionally, to avoid unnecessarily obscuring the art, many well-known processes and elements have not been described. Accordingly, the above description should not be construed as limiting the scope of the art.

[0090] Where a range of values ​​is given, unless otherwise clearly indicated in the context, each intermediate value existing between the upper limit and the lower limit of such range of values ​​is understood to also be specifically described up to the smallest fraction of the unit of the lower limit. Any narrower range between any specified values ​​or unspecified intermediate values ​​of a specified range and any other specified or intermediate value of that specified range is included. The upper and lower limit values ​​of these sub-ranges may independently be included in or excluded from such ranges, and each range is also included in the description insofar as any specifically excluded limit value is in the specified range, whether one or both of the upper and lower limit values ​​are included in such sub-ranges or both are excluded from such sub-ranges. Where a specified range includes one or both of the limit values, ranges excluding either or both of these included limit values ​​are also included.

[0091] As used herein and in the appended claims, singular forms include plural references unless otherwise clearly indicated in the context. Thus, for example, a reference to "precursor" includes plural such precursors, and a reference to "material" includes a reference to one or more materials and their equivalents known to those skilled in the art.

[0092] Additionally, as used herein and in the following claims, the words “comprise(s),” “comprising,” “contain(s),” “containing,” “include(s),” and “including” are intended to specify the presence of the specified features, integers, components, or actions, but do not exclude the presence or addition of one or more other features, integers, components, actions, acts, or groups.

Claims

Claim 1 A method for filling a feature on a semiconductor substrate, wherein the method comprises the step of performing a process for filling a feature on the semiconductor substrate in a semiconductor processing chamber, wherein the process comprises repeatedly performing first operations, and wherein the first operations are Providing a silicon-containing precursor; Contacting the substrate with the silicon-containing precursor to form a silicon-containing material within a feature defined on the substrate; Purging the above semiconductor processing chamber; Providing an oxygen-containing precursor plasma having power characteristics and pressure characteristics based at least partially on the frequency characteristics of a plasma power source of the semiconductor processing chamber — said power characteristics, said pressure characteristics, and said frequency characteristics are configured to increase the radical density of said oxygen-containing precursor plasma and provide kinetic energy within a certain range to the ions of said oxygen-containing precursor plasma —; and A method comprising contacting the substrate with the oxygen-containing precursor to form silicon and oxygen-containing materials within features defined on the substrate. Claim 2 A method according to claim 1, wherein providing the oxygen-containing precursor having the power characteristics, the pressure characteristics, and the frequency characteristics causes a gap in the feature to be closed by causing a first side of the silicon and oxygen-containing material in the feature to bond with a second side of the silicon and oxygen-containing material in the feature. Claim 3 A method according to claim 1, wherein forming the silicon-containing material within the feature comprises forming an atomic layer of silicon on the exposed surface of the feature; and forming the silicon and oxygen-containing material within the feature comprises providing oxygen to the atomic layer of silicon. Claim 4 A method according to claim 1, wherein the frequency characteristic is within the range of about 25 MHz to 30 MHz. Claim 5 In paragraph 4, the method wherein the pressure characteristic is within a second range of about 4 Torr to about 15 Torr. Claim 6 In paragraph 5, the power characteristic is within a third range of about 1500 watts to about 3000 watts. Claim 7 A method according to claim 4, wherein providing the oxygen-containing precursor plasma comprises providing the oxygen-containing precursor plasma at a second frequency characteristic of a second plasma power source of the semiconductor processing chamber, wherein the second frequency characteristic is within a fourth range of about 1 kHz to 1 MHz. Claim 8 A method according to claim 1, wherein the feature is characterized by an aspect ratio of about 10:1 or greater. Claim 9 In claim 1, the oxygen-containing precursor comprises O2. Claim 10 A method for filling features on a semiconductor substrate, wherein the method comprises the step of performing a process for filling features on the semiconductor substrate in a semiconductor processing chamber, wherein the process comprises repeatedly performing first operations, and wherein the first operations are Providing a silicon-containing precursor; Contacting the substrate with the silicon-containing precursor to form a silicon-containing material within a feature defined on the substrate; Purging the above semiconductor processing chamber; Providing an oxygen-containing precursor; and A method comprising contacting the substrate with the oxygen-containing precursor by forming a plasma having frequency characteristics, power characteristics and pressure characteristics — wherein the power characteristics, the pressure characteristics, and the frequency characteristics are configured to provide sufficient radical density and kinetic energy, and contacting the substrate with the oxygen-containing precursor forms silicon and oxygen-containing materials within features defined on the substrate. Claim 11 In claim 10, a method wherein contacting the silicon and oxygen-containing material with the oxygen-containing precursor having the frequency characteristics, the power characteristics, and the pressure characteristics causes a first side of the silicon and oxygen-containing material in the feature to bond with a second side of the silicon and oxygen-containing material in the feature, thereby closing a gap in the feature. Claim 12 In claim 10, the above power characteristics are within the range of about 1000 watts to about 2000 watts. Claim 13 In item 10, the above pressure characteristic is within a second range of about 8 Torr to about 15 Torr, method. Claim 14 In claim 10, the above frequency characteristic is within a third range of about 10 MHz to 15 MHz. Claim 15 In claim 10, the above process is performed at a temperature of about 400°C or higher, a method. Claim 16 A method for filling features on a semiconductor substrate, wherein the method comprises the step of performing a process for filling features on the semiconductor substrate in a semiconductor processing chamber, wherein the process comprises repeatedly performing first operations at a first pressure level, and wherein the first operations are Providing a silicon-containing precursor; Contacting the substrate with the silicon-containing precursor to form a silicon-containing material within a feature defined on the substrate; Purging the above semiconductor processing chamber; Providing an oxygen-containing precursor; and Includes providing an oxygen-containing precursor; A method for filling the above features, wherein the process further comprises second operations, the second operations comprising applying a silicon-containing and non-oxide-containing material through a conformal application process. Claim 17 In paragraph 16, the conformal application process is a chemical vapor deposition process, method. Claim 18 In paragraph 16, the conformal application process is a method in which the atomic layer deposition process is the above-mentioned conformal application process. Claim 19 In claim 16, the silicon-containing and non-oxide-containing material comprises at least one of SiC, SiN, and high-purity silicon. Claim 20 In paragraph 16, the above second operations are performed in the semiconductor processing chamber.

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