Wireless circuit with low-noise peak detection

Abstract

The electronic device may include an antenna, a receiver, and a transmit line path coupling the antenna to the receiver. The peak detector may receive a radio frequency signal from the transmit line path and output a DC voltage representing the peak voltage level of the signal. The peak detector may include a pair of square law transistors having source-drain terminals coupled to the output of the peak detector. The peak detector may include a differential pair of transistors coupled between the power supply voltage and the output. The peak detector may include diode-connected transistors coupled between the source-drain terminals and the gate terminals of the square law transistors. The diode-connected transistors may allow noise current to flow along feedback loop paths from the source-drain terminals to the gate terminals of the square law transistors. This may remove noise from the output of the peak detector.

Description

Technology Field

[0001] This application claims priority to U.S. Patent Application No. 18 / 594,749, filed on March 4, 2024, the entirety of which is incorporated herein by reference.

[0002] Technology field

[0003] The present disclosure relates to electronic devices comprising electronic devices having a wireless communication circuit portion, generally. Background Technology

[0004] Electronic devices are often provided with wireless communication capabilities. Electronic devices having wireless communication capabilities have a wireless circuit section having antennas used to transmit and receive radio frequency signals.

[0005] Some radio frequency signals are received by electronic devices at relatively low signal levels. If attention is not paid, radio frequency signals at relatively low signal levels can exhibit excessive noise, which can interfere with the satisfactory reception and measurement of radio frequency signals.

[0006] The electronic device may include a wireless circuit. The wireless circuit may include an antenna, a receiver, and a radio frequency transmission line path coupling the antenna to the receiver. The wireless circuit may include a peak detector coupled to the radio frequency transmission line path. The peak detector may receive a radio frequency signal from the radio frequency transmission line path. The peak detector may output a DC voltage representing the peak voltage level of the radio frequency signals (e.g., a DC voltage proportional to the square of the peak voltage level).

[0007] The peak detector may include a pair of square law transistors coupled in parallel between the power supply voltage and ground. The pair of square law transistors may have source-drain terminals coupled to the output of the peak detector. The peak detector may include a differential pair of transistors coupled between the power supply voltage and the output. The peak detector may include diode-connected transistors coupled between the source-drain terminals and the gate terminals of the pair of square law transistors. The diode-connected transistors may allow noise current to flow unidirectionally along feedback loop paths from the source-drain terminals to the gate terminals of the pair of square law transistors. This may serve to cancel out noise from the DC voltage output by the peak detector.

[0008] One aspect of the present disclosure provides a voltage peak detector having an input terminal and a differential output. The voltage peak detector may include a first transistor having a first gate terminal coupled communically to the input terminal, a first source-drain terminal coupled to a first output terminal of the differential output, and a second source-drain terminal coupled communically to ground. The voltage peak detector may include a second transistor having a third source-drain terminal coupled to a power supply voltage and a fourth source-drain terminal coupled to a first output terminal. The voltage peak detector may include a diode-connected transistor having a fifth source-drain terminal coupled to a first output terminal and a sixth source-drain terminal coupled to a first gate terminal.

[0009] One aspect of the present disclosure provides a radio circuit. The radio circuit may include a radio frequency transmission line path configured to transmit a radio frequency signal. The radio circuit may include an analog-to-digital converter (ADC). The radio circuit may include a peak detector having an output coupled to the ADC in a communicable manner. The peak detector may include a differential pair of transistors coupled between a power supply voltage and an output. The peak detector may include a first transistor having a first gate terminal configured to receive a radio frequency signal from the radio frequency transmission line path and a first source-drain terminal coupled to the output. The peak detector may include a second transistor having a second source-drain terminal coupled to the output and the first source-drain terminal, a second gate terminal coupled to the second source-drain terminal, and a third source-drain terminal coupled to the first gate terminal.

[0010] One aspect of the present disclosure provides an electronic device. The electronic device may include an antenna. The electronic device may include a receiver configured to receive a radio frequency signal using the antenna and coupled to communicate with the antenna. The electronic device may include a circuit configured to identify a peak voltage level of a radio frequency signal. The circuit may include a pair of square law transistors coupled in parallel between a power supply voltage and ground. The circuit may include a differential pair of transistors coupled between the pair of square law transistors and the power supply voltage. The circuit may include noise-sweeping devices coupled between the source-drain terminals and the gate terminals of the pair of square law transistors, wherein the noise-sweeping devices are configured to transfer current in a unidirectional manner from the source-drain terminals of the pair of square law transistors to the gate terminals of the pair of square law transistors. Brief explanation of the drawing

[0011] FIG. 1 is a drawing of an exemplary electronic device having a wireless circuit portion according to some embodiments. FIG. 2 is a diagram of an exemplary wireless circuit section having a radio frequency transmission line path according to some embodiments. FIG. 3 is a diagram of an exemplary wireless circuit having a peak detector coupled to a radio frequency transmission line path according to some embodiments. FIG. 4 is a flowchart of exemplary operations related to performing wireless communications using a wireless circuit having a peak detector coupled to a radio frequency transmission line path according to some embodiments. FIG. 5 is a circuit diagram of an exemplary peak detector having noise-canceling transistors according to some embodiments. FIG. 6 is a plot of noise as a function of input power showing how an exemplary peak detector having noise-canceling transistors according to some embodiments can minimize noise in signal peak measurements. Specific details for implementing the invention

[0012] The electronic device (10) of FIG. 1 may be a computing device such as a laptop computer or a desktop computer, a computer monitor including an embedded computer, a tablet computer, a cellular phone, a media player, or other handheld or portable electronic device, such as a wristwatch device, a pendant device, a headphone or earpiece device, a device embedded in glasses, goggles, a helmet, or other equipment worn on a user's head (e.g., a head-mounted display device), or other wearable or small device, a television, a computer display not including an embedded computer, a gaming device, a navigation device, an embedded system such as a system in which electronic equipment equipped with a display is installed in a kiosk or a car, a wireless internet-connected voice control speaker, a home entertainment device, a remote control device, a gaming controller, a peripheral user input device, a wireless base station or an access point, equipment that implements the functions of two or more of these devices, or other electronic equipment.

[0013] As illustrated in the functional block diagram of FIG. 1, the device (10) may include components located on or within an electronic device housing, such as a housing (12). The housing (12), which may sometimes be referred to as a case, may be formed from plastic, glass, ceramic, fiber composites, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or a combination of these materials. In some embodiments, parts or the whole of the housing (12) may be formed from a dielectric or other low-conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other embodiments, at least parts of the housing (12) or the structures constituting the housing (12) may be formed from metal elements.

[0014] The device (10) may include a control circuit (14). The control circuit (14) may include a storage such as a storage circuit (16). The storage circuit (16) may include a hard disk drive storage, non-volatile memory (e.g., flash memory, or other electrically programmable read-only memory configured to form a solid-state drive), volatile memory (e.g., static or dynamic random access memory), etc. The storage circuit (16) may include a storage and / or removable storage medium integrated within the device (10).

[0015] The control circuit (14) may include a processing circuit such as the processing circuit (18). The processing circuit (18) may be used to control the operation of the device (10). The processing circuit (18) may include one or more processors, such as microprocessors, microcontrollers, digital signal processors, host processors, baseband processor integrated circuits, application integrated circuits, central processing units (CPUs), etc. The control circuit (14) may be configured to perform operations on the device (10) using hardware (e.g., dedicated hardware or circuits), firmware, and / or software. Software code for performing operations on the device (10) may be stored on the storage circuit (16) (e.g., the storage circuit (16) may include non-transient (tangible) computer-readable storage media for storing software code). Software code may sometimes be referred to as program instructions, software, data, instructions, or code. The software code stored on the storage circuit (16) can be executed by the processing circuit (18).

[0016] The control circuit (14) can be used to execute software on the device (10), such as satellite navigation applications, internet browsing applications, VOIP (voice-over-internet-protocol) phone call applications, email applications, media playback applications, operating system functions, etc. To support interactions with external equipment, the control circuit (14) can be used to implement communication protocols. Communication protocols that can be implemented using the control circuit (14) include Internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols - sometimes referred to as Wi-Fi®), Bluetooth® protocols or other short-range wireless communication link protocols such as other wireless personal area network (WPAN) protocols, IEEE 802.11ad protocols (e.g., ultra-wideband protocols), cellular phone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G protocols, etc.), antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols or Includes other desired range detection protocols for signals transmitted at millimeter and centimeter frequency ranges), or any other desired communication protocols. Each communication protocol may be associated with a corresponding radio access technology (RAT) that specifies the physical connection methodology used to implement the protocol.

[0017] The device (10) may include an input-output circuit section (20). The input-output circuit section (20) may include input-output devices (22). The input-output devices (22) may be used to supply data to the device (10) and to provide data from the device (10) to external devices. The input-output devices (22) may include user interface devices, data port devices, and other input-output components. For example, input / output devices (22) may include light-emitting components such as touch sensors, displays (e.g., touch-sensitive and / or force-sensitive displays), displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touch pads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jacks and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, headphones, displays, pointing devices such as trackpads, mice and joysticks, and other input / output devices may be coupled to the device (10) using wired or wireless connections (e.g., some of the input / output devices (22) may be peripherals coupled to the main processing unit or other parts of the device (10) via wired or wireless links).

[0018] The input-output circuit section (20) may include a wireless circuit section (24) for supporting wireless communications. The wireless circuit section (24) (sometimes referred to herein as the wireless communication circuit section (24)) may include one or more antennas. The wireless circuit section (24) may also include a baseband processor circuit section, a transceiver circuit section, an amplifier circuit section, a filter circuit section, a switching circuit section, radio frequency transmission lines, and / or any other circuit section for transmitting and / or receiving radio frequency signals using the antenna(s).

[0019] The wireless circuit section (24) can transmit and / or receive radio frequency signals within a corresponding frequency band in radio frequencies (sometimes referred to in this specification as a communication band or simply "band"). The frequency bands handled by the wireless circuit section (24) are wireless local area network (WLAN) frequency bands (e.g., Wi-Fi® (IEEE 802.11) or other WLAN communication bands), such as a 2.4 GHz WLAN band (e.g., 2400 to 2480 MHz), a 5 GHz WLAN band (e.g., 5180 to 5825 MHz), a Wi-Fi® 6E band (e.g., 5925 to 7125 MHz), and / or other Wi-Fi® bands (e.g., 1875 to 5160 MHz), wireless personal area network (WPAN) frequency bands, such as a 2.4 GHz Bluetooth® band or other WPAN communication bands, cellular phone frequency bands (e.g., bands of about 600 MHz to about 5 GHz, 3G bands, 4G LTE). Bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands from 20 to 60 GHz, etc.), other centimeter or millimeter wave frequency bands from 10 to 300 GHz, near-field communication frequency bands (e.g., 13.(at 56 MHz), satellite navigation frequency bands (e.g., Global Positioning System (GPS) L1 band (e.g., at 1575 MHz), L2 band (e.g., at 1228 MHz), L3 band (e.g., at 1381 MHz), L4 band (e.g., at 1380 MHz), and / or L5 band (e.g., at 1176 MHz), Global Navigation Satellite System (GLONASS) band, BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) frequency bands operating under the IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols, communication bands under the 3GPP radio communication standard family, communication bands under the IEEE 802.XX standard family, satellite communication Bands, such as L-band, S-band (e.g., 2 to 4 GHz), C-band (e.g., 4 to 8 GHz), X-band, Ku-band (e.g., 12 to 18 GHz), Ka-band (e.g., 26 to 40 GHz), etc. (e.g., to support two-way wireless communications via satellites orbiting the Earth), industrial, scientific, and medical (ISM) bands, such as an ISM band of about 900 MHz to 950 MHz or other ISM bands of less than or greater than 1 GHz, one or more unlicensed bands, one or more bands reserved for emergency and / or public services, and / or any other desired frequency bands of interest may be included.

[0020] FIG. 2 is a drawing illustrating exemplary components within a wireless circuit section (24). As illustrated in FIG. 2, the wireless circuit section (24) may include one or more processors such as processor(s) (26), a radio frequency (RF) transceiver circuit section such as a radio frequency transceiver (28), a radio frequency front-end circuit section such as a radio frequency front-end module (FEM) (40), and antenna(s) (42). The processor (26) may be a baseband processor, an application processor, a digital signal processor, a microcontroller, a microprocessor, a central processing unit (CPU), a programmable device, a combination of these circuits, and / or one or more processors within the processing circuit section (18) ( FIG. 1). The processor (26) may be configured to generate digital (transmit or baseband) signals. The processor (26) can be coupled to the transceiver (28) via a path (34) (sometimes referred to as a baseband path). The transceiver (28) can be coupled to the antenna (42) via a radio frequency transmission line path (36). A radio frequency front-end module (40) can be interposed on the radio frequency transmission line path (36) between the transceiver (28) and the antenna (42).

[0021] The wireless circuit section (24) may include one or more antennas, such as the antenna (42). The antenna (42) may be formed using any desired antenna structure. For example, the antenna (42) may be an antenna having a resonant element formed from a loop antenna structure, a patch antenna structure, an inverted-F antenna structure, a slot antenna structure, a planar inverted-F antenna structure, a helical antenna structure, a monopole antenna, a dipole, a hybrid of these designs, etc. Two or more antennas (42) may be arranged into one or more phase antenna arrays (e.g., for transmitting radio frequency signals at millimeter wave frequencies). Parasitic elements may be included within the antenna (42) to adjust antenna performance. The antenna (42) may be provided with a conductive cavity that backs the antenna resonant element of the antenna (42) (e.g., the antenna (42) may be a cavity-backed antenna, such as a cavity-backed slot antenna).

[0022] In the example of FIG. 2, the wireless circuit section (24) is illustrated for clarity as comprising only a single processor (26), a single transceiver (28), a single front-end module (40), and a single antenna (42). Generally, the wireless circuit section (24) may include any desired number of processors (26), any desired number of transceivers (28), any desired number of front-end modules (40), and any desired number of antennas (42). Each processor (26) may be coupled to one or more transceivers (28) via their respective paths (34). Each transceiver (28) may include a transmitter circuit configured to output uplink signals to the antenna (42), a receiver circuit configured to receive downlink signals from the antenna (42), and may be coupled to one or more antennas (42) via their respective radio frequency transmission line paths (36). Each front-end module (40) may be placed on each radio frequency transmission line path (36). If desired, two or more front-end modules (40) may be placed on the same radio frequency transmission line path (36). If desired, one or more of the radio frequency transmission line paths (36) within the wireless circuit section (24) may be implemented without any front-end module interposed therein.

[0023] The front end module (FEM) (40) may include a radio frequency front end circuit that operates on radio frequency signals transmitted (transmitted and / or received) through a radio frequency transmission line path (36). The front-end module comprises, for example, a radio frequency filter circuit section (44) (e.g., low-pass filters, high-pass filters, notch filters, band-pass filters, multiplexing circuit section, duplexer circuit section, diplexer circuit section, triplexer circuit section, etc.), a switching circuit section (46) (e.g., one or more radio frequency switches), a radio frequency amplifier circuit section (48) (e.g., one or more power amplifiers and one or more low-noise amplifiers), an impedance matching circuit section (e.g., a circuit section that helps match the impedance of the antenna (42) to the impedance of the radio frequency transmission line (36), an antenna tuning circuit section (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of the antenna (42), a radio frequency coupler circuit section, a charge pump circuit section, a power management circuit section, a digital control and interface circuit section, and / or radio frequency signals transmitted and / or received by the antenna (42). It may include front-end module (FEM) components such as any other desired circuit section that are in operation. Each of the front-end module components may be mounted on a common (shared) board, such as a rigid printed circuit board or a flexible printed circuit board. If desired, various front-end module components may also be integrated into a single integrated circuit chip.

[0024] The filter circuit (44), switching circuit (46), amplifier circuit (48), and other circuits may be placed on the radio frequency transmission line path (36), integrated into the FEM (40), or integrated into the antenna (42) (e.g., to support antenna tuning, to support operation in desired frequency bands, etc.). These components, sometimes referred to herein as antenna tuning components, may be adjusted (e.g., using the control circuit (14)) to adjust the frequency response and radio performance of the antenna (42) over time.

[0025] A radio frequency transmission line path (36) may be coupled to an antenna feed of an antenna (42). For example, the antenna feed may include a positive antenna feed terminal and a ground antenna feed terminal. The radio frequency transmission line path (36) may have a positive transmission line signal path coupled to a positive antenna feed terminal in the antenna (42). The radio frequency transmission line path (36) may have a ground transmission line signal path coupled to a ground antenna feed terminal in the antenna (42). These examples are exemplary, and generally, antennas (42) may be fed using any desired antenna feeding scheme. If desired, the antenna (42) may have multiple antenna feeds coupled to one or more radio frequency transmission line paths (36).

[0026] A radio frequency transmission line path (36) may include transmission lines used to route radio frequency antenna signals within a device (10) (Fig. 1). Transmission lines within the device (10) may include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from a combination of these types of transmission lines, etc. Transmission lines within the device (10), such as transmission lines within the radio frequency transmission line path (36), may be integrated into rigid and / or flexible printed circuit boards. In one suitable arrangement, a radio frequency transmission line path, such as the radio frequency transmission line path (36), may include a transmission line conductor integrated within a laminated multilayer structure (e.g., a layer of a conductive material such as copper and a dielectric material such as resin laminated together without an intermediate adhesive). Multilayer laminated structures can be folded or bent into multiple dimensions (e.g., two or three dimensions) if desired, and can maintain the folded or bent shape after bending (e.g., multilayer laminated structures can be folded into a specific three-dimensional shape to route around other device components and can be rigid enough to maintain their shape after folding without being held in place by reinforcing materials or other structures). All of the multiple layers of the laminated structures can be batch laminated together (e.g., in a single pressurization process) without adhesive (in contrast to performing multiple pressurization processes to laminate multiple layers together using adhesive).

[0027] The transceiver (28) may include a wireless local area network transceiver circuit for handling WLAN communication bands, a wireless personal area network transceiver circuit for handling 2.4 GHz Bluetooth® bands or other WPAN communication bands, a cellular phone transceiver circuit for handling cellular phone bands, a near-field communications (NFC) transceiver circuit for handling near-field communication bands, a satellite navigation receiver circuit for handling satellite navigation bands, an ultra-wideband (UWB) transceiver circuit for handling communications using IEEE 802.15.4 protocol and / or other ultra-wideband communication protocols, and / or any other desired radio frequency transceiver circuit for covering any other desired communication bands of interest.

[0028] When performing wireless transmission, the processor (26) may provide digital signals to the transceiver (28) via the path (34). The transceiver (28) may additionally include a circuit for converting baseband signals received from the processor (26) into corresponding intermediate frequency or radio frequency signals. For example, the transceiver circuit (28) may include a mixer circuit (50) for upconverting (or modulating) the baseband signals to an intermediate frequency or radio frequency prior to transmission via the antenna (42). The transceiver (28) may also include a digital-to-analog converter (DAC) and / or analog-to-digital converter (ADC) circuit for converting signals between the digital domain and the analog domain. The transceiver (28) may include a transmitter component that transmits radio frequency signals via the antenna (42) via the radio frequency transmission line path (36) and the front-end module (40). The antenna (42) can radiate radio frequency signals into free space and transmit radio frequency signals to external wireless equipment.

[0029] In performing wireless reception, the antenna (42) can receive radio frequency signals from external wireless equipment. The received radio frequency signals can be transmitted to the transceiver (28) via the radio frequency transmission line path (36) and the front-end module (40). The transceiver (28) may include a circuit for converting the received radio frequency signals into corresponding intermediate frequency or baseband signals. For example, the transceiver (28) may use a mixer circuit (50) to downconvert (or demodulate) the received radio frequency signals to baseband frequencies before transmitting the received signals to the processor (26) via the path (34). The mixer circuit (50) may include a local oscillator circuit, such as a local oscillator (LO) circuit (52). The local oscillator circuit section (52) can generate oscillator signals that the mixer circuit section (50) uses to modulate transmission signals from baseband frequency to radio frequency and / or demodulate reception signals from radio frequency to baseband frequency.

[0030] The term “transmit radio frequency signals” as used herein means the transmission and / or reception of radio frequency signals (e.g., for performing unidirectional and / or bidirectional wireless communications with external devices). Likewise, the term “transmit radio data” as used herein means the transmission and / or reception of radio data using radio frequency signals (e.g., when radio data is modulated by one or more carrier waves of radio frequency signals). Antenna(s) (42) may transmit radio frequency signals by radiating radio frequency signals into free space (or into free space through interposed device structures such as dielectric cover layers). Antenna(s) (42) may additionally or alternatively receive radio frequency signals from free space (or from free space through interposed device structures such as dielectric cover layers). The transmission and reception of radio frequency signals by the antenna(s) (42) each involve the excitation or resonance of antenna currents on the antenna resonance element within the antenna(s) by radio frequency signals within the operating frequency band(s) of the antenna(s).

[0031] In practice, it may be desirable to be able to measure the levels of signal peaks in radio frequency signals transmitted through the radio frequency transmission line path (36) (e.g., between antenna(s) (42) and transceiver (28)). The wireless circuit (24) may include a peak detector that measures the levels of signal peaks in the radio frequency signals transmitted through the radio frequency transmission line path (36). FIG. 3 is a diagram showing an example of how the wireless circuit (24) may include a peak detector.

[0032] As illustrated in FIG. 3, the wireless circuit section (24) may include a signal peak detector such as a peak detector (54) and a peak detector ADC such as an ADC (56). The peak detector (54) may have an input terminal coupled to a radio frequency transmission line path (36) through a signal path (58). The signal path (58) may be a single-ended signal path, and the input of the peak detector (54) may be a single-ended input receiving single-ended signals from the radio frequency transmission line path (36) through the signal path (58). The signal path (58) may be coupled to the radio frequency transmission line path (36) by, for example, a radio frequency coupler, a signal splitter, a radio frequency transformer, and / or other circuit sections.

[0033] The peak detector (54) may have a differential output having output terminals of a differential pair coupled to the differential input of the ADC (56) through a differential signal path (60). The differential signal path (60) may include coupled lines of a differential pair, such as a first (positive) signal line (60P) and a second (negative) signal line (60N). The output terminals of the differential pair of the peak detector (54) may include a first output terminal coupled to the signal line (60P) and a second output terminal coupled to the signal line (60N). The ADC (56) may have a digital output coupled to a processor (26) (Fig. 3), a processing circuit (18) (Fig. 1), and / or another circuit within the device (10).

[0034] The radio frequency transmission line path (36) can transmit radio frequency signals between the mixer circuit (50) (Fig. 2) and the antenna(s) (42). The inputs of the signal path (58) and the peak detector (54) can be coupled to the radio frequency transmission line path (36) (e.g., at any desired location between the antenna(s) (42) and the mixer circuit (50)). The signal path (58), the peak detector (54), and the ADC (56) can be integrated into the transceiver circuit (28) or the front-end module (40), for example, or can be separated from the transceiver circuit (28) and the front-end module (40) of Fig. 2. While the radio frequency transmission line path (36) transmits radio frequency signals, the signal path (58) may extract some of the radio frequency signals (e.g., some of the power of the radio frequency signals) from the radio frequency transmission line path (36) and tap or couple them onto the input of the peak detector (54). The signal path (58) transmits the radio frequency signals to the input of the peak detector (54) as single-ended signals.

[0035] The peak detector (54) can perform measurements of the peak levels (e.g., amplitudes) of radio frequency signals received through the signal path (58). This may include, for example, measuring the peak current levels (e.g., peak current magnitude or current amplitude) and / or the peak voltage levels (e.g., peak voltage magnitude or voltage amplitude). Embodiments in which the peak detector (54) measures the peak voltage levels (e.g., voltage amplitudes) of radio frequency signals on the radio frequency transmission line path (36) are described herein as examples. Accordingly, the peak detector (54) is sometimes referred to herein as the voltage peak detector (54), the peak voltage magnitude detector (54), or the voltage amplitude detector (54).

[0036] The peak detector (54) can output a differential signal on the signal lines (60P and 60N) that identifies the peak level of radio frequency signals on the radio frequency transmission line path (36). The peak detector (54) can output a DC voltage having a magnitude based, for example, on the signal lines (60P and 60N). The ADC (56) can receive the DC voltage output by the peak detector (54) through the signal lines (60N and 60P). The ADC (56) can convert the DC voltage into a digital signal and output the digital signal as voltage level information (VLI). Voltage level information (VLI) may be a digital code identifying, for example, the magnitude of the DC voltage output by the peak detector (54) and / or the peak voltage level of radio frequency signals on the radio frequency transmission line path (36) (as detected, estimated, measured, and / or output by the peak detector (54)). The processing circuit within the device (10) can perform any desired operations based on voltage level information (VLI) (e.g., adjusting one or more tuning components of the antenna(s) (42), adjusting the impedance matching circuit, switching the antenna to an active or deactivated state, adjusting the transmission power level of the antenna, enabling or disabling the transceiver or antenna, turning one or more components of the device (10) on or off, adjusting the power consumption mode of the device (10), performing thermal mitigation operations, identifying and / or mitigating one or more jammer signals that cause interference and / or noise on the radio frequency transmission line path (36), providing the voltage level information (VLI) as an input to one or more software applications, etc.).

[0037] Some types of radio frequency signals are received at relatively low signal levels by antenna(s) (42) within the device (10). Such radio frequency signals may include, for example, radio frequency signals transmitted by one or more satellites in the satellite navigation band and / or satellite communication band. These radio frequency signals are received by the device (10) at low signal levels because the corresponding transmitter is located relatively far from the device (10) (e.g., on one or more satellites in space), causing the radio frequency signals to experience significant propagation / path loss in reaching the device (10). The transmitter may also have a limited output power level for transmitting the radio frequency signals. In some embodiments, the transmitter may be a sensor node of a wireless sensor network. Sensor nodes within a wireless sensor network may be deployed in remote and / or harsh environments where communication links experience significant attenuation. In some embodiments, the transmitter transmits radio frequency signals at relatively high frequencies (e.g., millimeter wave frequencies, centimeter wave frequencies, sub-THz frequencies, etc.) that experience significant signal attenuation.

[0038] In these types of situations, it may be difficult for the wireless circuit (24) to distinguish the signal of interest in the radio frequency signals (e.g., signal components carrying wireless data such as those transmitted by the corresponding transmitter) from noise. The noise may include thermal noise, electromagnetic noise, and / or other types of noise. At least some of the noise may be generated, for example, by one or more jammer signals present in the device (10). Such jammer signals may be generated by electronic components within the device (10), other antennas (42) within the device (10), transceiver circuits within the device (10), nearby devices, thermal noise, and / or other sources of electromagnetic interference. If attention is not paid, the low signal level of the signal of interest in the radio frequency signals may cause the noise to dominate the signal peak measurements performed by the peak detector (54). This may make it difficult for the peak detector (54) to perform accurate signal peak measurements. If desired, the peak detector (54) may include one or more noise-canceling transistors that help mitigate noise in radio frequency signals, which allows the peak detector (54) to perform accurate peak level measurements even when the signal of interest in the radio frequency signals is at a low signal level.

[0039] FIG. 4 is a flowchart of operations related to performing peak level measurements using a peak detector (54). In operation (62), the antenna (42) may begin receiving radio frequency signals. The radio frequency signals may be transmitted, for example, in a satellite band (e.g., a satellite navigation band or a satellite communication band). Thus, the radio frequency signals may contain signals of interest at a relatively low signal level. The radio frequency transmission line path (36) may transmit the radio frequency signals received by the antenna (42) to a receiver within the transceiver (28) (Fig. 2).

[0040] In operation (64), the transceiver (28) may begin receiving radio frequency signals through the radio frequency transmission line path (36). The transceiver (28) may begin downconverting the radio frequency signals into baseband signals (e.g., directly, or through a first downconversion to an intermediate frequency and a second downconversion to the baseband). The transceiver (28) may begin attempting to decode / demodulate radio data from the baseband signals. The radio circuit (24) may continue to perform operations (62 and 64) simultaneously with the remaining operations of FIG. 4.

[0041] In operation (66), the signal path (58) may transmit a portion of the radio frequency signals on the radio frequency transmission line path (36) to the peak detector (54). The peak detector (54) may measure the peak voltage level of the radio frequency signals (e.g., may collect, generate, output, calculate, estimate, and / or compute a peak voltage level value (measurement) corresponding to or identifying the peak voltage level of the radio frequency signals on the radio frequency transmission line path (36)). The peak detector (54) may generate a DC voltage across the signal lines (60P and 60N) having a magnitude that is proportional to or otherwise identifies the peak voltage level of the radio frequency signals on the radio frequency transmission line path (36) (e.g., the magnitude may be proportional to the square of the peak voltage level). The peak detector (54) may include one or more noise-canceling transistors that cancel out noise from radio frequency signals, which helps ensure the accuracy of the peak voltage level value output by the peak detector (54).

[0042] In operation (68), the ADC (56) can convert the voltage peak level measurement generated by the peak detector (54) into a corresponding digital value (e.g., voltage level information (VLI) of FIG. 3). The ADC (56) can convert, for example, the DC voltage across the signal lines (60P and 60N) into a corresponding digital code that identifies the magnitude of the DC voltage. The ADC (56) can transmit the digital value to another circuit for further processing.

[0043] In operation (70), one or more processors within the device (10) (e.g., processor (26) of FIG. 2 and / or processing circuit (18) of FIG. 1) may identify the peak voltage level of radio frequency signals based on a digital value by computing, calculating, estimating, or otherwise identifying (e.g., proportional to the square of the DC voltage level identified by the digital value). One or more processors within the device (10) may perform any desired operations based on the peak voltage level of the radio frequency signals (e.g., based on the digital value output by the ADC (56), and thus based on the measurement performed by the peak detector (54). As an example, one or more processors may identify a jammer signal in the radio frequency signals and take appropriate measures to mitigate the jammer signal based on the digital value output by the ADC (56). One or more processors may identify that a jammer signal is present, for example, when the peak voltage level of the radio frequency signals on the radio frequency transmission path exceeds / exceeds a threshold peak voltage level. One or more processors may attempt to mitigate a jammer signal by adjusting one or more tuning components of the antenna(s) (42), adjusting the impedance matching circuit, switching the antenna (42) to an active or deactivated state, adjusting the transmission power level of one or more of the antennas (42), enabling or disabling the transceiver or antenna within the device (10), turning one or more components of the device (10) on or off, adjusting the power consumption mode of the device (10), performing thermal mitigation operations, and / or using any other methods. Once the jammer signal is identified and mitigated, the transceiver (28) may be able to more clearly identify the signal of interest in the received radio frequency signals and successfully decode radio data from the signal of interest.As other examples, one or more processors can detect the signal strength of radio frequency signals based on digital values, perform impedance measurements (e.g., S-parameter measurements) based on digital values, adjust one or more amplifiers, impedance matching circuits, and / or antenna tuning circuits on the radio frequency transmission line path based on digital values, switch different antennas to an active or deactivated state based on digital values, and so on. These examples are exemplary, and generally, the device (10) can perform any desired operations based on the measured peak voltage level.

[0044] FIG. 5 is a circuit diagram of a peak detector (54). As illustrated in FIG. 5, the peak detector (54) may include a differential signal path (80) comprising a first (positive) signal line (80P) and a second (negative) signal line (80N) coupled in parallel between a reference voltage, such as a power supply voltage (VDD) and ground (82). The peak detector (54) may have an input terminal (72) (e.g., a single-ended input terminal) coupled to the signal path (58) (Fig. 3). The input terminal (72) may also be coupled to a circuit node (76) within the peak detector (54). If desired, the peak detector (54) may include a capacitor (74) (e.g., a coupling capacitor) coupled in series between the input terminal (72) and the circuit node (76).

[0045] The peak detector (54) may have a differential output (104) including a first (positive) output terminal (104P) coupled to a signal line (80P) and a second (negative) output terminal (104N) coupled to a signal line (80N). The output terminal (104P) may be coupled to a signal line (60P), and the output terminal (104N) may be coupled to a signal line (60N) of FIG. 3.

[0046] The peak detector (54) may include a differential pair of transistors (90), comprising a first transistor (90P) placed on a signal line (80P) and a second transistor (90N) placed on a signal line (80N). The differential pair of transistors (90) may perform single-ended to differential signal conversion for the peak detector (54). The transistor (90P) has a first source-drain terminal that is communically coupled to the power supply voltage (VDD) through a first segment of the signal line (80P) and a second source-drain terminal that is communically coupled to ground (82) through a second segment of the signal line (80P). The second source-drain terminal of the transistor (90P) is also coupled to an output terminal (104P). The gate terminal of the transistor (90P) is coupled to a circuit node (88).

[0047] Likewise, the transistor (90N) has a first source-drain terminal that is communically coupled to the power supply voltage (VDD) through a first segment of the signal line (80N), and a second source-drain terminal that is communically coupled to ground (82) through a second segment of the signal line (80N). The second source-drain terminal of the transistor (90N) is also coupled to the output terminal (104N). The gate terminal of the transistor (90N) is coupled to the circuit node (88). The peak detector (54) may include a resistor (92) coupled in series between the circuit node (88) and the output terminal (104P). The peak detector (54) may also include a resistor (94) coupled in series between the circuit node (88) and the output terminal (104N).

[0048] The peak detector (54) may include a pair of square law transistors such as transistors (78), comprising a first transistor (78P) placed on the signal line (80P) and a second transistor (78N) placed on the signal line (80N). The transistor (78P) has a first source-drain terminal coupled to an output terminal (104P) and a second source-drain terminal of the transistor (90P) (for example, the first source-drain terminal of the transistor (78P) may be communicably coupled to the power supply voltage (VDD) through the transistor (90P)). The transistor (78P) has a second source-drain terminal coupled to ground (82) (for example, through the second segment of the signal line (80P)). The gate terminal of the transistor (78P) can be coupled to the circuit node (76) and can be coupled to the input terminal (72) communically through the circuit node (76) and the capacitor (74).

[0049] The transistor (78N) has a first source-drain terminal coupled to the output terminal (104N) and the second source-drain terminal of the transistor (90N) (for example, the first source-drain terminal of the transistor (78N) can be communicably coupled to the power supply voltage (VDD) through the transistor (90N). The transistor (78N) has a second source-drain terminal coupled to ground (82) (for example, through the second segment of the signal line (80N)). The gate terminal of the transistor (78N) can be coupled to the circuit node (98). The transistors (78N and 78P) are square law devices and can perform a square function on signals passing through the transistors along the signal lines (80P and 80N).

[0050] The peak detector (54) may include a bias transistor (102) and a pair of bias resistors (100), including a bias resistor (100P) and a bias resistor (100N). The bias transistor (102) may have a first source-drain terminal coupled to its gate terminal. The bias transistor (102) may have a second source-drain terminal coupled to ground (82). The bias resistor (100P) may be coupled in series between the first source-drain terminal of the bias transistor (102) (or equivalently the gate terminal of the bias transistor (102)) and the circuit node (76) (or equivalently the gate terminal of the transistor (78P)). The bias resistor (100N) can be coupled in series between the first source-drain terminal of the bias transistor (102) (or equivalently the gate terminal of the bias transistor (102)) and the circuit node (98) (or equivalently the gate terminal of the transistor (78N)). The bias transistor (102) can bias the gate terminals of the transistors (78P and 78N) during peak detection.

[0051] To help mitigate noise in radio frequency signals measured by the peak detector (54), the peak detector (54) may include a pair of noise-sweeping transistors (96), comprising a first noise-sweeping transistor (96P) and a second noise-sweeping transistor (96N). The noise-sweeping transistor (96P) is a diode-connected transistor (e.g., having a source-drain terminal connected to its gate terminal) and is coupled between the output terminal (104P) and the circuit node (76). Thus, the noise-sweeping transistor (96P) is sometimes referred to herein as a diode-connected transistor (96P). The noise-sweeping transistor (96P) has a first source-drain terminal coupled to the output terminal (104P) (or equivalently the first source-drain terminal of the transistor (78P) and the second source-drain terminal of the transistor (90P)). The first source-drain terminal of the noise-erasing transistor (96P), the output terminal (104P), the second source-drain terminal of the transistor (90P), and the first source-drain terminal of the transistor (78P) are coupled to the gate terminal of the noise-erasing transistor (96P). The noise-erasing transistor (96P) has a second source-drain terminal coupled to the circuit node (76) (or equivalently the gate terminal of the transistor (78P)). Current through the diode-connected noise-erasing transistor (96P) may flow in a single direction from the first source-drain terminal of the noise-erasing transistor (96P) to the second source-drain terminal of the noise-erasing transistor (96P). Current may not flow in the opposite direction from the second source-drain terminal of the noise-erasing transistor (96P) to the first source-drain terminal.

[0052] The noise-erasing transistor (96N) is also a diode-connected transistor and is coupled between the output terminal (104N) and the circuit node (98). Therefore, the noise-erasing transistor (96N) is sometimes referred to herein as a diode-connected transistor (96N). The noise-erasing transistor (96N) has a first source-drain terminal coupled to the output terminal (104N) (or equivalently the first source-drain terminal of the transistor (78N) and the second source-drain terminal of the transistor (90N). The first source-drain terminal of the noise-erasing transistor (96N), the output terminal (104N), the second source-drain terminal of the transistor (90N), and the first source-drain terminal of the transistor (78N) are coupled to the gate terminal of the noise-erasing transistor (96N). The noise-erasing transistor (96N) has a second source-drain terminal coupled to the circuit node (98) (or equivalently the gate terminal of the transistor (78N)). Current through the diode-connected noise-erasing transistor (96P) can flow in a single direction from the first source-drain terminal of the noise-erasing transistor (96N) to the second source-drain terminal of the noise-erasing transistor (96N). Current does not flow in the opposite direction from the second source-drain terminal of the noise-erasing transistor (96N) to the first source-drain terminal.

[0053] Embodiments in which the peak detector (54) includes noise-sweeping transistors (96P and 96N) are described herein as examples. Generally, the noise-sweeping transistors (96P and 96N) can be replaced with any desired type of noise-sweeping device. As another example, the noise-sweeping transistor (96P) can be replaced with a PN junction diode coupled between the output terminal (104P) and the circuit node (76), and / or the noise-sweeping transistor (96N) can be replaced with a PN junction diode coupled between the output terminal (104N) and the circuit node (98).

[0054] The transistors (90P, 90N, 78P, 78N, 96P, 96N, and 102) may be implemented using any desired transistor technology. The transistors (90P, 90N, 78P, 78N, 96P, 96N, and / or 102) may include, for example, n-channel transistors such as n-type metal-oxide-semiconductor (NMOS) devices, p-channel transistors such as p-type metal-oxide-semiconductor (PMOS) devices, complementary metal-oxide-semiconductor (CMOS) devices, etc. The transistors (90P, 90N, 78P, 78N, 96P, 96N, and 102) each have source, drain, and gate terminals. When referring to the current-conducting terminals of metal-oxide-semiconductor transistors, the terms "source" and "drain" are sometimes used interchangeably. Thus, the source and drain terminals are sometimes referred to as "source-drain" terminals (e.g., the transistor has a gate terminal, a first source-drain terminal, and a second source-drain terminal).

[0055] During signal peak measurement (e.g., during processing operation (66) of FIG. 4), a portion of the radio frequency signals on the radio frequency transmission line path (36) (Fig. 3) is received as an input signal (RFIN) at the input terminal (72). The input signal (RFIN) is a single-ended signal. The peak detector (54) can measure the peak voltage level of the input signal (RFIN), and thus the radio frequency signals on the radio frequency transmission line path (36). The peak detector (54) can output a DC voltage (VOUT) representing the measured peak voltage level of the input signal (RFIN) across the output terminals (104P and 104N). The voltage (VOUT) is sometimes also referred to herein as the output signal (VOUT).

[0056] The magnitude of the output signal (VOUT) (e.g., the DC voltage across the output terminals (104P and 104N)) is given by the difference between the voltage (VOUTP) on the output terminal (104P) and the voltage (VOUTN) on the output terminal (104N) (e.g., |VOUT| = |VOUTP - VOUTN|). If the input signal (RFIN) has a peak voltage level (VIN), the magnitude of the output signal (VOUT) is proportional to the square of the absolute value of the peak voltage (VIN) of the input signal (RFIN) (e.g., |VOUTP - VOUTN| ~ |VIN|). 2 (). Accordingly, the processing circuit on the device (10) can identify the peak voltage (VIN) of radio frequency signals received through the radio frequency transmission line path (36) based on the magnitude of the output signal (VOUT) generated by the peak detector (54) (for example, after converting the magnitude of the output signal (VOUT) into corresponding digital voltage level information (VLI) and taking into account the square law relationship between the magnitude (VIN) of the generated output signal (VOUT) and the input signal (RFIN)).

[0057] This relationship between the output signal (VOUT) and the input signal (RFIN) is caused by the square law operation of the transistors (78P and 78N). During peak measurement, the input signal (RFIN) drives the gate terminal of the transistor (78P) (e.g., while the gate terminals of the transistors (78P and 78N) are biased by the bias transistor (102). As indicated by the arrows (106), the corresponding current flows through the transistor (78P) along the signal line (80P) and through the transistor (78N) along the signal line (80N). The current flowing through the transistors (78P and 78N) is the signal current (I) associated with the signal of interest in the input signal (RFIN). S ), and noise current (I) associated with noise in the input signal (RFIN). N It can be decomposed into). The transistors (78P and 78N) apply a square law function to the voltage provided to the output terminals (104P and 104N) to generate a voltage (VOUTP) on the output terminal (104P) and a voltage (VOUTN) on the output terminal (104N) (e.g., outputting the output signal (VOUT) as a DC voltage across the output terminals (104P and 104N)). The transistors (90P and 90N) perform single-ended to differential signal conversion on the signal lines (80P and 80N) to effectively convert from the single-ended signal domain of the input signal (RFIN) to the differential signal domain of the output signal (VOUT).

[0058] If there are no noise-erasing transistors (96P and 96N) in the peak detector (54), the output signal (VOUT) may be dominated by noise when the signal of interest in the input signal (RFIN) is at a relatively low signal level. The noise-erasing transistors (96P and 96N) can form current feedback loops for each of the transistors (78P and 78N), which serve to remove this noise from the output signal (VOUT).

[0059] For example, as illustrated by the current loop (84) in FIG. 5, when the gate terminal of the transistor (78P) is driven using the input signal (RFIN), a noise current (I) flows through the source-drain terminals of the transistor (78P). N ) is transmitted from the first source-drain terminal of the transistor (78P) to the first source-drain terminal of the noise-erasing transistor (96P), through the noise-erasing transistor (96P) to the second source-drain terminal of the noise-erasing transistor (96P), and from the second source-drain terminal of the noise-erasing transistor (96P) to the gate terminal of the circuit node (76) and the transistor (78P). Because the noise-erasing transistor (96P) is diode-connected (e.g., the same noise current (I N Because ) is simultaneously supplied to the gate terminal and the first source-drain terminal of the noise-erasing transistor (96P), the current does not flow back in the reverse direction through the noise-erasing transistor (96P) to the first source-drain terminal of the transistor (78P). The noise current (I) driven onto the gate terminal of the transistor (78P) by the noise-erasing transistor (96P) N ) is the noise current (I) flowing between the source-drain terminals of the transistor (78P). N It is inverted with respect to ) (e.g., noise current (I) at the gate terminal of the transistor (78P) NNoise current (I) flowing through the source-drain terminals of the transistor (78P) and the ) N ) has opposite signs). This is the noise current (I) of the voltage (VOUTP) generated at the output terminal (104P) by the transistor (78P). N It plays a role in effectively eliminating the ) component.

[0060] Likewise, as illustrated by the current loop (86) in FIG. 5, the noise current (I) flowing through the source-drain terminals of the transistor (78N) N ) is transmitted from the first source-drain terminal of the transistor (78N) to the first source-drain terminal of the noise-erasing transistor (96N), through the noise-erasing transistor (96N) to the second source-drain terminal of the noise-erasing transistor (96N), and from the second source-drain terminal of the noise-erasing transistor (96N) to the circuit node (98) and the gate terminal of the transistor (78N). Because the noise-erasing transistor (96N) is diode-connected (e.g., the same noise current (I N Because ) is supplied simultaneously to the gate terminal and the first source-drain terminal of the noise-erasing transistor (96N), the current does not flow back in the reverse direction through the noise-erasing transistor (96P) to the first source-drain terminal of the transistor (78N). The noise current (I) driven onto the gate terminal of the transistor (78N) by the noise-erasing transistor (96N) N ) is the noise current (I) flowing between the source-drain terminals of the transistor (78N). N It is inverted with respect to ) (e.g., noise current (I) at the gate terminal of the transistor (78N) N Noise current (I) flowing through the source-drain terminals of the transistor (78N) and the ) N ) has opposite signs). This is the noise current (I) of the voltage (VOUTN) generated at the output terminal (104N) by the transistor (78N).N It serves to effectively eliminate the ) component. In this way, the noise-eliminating transistors (96P and 96N) eliminate noise (e.g., noise current (I)) from the input signal (RFIN) while generating the output signal (VOUT). N Contributions from ) can be eliminated, which prevents noise from dominating the output signal (VOUT) and allows the peak detector (54) to produce very accurate and noise-reduced peak voltage level measurements of radio frequency signals on the radio frequency transmission line path (36).

[0061] Figure 6 is a plot showing how noise-canceling transistors (96P and 96N) can serve to minimize noise in the output signals (VOUT). The vertical axis of Figure 6 plots the noise level (e.g., from nV² to uV²). The horizontal axis of Figure 6 plots the input power level (P) of the input signal (RFIN). IN ...plots. Curve (110) plots the noise in the output signal (VOUT) in embodiments where the noise-sweeping transistors (96P and 96N) are omitted from the peak detector (54). Curve (112) plots the noise in the output signal (VOUT) when the peak detector (54) includes the noise-sweeping transistors (96P and 96N). As illustrated by curves (110 and 112), the noise-sweeping transistors (96P and 96N) [are at all input power levels (P) of the input signal (RFIN). IN Over the range, it can serve to reduce noise in the output signal (VOUT) by at least a margin (114) (e.g., 10 to 30 dB). The example in FIG. 6 is exemplary, and in reality, the curves (110 and 112) may have different shapes.

[0062] As used herein, the term “concurrent” means at least partially overlapping in time. In other words, the first and second events are referred to as “concurrent” with each other in this specification when at least a part of the first event occurs simultaneously with at least a part of the second event (e.g., when at least a part of the first event occurs during, while, or at the time of the occurrence of at least a part of the second event). The first and second events may be concurrent when they occur simultaneously (e.g., when the entire duration of the first event overlaps in time with the entire duration of the second event), and may also be concurrent when they do not occur simultaneously (e.g., when the first event begins before or after the start of the second event, when the first event ends before or after the end of the second event, or when the first and second events do not partially overlap in time). As used herein, the term “during” is synonymous with “concurrent.” The term "when" also implies at least some simultaneous execution (for example, that Event A occurs "when" Event B occurs means that at least some part of Event A is simultaneous with at least some part of Event B).

[0063] The methods and operations described above in relation to FIGS. 1 through 6 may be performed by components of the device (10) using software, firmware and / or hardware (e.g., dedicated circuitry or hardware). Software code for performing these operations may be stored in a non-transient computer-readable storage medium (e.g., tangible computer-readable storage medium) stored in one or more of the components of the device (10) (e.g., storage circuitry (16) and / or wireless circuitry (24) of FIG. 1). Software code may sometimes be referred to as software, data, instructions, program instructions, or code. A non-transient computer-readable storage medium may include a drive, non-volatile memory (e.g., non-volatile random access memory (NVRAM)), a removable flash drive or other removable media, other types of random access memory, etc. Software stored on a non-transient computer-readable storage medium can be executed in a processing circuit in one or more components of the device (10) (e.g., a processing circuit of a wireless circuit (24), a processing circuit (18) of FIG. 1, etc.). The processing circuit may include a microprocessor, an application processor, a digital signal processor, a central processing unit (CPU), an application integrated circuit equipped with a processing circuit, or other processing circuits.

[0064] Devices (10) may collect and / or use personally identifiable information. It is well understood that the use of personally identifiable information must follow privacy policies and practices generally recognized as meeting or exceeding industry or government requirements for maintaining users' privacy. In particular, personally identifiable information data must be managed and handled to minimize the risk of unintended or unauthorized access or use, and the nature of authorized use must be clearly indicated to users.

[0065] According to one embodiment, a voltage peak detector having an input terminal and a differential output is provided, wherein the voltage peak detector comprises: a first transistor having a first gate terminal coupled to the input terminal, a first source-drain terminal coupled to the first output terminal of the differential output, and a second source-drain terminal coupled to ground; a second transistor having a third source-drain terminal coupled to the power supply voltage and a fourth source-drain terminal coupled to the first output terminal; and a diode-connected transistor having a fifth source-drain terminal coupled to the first output terminal and a sixth source-drain terminal coupled to the first gate terminal.

[0066] According to another embodiment, the diode-connected transistor optionally has a second gate terminal connected to a fifth source-drain terminal.

[0067] According to another embodiment, the diode-connected transistor is optionally configured to transmit noise current from the fifth source-drain terminal to the first gate terminal.

[0068] According to another embodiment, the first transistor is optionally configured to transmit a noise current between the first source-drain terminal and the second source-drain terminal, and the noise current transmitted to the first gate terminal by the diode-connected transistor is the inversion of the noise current transmitted between the first source-drain terminal and the second source-drain terminal.

[0069] According to another embodiment, the voltage peak detector optionally includes a third transistor having a second gate terminal coupled to a first circuit node, a seventh source-drain terminal coupled to a second output terminal of a differential output, and an eighth source-drain terminal coupled to ground.

[0070] According to another embodiment, the voltage peak detector optionally comprises a fourth transistor having a ninth source-drain terminal coupled to a power supply voltage and a tenth source-drain terminal coupled to a second output terminal—the second transistor having a third gate terminal coupled to a second circuit node and the fourth transistor having a fourth gate terminal coupled to a second circuit node—a first resistor coupled in series between the second circuit node and the first output terminal, and a second resistor coupled in series between the second circuit node and the second output terminal.

[0071] According to another embodiment, the voltage peak detector optionally comprises: a fifth transistor having a fifth gate terminal, a first source-drain terminal coupled to the fifth gate terminal, and a second source-drain terminal, wherein the second source-drain terminal is coupled to ground; a third resistor coupled in series between the first source-drain terminal and the first gate terminal; and a fourth resistor coupled in series between the first source-drain terminal and the first circuit node.

[0072] According to another embodiment, the voltage peak detector optionally includes an additional diode-connected transistor having a 13th source-drain terminal coupled to a 2nd output terminal, a 14th source-drain terminal coupled to a 1st circuit node, and a 6th gate terminal connected to the 13th source-drain terminal.

[0073] According to another embodiment, the voltage peak detector optionally includes an additional diode-connected transistor having a ninth source-drain terminal coupled to a second output terminal and a tenth source-drain terminal coupled to a first circuit node.

[0074] According to another embodiment, the voltage peak detector optionally includes a fourth transistor having a first source-drain terminal coupled to a power supply voltage and a second source-drain terminal coupled to a second output terminal, and the second transistor has a third gate terminal coupled to a fourth gate terminal of the fourth transistor.

[0075] According to another embodiment, the first transistor and the third transistor are optionally square law devices.

[0076] According to one embodiment, a radio frequency transmission line path configured to transmit a radio frequency signal; an analog-to-digital converter (ADC); and a peak detector having an output coupled to the ADC are provided, wherein the peak detector comprises a differential pair of transistors coupled between a power supply voltage and an output, a first transistor having a first source-drain terminal coupled to an output and a first gate terminal configured to receive a radio frequency signal from the radio frequency transmission line path, and a second transistor having a second source-drain terminal coupled to an output and a first source-drain terminal, a second gate terminal coupled to a second source-drain terminal, and a third source-drain terminal coupled to a first gate terminal.

[0077] According to another embodiment, the wireless circuit optionally includes a third transistor having a third gate terminal and a fourth source-drain terminal, the fourth source-drain terminal being coupled to an output.

[0078] According to another embodiment, the wireless circuit includes a fourth transistor having a fifth source-drain terminal coupled to an output and a fourth source-drain terminal, a fourth gate terminal coupled to the fifth source-drain terminal, and a sixth source-drain terminal coupled to a third gate terminal.

[0079] According to another embodiment, the wireless circuit includes, optionally, a fifth transistor having a seventh source-drain terminal coupled to a first gate terminal and a third gate terminal for communication, and a fifth gate terminal coupled to the seventh source-drain terminal.

[0080] According to another embodiment, the peak detector is optionally configured to generate a DC voltage at the output based on a radio frequency signal, and the ADC is configured to generate a digital value based on the DC voltage.

[0081] According to another embodiment, the radio frequency signals are optionally in the satellite navigation band, and the wireless circuitry optionally includes one or more processors configured to mitigate a jammer signal in response to a digital value exceeding a threshold value.

[0082] According to one embodiment, an electronic device is provided, the electronic device comprising: an antenna; a receiver configured to be communicably coupled to the antenna and to receive a radio frequency signal using the antenna; and a circuit configured to identify a peak voltage level of the radio frequency signal, the circuit comprising a pair of square law transistors coupled in parallel between a power supply voltage and ground, a differential pair of transistors coupled between the pair of square law transistors and the power supply voltage, and a noise-suppressing device coupled between the source-drain terminals and the gate terminals of the pair of square law transistors, wherein the noise-suppressing device is configured to transfer current in a unidirectional manner from the source-drain terminals of the pair of square law transistors to the gate terminals of the pair of square law transistors.

[0083] According to another embodiment, noise-canceling devices optionally include diode-connected transistors.

[0084] According to another embodiment, noise-canceling devices optionally include diodes.

[0085] The foregoing is exemplary, and various modifications may be made to the described embodiments. The foregoing embodiments may be implemented individually or in any combination.

Claims

Claim 1 A voltage peak detector having an input terminal and a differential output, wherein the voltage peak detector comprises: a first transistor having a first gate terminal coupled to the input terminal, a first source-drain terminal coupled to the first output terminal of the differential output, and a second source-drain terminal coupled to ground; a second transistor having a third source-drain terminal coupled to a power supply voltage and a fourth source-drain terminal coupled to the first output terminal; and a diode-connected transistor having a fifth source-drain terminal coupled to the first output terminal and a sixth source-drain terminal coupled to the first gate terminal. Claim 2 In claim 1, the diode-connected transistor is a voltage peak detector having a second gate terminal connected to the fifth source-drain terminal. Claim 3 A voltage peak detector according to claim 1, wherein the diode-connected transistor is configured to transmit noise current from the fifth source-drain terminal to the first gate terminal. Claim 4 A voltage peak detector according to claim 3, wherein the first transistor is configured to transmit the noise current between the first source-drain terminal and the second source-drain terminal, and the noise current transmitted to the first gate terminal by the diode-connected transistor is the inversion of the noise current transmitted between the first source-drain terminal and the second source-drain terminal. Claim 5 A voltage peak detector according to claim 1, further comprising a third transistor having a second gate terminal coupled to a first circuit node, a seventh source-drain terminal coupled to a second output terminal of the differential output, and an eighth source-drain terminal coupled to ground. Claim 6 A voltage peak detector according to claim 5, further comprising: a fourth transistor having a ninth source-drain terminal coupled to the power supply voltage and a tenth source-drain terminal coupled to the second output terminal, wherein the second transistor has a third gate terminal coupled to the second circuit node and the fourth transistor has a fourth gate terminal coupled to the second circuit node; a first resistor coupled in series between the second circuit node and the first output terminal; and a second resistor coupled in series between the second circuit node and the second output terminal. Claim 7 A voltage peak detector according to claim 6, further comprising: a fifth transistor having a fifth gate terminal, a first source-drain terminal coupled to the fifth gate terminal, and a second source-drain terminal, wherein the second source-drain terminal is coupled to ground; a third resistor coupled in series between the first source-drain terminal and the first gate terminal; and a fourth resistor coupled in series between the first source-drain terminal and the first circuit node. Claim 8 A voltage peak detector according to claim 7, further comprising an additional diode-connected transistor having a 13th source-drain terminal coupled to the 2nd output terminal, a 14th source-drain terminal coupled to the 1st circuit node, and a 6th gate terminal connected to the 13th source-drain terminal. Claim 9 A voltage peak detector according to claim 5, further comprising an additional diode-connected transistor having a ninth source-drain terminal coupled to the second output terminal and a tenth source-drain terminal coupled to the first circuit node. Claim 10 A voltage peak detector according to claim 9, further comprising a fourth transistor having a first source-drain terminal coupled to the power supply voltage and a second source-drain terminal coupled to the second output terminal, wherein the second transistor has a third gate terminal coupled to the fourth gate terminal of the fourth transistor. Claim 11 In paragraph 5, the voltage peak detector, wherein the first transistor and the third transistor are square law devices. Claim 12 A wireless circuit section comprising: a radio frequency transmission line path configured to transmit a radio frequency signal; an analog-to-digital converter (ADC); and a peak detector having an output communicationably coupled to the ADC, wherein the peak detector Differential pair of transistors coupled between the power supply voltage and the output, A first transistor having a first gate terminal configured to receive the radio frequency signal from the radio frequency transmission line path and a first source-drain terminal coupled to the output, and A wireless circuit part comprising a second transistor having a second source-drain terminal coupled to the output and the first source-drain terminal, a second gate terminal coupled to the second source-drain terminal, and a third source-drain terminal coupled to the first gate terminal. Claim 13 In claim 12, the wireless circuit further comprises a third transistor having a third gate terminal and a fourth source-drain terminal, wherein the fourth source-drain terminal is coupled to the output. Claim 14 A wireless circuit portion according to claim 13, further comprising a fourth transistor having a fifth source-drain terminal coupled to the output and the fourth source-drain terminal, a fourth gate terminal coupled to the fifth source-drain terminal, and a sixth source-drain terminal coupled to the third gate terminal. Claim 15 A wireless circuit portion according to claim 14, further comprising a fifth transistor having a seventh source-drain terminal coupled to the first gate terminal and the third gate terminal for communication, and a fifth gate terminal coupled to the seventh source-drain terminal. Claim 16 A wireless circuit section according to claim 12, wherein the peak detector is configured to generate a DC voltage at the output based on the radio frequency signal, and the ADC is configured to generate a digital value based on the DC voltage. Claim 17 In claim 16, the radio frequency signal is in the satellite navigation band, and the wireless circuit further comprises one or more processors configured to mitigate a jammer signal in response to the digital value exceeding a threshold value. Claim 18 As an electronic device, the device comprises: an antenna; a receiver coupled to the antenna in a communicable manner and configured to receive a radio frequency signal using the antenna; and a circuit portion configured to identify a peak voltage level of the radio frequency signal, wherein the circuit portion comprises A pair of square law transistors coupled in parallel between the power supply voltage and ground, A differential pair of transistors coupled between the above-mentioned pair of square law transistors and the power supply voltage, and An electronic device comprising noise-canceling devices coupled between the source-drain terminals and the gate terminals of the pair of square law transistors, wherein the noise-canceling devices are configured to transfer current in a unidirectional manner from the source-drain terminals of the pair of square law transistors to the gate terminals of the pair of square law transistors. Claim 19 In paragraph 18, the noise-canceling devices are electronic devices comprising diode-connected transistors. Claim 20 In paragraph 18, the above noise-canceling devices are electronic devices comprising diodes.

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