Semiconductor device

Abstract

A semiconductor device comprises a first active region and a second active region extending in a first direction parallel to the surface of the substrate on a substrate, a field region disposed between the first active region and the second active region, first gate structures extending in a second direction intersecting the first direction, second gate structures extending in the second direction intersecting the second active region and facing the first gate structures in the second direction, a gate isolation pattern including a portion disposed between the first gate structures and the second gate structures, a first source / drain region disposed on the first active region and disposed between the first gate structures, and a second source / drain region disposed on the second active region and disposed between the second gate structures, wherein the gate isolation pattern comprises a plurality of first isolation patterns including a portion in which the width of the second direction changes according to the first direction, and a second isolation pattern extending in a third direction intersecting the upper surface of the substrate between the plurality of first isolation patterns, contacting the field region, and comprising a material different from the plurality of first isolation patterns. At least some of the plurality of first separation patterns include a first side wall in contact with the second separation pattern and a second side wall opposite to the first side wall, and with respect to the first direction, the first side wall has a first slope and the second side wall may have a second slope different from the first slope.

Description

Technology Field

[0001] The present disclosure relates to a semiconductor device. Background Technology

[0002] As the demand for high performance, high speed, and / or multifunctionality of semiconductor devices increases, the integration density of semiconductor devices is increasing. In manufacturing semiconductor devices with fine patterns to meet the trend of high integration of semiconductor devices, it is required to implement patterns with fine widths or fine spacing. In addition, efforts are being made to develop semiconductor devices including FinFETs with three-dimensional channel structures to overcome the limitations of operating characteristics resulting from the size reduction of planar MOSFETs (metal oxide semiconductor FETs). The problem to be solved

[0003] The technical problem that the present disclosure aims to solve is to improve the manufacturing yield of semiconductor devices and to provide semiconductor devices with improved performance and reliability.

[0004] The technical problems of the present disclosure are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A semiconductor device according to an exemplary embodiment of the present disclosure for achieving the above technical problem comprises: a first active region extending in a first direction parallel to the surface of the substrate on the substrate; a second active region extending in a first direction parallel to the first active region on the substrate; a field region disposed between the first active region and the second active region; a plurality of first gate structures disposed parallel to the substrate and extending in a second direction parallel to the surface of the substrate and intersecting the first direction; second gate structures extending in a second direction intersecting the second active region on the substrate and facing the first gate structures in the second direction; a gate isolation pattern comprising a portion disposed between the first gate structures and the second gate structures; a first source / drain region disposed on the first active region and disposed between the first gate structures; and a second source / drain region disposed on the second active region and disposed between the second gate structures, wherein the gate isolation pattern comprises the second according to the first direction A plurality of first separation patterns including a portion in which the width of the direction changes, and a second separation pattern extending in a third direction intersecting the upper surface of the substrate between the plurality of first separation patterns and contacting the field region, and including a material different from the plurality of first separation patterns, wherein at least some of the plurality of first separation patterns include a first sidewall in contact with the second separation pattern and a second sidewall opposite to the first sidewall, and with respect to the first direction, the first sidewall has a first slope and the second sidewall may have a second slope different from the first slope.

[0006] A semiconductor device according to an exemplary embodiment of the present disclosure for achieving the above technical problem comprises: a first active region extending in a first direction parallel to the surface of the substrate on a substrate; a second active region extending in a first direction parallel to the first active region on the substrate; a plurality of first gate structures arranged in parallel on the substrate, extending in a second direction parallel to the surface of the substrate and intersecting the first direction and intersecting the first active region; second gate structures extending in a second direction intersecting the second active region on the substrate and facing the first gate structures in the second direction; a gate isolation pattern including a portion disposed between the first gate structures and the second gate structures; a plurality of first source / drain regions disposed on the first active region and disposed between the first gate structures; a plurality of second source / drain regions disposed on the second active region and disposed between the second gate structures; and a common contact plug connected to the plurality of first source / drain regions and the plurality of second source / drain regions. The gate separation pattern comprises a plurality of first separation patterns including a portion in which the width of the second direction changes according to the first direction, and at least one second separation pattern extending in a third direction intersecting the upper surface of the substrate between the plurality of first separation patterns and including a material different from the plurality of first separation patterns, wherein the lowest level of the common contact plug is equal to or lower than at least some of the levels in which each of the first source / drain regions and the second source / drain regions has a maximum width, and the lowest level of the second separation pattern may be equal to or higher than the lowest level of each of the plurality of first separation patterns.

[0007] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0008] According to embodiments of the present disclosure, a gate separation pattern for separating a plurality of gate structures comprises first separation patterns and a second separation pattern, and a common contact plug penetrating at least a portion of the second separation pattern can be easily formed due to the second separation pattern comprising a material different from the first separation patterns. Accordingly, defects in the semiconductor device can be reduced.

[0009] The common contact plug can reduce contact resistance by increasing the contact area with the source / drain regions due to the second separation pattern. As a result, the operating speed of the semiconductor device can be improved and power consumption reduced. Brief explanation of the drawing

[0010] FIG. 1 is an exemplary plan view illustrating a semiconductor device according to one embodiment of the present disclosure. FIG. 2a is an exemplary drawing for illustrating a cross-section cut along the line I-I' of FIG. 1. FIG. 2b is an exemplary drawing to illustrate a cross-section cut along the line II-II' of FIG. 1. FIG. 2c is an exemplary drawing to illustrate a cross-section cut along the line III-III' of FIG. 1. FIG. 2d is an exemplary drawing to illustrate a cross-section cut along the line IV-IV' of FIG. 1. Figure 3 is an exemplary drawing showing an enlarged view of area A of Figure 1. FIG. 4 is a plan view illustrating a semiconductor device according to another embodiment of the present disclosure. FIGS. 5a and 5b are cross-sectional views illustrating a semiconductor device according to another embodiment of the present disclosure. Figure 6 is an exemplary drawing showing an enlarged view of area A of Figure 4. FIG. 7 is an exemplary drawing for illustrating a cross-section cut along the line II-II' of FIG. 1, according to another embodiment of the present disclosure. FIG. 8 is an exemplary drawing for illustrating a cross-section cut along the line II-II' of FIG. 1, according to another embodiment of the present disclosure. FIG. 9 is an exemplary drawing for illustrating a cross-section cut along the line II-II' of FIG. 1, according to another embodiment of the present disclosure. FIG. 10 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 11a is a cross-sectional view showing a cross section cut along line I-I' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 11b is a cross-sectional view showing a cross section cut along the line II-II' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 11c is a cross-sectional view showing a cross-section cut along the line III-III' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIG. 11d is a cross-sectional view taken along line IV-IV' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIGS. 12a, FIGS. 13a, FIGS. 14a, FIGS. 15a, FIGS. 16a, FIGS. 17a, FIGS. 18a, FIGS. 19a, and FIGS. 20a are enlarged views illustrating an area corresponding to region A of FIG. 1 to explain a method for manufacturing a gate separation pattern (200) among the configurations of a semiconductor device according to one embodiment of the present disclosure. FIGS. 12b, FIGS. 13B, FIGS. 14b, FIGS. 15B, FIGS. 16B, FIGS. 17B, FIGS. 18b, FIGS. 19b, and FIGS. 20b are sequential cross-sectional views showing a cross-section cut along the line II-II' of FIG. 1 to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. Specific details for implementing the invention

[0011] Prior to the detailed description of the embodiments, terms and words used in this specification and claims should not be interpreted as being limited to their ordinary or dictionary meanings, but should be interpreted in a meaning and concept consistent with the technical spirit of this disclosure, based on the principle that the inventor may appropriately define the concept of the terms to best describe his invention. Accordingly, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of this disclosure and do not represent all of the technical spirit of this disclosure; therefore, it should be understood that various equivalents and modifications that can replace them may exist at the time of filing this application.

[0012] In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise. Terms such as "comprising" or "constituting" are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0013] Furthermore, it should be noted in advance that expressions such as upper side, top, lower side, bottom, side, front, and rear in the following description are based on the direction depicted in the drawings, and may be expressed differently if the direction of the object changes. The shapes and sizes of elements in the drawings may be exaggerated for clearer explanation.

[0014] Hereinafter, embodiments according to the technical concept of the present disclosure will be described with reference to the attached drawings.

[0015] FIG. 1 is a plan view illustrating a semiconductor device (100) according to one embodiment of the present disclosure. FIG. 2a to 2d are cross-sectional views illustrating a semiconductor device (100) according to one embodiment of the present disclosure. FIG. 3 is an exemplary drawing showing an enlarged view of area A of FIG. 1. FIG. 2a illustrates a cross-section of the semiconductor device (100) of FIG. 1 cut along the cutting line I-I', FIG. 2b illustrates a cross-section of the semiconductor device (100) of FIG. 1 cut along the cutting line II-II', FIG. 2c illustrates a cross-section of the semiconductor device (100) of FIG. 1 cut along the cutting line III-III', and FIG. 2d illustrates a cross-section of the semiconductor device (100) of FIG. 1 cut along the cutting line IV-IV'. For convenience of explanation, only the main components of the semiconductor device are illustrated in FIG. 1 to 3.

[0016] Referring to FIGS. 1 to 3, a semiconductor device (100) may include a substrate (101), active regions (105) on the substrate (101), field regions (110) separating the active regions (105) from each other, a channel structure (140) including first to third channel layers (141, 142, 143) spaced perpendicularly apart from each other on the active regions (105), source / drain regions (150) in contact with the first to third channel layers (141, 142, 143), gate structures (GS) extending intersecting the active regions (105), contact plugs (180, 280), a gate separation pattern (200), and an interlayer insulating layer (190). The gate structures (GS) may include a gate dielectric layer (162), a gate electrode (165), a gate spacer (164), and a gate capping layer (166).

[0017] According to one embodiment, the first to third channel layers (141, 142, 143) may be spaced perpendicularly apart from each other on the active regions (105). Accordingly, the active regions (105) may have a fin structure, and a gate electrode (165) may be disposed between the active regions (105) and the lowest channel layer (141), between the first to third channel layers (141, 142, 143), and on top of the uppermost channel layer (143). Accordingly, the semiconductor device (100) is a Gate-All-Around type field-effect transistor (MBCFET) formed by the first to third channel layers (141, 142, 143), source / drain regions (150), and gate structures (GS). TM It can be a transistor with a (Multi-Bridge Channel FET) structure.

[0018] However, according to the embodiment, unlike the descriptions above, the channel structure may be a plurality of fin structures disposed on active regions (105) rather than channel layers arranged perpendicularly apart from each other. Accordingly, the semiconductor device (100) may be a fin-type field-effect transistor formed by the channel structure, source / drain regions (150), and gate structures (GS).

[0019] According to one embodiment, the substrate (101) may have an upper surface extending in a first direction (D1) and a second direction (D2). The substrate (101) may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, the group IV semiconductor may include silicon, germanium, or silicon-germanium. The substrate (101) may be provided as a bulk wafer, an epitaxial layer, an epitaxial layer, a Silicon On Insulator (SOI) layer, or a Semiconductor On Insulator (SeOI) layer, etc.

[0020] According to one embodiment, active regions (105) may be arranged to extend in a direction parallel to the upper surface of the substrate (101), for example, in a first direction (D1). Active regions (105) may be arranged parallel to each other and spaced apart in a second direction (D2). Active regions (105) may protrude in a third direction (D3) intersecting the upper surface of the substrate (101). The upper portion of the active regions (105) may be arranged to protrude to a predetermined height from the upper portion of the field regions (110). The active regions (105) may be formed as part of the substrate (101) or may include an epitaxial layer grown from the substrate (101). However, on both sides of the gate structures (GS), the active regions (105) on the substrate (101) may be partially recessed, and source / drain regions (150) may be arranged on the recessed active regions (105).

[0021] According to one embodiment, the active regions (105) may include a first active region (105A) and a second active region (105B) adjacent to each other. The first active region (105A) and the second active region (105B) may each have a line shape or a bar shape extending in a first direction (D1). The first active region (105A) and the second active region (105B) may be spaced apart from each other and extend parallel to each other, but are not limited thereto. The first active region (105A) and the second active region (105B) may have the same conductivity type. For example, the first active region (105A) and the second active region (105B) may have an N-type conductivity type.

[0022] According to another embodiment, the first active region (105A) and the second active region (105B) may have different conductivity types. When the first active region (105A) has a first conductivity type, the second active region (105B) may have a second conductivity type different from the first conductivity type. The first conductivity type may be an N-type conductivity type, and the second conductivity type may be a P-type conductivity type.

[0023] According to one embodiment, field regions (110) may define active regions (105) on a substrate (101). Field regions (110) may be positioned between the active regions (105). Field regions (110) may have an upper portion at a lower level than the upper portion of the active regions (105). Accordingly, field regions (110) may partially expose the upper portion of the active regions (105). According to one embodiment, field regions (110) may have a curved upper surface having a higher level as it is adjacent to the active regions (105), but is not limited thereto. Field regions (110) may be formed, for example, by a shallow trench isolation (STI) process. Field regions (110) may be made of an insulating material. Field regions (110) may be, for example, an oxide, a nitride, or a combination thereof.

[0024] According to one embodiment, the channel structure (140) may include first to third channel layers (141, 142, 143), which are two or more channel layers spaced apart from each other in a direction perpendicular to the upper surface of the active region (105), for example, in a third direction (D3), on the active region (105). The first to third channel layers (141, 142, 143) may be spaced apart from the upper surface of the active region (105) while being connected to the source / drain region (150). The first to third channel layers (141, 142, 143) may have a width equal to or similar to that of the active region (105) in the second direction (D2) and may have a width equal to or similar to that of the gate structure (GS) in the first direction (D1). However, according to the embodiments, the first to third channel layers (141, 142, 143) may have a reduced width such that their sides are located at the bottom of the gate structure (GS) in the first direction (D1). As a result, the contact area between the source / drain region (150) and the first to third channel layers (141, 142, 143) may be reduced.

[0025] According to one embodiment, the first to third channel layers (141, 142, 143) may be made of a semiconductor material and may include, for example, silicon (Si). The first to third channel layers (141, 142, 143) may be made of, for example, the same material as the substrate (101). The number and shape of the channel layers (141, 142, 143) forming a channel structure (140) may be varied in the embodiments. For example, according to the embodiments, the channel structure (140) may further include a channel layer disposed on the upper surface of the active region (105).

[0026] According to one embodiment, source / drain regions (150) may be disposed on active regions (105) at least on one side of the channel structure (140). The source / drain regions (150) may be disposed to cover the upper surface of the active regions (105) at the side of each of the first to third channel layers (141, 142, 143) and at the bottom of the source / drain regions (150). The source / drain regions (150) may be in contact with the first to third channel layers (141, 142, 143). The source / drain regions (150) may be disposed by partially recessing the upper portion of the active regions (105), but the presence and depth of the recess may vary in the embodiments. The source / drain regions (150) may be a semiconductor layer comprising silicon (Si) and may be made of an epitaxial layer.

[0027] According to one embodiment, the source / drain regions (150) may include a first source / drain region (150A) disposed on a first active region (105A) and a second source / drain region (150B) disposed on a second active region (105B). The first and second source / drain regions (105A, 105B) may contain impurities of different types and / or concentrations. For example, the first source / drain region (150A) may have a second conductivity type, and the second source / drain region (150B) may have a first conductivity type. That is, the first source / drain region (150A) and the first active region (105A) may have different conductivity types, but are not limited thereto.

[0028] According to embodiments, the first source / drain region (150A) may have a merged form in which it is connected to adjacent active regions (105) along the second direction (D2), but is not limited thereto. For example, in the second direction (D2), a second separation pattern (202) may be disposed between the first source / drain region (150A) and the second source / drain region (150B). In this case, even if the first source / drain region (150A) and the second source / drain region (150B) are formed connected to each other, they may be separated by the second separation pattern (202) during the process of forming the gate separation pattern (200) described later. By the second separation pattern (202), the contact plug (180) described later increases the contact area with the source / drain regions (150), thereby reducing the resistance of the semiconductor device.

[0029] According to one embodiment, gate structures (GS) may be arranged to extend in one direction, e.g., a second direction (D2), intersecting the active regions (105) and the channel structure (140) on top of the active regions (105) and the channel structure (140). Channel regions of transistors may be formed in the active regions (105) and / or the channel structure (140) intersecting the gate structures (GS).

[0030] According to one embodiment, each of the gate structures (GS) may include a gate dielectric layer (162), a gate electrode (165), a gate spacer (164), and a gate capping layer (166). Between the channel structures (140), each of the gate structures (GS) may have its upper and lower surfaces in contact with the first to third channel layers (141, 142, 143).

[0031] According to one embodiment, the gate dielectric layer (162) may be disposed between each of the active regions (105) and the gate electrode (165) and between the first to third channel layers (141, 142, 143) and the gate electrode (165), and may be disposed to cover at least some of the faces of the gate electrode (165). For example, the gate dielectric layer (162) may be disposed to surround all faces except the top face of the gate electrode (165). The gate dielectric layer (162) may extend between the gate electrode (165) and the gate spacer (164), but is not limited thereto. The gate dielectric layer (162) may comprise an oxide, a nitride, or a high-k dielectric material. A high-k dielectric material may mean a dielectric material having a dielectric constant higher than that of silicon oxide (SiO2). High dielectric constant materials can refer to dielectric materials having a dielectric constant higher than that of silicon oxide (SiO2). Examples of high dielectric constant materials include aluminum oxide (Al2O3), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), and zirconium silicon oxide (ZrSi2). x O y ), hafnium oxide (HfO2), hafnium silicon oxide (HfSi x O y ), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAl x O y ), lanthanum hafnium oxide (LaHf x O y ), hafnium aluminum oxide (HfAl x O y It may be any one of ), and praseodymium oxide (Pr2O3). According to the embodiments, the gate dielectric layer (162) may be made of multiple layers.

[0032] According to one embodiment, the gate electrode (165) may be disposed extending above the channel structure (140) and filling the space between the channel structures (140) on the active regions (105). The gate electrode (165) may be spaced apart from the channel structure (140) by a gate dielectric layer (162). The gate electrode (165) may include a conductive material and may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metal material such as aluminum (Al), tungsten (W), or molybdenum (Mo), or a semiconductor material such as doped polysilicon. According to embodiments, the gate electrode (165) may be composed of two or more multilayers. Depending on the configuration of the semiconductor device (100), the gate electrode (165) may be disposed separated by a separate separator between at least some adjacent transistors. The gate electrode (165) may contain different materials depending on the transistor regions.

[0033] According to one embodiment, the gate spacer (164) is disposed on both side walls of the gate electrode (165) and may extend in a third direction (D3) perpendicular to the upper surface of the substrate (101). The gate spacer (164) may include a portion in which the upper width is smaller than the lower width. However, the shape of the gate spacer (164) may be varied according to the embodiment. The gate spacer (164) may insulate the source / drain regions (150) from the gate electrode (165). The gate spacer (164) may be made of multiple layers according to the embodiments. The gate spacer (164) may be made of oxide, nitride, and oxynitride.

[0034] According to one embodiment, a gate capping layer (166) may be disposed on a gate electrode (165). The gate capping layer (166) may be a structure for protecting the gate electrode (165) from etching in a subsequent process after the gate electrode (165) is formed, but the role of the gate capping layer (166) is not limited thereto. The gate capping layer (166) may be disposed on top of the gate electrode (165) and the gate spacer (164), and at least a portion of the lower surface may be surrounded by the gate electrode (165) and the gate spacer (164). According to one embodiment, the gate capping layer (166) may include a lower surface that is convex toward the substrate (101). The gate capping layer (166) may include silicon nitride or an insulating material of the silicon nitride family.

[0035] According to one embodiment, the gate structures (GS) may include first gate structures (GS1) and second gate structures (GS2) separated from each other and facing in a second direction (D2), which is the direction in which the gate structures (GS) extend. A plurality of first gate structures (GS1) may be arranged in parallel on a substrate (101) and may extend in a second direction (D2) that intersects a first active region (105A), is parallel to the surface of the substrate (101), and intersects a first direction (D1). The second gate structures (GS2) may extend in a second direction (D2) that intersects a second active region (105B) on the substrate (101) and may face the first gate structures (GS1) in the second direction (D2). The first gate structures (GS1) and the second gate structures (GS2) may have substantially the same width in the first direction (D1). The first gate structures (GS1) and the second gate structures (GS2) can be physically spaced apart and electrically separated.

[0036] Although not illustrated, according to embodiments, the semiconductor device (100) may further include internal spacer layers positioned parallel to the gate electrode (165) between the channel structures (140). The gate electrode (165), located below the channel layer positioned at the top of the channel structures (140), may be electrically isolated from the source / drain regions (150) by the internal spacer layers. The internal spacer layers may have a shape in which the side facing the gate electrode (165) is rounded inwardly convex toward the gate electrode (165), but is not limited thereto. The internal spacer layers may be made of oxides, nitrides, and oxynitrides, and in particular may be made of low dielectric constant films. According to embodiments, the internal spacer layers may be omitted.

[0037] According to one embodiment, the gate separation pattern (200) may be disposed on field regions (110) between the first active region (105A) and the second active region (105B). The gate separation pattern (200) may include a portion disposed between the first gate structures (GS1) and the second gate structures (GS2). According to one embodiment, the gate separation pattern (200) may be dumbbell-shaped, with a width that changes as it moves toward the first direction (D1) in the plane, but is not limited thereto. The gate separation pattern (200) may include at least one of silicon nitride, silicon oxide, silicon oxynitride, or a nitride-based material. The gate separation pattern (200) may include the same material as the gate spacer (164), but is not limited thereto. The gate separation pattern (200) may include a portion that becomes narrower as it approaches the upper surface of the substrate (101).

[0038] According to one embodiment, the gate separation pattern (200) may include a plurality of first separation patterns (201) comprising a portion in which the width of the second direction (D2) changes according to the first direction (D1), and a second separation pattern (202) that extends in a third direction (D3) intersecting the upper surface of the substrate (101) between the plurality of first separation patterns (201) and contacts the field region (110), and comprises a material different from that of the plurality of first separation patterns (201). For example, the plurality of first separation patterns (201) may comprise a nitride-based material, and the plurality of second separation patterns (202) may comprise an oxide-based material. As a result, the common contact plug (280) described below can penetrate at least a portion of the second separation patterns (202) between the source / drain regions (150) in the third direction (D3), and since the contact area of ​​the common contact plug (280) with the source / drain regions (150) is increased, the resistance of the semiconductor device (100) can be reduced overall.

[0039] According to one embodiment, at least some of the plurality of first separation patterns (201) may include a first sidewall (S1) in contact with a second separation pattern (202) and a second sidewall (S2) opposite to the first sidewall (S1). With respect to the first direction (D1), the first sidewall (S1) may have a first slope, and the second sidewall (S2) may have a second slope different from the first slope. For example, the first slope may have a slope of about 80 degrees to about 100 degrees with respect to the upper surface of the substrate (101), but is not limited thereto. With respect to a line perpendicular to the upper surface of the substrate (101), the slope of the second sidewall (S2) may have the same sign as the slope of the first sidewall (S1), but is not limited thereto. It can be defined that a line perpendicular to the upper surface of the substrate has a positive slope when tilted clockwise, and a line perpendicular to the upper surface of the substrate has a negative slope when tilted counterclockwise.

[0040] As shown in FIG. 2b, the lowest level (L2) of the second separation pattern (202) according to the third direction (D3) may be higher than the lowest level (L1) of each of the plurality of first separation patterns (201), but is not limited thereto.

[0041] As shown in FIGS. 2b and 2c, the gate isolation pattern (200) can isolate the gate structures (GS). The gate isolation pattern (200) can penetrate the gate structures (GS), including the gate dielectric layer (162), the gate electrode (165), and the gate capping layer (166). The gate isolation pattern (200) may also penetrate at least a portion of the field region (110). This increases the insulation between the gate structures (GS), thereby improving the reliability of the semiconductor device (100). A second isolation pattern (202) is located between the first isolation pattern (201) and can contribute to increasing the contact area between the common contact plug (280) and the source / drain region (150).

[0042] As shown in FIG. 3, the first separation pattern (201) may have a first part and a second part. The first part is positioned between the first gate structure (GS1) and the second gate structure (GS2) in the second direction (D2) and may have a first width (Wa1) in the second direction (D2). The first width (Wa1) may be larger than the width (Wb) along the second direction (D2) of the second separation pattern (202). The second part may include a second part positioned between the first source / drain region (150A) and the second source / drain region (150B), connected to the first part, and having a second width (Wa2) smaller than the first width (Wa1). The first separation pattern (201) may have a width along the second direction (D2) that gradually decreases from the first width (Wa1) to the second width (Wa2) as it moves toward the first direction (D1) away from the second separation pattern (202). The width (Wb) along the second direction (D2) of the second separation pattern (202) may be constant, but is not limited thereto. For example, the second separation pattern (202) may include a part where the width changes as it moves toward the first direction (D1), that is, a part connected to the first part of the first separation pattern (201).

[0043] According to one embodiment, the interlayer insulating layer (190) covers source / drain regions (150) and gate structures (GS) and may be arranged to cover field regions (110). The interlayer insulating layer (190) may include, for example, at least one of oxide, nitride, and oxynitride, and may include a low dielectric constant material. Although not illustrated, the semiconductor device (100) may further include wiring lines and upper insulating layers on the interlayer insulating layer (190).

[0044] According to one embodiment, the contact plugs (180, 280) may penetrate the interlayer insulation layer (190). The contact plugs (180, 280) may include a single contact plug (180) connected to the first source / drain regions (150A) or the second source / drain regions (150B), and a common contact plug (280) connected to the first source / drain regions (150A) and the second source / drain regions (150B).

[0045] According to one embodiment, a single contact plug (180) may be connected to each of the source / drain regions (150) by penetrating the interlayer insulating layer (190) and may apply an electrical signal to the source / drain regions (150). The single contact plug (180) may be placed on the source / drain regions (150) as shown in FIG. 1. The single contact plug (180) may have a slanted side that decreases in width toward the substrate (101) according to the aspect ratio, but is not limited thereto. The single contact plug (180) may be recessed to a certain depth from the source / drain regions (150), but is not limited thereto. In exemplary embodiments, the single contact plug (180) may be placed to make contact along the upper surface of the source / drain regions (150) without recessing the source / drain regions (150). A single contact plug (180) can be spaced apart from the gate separation pattern (200).

[0046] According to one embodiment, the common contact plug (280) may simultaneously contact the first and second source / drain regions (150A, 150B). The common contact plug (280) may be in the shape of a line extending in a second direction (D2) between the gate structures (GS). According to one embodiment, the common contact plug (280) may be recessed to a certain depth from the source / drain regions (150). In this case, the lower surface of the common contact plug (280) may extend from within the source / drain regions (150A) to the upper surface of the second separation pattern (202) and cover the upper surface of the second separation pattern (202). The second separation pattern (202) may contain a material different from the first separation pattern (201) during the etching process for forming the common contact plug (280) and may have higher etch selectivity compared to the first separation pattern (201). As a result, the lowest level of the common contact plug (280) may be lower than the lowest level of the single contact plug (180). One side of the common contact plug (280) may extend along the first gate structures (GS1), the gate separation pattern (200), and the second gate structures (GS2). The common contact plug (280) may penetrate the second separation pattern (202) in the second direction (D2). The common contact plug (280) may penetrate at least a portion of the second separation pattern (202) in the third direction (D3). As a result, the lowest level (L4) of the common contact plug (280) in the third direction (D3) may be the same as the level (L3) in the third direction (D3) where the source / drain regions (150) have the maximum width in the second direction (D2), but is not limited thereto.

[0047] According to one embodiment, contact plugs (180, 280) may include a plug layer (180a, 280a) and a barrier layer (180b, 280b). The plug layer (180a, 280a) may include a metal nitride, such as, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN), and / or a metallic material such as aluminum (Al), tungsten (W), or molybdenum (Mo). The barrier layer (180b, 280b) may conformally cover the side and bottom surfaces of the plug layer (180a, 280a). The barrier layer (180b, 280b) may include a metal nitride, such as, for example, titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN).

[0048] According to one embodiment, the semiconductor device (100) may include a first transistor region in which a first active region (105A), first source / drain regions (150A), and first gate structures (GS1) are disposed, and a second transistor region in which a second active region (105B), second source / drain regions (150B), and second gate structures (GS2) are disposed. Both the first and second transistor regions may be NMOS transistor regions, but are not limited thereto. Either one of the first and second transistor regions may be an NMOS transistor region, and the other may be a PMOS transistor region. Each of the first and second transistor regions may include a transistor of the MBCFET™ (Multi Bridge Channel FET) structure described above. The first and second transistor regions may be separated by a gate separation pattern (200). According to one embodiment, the first and second transistor regions may be electrically connected by a common contact plug (280).

[0049] With respect to the following embodiments, redundant drawings are omitted to aid in understanding the present disclosure, and the differences from those described with reference to FIGS. 1 to 3 are explained primarily.

[0050] FIG. 4 is a plan view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 5a and FIG. 5b are cross-sectional views illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 6 is an exemplary drawing showing an enlarged view of area A of FIG. 4. FIG. 5a illustrates a cross-section of the semiconductor device (100A) of FIG. 4 cut along the cutting line II-II', and FIG. 5b illustrates a cross-section of the semiconductor device (100A) of FIG. 4 cut along the cutting line IV-IV'.

[0051] Referring to FIGS. 4 to 6, the width (Wb) along the second direction (D2) of the second separation pattern (202) of the gate separation pattern (200) of the semiconductor device (100A) may be constant. As the first separation pattern (201) moves toward the first direction (D1) away from the second separation pattern (202), the width along the second direction (D2) may gradually decrease from the first width (Wa1) to the second width (Wa2). The maximum width (Wa1) along the second direction (D2) of the first separation pattern (201) and the maximum width (Wb) along the second direction (D2) of the second separation pattern (202) may be the same. As a result, the lower part of the gate separation pattern (200) may have a gentle convex shape compared to the lower part of the gate separation pattern (200) shown in FIG. 2b. The uppermost level of the convex shape facing the second separation pattern (202) in the field area (110) may be lower than the lowermost level of the gate structure (GS).

[0052] According to one embodiment, the second separation pattern (202) may penetrate at least a portion of the field region (110). The lowest level (L4) of the common contact plug (280) may cover the upper surface of the second separation pattern (202) and may be lower than the level (L3) in the third direction (D3) having a maximum width in the second direction (D2) for the source / drain regions (150). As a result, the area of ​​contact between the common contact plug (280) and the first source / drain region (150A) and the second source / drain regions (150B) is increased, thereby reducing the resistance of the semiconductor device (100A).

[0053] According to one embodiment, the lower portion of the second separation pattern (202) of the semiconductor device (100A) may have an upwardly convex shape. Specifically, the lower portion of the second separation pattern (202) may include a portion that is recessed upward along a third direction (D3) between the first separation patterns (201). The height of the recessed portion in the third direction (D3) may gradually increase as it moves toward the center from the point where it contacts the first separation pattern (201) on both sides of the second separation pattern (202). The apex of the recessed portion may be located at the center along the second direction (D2) of the second separation pattern (202), but is not limited thereto.

[0054] FIG. 7 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 7 illustrates a region corresponding to a cross section cut along the cutting line II-II' of FIG. 1.

[0055] Referring to FIG. 7, unlike the semiconductor device (100A) of FIG. 5a, the semiconductor device (100B) may have a flat shape at the bottom of the second separation pattern (202). The bottom of the second separation pattern (202) may form a substantially horizontal plane between the first separation patterns (201). The flat plane may be in the shape of a straight line connecting points on both sides of the second separation pattern (202) that contact the first separation pattern (201), but is not limited thereto. The lowest level of the second separation pattern (202) according to the third direction (D3) may be the same as the lowest level of each of the plurality of first separation patterns (201).

[0056] FIG. 8 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 8 illustrates a region corresponding to a cross section cut along the cutting line II-II' of FIG. 1.

[0057] Referring to FIG. 8, the semiconductor device (100C) may include an air gap (AG) within the second separation pattern (202). The air gap (AG) may be formed at the bottom of the second separation pattern (202). According to one embodiment, the air gap (AG) may be formed when the slopes of the first sidewall (S1) and the second sidewall (S2) have different signs during the deposition process of forming the second separation pattern (202), but is not limited thereto. For example, when the first sidewall (S1) has a negative slope in which the width of the second direction (D2) decreases as it goes upward (e.g., a negative slope in which it is tilted counterclockwise from a line perpendicular to the upper surface of the substrate), and the second sidewall (S2) has a positive slope in which the width of the second direction (D2) increases as it goes upward (e.g., a slope in which it is tilted clockwise from a line perpendicular to the upper surface of the substrate), the lower part of the second separation pattern (202) may not be completely filled during the deposition process, so an air gap (AG) may be formed. The air gap (AG) may contain an inert gas such as nitrogen (N2), hydrogen (H2), argon (Ar), or helium (He), or may contain a gas generated during the semiconductor device (100C) process. The air gap (AG) may have a substantially elliptical or teardrop shape at the bottom of the second separation pattern (202), and its upper part may be sealed by the second separation pattern (202). The air gap (AG) can improve the reliability of the semiconductor device (100C) by separating the gate structure (GS).

[0058] FIG. 9 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 9 illustrates a region corresponding to a cross section cut along the cutting line II-II' of FIG. 1.

[0059] Referring to FIG. 9, the semiconductor device (100D) may have a first slope and a second slope having the same sign. The semiconductor device (100D) may have side walls on both sides of the second separation pattern (202) having slopes of the same sign. Specifically, the first side wall (S1) of the first separation pattern (202) and the adjacent second side wall (S2) may both have a positive slope or a negative slope. In this way, by having the first side wall (S1) and the second side wall (S2) have slopes of the same sign, the material can be uniformly filled to the bottom during the deposition process forming the second separation pattern (202).

[0060] FIG. 10 is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present disclosure. FIG. 10 illustrates a region corresponding to a cross section cut along the cutting line II-II' of FIG. 1.

[0061] Referring to FIG. 10, the semiconductor device (100E) may further include third separation patterns (203) disposed on the outer side of each of the plurality of first separation patterns (201). The gate separation pattern (200) may include a plurality of first separation patterns (201), a second separation pattern (202), and third separation patterns (203). The first separation patterns (201) may be disposed between the second separation pattern (202) and the third separation patterns (203) in a first direction (D1). The second separation pattern (202) may be disposed between the first separation patterns (201) that are spaced apart from each other in the first direction (D1). The third separation patterns (203) may be disposed on the outer side of the first separation patterns (201) and may surround the outer wall of the first separation patterns (201). The third separation patterns (203) may contain the same material as the second separation pattern (202). For example, the second separation pattern (202) and the third separation patterns (203) may contain oxides, and the first separation patterns (201) may contain nitrides.

[0062] FIGS. 11a to 20b are cross-sectional and enlarged views illustrated in the order of process to explain a method for manufacturing a semiconductor device according to one embodiment of the present disclosure. FIGS. 11a to 20b describe an example of a method for manufacturing a semiconductor device (100) of FIGS. 1 to 2d.

[0063] FIG. 11a is a cross-sectional view showing a cross-section cut along line I-I' of FIG. 1, FIG. 11b is a cross-sectional view showing a cross-section cut along line II-II' of FIG. 1, FIG. 11c is a cross-sectional view showing a cross-section cut along line III-III' of FIG. 1, and FIG. 11d is a cross-sectional view showing a cross-section cut along line IV-IV' of FIG. 1. FIG. 12a, FIG. 13a, FIG. 14a, FIG. 15a, FIG. 16a, FIG. 17a, FIG. 18a, FIG. 19a, and FIG. 20a are enlarged views illustrated to explain a method for manufacturing a gate separation pattern (200) among the configurations of a semiconductor device according to one embodiment of the present disclosure. FIGS. 12b, FIGS. 13B, FIGS. 14b, FIGS. 15B, FIGS. 16B, FIGS. 17B, FIGS. 18b, FIGS. 19b, and FIGS. 20b are sequential cross-sectional views showing a cross section cut along the line II-II' of FIGS. 1. FIGS. 12a to 14b, FIGS. 20a, and FIGS. 20b are exemplary processes for forming a gate separation pattern (200), FIGS. 15a to 17B, FIGS. 20a, and FIGS. 20b are another exemplary process for forming a gate separation pattern (200), and FIGS. 18a to 19b, FIGS. 20a, and FIGS. 20b are yet another exemplary process for forming a gate separation pattern (200).

[0064] Referring to FIGS. 11a, 11b, 11c, and 11d, active regions (105) and a channel structure (140) can be formed on a substrate (101), a gate structure (GS) intersecting the active regions (105) and the channel structure (140), source / drain regions (150) disposed on the active regions (105), and an interlayer insulating layer (190) can be formed.

[0065] According to one embodiment, alternately stacked sacrificial layers and channel layers (141, 142, 143) are formed on a substrate (101), and at least a portion of the alternately stacked sacrificial layers and channel layers (141, 142, 143) and the substrate (101) is etched to form a trench defining active regions (105), thereby forming active structures (105, 140) comprising active regions (105), sacrificial layers, and channel layers (141, 142, 143). The active structures (105, 140) may include active regions (105) and alternately stacked sacrificial layers and channel layers (141, 142, 143) on the active regions (105).

[0066] According to one embodiment, the sacrificial layers and channel layers (141, 142, 143) may be formed by an epitaxial growth process. The sacrificial layers may be layers that are replaced by a gate dielectric layer (162) and a gate electrode (165) as shown in FIG. 2A through a subsequent process. The sacrificial layers may be made of a material having etch selectivity with respect to the channel layers (141, 142, 143). The sacrificial layers and channel layers (141, 142, 143) may comprise a semiconductor material including, for example, at least one of silicon (Si), silicon germanium (SiGe), and germanium (Ge), but may comprise different materials. For example, the sacrificial layers may comprise silicon germanium (SiGe), and the channel layers (141, 142, 143) may comprise silicon (Si). In an exemplary embodiment, the channel layers (141, 142, 143) may be stacked such that three layers have substantially the same thickness, but are not limited thereto, and the number and thickness of the channel layers may vary depending on the embodiment.

[0067] According to one embodiment, the active regions (105) may be regions defined by the trench. The active regions (105) may be regions formed to protrude onto the upper surface of the substrate (101) by removing a portion of the substrate (101). The active regions (105) may be shaped to protrude in a third direction (D3), which is perpendicular to the substrate (101), and may be formed of the same material as the substrate (101). The active regions (105) may be formed in the shape of a line extending in one direction, for example, a first direction (D1), and may be spaced apart from each other in a second direction (D2).

[0068] In an exemplary embodiment, the active structures (105, 140) may include a first active structure and a second active structure spaced apart from each other in a second direction (D2). The first active structure may include a first active region (105A), first sacrificial layers and first channel layers alternately stacked on the first active region (105A), and the second active structure may include a second active region (105B), second sacrificial layers and second channel layers alternately stacked on the second active region (105B). The first active region (105A) and the second active region (105B) may have the same conductivity type, but are not limited thereto. According to another embodiment, the first active region (105A) may have an N-type conductivity type and the second active region (105B) may have a P-type conductivity type.

[0069] According to one embodiment, field regions (110) may be formed by removing a portion of an insulating material in an area where a portion of the substrate (101) has been removed, so that active regions (105) protrude after the insulating material has been buried. The field regions (110) may be formed to cover a portion of the side of the active regions (105). The upper surface of the field regions (110) may be formed lower than the upper surface of the active regions (105). The field regions (110) may include silicon oxide.

[0070] Next, sacrificial gate structures can be formed across the active structures (105, 140) and parallel to each other. Each of the sacrificial gate structures may be in the form of a line extending in one direction, for example, a second direction (D2). The sacrificial gate structures may be sacrificial structures formed in a region where a gate dielectric layer (162) and a gate electrode (165) are disposed on top of the channel layers (141, 142, 143) as in FIG. 2A through a subsequent process. The sacrificial gate structures may include a sacrificial gate layer and a sacrificial gate capping layer. The sacrificial gate layer may be made of, for example, polysilicon, and the sacrificial gate capping layer may be made of a silicon nitride film. In an exemplary embodiment, each of the sacrificial gate structures may further include a sacrificial gate insulating layer disposed below the sacrificial gate layer. The sacrificial gate insulating layer may be made of a material having an etch selectivity with respect to the sacrificial gate layer, and may be, for example, one of a thermal oxide, silicon oxide, and silicon nitride.

[0071] Next, a gate spacer (164) can be formed on both sidewalls of the sacrificial gate structures. The gate spacer (164) can be formed by forming a film of uniform thickness along the top and side surfaces of the sacrificial gate structures and active structures (105, 140) and then performing anisotropic etching. The gate spacer (164) may include an insulating material, for example, at least one of SiO, SiN, SiCN, SiOC, SiON, and SiOCN. In this specification, the sacrificial gate structures and the gate spacer (164) may be referred to as preliminary gate structures.

[0072] Next, between the sacrifice gate structures, the exposed sacrifice layers and channel layers (141, 142, 143) can be removed to form a recess and expose active regions (105). The recess can be formed deeply to recess a portion of the substrate (101), but is not limited thereto, and the recess can also be formed so that the lower surface of the recess contacts the substrate (101).

[0073] At this stage, a portion may be further removed from the side of the sacrificial layers exposed by the recess. The sacrificial layers exposed by the recess may be selectively etched with respect to the channel layers (141, 142, 143) by, for example, a wet etching process to be partially removed from the side along the first direction (D1).

[0074] Next, source / drain regions (150) may be formed on active regions (105) at least on one side of the sacrificial gate structures and the gate spacer (164). The source / drain regions (150) may be formed by performing an epitaxial growth process within the recess. The source / drain regions (150) may contain impurities, for example, by in-situ doping. In an exemplary embodiment, the source / drain regions (150) may include first source / drain regions (150A) formed on a first active region (105A) and second source / drain regions (150B) formed on a second active region (105B).

[0075] Next, an interlayer insulating layer (190) can be formed, and the sacrificial layers and sacrificial gate structures can be removed. The interlayer insulating layer (190) can be formed by filling and flattening the sacrificial gate structures, gate spacers (164), source drain regions (150), and field regions (110).

[0076] According to one embodiment, sacrificial layers and sacrificial gate structures can be selectively removed with respect to gate spacers (164), interlayer insulating layer (190), and first to third channel layers (141, 142, 143). First, the sacrificial gate structures can be removed to form upper gap regions, and then the sacrificial layers exposed through the upper gap regions can be removed to form lower gap regions. For example, when the sacrificial layers comprise silicon germanium (SiGe) and the first to third channel layers (141, 142, 143) comprise silicon (Si), the sacrificial layers can be selectively removed by performing a wet etching process using peracetic acid and / or a solution (NH4OH:H2O2:H2O=1:1:5) used in the SC1 (Standard clean-1) cleaning process as an etchant.

[0077] Next, a gate structure (GS) can be formed within the upper gap regions and the lower gap regions.

[0078] According to one embodiment, the gate dielectric layer (162) may be formed to conformally cover the inner surfaces of the upper gap regions and the lower gap regions. The gate electrode (165) may be formed to fill the upper gap regions and the lower gap regions. The gate electrode (165) and the gate spacers (164) may be removed from the upper gap regions to a predetermined depth. A gate capping layer (166) may be formed in the region where the gate electrode (165) and the gate spacers (164) have been removed from the upper gap regions. By doing so, a gate structure (GS) comprising the gate dielectric layer (162), the gate electrode (165), the gate spacers (164), and the gate capping layer (166) may be formed.

[0079] Referring to FIGS. 12a through 20b, a gate separation pattern (200) can be formed. The process of forming the gate separation pattern (200) can be performed in various ways. FIGS. 12a through 14b, FIG. 20a, and FIG. 20b are exemplary processes for forming the gate separation pattern (200), FIGS. 12a, FIG. 12b, FIGS. 15a through 17B, FIG. 20a, and FIG. 20b are other exemplary processes for forming the gate separation pattern (200), and FIGS. 12a, FIG. 12b, FIGS. 18a through 19b, FIG. 20a, and FIG. 20b are other exemplary processes for forming the gate separation pattern (200). Below, each process will be described sequentially, and duplicate drawings and duplicate content will be omitted.

[0080] Referring to FIGS. 12a, FIGS. 12b, FIGS. 13a, FIGS. 13B, FIGS. 14a, FIGS. 14b, FIGS. 20a, and FIGS. 20b, a gate separation pattern (200) can be formed.

[0081] Referring to FIGS. 12a and 12b, first, an opening (OP) can be formed that penetrates a gate structure (GS), field regions (110), and an interlayer insulating layer (190). The opening (OP) may be shaped to extend in a first direction (D1) to penetrate a plurality of gate structures (GS), but is not limited thereto. For example, the opening (OP) may be dumbbell-shaped, including a portion in which the width along the second direction (D2) increases and then decreases as it goes toward the first direction (D1). This may be due to material differences between the gate structures (GS), the interlayer insulating layer (190), and the field regions (110). Because the etching rates differ between the gate structures (GS), the interlayer insulating layer (190), and the field regions (110), the region where the gate structures (GS) are located may be deeply etched in a third direction (D3). As a result, the opening (OP) may include a concave or convex portion at the bottom. The opening (OP) may be formed by penetrating to a depth lower than the bottom surface of the gate structure (GS). By the opening (OP), a plurality of gate structures (GS) may be separated to form first gate structures (GS1) and second gate structures (GS2) that are separated from each other while facing each other in a second direction (D2).

[0082] Referring to FIGS. 13a and 13B, a preliminary separation pattern (201') can be formed by filling an insulating material into an opening (OP) and then performing a flattening process so that the upper surface of the interlayer insulating layer (190) is exposed. The preliminary separation pattern (201') may include silicon nitride or a nitride-based material.

[0083] Referring to FIGS. 14a and 14b, an etching mask is placed on the upper surface of the area where the second separation pattern (202) is to be formed, and the area where the second separation pattern (202) is to be formed is removed, thereby forming a second separation pattern opening (OP2). The inclination of the side wall of the second separation pattern opening (OP2) may be perpendicular to the upper surface of the substrate (101), but is not limited thereto. Since the inclination of the side wall of the second separation pattern opening (OP2) may have the same sign as the sign of the inclination of the side wall of the opening (OP), the semiconductor device (100D) of FIG. 9 can be manufactured.

[0084] Referring to FIGS. 20a and 20b, the second separation pattern (202) can be formed by filling the second separation pattern opening (OP2) with an insulating material different from that of the first separation pattern (201) and then performing a flattening process so that the upper surface of the interlayer insulating layer (190) and the first separation pattern (201) is exposed. As a result, the gate separation pattern (200) of FIGS. 20a and 20b can be formed.

[0085] Referring to FIG. 12a, FIG. 12b, FIG. 15a, FIG. 15B, FIG. 16a, FIG. 16B, FIG. 17a, FIG. 17B, FIG. 20a, and FIG. 20b, a gate separation pattern (200) can be formed.

[0086] Referring to FIGS. 12a, 12b, 15a, and 15B, as described above, an opening (OP) can be formed first, and then a sacrificial separation pattern (200') can be filled into the opening (OP). A mask layer can be placed on the upper surface of the sacrificial separation pattern (200'), and the upper surface of the sacrificial separation pattern (200') can be partially exposed to perform a photolithography process and an etching process. The sacrificial separation pattern (200') can be removed in an area corresponding to the area where the second separation pattern (202) is to be formed to form a second separation pattern opening (OP2). The mask layer may be composed of at least one of a silicon-containing material such as silicon oxide, silicon oxynitride, silicon nitride, or polysilicon, a carbon-containing material composed of a hydrocarbon compound or a derivative thereof such as ACL (amorphous carbon layer) or SOH (Spin-On Hardmask), BARC (Bottom Anti-Reflective Coating), a metal, or an organic material. The mask layer may include a material having a sacrificial separation pattern (200') and an etching selectivity ratio.

[0087] Referring to FIG. 16a and FIG. 16B, the second separation pattern (202) can be formed by filling the second separation pattern opening (OP2) with an insulating material different from the first separation pattern (201) and then performing a flattening process so that the upper surface of the interlayer insulating layer (190) and the first separation pattern (201) is exposed.

[0088] Next, referring to FIGS. 17a and 17B, a first separation pattern opening (OP1) can be formed by removing the sacrificial separation pattern (200') using the etching selectivity of the second separation pattern (202) and the sacrificial separation pattern (200'). After filling the first separation pattern opening (OP1) with the first separation pattern (201), a planarization process can be performed so that the upper surfaces of the first separation pattern (201) and the second separation pattern (202) are exposed. As a result, the gate separation pattern (200) of FIGS. 20a and 20b can be formed.

[0089] Referring to FIGS. 12a, FIGS. 12b, FIGS. 18a, FIGS. 18b, FIGS. 19a, FIGS. 19b, FIGS. 20a, and FIGS. 20b, a gate separation pattern (200) can be formed.

[0090] Referring to FIG. 18a and FIG. 18b, as described above, an opening (OP) can be formed first, and then a sacrificial separation pattern (200') can be filled into the opening (OP). A mask layer can be placed on the upper surface of the sacrificial separation pattern (200'), and the upper surface of the sacrificial separation pattern (200') can be partially exposed to perform photolithography and etching processes. The sacrificial separation pattern (200') can be removed in an area corresponding to the area where the first separation pattern (201) is to be formed to form the first separation pattern opening (OP1). According to another embodiment, the slope of the sidewall of the sacrificial separation pattern (200') and the slope of the sidewall of the opening (OP) may have different signs, but are not limited thereto.

[0091] Referring to FIG. 19a and FIG. 19b, the first separation pattern (201) can be formed by filling the first separation pattern opening (OP1) with the first separation pattern (201) and then performing a flattening process so that the upper surface of the sacrificial separation pattern (200') and the interlayer insulation layer (190) is exposed.

[0092] Referring to FIGS. 20a and 20b, the sacrificial separation pattern (200') can be removed using the etching selectivity of the first separation pattern (201) and the sacrificial separation pattern (200'). After filling the area where the sacrificial separation pattern (200') has been removed with the second separation pattern (202), a planarization process can be performed so that the upper surface of the first separation pattern (201) is exposed, thereby forming a gate separation pattern (200) including the first separation pattern (201) and the second separation pattern (202).

[0093] Next, a process of forming contact plugs (180, 280) may be performed. Contact openings that penetrate the interlayer insulation layer (190) on the active regions (105) may be formed. The contact openings may penetrate the interlayer insulation layer (190) and extend into the source / drain regions (150) to make contact with the source / drain regions (150).

[0094] In an exemplary embodiment, the contact openings may have inclined sides that decrease in width toward the substrate (101) according to the aspect ratio, but are not limited thereto.

[0095] Single contact openings among the contact openings may be hole-shaped and connected to one of the first source / drain regions (150A) or the second source / drain regions (150B) of the source / drain region (150).

[0096] Among the contact openings according to one embodiment, a common contact opening may penetrate the interlayer insulating layer (190) and simultaneously contact the first and second source / drain regions (150A, 150B). The common contact opening may be a line extending in the second direction (D2) in a plane or a dumbbell shape. The common contact opening may be formed to penetrate the second separation pattern (202) in the second direction (D2) and the third direction (D3). The common contact opening may be formed to pass between the first source / drain region (150A) and the second source / drain region (150B) to expose a portion of the second separation pattern (202). This may be because the second separation pattern (202) contains a different material from the first separation pattern (201), so that the etching is performed deeply. As a result, the lower portion of the common contact plug (280) described below is formed between the source / drain regions (150), and since the contact area between the common contact plug (280) and the source / drain regions (150) is larger than the contact area between the single contact plug (180) and the source / drain regions (150), the resistance of the semiconductor device (100) can be reduced and the electrical characteristics improved.

[0097] Next, referring to FIGS. 1 to 3, a single contact plug (180) and a common contact plug (280) can be formed by filling the contact openings with a conductive material and performing a flattening process.

[0098] In this step, a barrier layer (180b, 280b) covering the side and bottom surfaces of the contact openings is first conformally formed, and a plug layer (180a, 280a) can be formed by embedding a conductive material in the contact openings and performing a flattening process so that the upper surface of the interlayer insulating layer (190) is exposed. Accordingly, a single contact plug (180) filling the single contact openings and a common contact plug (280) filling the common contact openings can be formed.

[0099] Although various embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto, and it will be obvious to those with average knowledge in the art that various modifications and variations are possible within the scope of the technical concept of the present disclosure as described in the claims. Furthermore, the above-described embodiments may be implemented by deleting some components, and each embodiment may be implemented in combination with one another. Explanation of the symbols

[0100] 101: Board 105: Active regions 110: Field Areas 140: Channel structure 150: Source / Drain Areas 180: Single contact plug 190: Interlayer insulation layer 200: Gate separation pattern 280: Common contact plug GS: Gate structure

Claims

Claim 1 A first active region extending in a first direction parallel to the surface of the substrate on the substrate; a second active region extending in parallel to the first active region on the substrate; a field region disposed between the first active region and the second active region; a plurality of first gate structures disposed parallel to the substrate and extending in a second direction parallel to the surface of the substrate and intersecting the first direction; second gate structures on the substrate that intersect the second active region and extend in the second direction and face the first gate structures in the second direction; a gate separation pattern comprising a portion disposed between the first gate structures and the second gate structures; a first source / drain region disposed on the first active region and disposed between the first gate structures; and a second source / drain region disposed on the second active region and disposed between the second gate structures, wherein the gate separation pattern comprises a plurality of first separation patterns including a portion in which the width of the second direction changes according to the first direction. A semiconductor device comprising a plurality of first separation patterns and a second separation pattern extending in a third direction intersecting the upper surface of the substrate between the plurality of first separation patterns and contacting the field region, and comprising a material different from the plurality of first separation patterns, wherein at least some of the plurality of first separation patterns include a first sidewall in contact with the second separation pattern and a second sidewall opposite to the first sidewall, wherein with respect to the first direction, the first sidewall has a first slope and the second sidewall has a second slope different from the first slope. Claim 2 A semiconductor device according to claim 1, further comprising a common contact plug connected to the first and second source / drain regions, wherein the lowest level of the common contact plug according to the third direction is equal to or lower than the level according to the third direction in which the source / drain regions have a maximum width according to the second direction. Claim 3 In claim 2, the common contact plug is a semiconductor device that penetrates at least a portion of the second separation pattern in the third direction. Claim 4 A semiconductor device according to claim 1, wherein the first slope and the second slope have the same sign. Claim 5 A semiconductor device according to claim 1, wherein the first separation pattern comprises: a first portion disposed between a first gate structure and a second gate structure in the second direction and having a first width in the second direction; and a second portion disposed between a first source / drain region and a second source / drain region, connected to the first portion, and having a second width smaller than the first width. Claim 6 In claim 1, the lowest level of the second separation pattern according to the third direction is equal to or higher than the lowest level of each of the plurality of first separation patterns. Claim 7 A semiconductor device according to claim 1, wherein in the second direction, the maximum width of the plurality of first separation patterns and the maximum width of the second separation pattern are the same. Claim 8 A first active region extending in a first direction parallel to the surface of the substrate on the substrate; a second active region extending in parallel to the first active region on the substrate; a plurality of first gate structures arranged in parallel on the substrate, intersecting the first active region and extending in a second direction parallel to the surface of the substrate and intersecting the first direction; second gate structures extending in the second direction intersecting the second active region on the substrate and facing the first gate structures in the second direction; a gate isolation pattern comprising a portion disposed between the first gate structures and the second gate structures; a plurality of first source / drain regions disposed on the first active region and disposed between the first gate structures; a plurality of second source / drain regions disposed on the second active region and disposed between the second gate structures; A semiconductor device comprising a common contact plug connected to the plurality of first source / drain regions and the plurality of second source / drain regions, wherein the gate separation pattern comprises: a plurality of first separation patterns including a portion in which the width of the second direction changes according to the first direction; and at least one second separation pattern extending in a third direction intersecting the upper surface of the substrate between the plurality of first separation patterns and comprising a material different from the plurality of first separation patterns, wherein the lowest level of the common contact plug is equal to or lower than at least some of the levels in which each of the first source / drain regions and the second source / drain regions has a maximum width, and the lowest level of the second separation pattern is equal to or higher than the lowest level of each of the plurality of first separation patterns. Claim 9 A semiconductor device according to claim 8, further comprising a single contact plug connected to some of the plurality of first source / drain regions, wherein the lowest level of the common contact plug is lower than the lowest level of the single contact plug. Claim 10 A semiconductor device according to claim 8, further comprising third separation patterns disposed on the outer side of each of the plurality of first separation patterns.

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