Storage device, controller and memory device

Abstract

Embodiments of the present disclosure allow a storage device to efficiently perform a refresh operation on a memory block by comparing the number of first error bits of a first word line included in a first weak word line group of a target memory block during a first period with a preset first reference value, comparing the difference between the number of second error bits of a second word line included in a strong word line group of the target memory block and the first reference value with a preset second reference value, and setting a data movement range of the target memory block to be moved to a preset space based on the result of comparing the difference and the second reference value.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a controller, a memory device, and a storage device. Background Technology

[0002] The storage device may include at least one memory for storing data. The storage device may include a controller for controlling the operation of at least one memory.

[0003] The controller can control a memory device (e.g., volatile memory / non-volatile memory). For example, it can execute or control the movement of data contained in memory by setting a range within a memory block included in the memory device.

[0004] In addition, memory devices may include not only devices that store data on magnetic disks, such as hard disk drives (HDDs), but also devices that store data in non-volatile memory, such as solid-state drives (SSDs), Universal Flash Storage (UFS) devices, and embedded MMC (eMMC) devices. For example, to ensure the reliability of data stored in a memory device, a refresh operation may be performed in which the stored data is moved to a pre-configured space or rewritten. The problem to be solved

[0005] The embodiments of the present disclosure provide a method to prevent the problem of shortening the lifespan of a memory device by performing a refresh operation even on unnecessary areas, by presenting a criterion for determining an area within a memory block that requires a refresh. means of solving the problem

[0006] Embodiments of the present disclosure may provide a storage device comprising a memory including a plurality of memory blocks including a plurality of word lines, and a controller that compares a first error bit number of a first word line included in a first weak word line group of a target memory block during a first period with a preset first reference value, compares the difference between a second error bit number of a second word line included in a strong word line group of the target memory block and the first reference value with a preset second reference value, and sets a data movement range of a target memory block to be moved to a preset space based on the result of comparing the difference and the second reference value.

[0007] Embodiments of the present disclosure may provide a controller comprising: an error bit search unit that checks the number of first error bits of a first word line included in a first weak word line group of a target memory block located outside of a first period, and checks the number of second error bits of a second word line included in a strong word line group of the target memory block based on the result of comparing the number of first error bits with a preset first reference value; and a movement range determination unit that compares the number of first error bits with a first reference value, compares the difference between the number of second error bits and the first reference value with a preset second reference value, and sets the data movement range of the target memory block to be moved to a preset space based on the result of comparing the difference with the second reference value.

[0008] Embodiments of the present disclosure may provide a memory device comprising a first memory block including a target memory block including a first weak word line group and a strong word line group, and a second memory block to which data of the target memory block is to be moved, wherein the range of movement for the data of the target memory block to be moved to the second memory block is determined based on the result of comparing a first error bit number of a first word line included in the first weak word line group during a first period with a preset first reference value and the result of comparing a difference between a second error bit number of a second word line included in the strong word line group and the first reference value with a preset second reference value. Effects of the invention

[0009] According to the embodiments of the present disclosure, by providing criteria for determining an area within a memory block that requires a refresh operation, the problem of the lifespan of a memory device being shortened due to excessive refresh operations can be solved. Brief explanation of the drawing

[0010] FIG. 1 is a drawing showing an example of a schematic configuration of a storage device according to embodiments of the present disclosure. FIG. 2 is a drawing showing an example of a schematic configuration of a memory device according to embodiments of the present disclosure. FIG. 3 is a diagram showing an example of a schematic configuration of a controller according to embodiments of the present disclosure. FIG. 4 is a diagram showing the configuration of a target memory block in which a refresh operation is executed according to one embodiment of the present disclosure. FIG. 5 is a flowchart for explaining the process of determining whether to perform a refresh operation for a target memory block according to one embodiment of the present disclosure. FIG. 6 is a diagram showing the configuration of a target memory block in which a refresh operation is executed according to other embodiments of the present disclosure. FIG. 7 is a flowchart for explaining the process of determining the range of a target memory block on which a refresh operation is performed according to other embodiments of the present disclosure. FIG. 8 is a diagram illustrating a refresh operation performed in a target memory block according to other embodiments of the present disclosure. Specific details for implementing the invention

[0011] In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral whenever possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions could obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless otherwise explicitly stated.

[0012] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0013] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0014] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0015] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0016] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0017] FIG. 1 is a drawing showing an example of a schematic configuration of a storage device according to embodiments of the present disclosure.

[0018] Referring to FIG. 1, a storage device (100) according to embodiments of the present disclosure may include at least one memory (110). The storage device (100) may include a controller (120) that controls the operation of the memory (110).

[0019] The memory (110) may be a volatile memory such as, for example, DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, but the embodiments of the present disclosure are not limited thereto. The memory (110) may be a non-volatile memory such as NAND flash memory, 3D NAND flash memory, NOR flash memory, etc. Additionally, depending on the case, a part of the memory (110) included in the storage device (100) may be a volatile memory and another part may be a non-volatile memory.

[0020] Additionally, the memory (110) may be one of various types of memory, such as resistive RAM, phase change memory, magnetoresistance memory, ferroelectric memory, or spin injection magnetization inversion memory. Additionally, the memory (110) may, in some cases, be a processing-in-memory including computational functions or data processing functions.

[0021] The memory (110) may include a plurality of memory cells that store data. A memory cell may, for example, be a single-level cell that stores 1 bit of data. Alternatively, a memory cell may be a multi-level cell that stores 2 bits of data or a triple-level cell that stores 3 bits of data. A memory cell may store 4 bits or more of data, and may operate by changing the type of memory cell. For example, a memory cell may operate as a single-level cell to store data, and the same memory cell may operate as a triple-level cell to store data. Two or more memory cells may form a unit storage area such as a page.

[0022] The controller (120) can receive a command from the outside and control the operation of the memory (110) based on the received command. Additionally, the controller (120) can control the operation of the memory (110) based on a command generated internally. In this specification, a command received by the controller (120) from the outside may be referred to as an external command, and a command generated internally by the controller (120) may be referred to as an internal command.

[0023] The controller (120) can control the operation of the memory (110) based on external commands or internal commands. The controller (120) can, for example, control the operation of writing data to the memory (110). The controller (120) can control the operation of reading data written to the memory (110). Data can be transmitted and received between the controller (120) and the memory (110). Additionally, the controller (120) can control all or part of the data contained in the memory (110) to be moved to a preset space. The aforementioned preset space may include a specific memory block within the memory.

[0024] The controller (120) can control data preservation operations (e.g., refresh operations, patrol scrub operations, etc.) or erasure operations for data written to the memory (110) depending on the type of memory (110).

[0025] The controller (120) can perform background operations associated with memory (110) based on external commands received from an external host device (200) or based on internal commands to maintain and improve the operational performance of the storage device (100).

[0026] Background operations may include, for example, one or more of garbage collection, wear leveling, read reclaim, or bad block management operations. The controller (120) can improve the operational performance of the storage device (100) or prevent the operational performance from degrading by controlling the background operations.

[0027] The controller (120) can control the operation of the memory (110) based on a command received from the host device (200). The controller (120) can provide the processing result corresponding to the operation corresponding to the command to the host device (200). The controller (120) can transmit data or a response signal to the host device (200).

[0028] The host device (200) may be, for example, a computer, UMPC (Ultra Mobile PC), workstation, PDA (Personal Digital Assistant), tablet, mobile phone, smartphone, e-book, PMP (Portable Multimedia Player), portable game console, navigation device, black box, digital camera, DMB (Digital Multimedia Broadcasting) player, smart television, digital voice recorder, digital voice player, digital video recorder, digital video player, digital video recorder, digital video player, storage constituting a data center, one of various electronic devices constituting a home network, one of various electronic devices constituting a telematics network, RFID (Radio Frequency Identification) device, a mobile device capable of driving under human control or autonomous driving (e.g., vehicle, robot, drone), etc. Alternatively, the host device (200) may be a virtual / augmented reality device that provides two-dimensional or three-dimensional virtual reality images or augmented reality images. The host device (200) may be any one of various electronic devices that require a storage device (100) capable of storing data in addition to the above.

[0029] The host device (200) may include at least one operating system. The operating system can manage and control the overall functions and operations of the host device (200) and control the interaction between the host device (200) and the storage device (100). The operating system may be classified into a general operating system and a mobile operating system depending on the mobility of the host device (200).

[0030] The controller (120) and the host device (200) may be separate devices. In some cases, the controller (120) and the host device (200) may be integrated into a single device. Alternatively, some configurations or functions of the controller (120) may be included in the host device (200). For convenience of explanation, the controller (120) and the host device (200) are described below as separate devices.

[0031] The storage device (100) may further include a working memory to provide a buffer used for operation control by the controller (120).

[0032] The working memory may be a volatile memory such as, for example, SRAM, DRAM, etc., but is not limited thereto. Depending on the case, the working memory may be located outside the controller (120) or inside the controller (120).

[0033] The controller (120) can control various operations of the memory (110) using the working memory. For example, the controller (120) can load data representing the correspondence between a logical address (or logical block address, logical page number) indicated by the host device (200) and a physical address (or physical block address, virtual page number) of the memory (110) into the working memory and perform write operations or read operations.

[0034] The controller (120) may, depending on the case, load the entire data into the working memory to perform control, or load only a part of the data into the working memory to perform control.

[0035] FIG. 2 is a drawing showing an example of a schematic configuration of a memory device according to embodiments of the present disclosure.

[0036] Referring to FIG. 2, a memory device (110) according to embodiments of the present disclosure may include a memory cell array (210), an address decoder (220), a read and write circuit (230), control logic (240), and a voltage generation circuit (250), etc.

[0037] The memory cell array (210) of the present disclosure may include n storage blocks SB_1, SB_2, SB_n. The present disclosure may refer to the aforementioned storage blocks as memory blocks, and may refer to SB_1 as the first memory block and SB_2 as the second memory block.

[0038] In a plurality of memory blocks, a plurality of word lines (WL) and a plurality of bit lines (BL) are arranged, and a plurality of memory cells (MC) may be arranged. Additionally, a plurality of memory blocks may include a word line group that includes at least one word line among a plurality of word lines.

[0039] Two or more memory cells contained in each of a plurality of memory blocks can constitute a single page, which is a unit storage area. Each of the plurality of memory blocks may refer to a block containing a plurality of pages.

[0040] The aforementioned word line group may be classified into one of weak word lines, normal word lines, and strong word lines according to preset criteria. The preset criteria may include classifying the word line group into weak word lines, normal word lines, and strong word lines in order of highest sum of bit errors detected for each word line group. Depending on the criteria set, there may be two or more weak word lines and strong word lines.

[0041] Multiple memory blocks can be connected to an address decoder (220) through multiple word lines. Multiple memory blocks can be connected to a read and write circuit (230) through multiple bit lines.

[0042] Each of the multiple memory blocks may include multiple memory cells. For example, the multiple memory cells may be non-volatile memory cells and may be composed of non-volatile memory cells having a vertical channel structure.

[0043] The memory cell array (210) may be configured as a memory cell array with a two-dimensional structure, and in some cases, may be configured as a memory cell array with a three-dimensional structure.

[0044] Meanwhile, each of the plurality of memory cells included in the memory cell array (210) can store at least 1 bit of data.

[0045] For example, each of the plurality of memory cells included in the memory cell array (210) may be a single-level cell (SLC) that stores 1 bit of data.

[0046] As another example, each of the plurality of memory cells included in the memory cell array (210) may be a multi-level cell (MLC) that stores 2 bits of data.

[0047] As another example, each of the multiple memory cells included in the memory cell array (210) may be a triple-level cell (TLC) that stores 3 bits of data.

[0048] As another example, each of the plurality of memory cells included in the memory cell array (210) may be a Quad-Level Cell (QLC) that stores 4 bits of data.

[0049] As another example, the memory cell array (210) may include a plurality of memory cells each storing 5 bits or more of data.

[0050] According to FIG. 2, an address decoder (220), a read and write circuit (230), a control logic (240), and a voltage generation circuit (250), etc., can operate as peripheral circuits that drive a memory cell array (210).

[0051] The address decoder (220) can be connected to the memory cell array (210) through a plurality of word lines.

[0052] The address decoder (220) can be configured to operate in response to the control of the control logic (240).

[0053] The address decoder (220) can receive an address through an input / output buffer inside the memory device (110). The address decoder (220) can be configured to decode a block address among the received addresses. The address decoder (220) can select at least one memory block according to the decoded block address.

[0054] The address decoder (220) can receive a read voltage (Vread) and a pass voltage (Vpass) from the voltage generation circuit (350).

[0055] The address decoder (220) can apply a read voltage to a selected word line (WL) within a selected memory block and apply a pass voltage to the remaining unselected word lines (WL) when applying a read voltage during a read operation.

[0056] When a program verification operation is performed, the address decoder (220) can apply a verification voltage generated by the voltage generation circuit (250) to a selected word line within a selected memory block and apply a pass voltage to the remaining unselected word lines.

[0057] The address decoder (220) may be configured to decode column addresses among the received addresses. The address decoder (220) may transmit the decoded column addresses to the read and write circuit (330).

[0058] The read operation and program operation of the memory device (110) can be performed in page units. The address received when requesting the read operation and program operation may include one or more of a block address, a row address, and a column address.

[0059] The address decoder (220) can select one memory block and one word line according to the block address and row address. The column address can be decoded by the address decoder (220) and provided to the read and write circuit (230).

[0060] The address decoder (220) may include one or more of a block decoder, a row decoder, a column decoder, and an address buffer.

[0061] The read and write circuit (230) may include a plurality of page buffers (PB). The read and write circuit (230) may operate as a "read circuit" during a read operation of the memory cell array (210) and as a "write circuit" during a write operation.

[0062] The aforementioned read and write circuit (230) is also referred to as a page buffer circuit or data register circuit that includes a plurality of page buffers. Here, the read and write circuit (230) may include a data buffer responsible for data processing functions, and, in some cases, may additionally include a cache buffer responsible for caching functions.

[0063] A plurality of page buffers can be connected to a memory cell array (210) through a plurality of bit lines. During read operations and program verification operations, the plurality of page buffers can continuously supply sensing current to the bit lines connected to the memory cells to sense the threshold voltage (Vth) of the memory cells, and can detect through a sensing node that the amount of current flowing changes according to the program state of the corresponding memory cell and latch it as sensing data.

[0064] The read and write circuit (230) can operate in response to page buffer control signals output from the control logic (240).

[0065] The read and write circuit (230) senses the data of the memory cell during a read operation, temporarily stores the read data, and then outputs the data (DATA) to the input / output buffer of the memory device (110). As an exemplary embodiment, the read and write circuit (230) may include, in addition to page buffers or page registers, a column selection circuit, etc.

[0066] The control logic (240) can be connected to an address decoder (220), a read and write circuit (230), and a voltage generation circuit (250), etc. The control logic (240) can receive a command (CMD) and a control signal (CTRL) through the input / output buffer of the memory device (110).

[0067] The control logic (240) may be configured to control the general operation of the memory device (110) in response to a control signal (CTRL). The control logic (240) may output a control signal to adjust the precharge potential level of the sensing nodes of a plurality of page buffers.

[0068] The control logic (240) can control the read and write circuit (230) to perform a read operation of the memory cell array (210). The voltage generation circuit (250) can generate a read voltage and a pass voltage used during a read operation in response to a voltage generation circuit control signal output from the control logic (240).

[0069] Meanwhile, each memory block of the aforementioned memory device (110) may be composed of multiple pages corresponding to multiple word lines and multiple strings corresponding to multiple bit lines.

[0070] In a memory block, multiple word lines and multiple bit lines may be arranged intersectingly. For example, each of the multiple word lines may be arranged in a row direction, and each of the multiple bit lines may be arranged in a column direction. As another example, each of the multiple word lines may be arranged in a column direction, and each of the multiple bit lines may be arranged in a row direction.

[0071] A memory cell connected to one of a number of word lines and one of a number of bit lines can be defined. A transistor can be placed in each memory cell.

[0072] For example, a transistor placed in a memory cell may include a drain, a source, and a gate, etc. The drain (or source) of the transistor may be connected directly to the corresponding bit line or via another transistor. The source (or drain) of the transistor may be connected directly to a source line (which may be ground) or via another transistor. The gate of the transistor may include a floating gate surrounded by an insulator and a control gate to which a gate voltage is applied from a word line.

[0073] In each memory block, a first selection line (also called a source selection line or drain selection line) may be further disposed outside the first outermost word line that is more adjacent to the read and write circuit (230) among the two outermost word lines, and a second selection line (also called a drain selection line or source selection line) may be further disposed outside the other second outermost word line.

[0074] In some cases, one or more dummy word lines may be placed between the first outermost word line and the first selection line. Additionally, one or more dummy word lines may be placed between the second outermost word line and the second selection line.

[0075] The storage block (111) can store user data in response to a request from the host device (200). A portion of the storage block (111) may store metadata containing various information used for the operation of the memory (110). Alternatively, metadata may be stored in a storage area separate from the storage block (111) that stores user data.

[0076] The read operation and program operation (write operation) of the aforementioned memory block can be performed on a page basis, and the erase operation can be performed on a memory block basis.

[0077] The movement range for the data of a target memory block to be moved to a preset space may be determined by a judgment of a controller (120) based on the number of error bits of a weak word line in a weak word line group and the number of error bits of a strong word line in a strong word line group included in the target memory block of the memory device (110) of the present disclosure. The aforementioned preset space may include other memory blocks other than the target memory block included in the memory device (110).

[0078] FIG. 3 is a block diagram schematically showing a controller according to embodiments of the present invention.

[0079] Referring to FIG. 3, the controller (120) of the present disclosure includes an error bit search unit (310) that checks the number of error bits in a word line included in a memory block, and a data movement range determination unit (320) that determines the range of data to be moved within the memory block that needs to be refreshed based on the number of error bits in the word line.

[0080] Alternatively, as described above, the controller of the present disclosure may further include a control circuit and an auxiliary memory.

[0081] The controller (120) of the present disclosure can control the operation of the memory (110) based on external commands or internal commands. The controller (120) can, for example, control the operation of writing data to the memory (110) or the operation of reading written data. Data can be transmitted and received between the controller (120) and the memory (110). Additionally, the controller (120) can control all or part of the data contained in the memory (110) to be moved to a preset space. The aforementioned preset space may include a specific memory block within the memory.

[0082] The controller (120) can control data preservation operations (e.g., refresh operations, patrol scrub operations, etc.) or erasure operations for data written to the memory (110) depending on the type of memory (110).

[0083] The present disclosure controller (120) can determine the number of first error bits of a first word line included in a first weak word line group of a target memory block located outside of a first period through an error bit search unit (310), determine the number of second error bits of a second word line included in a strong word line group of the target memory block based on the result of comparing the number of first error bits with a preset first reference value, and can determine the number of data movement of the target memory block to be moved to a preset space based on the result of comparing the difference with the second reference value through a movement range determination unit (320), compare the number of first error bits with the first reference value, compare the difference between the number of second error bits and the first reference value with a preset second reference value, and set the data movement range of the target memory block to be moved to a preset space based on the result of comparing the difference with the second reference value.

[0084] FIG. 4 is a diagram showing the configuration of a target memory block in which a refresh operation is executed according to one embodiment of the present disclosure.

[0085] Referring to FIG. 4, the memory device (110) of the present disclosure includes a plurality of memory blocks, and each memory block includes a plurality of word lines and a plurality of bit lines. For convenience of explanation, the present disclosure describes one memory block as an example.

[0086] Recently, many methods have been studied to increase capacity while reducing the NAND size. As for the aforementioned methods, increasing the page size or increasing the number of word lines included in the memory block may be considered. However, if the capacity increases while the NAND size decreases, retention phenomena or read disturb phenomena may occur. To solve this, the present disclosure proposes a method of detecting the number of bit errors per word line and moving data included in the memory to another space based on the aforementioned number of bit errors. The present disclosure refers to moving data to another space included in the memory as "refresh."

[0087] According to FIG. 4, when the storage device (100) of the present disclosure determines a refresh for a target memory block (BL), it can move data included in word line 1 (WL1) to word line 9 (WL9) included in the target memory block to a preset space. The number of word lines and the refresh range described above are merely examples, and can be set and performed with various numbers or ranges as needed.

[0088] In this disclosure, a memory block to which the scope and whether to perform a refresh operation are determined is referred to as a target memory block (BL). As described above, the target memory block may include a plurality of word lines.

[0089] For example, the storage device (100) of the present disclosure may determine whether a refresh operation is required by setting a target memory block and calculating the number of reads (Block read count) of the target memory block, and if the number of reads is greater than or equal to a preset reference value, determine to perform a refresh operation on the entire target memory block.

[0090] As another example, the storage device (100) of the present disclosure may check the number of error bits per word line at a predetermined time cycle (Cycle), and if the largest number of error bits is greater than or equal to a preset reference value, determine to perform a refresh operation on the entire target memory block.

[0091] As another example, the storage device (100) of the present disclosure checks the number of error bits per word line for every read cycle of a target memory block, and if the largest number of error bits is greater than or equal to a preset reference value, it can decide to perform a refresh operation on the entire target memory block.

[0092] In this disclosure, the entity determining whether to perform a refresh operation is referred to as a storage device (100), but is not limited thereto and may also be referred to as a controller (120) included in the storage device (100) determining whether to perform a refresh operation.

[0093] Specifically, with reference to FIG. 4, the memory device (110) of the present disclosure may include a core region where memory cells are gathered and an auxiliary region corresponding to the remaining region of the core region that supports the operation of the memory cell array.

[0094] The aforementioned core region may consist of pages (PG) and strings (STR). In this core region, multiple word lines and multiple bit lines may be arranged intersectingly.

[0095] Multiple word lines may be connected to a separate decoder, and multiple bit lines may be connected to another decoder. Between the multiple bit lines and the decoder, there may be data registers corresponding to read and write circuits.

[0096] Multiple word lines correspond to multiple pages.

[0097] A controller (120) included in the storage device (100) of the present disclosure can check the number of error bits in word line 1 (WL1) to determine whether a refresh operation is required.

[0098] The controller (120) of the present disclosure may determine that if the number of error bits of word line 1 (WL1) is greater than or equal to a preset reference value, a refresh operation is required for the entire target memory block containing word line 1.

[0099] The controller (120) of the present disclosure can determine whether to refresh the target memory block by checking the number of error bits in word line 2 (WL1) and comparing it with the preset reference value if the number of error bits in word line 1 (WL1) is less than a preset reference value.

[0100] The above process can be performed until the number of error bits for all word lines is checked, and can be performed periodically as needed.

[0101] FIG. 5 is a flowchart for explaining the process of determining whether to perform a refresh operation for a target memory block according to one embodiment of the present disclosure.

[0102] Referring to FIG. 5, the controller of the present disclosure can determine whether to perform a refresh operation for the entire block while sequentially checking the number of error bits of the word lines included in the block.

[0103] The controller of the present disclosure may initialize a variable (K) related to the order of word lines included in a memory block as needed (S500).

[0104] The controller of the present disclosure can determine a target memory block to determine whether to perform a refresh operation and can determine the order of word lines to check the number of error bits. The aforementioned variable K is an integer greater than or equal to 0 and can be initially set to 1.

[0105] When a variable (K) related to the order of word lines is initialized, the controller of the present disclosure can check the number of error bits of the first word line (S510).

[0106] As described above, each memory block included in the memory may include multiple memory cells and multiple word lines. Additionally, the word lines may read data stored in the memory cells and store the corresponding data.

[0107] Meanwhile, an error may occur during the process of reading or writing data contained in a memory cell, and if an error is detected, the bit where the error occurred in the memory cell may be set as an error bit. Therefore, an error may exist in the data that the word line reads and stores through the memory cell, and the number of error bits for the data can be checked by the controller.

[0108] When the number of error bits is checked, the controller of the present disclosure can compare the checked number of error bits with a preset reference value and check whether the number of error bits is greater than or equal to the preset reference value (S520).

[0109] If the number of error bits is greater than or equal to a preset threshold value, a refresh operation can be performed on the entire target memory block (S530).

[0110] If the number of error bits is less than a preset threshold value, 1 is added to the variable (K) associated with the order of the word lines (S540).

[0111] This is to check the number of error bits in the word lines set in the following order.

[0112] However, if the variable (K) related to the reset word line order is greater than or equal to the preset N, it is determined that the error bit count check for all word lines is finished and that a refresh operation for the target memory block is not necessary (S550).

[0113] The aforementioned N is an integer greater than or equal to 0, used to determine whether a check of the number of error bits has been performed for all word lines, and can be set to an integer greater than the number of word lines included in the target memory block. For example, if the number of word lines included in the target memory block is 99, the aforementioned N can be set to 100.

[0114] If the variable (K) related to the order of the reset word lines is less than a preset N, the controller of the present disclosure can check the number of error bits for the word lines set in the next order and compare it with a preset reference value to determine whether to perform a refresh on the target memory block.

[0115] The above process may be repeated until the check of the number of error bits for all word lines is finished or until it is determined that a refresh operation is required for the target memory block.

[0116] FIG. 6 is a diagram showing the configuration of a target memory block in which a refresh operation is executed according to other embodiments of the present disclosure.

[0117] Referring to FIG. 6, the memory device (110) of the present disclosure may include a plurality of word line groups including a plurality of word lines and a plurality of bit lines.

[0118] A word line group may include a preset number of word lines and bit lines included in a target memory block.

[0119] In this disclosure, among each word line group, a word line group containing a word line with a large number of bit errors may be referred to as a weak word line group, a word line group containing a word line with a small number of bit errors may be referred to as a strong word line group, and the remaining word line groups may be referred to as basic word line groups. As described above, the number of weak word line groups and strong word line groups is not limited to one, but may be set to multiple according to the established criteria.

[0120] In addition, the classification of weak word line groups, strong word line groups and basic word line groups is not fixed and may vary depending on the number of bit errors in the word lines.

[0121] The controller (120) of the present disclosure can determine a range of memory blocks for which a refresh operation is required based on the number of bit errors in the word lines included in each word line group, and can determine that a refresh operation is performed only for the corresponding range.

[0122] For example, the controller (120) of the present disclosure may compare the number of first error bits of a first word line included in a first weak word line group of a target memory block during a first period with a preset first reference value, and compare the difference between the number of second error bits of a second word line included in a strong word line group of a target memory block and the first reference value with a preset second reference value, and set a data movement range of the target memory block to be moved to a preset space based on the result of comparing the difference and the second reference value.

[0123] As another example, the controller (120) of the present disclosure may determine the second error bit number of a second word line included in a strong word line of a target memory block and determine the difference between the second error bit number and the first reference value if the first error bit number of the first word line mentioned above is greater than or equal to a first reference value.

[0124] As another example, if the difference between the second error bit number and the first reference value is greater than or equal to the second reference value, the controller (120) of the present disclosure may set only the first weak word line group of the target memory block as the data movement range and exclude areas other than the first weak word line group of the target memory block from the data movement range.

[0125] As another example, the controller (120) of the present disclosure may check the number of third error bits of a third word line included in a second word line group other than a first word line group in a target memory block during a second period after a first period. The controller (120) of the present disclosure may not check the number of error bits for an area where a refresh was performed during the previous period in order to determine whether to perform a refresh and the area to perform in the next period, and may exclude it from the word line group to be refreshed.

[0126] In this disclosure, the region of the target memory block where the refresh is performed may be referred to as the region in an erased state. The size of the region of the target memory block to be refreshed may be variable and may vary depending on the state of the memory device.

[0127] As another example, the controller (120) of the present disclosure may set the entire target memory block as a data movement range if the difference between the second error bit number and the first reference value is less than the second reference value.

[0128] As another example, the controller (120) of the present disclosure may decide to skip a data movement operation for a target memory block during a first period if the number of first error bits is less than a first reference value.

[0129] As another example, the controller (120) of the present disclosure may set the first word line group of the target memory block as the data movement range if at least one of the first error bit number of the first word line included in the first word line group or the third error bit number of the third word line is greater than or equal to the first reference value and the difference between the second error bit number and the first reference value is greater than or equal to the second reference value.

[0130] As another example, the controller (120) of the present disclosure may check the number of second error bits if at least one of the number of first error bits of a first word line included in a first word line group or the number of fourth error bits of a fourth word line included in a second word line group is greater than or equal to a first reference value, and compare the difference between the number of second error bits and the first reference value with the second reference value.

[0131] As another example, the controller (120) of the present disclosure may set only the first and second word line groups of the target memory block as the data movement range if the difference between the second error bit number and the first reference value is greater than or equal to the second reference value, and exclude the area other than the first and second word line groups of the target memory block from the data movement range, and if the difference between the second error bit number and the first reference value is less than the second reference value, set the entire target memory block as the data movement range.

[0132] The operation by the controller (120) of the present disclosure described above may be performed by an error bit search unit (310) or a data movement range determination unit (320) included in the controller.

[0133] The core area, auxiliary area, pages (PG) and strings (STR), etc. of the memory device (110) shown in FIG. 6 are the same as those in FIG. 4, so a detailed description is omitted.

[0134] FIG. 7 is a flowchart for explaining the process of determining the range of a target memory block on which a refresh operation is performed according to other embodiments of the present disclosure.

[0135] Referring to FIG. 7, the controller of the present disclosure can determine the range in which a refresh operation is to be performed within a target memory block based on the number of error bits for a word line group included in the target memory block through the following process.

[0136] The controller of the present disclosure checks the number of error bits for a word line included in a weak word line group (S700).

[0137] As described above, a word line group may include a preset number of word lines, and a weak word line can be determined by checking the number of error bits for each word line.

[0138] The controller of the present disclosure determines the word line having the highest number of error bits among the word lines included in the weak word line group as the weak word line (S710).

[0139] The present disclosure may refer to the number of error bits of the word line described above as the number of error bits of the word line included in the weak word line group or the number of error bits of the weak word line, and likewise, the number of error bits for the word line having the higher number of error bits among the number of error bits of the word line included in the strong word line may refer to the number of error bits of the word line included in the strong word line group or the number of error bits of the strong word line.

[0140] One target memory block may include at least one weak word line group or at least one strong word line group, and each word line group may include at least one weak word line or at least one strong word line.

[0141] When checking the number of error bits of the aforementioned weak word line, the controller of the present disclosure compares the number of error bits of the weak word line with a preset first reference value to check whether the number of error bits of the weak word line is greater than or equal to the preset first reference value (S720).

[0142] If the number of error bits of a word line included in a weak word line group is not greater than or equal to a preset first reference value, the controller of the present disclosure determines that a refresh operation for a memory block including a weak word line group is not necessary, skips the refresh for the target memory block, and can perform a determination on whether to refresh the next target memory block.

[0143] However, if the number of error bits of a word line included in a weak word line group is greater than or equal to a preset first reference value, the controller of the present disclosure checks the number of bit errors for each word line included in a strong word line group (S730).

[0144] The controller of the present disclosure determines a strong word line based on the number of bit errors of each word line included in a strong word line group (S740).

[0145] When a strong word line is determined, the controller of the present disclosure determines the difference between the number of error bits of the strong word line and a first reference value, and compares the difference with a second reference value to determine whether the difference is greater than or equal to the second reference value (S750).

[0146] If the aforementioned difference is greater than or equal to a second reference value, the controller of the present disclosure limits the scope of refresh execution to a weak word line group (S760).

[0147] On the other hand, if the aforementioned difference is less than the second reference value, the controller of the present disclosure determines the refresh execution range to be the entire target memory block (S770).

[0148] The present disclosure can prevent the performance of a refresh operation on a memory area that does not require a refresh operation by determining whether a refresh is required for a target memory block based on the number of error bits in each word line included in a weak word line group, and if it is determined that a refresh is required, determining the range of refresh operation for the entire or partial area of ​​the target memory block based on the number of error bits in each word line included in a strong word line group.

[0149] FIG. 8 is a drawing for illustrating a refresh performed in a target memory block according to other embodiments of the present disclosure.

[0150] Referring to FIG. 8, the memory device of the present disclosure may include a plurality of memory blocks, and each memory block may include a plurality of word line groups.

[0151] For example, as illustrated in FIG. 8, the memory device may include memory blocks including BLOCK0, BLOCK1, and BLOCK2, and may include a strong word line group (W1) and a weak word line group (W2) as in BLOCK0, may include a strong word line group (W3) and two word line groups (W4, W5) having word lines greater than or equal to a first reference value as in BLOCK1, and may include a word line group having only word lines less than a first reference value as in BLOCK2.

[0152] Additionally, the present disclosure may refer to a portion of each word line group that corresponds to an error bit number higher than the error bit number of surrounding word lines as a peak. For example, W2 has two peaks, and W5 has one peak.

[0153] For example, if there are two peaks, such as in the weak word line group (W2) of BLOCK0 among the memory blocks of the memory device of FIG. 8, and at least one of the two peaks is greater than or equal to a first reference value, the difference between the number of error bits of the strong word line included in the strong word line group and the first reference value is compared with a second reference value, and if the difference is greater than or equal to the second reference value, only the weak word line group of the target memory block can be set as the data movement range.

[0154] That is, the controller of the present disclosure does not immediately decide to refresh the entire block when it is confirmed that at least one of two peaks is greater than or equal to a first reference value, but can determine the area to be refreshed based on the number of error bits of the strong word lines included in the strong word line group.

[0155] Accordingly, the controller of the present disclosure may set only the weak word line group included in the target memory block as the data movement range where a refresh operation is performed, when at least one of the error bit count of one word line included in the weak word line group and the error bit count of another word line is greater than or equal to a first reference value, and the difference between the error bit count of a word line included in the strong word line group and the first reference value is greater than or equal to a preset second reference value.

[0156] On the other hand, the controller of the present disclosure may set the entire target memory block as a data movement range in which a refresh operation is performed when at least one of the error bit count of one word line included in a weak word line group and the error bit count of another word line is greater than or equal to a first reference value, and the difference between the error bit count of a word line included in a strong word line group and the first reference value is less than a preset second reference value.

[0157] As another example, there may be two or more weak word line groups in a single target memory block, such as BLOCK1 among the memory blocks of the memory device of FIG. 8. In this case, the controller of the present disclosure may check the number of error bits of the third strong word line group (W3) if at least one of the number of error bits of the word line included in the fourth weak word line group (W4) or the number of error bits of the word line included in the fifth weak word line group (W5) is greater than or equal to a first reference value, and compare the difference between the number of error bits of W3 and the first reference value with a second reference value.

[0158] In addition, in the case of the aforementioned BLOCK1, the controller of the present disclosure may set only the fourth and fifth weak word line groups of the target memory block as the data movement range if the difference between the number of error bits of W3 and the first reference value is greater than or equal to the second reference value, and may set the entire target memory block as the data movement range if the aforementioned difference is less than the second reference value.

[0159] Accordingly, the controller of the present disclosure may determine the range for which a refresh is to be performed based on the number of error bits of the word lines included in the strong word lines, rather than immediately determining a refresh for the entire target memory block if at least one of the error bits of each weak word line of two or more weak word line groups is greater than or equal to a first reference value.

[0160] As another example, among the memory blocks of the memory device of FIG. 8, there may not be a group of word lines containing word lines greater than or equal to a first reference value, such as BLOCK2. In this case, the controller of the present disclosure may determine that a refresh operation for the entire memory block is not necessary.

[0161] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, since the embodiments disclosed in the present disclosure are intended to explain, not limit, the scope of the technical concept of the present disclosure is not limited by these embodiments.

Claims

Claim 1 A storage device comprising: a memory including a plurality of memory blocks including a plurality of word lines; and a controller that compares the number of first error bits of a first word line included in a first weak word line group of a target memory block during a first period with a preset first reference value, compares the difference between the number of second error bits of a second word line included in a strong word line group of the target memory block and the first reference value with a preset second reference value, and sets a data movement range of the target memory block to be moved to a preset space based on the result of comparing the difference and the second reference value. Claim 2 A storage device according to claim 1, wherein the controller checks the second error bit number of the second word line included in the strong word line of the target memory block and determines the difference between the second error bit number and the first reference value if the first error bit number of the first word line is greater than or equal to the first reference value. Claim 3 A storage device according to claim 1, wherein the controller sets only the first weak word line group of the target memory block as the data movement range and excludes an area other than the first weak word line group of the target memory block from the data movement range if the difference between the second error bit number and the first reference value is greater than or equal to the second reference value. Claim 4 In claim 3, the controller is a storage device that checks the number of third error bits of a third word line included in a second word line group other than the first word line group in the target memory block during a second period after the first period. Claim 5 A storage device according to claim 1, wherein the controller sets the entire target memory block as the data movement range if the difference between the second error bit number and the first reference value is less than the second reference value. Claim 6 A storage device according to claim 1, wherein the controller determines to skip a data movement operation for the target memory block during the first period if the number of the first error bits is less than the first reference value. Claim 7 A storage device according to claim 1, wherein the controller sets only the first word line group of the target memory block as the data movement range and excludes an area other than the first word line group of the target memory block from the data movement range, if at least one of the first error bit number of the first word line included in the first word line group or the third error bit number of the third word line included in the first word line group is greater than or equal to the first reference value and the difference between the second error bit number and the first reference value is greater than or equal to the second reference value. Claim 8 A storage device according to claim 1, wherein the controller checks the second error bit number if at least one of the first error bit number of the first word line included in the first weak word line group or the fourth error bit number of the fourth word line included in the second weak word line group is greater than or equal to the first reference value, and compares the difference between the second error bit number and the first reference value with the second reference value. Claim 9 A storage device according to claim 8, wherein if the difference between the second error bit number and the first reference value is greater than or equal to the second reference value, only the first weak word line group and the second weak word line group of the target memory block are set as the data movement range, and an area other than the first weak word line group and the second weak word line group of the target memory block is excluded from the data movement range, and if the difference between the second error bit number and the first reference value is less than the second reference value, the entire target memory block is set as the data movement range. Claim 10 A memory device comprising: a first memory block including a target memory block including a first weak word line group and a strong word line group; and a second memory block to which data of the target memory block is to be moved, wherein the movement range for the data of the target memory block to be moved to the second memory block is set based on a first comparison result in which a first error bit number of a first word line included in the first weak word line group of the target memory block during a first period is compared with a preset first reference value, and a second comparison result in which a preset second reference value is compared with the difference between a second error bit number of a second word line included in the strong word line group of the target memory block and the first reference value. Claim 11 A memory device according to claim 10, wherein the movement range for data of the target memory block to be moved to the second memory block is such that if the difference between the second error bit number and the first reference value is greater than or equal to the second reference value, only the first weak word line group of the target memory block is set as the data movement range, and the area other than the first weak word line group of the target memory block is excluded from the data movement range. Claim 12 In claim 10, the movement range for the data of the target memory block to be moved to the second memory block is such that if the difference between the second error bit number and the first reference value is less than the second reference value, the entire target memory block is set as the data movement range. Claim 13 In claim 10, the data movement for the first memory block is determined to skip the data movement operation for the target memory block during the first period if the number of first error bits is less than the first reference value. Claim 14 A memory device according to claim 10, wherein the movement range for data of the target memory block to be moved to the second memory block is such that at least one of the number of first error bits of the first word line included in the first word line group or the number of third error bits of the third word line is greater than or equal to the first reference value, and the difference between the number of second error bits and the first reference value is greater than or equal to the second reference value, wherein the first word line group of the target memory block is set as the data movement range. Claim 15 An error bit search unit that checks the number of first error bits of a first word line included in a first weak word line group of a target memory block located outside of a first period, and checks the number of second error bits of a second word line included in a strong word line group of the target memory block based on the result of comparing the number of first error bits with a preset first reference value; and a movement range determination unit that compares the number of first error bits with the first reference value, compares the difference between the number of second error bits and the first reference value with a preset second reference value, and sets the data movement range of the target memory block to be moved to a preset space based on the result of comparing the difference with the second reference value. Claim 16 In claim 15, the movement range determining unit is a controller that, if the number of first error bits of the first word line is greater than or equal to the first reference value, checks the number of second error bits of the second word line included in the strong word line of the target memory block and determines the difference between the number of second error bits and the first reference value. Claim 17 In claim 15, the movement range determining unit is a controller that, if the difference between the second error bit number and the first reference value is greater than or equal to the second reference value, sets only the first weak word line group of the target memory block as the data movement range and excludes an area other than the first weak word line group of the target memory block from the data movement range. Claim 18 In claim 15, the movement range determining unit is a controller that checks the number of third error bits of a third word line included in a second word line group other than the first word line group in the target memory block during a second period after the first period. Claim 19 In claim 15, the movement range determining unit is a controller that sets the entire target memory block as the data movement range if the difference between the second error bit number and the first reference value is greater than or equal to the second reference value. Claim 20 In claim 15, the movement range determining unit is a controller that decides to skip a data movement operation for the target memory block during the first period if the number of the first error bits is less than the first reference value.

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