First-in first-out device including a buffer and its operating method

Abstract

A first-in, first-out device including a buffer is disclosed. A first-in, first-out device including a buffer according to one embodiment may include a first-in, first-out circuit for storing first data to be output to the buffer. The first-in, first-out device may include the buffer in which the first data is stored based on the number of previously stored second data. The first-in, first-out device may include a controller for controlling the output of the first data from the FIFO circuit to the buffer based on the state of each of the FIFO circuit and the buffer. The controller may provide the sum of the number of the first data and the number of the second data, which is the number of readable data, in response to a read request for the second data.

Description

Technology Field

[0001] The following disclosure relates to a first-in, first-out device including a buffer and a method of operating the same. Background Technology

[0003] Designing a First-In, First-Out (FIFO) is a common and critical issue in hardware design using ASICs or FPGAs. When designing a FIFO, the operating frequency may decrease as the data width increases or the storage depth deepens. This phenomenon is more pronounced in Field Programmable Gate Arrays (FPGAs), and it is common for the IP cores provided by FPGAs to use additional registers for high-frequency operation. The use of additional registers can lead to read latency. Read latency causes a discrepancy from the timing diagram of a standard FIFO, requiring hardware modifications on the data reading side to accommodate the adjusted timing diagram.

[0004] The background technology described above is possessed or acquired by the inventor in the process of deriving the content of the disclosure of the present application, and cannot necessarily be considered as prior art disclosed to the general public prior to the filing of this application. The problem to be solved

[0006] One embodiment can provide a device that performs high-speed first-in, first-out in an FPGA.

[0007] One embodiment can provide a technique for performing first-in, first-out without read latency.

[0008] However, technical challenges are not limited to the technical challenges described above, and other technical challenges may exist. means of solving the problem

[0010] A first-in, first-out device including a buffer according to one embodiment may include a first-in, first-out circuit for storing first data to be output to the buffer, the buffer in which the first data is stored based on the number of previously stored second data, and a controller for controlling the output of the first data from the FIFO circuit to the buffer based on the respective states of the FIFO circuit and the buffer. The controller may provide the sum of the number of the first data and the number of the second data, which is the number of readable data, in response to a read request for the second data.

[0011] The above buffer may include one or more registers in which each of the second data is stored. The number of registers may be equal to the maximum number in which the second data can be stored.

[0012] The controller may store the first data in the buffer in response to the case where the first data is valid and the number of registers is less than the number of the second data, and stop the output of the first data in response to the case where the number of registers is equal to the number of the second data.

[0013] The controller may provide the sum of the number of data stored in the FIFO circuit and the second data in response to the read request.

[0014] The operation method of a first-in, first-out device may include an operation of obtaining first data to be output to a buffer. The operation method may include an operation of storing the first data in the buffer based on the number of previously stored second data. The operation method may include an operation of reading the second data in response to a read request for the second data, while simultaneously providing the sum of the number of the first data and the second data.

[0015] The above buffer may include one or more registers in which each of the second data is stored. The number of registers may be equal to the maximum number in which the second data can be stored.

[0016] The above-mentioned storage operation may include an operation to store the first data in response to the case where the first data is valid and the number of the registers is less than the number of the second data. The above-mentioned storage operation may include an operation to stop storing the first data in response to the case where the number of the registers is equal to the number of the second data.

[0017] The above operation method may further include an operation of providing the sum of the number of data stored in the FIFO circuit (first-in, first-out circuit) and the second data in response to the read request. Brief explanation of the drawing

[0019] FIG. 1 is a schematic diagram of a first-in, first-out device according to one embodiment. Figure 2 shows an example of a timing diagram on the reading side for a typical first-in, first-out device. Figure 3 shows an example of a timing diagram on the reading side for a first-word fall-through (FWFT) type first-in, first-out device. Figure 4 shows an example of a timing diagram on the read side for a first-in, first-out device with added registers. FIG. 5 shows the internal structure of a first-in, first-out device according to one embodiment. Figure 6 is a schematic diagram of the buffer shown in Figure 1. Figure 7 is a schematic diagram of the controller shown in Figure 1. Figure 8 is a flowchart illustrating the operation of a first-in, first-out device. Specific details for implementing the invention

[0020] Specific structural or functional descriptions of the embodiments are disclosed for illustrative purposes only and may be modified and implemented in various forms. Accordingly, actual implementations are not limited to the specific embodiments disclosed, and the scope of this specification includes modifications, equivalents, or substitutions included in the technical concept described by the embodiments.

[0021] Terms such as "first" or "second" may be used to describe various components, but these terms should be interpreted solely for the purpose of distinguishing one component from another. For example, the first component may be named the second component, and similarly, the second component may be named the first component.

[0022] When it is stated that a component is "connected" to another component, it should be understood that it may be directly connected to or coupled with that other component, or that there may be other components in between.

[0023] Singular expressions include plural expressions unless the context clearly indicates otherwise. In this document, phrases such as “A or B,” “at least one of A and B,” “at least one of A or B,” “A, B or C,” “at least one of A, B and C,” and “at least one of A, B, or C” may each include any one of the items listed together with the corresponding phrase, or all possible combinations thereof. In this specification, terms such as “comprising” or “having” are intended to designate the existence of the described feature, number, step, action, component, part, or combination thereof, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0024] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an ideal or overly formal sense unless explicitly defined in this specification.

[0025] As used in this document, the term "part" refers to software or hardware components, such as FPGAs or ASICs, and the "part" performs certain roles. However, the meaning of "part" is not limited to software or hardware. The "part" may be configured to reside in an addressable storage medium or configured to operate one or more processors. For example, the "part" may include components such as software components, object-oriented software components, class components, and task components, as well as processes, functions, attributes, procedures, subroutines, segments of program code, drivers, firmware, microcode, circuits, data, databases, data structures, tables, arrays, and variables. The functions provided within the components and "parts" may be combined into a smaller number of components and "parts" or further separated into additional components and "parts." Furthermore, the components and "parts" may be implemented to operate one or more CPUs within a device or secure multimedia card. Additionally, '~part' may include one or more processors.

[0026] Hereinafter, embodiments will be described in detail with reference to the attached drawings. In the description with reference to the attached drawings, identical components are given the same reference numeral regardless of the drawing number, and redundant descriptions thereof will be omitted.

[0028] FIG. 1 is a schematic diagram of a first-in, first-out device according to one embodiment.

[0029] Referring to FIG. 1, according to one embodiment, a first-in first-out device (10) may include a first-in, first-out circuit (11), a buffer (13), and / or a controller (15).

[0030] The first-in, first-out device (10) may be a device having a structure in which data is output in the order in which it is input. The first-in, first-out device (10) can input (or write) data to the first-in, first-out device (10) in order, and can output the written data in the order in which it is input. When the first-in, first-out device (10) is implemented in hardware, it may be provided in the form of an IP core (intellectual property core) and may perform a data buffering role to buffer the difference in data processing speed between systems that process data at different speeds. The first-in, first-out device (10) may use the same clock for reading and writing, but may also use different clocks for reading and writing. When the hardware operates in two or more clock domains, an asynchronous FIFO may be used when the first-in, first-out device (10) transfers data to another clock domain. The first-in, first-out device (10) may be a device designed to use different clocks for reading and writing. The first-in, first-out device (10) may control the write pointer and the read pointer independently, respectively, and may further include a synchronization circuit (not shown) between clock domains. The first-in, first-out device (10) can prevent data loss or collision. The first-in, first-out device (10) can ensure that data transmission between systems with different clock frequencies is stable and reliable.

[0031] The FIFO circuit (11) may be a FIFO (First-In-First-Out) type data storage device. The FIFO circuit (11) may temporarily store data input into the first-in, first-out device (10). The FIFO circuit (11) may transfer (or transmit) the input data to the buffer (13). For example, based on a signal (e.g., a control signal) from the controller (15), the FIFO circuit (11) may transfer (or transmit) the input data to the buffer (13).

[0032] The buffer (13) can receive (or acquire) data from the FIFO circuit (11). The buffer (13) may include memory for temporarily storing data. The buffer (13) can output the stored data externally. For example, the buffer (13) can output the stored data to the read station (19) based on a signal (e.g., a control signal) from the controller (15). The buffer (13) can receive (or acquire) data from the FIFO circuit (11) in advance of the read request from the read station (19). The buffer (13) can minimize delays in data transmission and can ensure stable data transmission.

[0033] The controller (15) can control the operation of the FIFO circuit (11) and / or the buffer (13). The controller (15) can cause the FIFO circuit (11) to input new data. The controller (15) can cause the buffer (13) to receive data from the FIFO circuit (11). The controller (15) can cause the buffer (13) to transfer data to the outside.

[0034] The first-in, first-out device (10) can communicate with each of the write station (17) and / or the read station (19). The first-in, first-out device (10) can receive data from the write station (17) or transfer data to the read station (19). For example, the first-in, first-out device (10) can receive a read request for data from the read station (19) and, in response to the read request, transfer data to the read station (19).

[0036] Figure 2 shows an example of a timing diagram on the reading side for a typical first-in, first-out device.

[0037] Referring to FIG. 2, according to one embodiment, a general first-in, first-out device may receive a data read request from a read unit. In response to the read request from the read unit, the general first-in, first-out device may deliver (or transmit) data to the read unit.

[0038] A standard first-in, first-out device can output an empty signal based on whether there is data within the standard first-in, first-out device. For example, a standard first-in, first-out device can output an empty signal of 0 if there is data to be output within the device, and an empty signal of 1 if there is no data to be output within the device.

[0039] If the empty signal is not 1, the read unit may make a read request to a general first-in, first-out device. The first-in, first-out device (10) may receive (or acquire) a read signal corresponding to the read request from the read unit. The read signal may be a data request from the read side. Based on the read signal, the general first-in, first-out device may transfer stored data to the read side. For example, the general first-in, first-out device may transfer stored data (e.g., D0, D1, D2, D3) to the read side at the clock next to the clock at which the read signal was acquired.

[0041] Figure 3 shows an example of a timing diagram on the read side for a first-in, first-out (FIFO) device of the FWFT method.

[0042] The operation method of a FWFT type first-in, first-out device may differ from the operation method of a general first-in, first-out device described in FIG. 2. A FWFT type first-in, first-out device (e.g., the first-in, first-out device (10) of FIG. 1) can process the stored data to make the stored data readable in the read_data path when data is stored. Referring to FIG. 3, according to one embodiment, the first-in, first-out device ((10)) can receive a request to read data from a reading unit (e.g., the reading unit (19) of FIG. 1). The first-in, first-out device (10) can deliver (or transmit) data to the reading unit (19) in response to the read request from the reading unit (19).

[0043] The first-in, first-out device (10) may wait for the output of data before a read request from the read unit (19). For example, the first-in, first-out device (10) may wait for the output of data D0 of the read_data signal until it receives a read signal. Based on the read signal, the first-in, first-out device (10) may output the waiting data (e.g., D0) and the next data (e.g., D1). If there is no next data, the first-in, first-out device (10) may output an empty signal as 1.

[0045] Figure 4 shows an example of a timing diagram on the read side for a first-in, first-out device with added registers.

[0046] Referring to FIG. 4, according to one embodiment, when a first-in, first-out device (e.g., a conventional first-in, first-out device) is implemented in an FPGA, the conventional first-in, first-out device may include registers to expand the width and depth of data that can be stored by the FIFO circuit included in the conventional first-in, first-out device. The registers may include pipeline registers. The more pipeline registers a conventional first-in, first-out device includes, the faster the operating speed, but the problem of read latency may occur in proportion to the number of pipeline registers. A conventional first-in, first-out device including a large FIFO circuit may fail to meet the clock speed required by a user (not shown) due to read latency.

[0047] A reading unit (e.g., the reading unit (19) of FIG. 1) may make a read request to a conventional first-in, first-out device. The conventional first-in, first-out device may output (or provide) valid data to the reading unit (19) when the data_valid signal is 1. The conventional first-in, first-out device may output (or provide) valid data to the reading unit (19) after the time when the read signal corresponding to the read request of the reading unit (19) becomes 1.

[0048] Conventional first-in, first-out devices need to identify valid data due to pipeline registers. Conventional first-in, first-out devices can output valid data to the read unit (19) only when the data_valid signal is 1. The read unit (19) can receive valid data only when the data_valid signal is 1, and a problem may arise where valid data cannot be received immediately after a read request. Conventional first-in, first-out devices may experience performance degradation by deciding whether to process data obtained from the write side (e.g., the write side (17) in FIG. 1) or to perform other operations. Therefore, a first-in, first-out device that includes pipeline registers and does not cause read delays may be required. For example, a first-in, first-out device that includes pipeline registers and has the timing diagram of FIG. 3 may be required.

[0050] FIG. 5 shows the internal structure of a first-in, first-out device according to one embodiment.

[0051] Referring to FIG. 5, according to one embodiment, the first-in, first-out device (10) may be an asynchronous first-in, first-out device (10) that uses different clocks for reading and writing, but is not limited thereto.

[0052] The FIFO circuit (11) may include one or more pipeline registers for high-speed operation. The FIFO circuit (11) may write data based on a write_data signal. The FIFO circuit (11) may obtain the number of data stored (or written) in the memory (not shown) of the FIFO circuit (11). The FIFO circuit (11) may generate a wr_count signal, which is the number of data stored (or written) in the memory of the FIFO circuit (11). The FIFO circuit (11) may output a first data, which is a portion of the data stored (or written) in the memory of the FIFO circuit (11), to a buffer (13). The FIFO circuit (11) may output a PFIFO_rd_data signal corresponding to the first data to the buffer (13). If there is no data recorded in the FIFO circuit (11), the PFIFO_rd_data signal may be a garbage value. The FIFO circuit (11) may output a data_valid signal to the buffer (13) indicating whether the data included in the first data is valid. If the FIFO circuit (11) is unable to output to the buffer (13) because there is no data recorded in the FIFO circuit (11) or outputs a value that is invalid, the data_valid signal may be output as 0.

[0053] The buffer (13) can store data obtained from the FIFO circuit (11). The data obtained from the FIFO circuit (11) may be second data that has already been stored. The buffer (13) can store first data based on the number of second data that has already been stored in the buffer (13).

[0054] The buffer (13) may output an empty signal as 1 if there is no previously stored data. The reading unit (e.g., the reading unit (19) of FIG. 1) may not be able to read or acquire the second data if the empty signal output from the buffer (13) is 1. The buffer (13) may not provide the second data to the reading unit (19) while outputting the empty signal as 1. The first-in, first-out device (10) may use the buffer (13) to process data at high speed even if the width and depth of the data of the FIFO circuit (11) increase. The first-in, first-out device (10) may include the buffer (13) to implement hardware that operates at high speed. The first-in, first-out device (10) may include the buffer (13) to eliminate read latency. The first-in, first-out device (10) may include the buffer (13) to offset the changed behavior mechanism of the FIFO circuit (11). The first-in, first-out device (10) may include a buffer (13) to reduce the complexity of implementing a read unit (e.g., the read unit (19) of FIG. 1). The first-in, first-out device (10) including a buffer (13) may enable the reuse of the existing read unit (19).

[0055] The controller (15) can control the output of the first data from the FIFO circuit (11) to the buffer (13) based on the respective states of the FIFO circuit (11) and the buffer (13). The controller (15) can receive (or obtain) a read request for the second data from the read unit (19). In response to the read request for the second data from the read unit (19), the controller (15) can provide the number of the first data and / or the number of the second data, which is the number of readable data. For example, the controller (15) can obtain a PFIFO_rd_count signal corresponding to the number of the first data from the FIFO circuit (11). As another example, the controller (15) can obtain a buf_count signal corresponding to the number of the second data from the buffer (13). The controller (15) may provide the PFIFO_rd_count signal, the buf_count signal, and / or the rd_data_count signal corresponding to the sum of the number of first data and the number of second data to the reading unit (19). The controller (15) may provide a consecutive_count signal corresponding to the number of data that can be provided consecutively in response to a request to read the second data from the reading unit (19). The controller (15) may provide the consecutive_count signal to prevent the reading unit (19) from obtaining an invalid value even though the empty signal is being output as 1 to the reading unit (19). The controller (15) may provide the consecutive_count signal in addition to the number of first data and second data to prevent the reading unit (19) from reading data based only on the number of stored data without checking the empty signal.

[0057] Figure 6 is a schematic diagram of the buffer shown in Figure 1.

[0058] Referring to FIG. 6, according to one embodiment, the buffer (13) may include one or more registers (131-0, to 131-n-1) for storing data. The one or more registers may be spaces where each of the second data is stored. The number of registers may be equal to the maximum number of second data that can be stored. For example, the buffer (13) may include n registers, and the buffer (13) may store up to n second data.

[0059] The buffer (13) may include a store signal generator (133), and the store signal generator (133) may be controlled by one or more signals. The one or more signals may include a data_valid signal, a read_en signal corresponding to a read request from a read unit (e.g., the read unit (19) of FIG. 1), and / or a full signal corresponding to a state in which the data that can be stored in the buffer (13) has reached its maximum capacity. The store signal generator (133) may acquire the data_valid signal and determine whether the first data is valid.

[0060] The storage signal generator (133) can store the first data in the buffer (13) in response to the case where the first data is valid and the number of registers is less than the number of second data. For example, the storage signal generator (133) can store the first data in the register (131-0) when the data_valid signal is 1 and the number of second data is less than n. The storage signal generator (133) can copy the second data to the next register when the first data is stored in the register (131-0). For example, the storage signal generator (133) can copy the second data stored in the register (131-7) to the register (131-8).

[0061] The controller (15) may respond to the case where a read request is made to the FIFO circuit (e.g., the FIFO circuit (11) of FIG. 5) but the number of data not delivered to the reading unit (19) is equal to the number of second data, and cause the FIFO circuit (11) to stop outputting the first data. The storage signal generator (133) may respond to the case where a read request is made to the FIFO circuit (11) but the number of data not delivered to the reading unit (19) is equal to the number of second data, and delay the storage of the first data until a read_en signal corresponding to the read request is obtained.

[0062] The buffer (13) may include a register (135) for providing the number of second data stored in the buffer (13) in response to a read request. The register (135) may transmit (or send) a buf_count signal corresponding to the number of data stored in the buffer (13) to the controller (15). The register (135) may transmit (or send) to the controller (15) the number of registers in which data to be output among the second data is stored in response to a read request. For example, when the buf_count signal value is 0, the buffer (13) may output an empty signal as 1 to inform the reading unit (e.g., the reading unit (19) of FIG. 1) that there is no data stored in the buffer (13). When the read_en signal corresponding to the read request of the reading unit (19) is 1, the register (135) may decrease the buf_count signal value. Register (135) can increase the buf_count signal value when the store signal corresponding to the store signal output from the store signal generator (133) is 1. Buffer (13) can select the second data stored in the register corresponding to the determined buf_count signal value as the read_data signal. For example, when the buf_count signal value is 1, buffer (13) can select register (131-0) by setting head_pointer to 0. As another example, when the buf_count signal value is n, buffer (13) can select register (131-n-1) by setting head_pointer to n-1. When the buf_count signal value is 0, buffer (13) outputs an empty signal as 1, and read_data can be an invalid value.

[0064] Figure 7 is a schematic diagram of the controller shown in Figure 1.

[0065] Referring to FIG. 7, according to one embodiment, a controller (e.g., controller (15) of FIG. 1) may include a register (151) for providing the number of data that was requested from a FIFO circuit (e.g., FIFO circuit (11) of FIG. 1) but was not delivered to a read unit (e.g., read unit (19) of FIG. 1). The register (151) may generate a pipe_count signal corresponding to the number of data that was requested from the FIFO circuit (11) but was not delivered to the read unit (19). The value of the pipe_count signal may be the sum of the number of data stored in the pipeline register included in the FIFO circuit (11) and the number of second data. The controller (15) may provide the sum of the number of data stored in the FIFO circuit (11) and the number of second data to the read unit (19) in response to a read request for the second data from the read unit (19). Register (151) can increase the pipe_count signal value when the read_PFIFO signal value corresponding to the signal to read data from the FIFO circuit (11) is 1. Register (151) can decrease the pipe_count signal value when the read_en signal corresponding to the read request of the read unit (19) is 1. Register (151) can generate a full signal of 1 when the pipe_count signal value exceeds the number of registers (131). Register (151) can generate a full signal of 1 to stop the data read request of the controller (15).

[0066] The controller (15) can generate a read_PFIFO signal value of 1 when the PFIFO_empty signal, which corresponds to no data stored in the FIFO circuit (11), is not 1 and the full signal is 0. The controller (15) can cause the FIFO circuit (11) to output the first data in response to the read_PFIFO signal value being 1. The controller (15) can generate a read_PFIFO signal value of 1 when the PFIFO_empty signal is not 1, the full signal is 1, and the read_en signal is 1. In this case, the pipe_count signal value may not change.

[0067] When the pipe_count signal value exceeds the number of registers (131), the controller (15) can represent the consecutive_count signal value as the number of data stored in the first-in, first-out device (e.g., the first-in, first-out device (10) of FIG. 1). When the pipe_count signal value is less than or equal to the number of registers (131), the controller (15) can represent the consecutive_count signal value as the buf_count signal value.

[0069] Figure 8 is a flowchart illustrating the operation of a first-in, first-out device.

[0070] Referring to FIG. 8, according to one embodiment, operations 810 to 850 may be operations performed by a first-in, first-out device (e.g., the first-in, first-out device (10) of FIG. 1) described with reference to FIG. 1 to 8.

[0071] In operation 810, the first-in, first-out device (10) can obtain first data to be output to a buffer (e.g., buffer (13) of FIG. 1) from a FIFO circuit (e.g., FIFO circuit (11) of FIG. 1) included in the first-in, first-out device (10). For example, the first-in, first-out device (10) can write the first data to the FIFO circuit (11) in response to a write request from the write side.

[0072] In operation 830, the first-in, first-out device (10) can obtain the number of second data already stored in the buffer (13) included in the first-in, first-out device (10). Based on the number of second data already stored in the buffer (13), the first data can be stored in the buffer (13).

[0073] In operation 850, the first-in, first-out device (10) may receive (or obtain) a read request from a reading unit (e.g., the reading unit (19) of FIG. 1). The first-in, first-out device (10) may read the second data in response to the read request for the second data. The first-in, first-out device (10) may calculate the sum of the first data and the second data. The first-in, first-out device (10) may provide the sum of the first data and the second data to the reading unit (19) in response to the read request for the second data.

[0074] Operations 810 through 850 may be performed sequentially, but are not limited thereto. For example, two or more operations may be performed in parallel.

[0076] The embodiments described above may be implemented as hardware components, software components, and / or combinations of hardware and software components. For example, the devices, methods, and components described in the embodiments may be implemented using a general-purpose computer or a special-purpose computer, such as, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a programmable logic unit (PLU), a microprocessor, or any other device capable of executing and responding to instructions. The processing unit may execute an operating system (OS) and software applications executed on said operating system. Additionally, the processing unit may access, store, manipulate, process, and generate data in response to the execution of the software. For ease of understanding, the processing unit may be described as being used as a single unit, but those skilled in the art will understand that the processing unit may include multiple processing elements and / or multiple types of processing elements. For example, the processing unit may include multiple processors or one processor and one controller. In addition, other processing configurations, such as parallel processors, are also possible.

[0077] Software may include computer programs, code, instructions, or a combination of one or more of these, and may configure a processing unit to operate as desired or instruct the processing unit independently or collectively. Software and / or data may be stored on any type of machine, component, physical device, virtual equipment, computer storage medium, or device so as to be interpreted by the processing unit or to provide instructions or data to the processing unit. Software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on computer-readable recording media.

[0078] The method according to the embodiment may be implemented in the form of program instructions that can be executed through various computer means and recorded on a computer-readable medium. The computer-readable medium may store program instructions, data files, data structures, etc., either individually or in combination, and the program instructions recorded on the medium may be those specifically designed and configured for the embodiment or those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc.

[0079] The hardware device described above may be configured to operate as one or more software modules to perform the operation of the embodiment, and vice versa.

[0080] Although the embodiments have been described above with reference to the limited drawings, those skilled in the art can apply various technical modifications and variations based thereon. For example, suitable results may be achieved even if the described techniques are performed in a different order than described, and / or if the components of the described system, structure, device, circuit, etc. are combined or assembled in a form different from described, or replaced or substituted by other components or equivalents.

[0081] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims set forth below.

Claims

Claim 1 A first-in, first-out device comprising a buffer, the device comprising: a first-in, first-out circuit for storing first data to be output to the buffer; the buffer in which the first data is stored based on the number of second data stored; and a controller for controlling the output of the first data from the FIFO circuit to the buffer based on the state of each of the FIFO circuit and the buffer, wherein the controller provides the sum of the number of the first data and the number of the second data, which is the number of readable data, in response to a read request for the second data.

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