Memory device and computing device

Abstract

A memory device comprises a memory cell array including memory cells connected to word lines and bit lines, wherein the memory cells are NAND flash memory cells; and a plurality of page buffers configured to store first values ​​read from first memory cells connected to a first word line among the word lines through the bit lines in a deep neural network operation, and to perform multiplication operations on the inputs and the first values, respectively.

Description

Technology Field

[0001] The present invention relates to a memory device and an arithmetic device including a memory device. Background Technology

[0002] Recently, artificial intelligence (AI) technology requires high-performance computing capabilities and large-capacity memory; to this end, cloud-based computing systems including GPUs and High Bandwidth Memory (HBM) are generally utilized. However, mobile devices such as smartphones may find it difficult to perform high-complexity AI computations at the cloud level due to limitations in computing power, memory capacity, and battery life. Despite these limitations, On-Device AI can enable basic AI services with limited computing resources by adopting relatively simple AI models. Therefore, technologies that perform computations using Universal Flash Storage (UFS) or NAND flash memory, which are built-in storage devices in smartphones, are currently being researched. The problem to be solved

[0003] An embodiment of the present invention provides a memory device and a computing device capable of improving the accuracy and efficiency of deep neural network computation operations. means of solving the problem

[0004] A memory device according to an embodiment of the present invention may include a memory cell array comprising memory cells connected to word lines and bit lines, wherein the memory cells are NAND flash memory cells; and a plurality of page buffers configured to store first values ​​read from first memory cells connected to a first word line among the word lines through the bit lines in a deep neural network operation, and to perform multiplication operations on the inputs and the first values, respectively.

[0005] A memory device according to an embodiment of the present invention comprises: a memory cell array including memory cells connected to word lines and bit lines, wherein the memory cells are NAND flash memory cells; a plurality of page buffers configured to store first values ​​read from first memory cells connected to a first word line among the word lines through the bit lines in a deep neural network operation, and to perform multiplication operations on the inputs and the first values, respectively; and a plurality of majority check circuits each connected to a plurality of page buffer groups into which the plurality of page buffers are divided, wherein each of the plurality of majority check circuits can perform a majority check operation on multiplication results received from one or more corresponding page buffers included in the corresponding page buffer group in the deep neural network operation, and output a final multiplication result.

[0006] An arithmetic device according to an embodiment of the present invention comprises: a memory device including memory cells connected to word lines and bit lines, wherein the memory cells are NAND flash memory cells; and a controller configured to control the memory device to perform a deep neural network operation by storing first parameters corresponding to input connections of nodes of a first hidden layer of a deep neural network in first memory cells connected to a first word line among the word lines, and transmitting external inputs to the memory device, wherein the memory device may further include a plurality of page buffers configured to store the first parameters read from the first memory cells through the bit lines, store the external inputs, and perform multiplication operations on the external inputs and the first parameters, respectively, in the deep neural network operation. Effects of the invention

[0007] The memory device and computing device according to an embodiment of the present invention can improve the accuracy and efficiency of deep neural network computation operations. Brief explanation of the drawing

[0008] FIG. 1a is a diagram schematically showing the structure of a deep neural network, FIG. 1b is a diagram illustrating the operation of each node of a deep neural network (DNN). FIG. 2 is a block diagram illustrating a memory device capable of performing deep neural network operation according to an embodiment, FIG. 3 is a circuit diagram illustrating a memory block according to an embodiment, FIG. 4 is a circuit diagram illustrating a page buffer according to an embodiment, FIG. 5a is a circuit diagram illustrating a fail bit counter and a pass / fail determination circuit according to an embodiment, FIG. 5b is a table illustrating pass / fail results according to a reference signal according to an embodiment, FIGS. 6 and 7 are drawings for explaining the deep neural network operation of a memory device according to an embodiment, FIG. 8 is a diagram illustrating the deep neural network operation of a memory device according to an embodiment, FIG. 9 is a block diagram illustrating a memory device capable of performing deep neural network operation according to an embodiment, FIG. 10 is a diagram for explaining the deep neural network operation of a memory device according to an embodiment, FIG. 11 is a block diagram illustrating a computing device that performs deep neural network computation operations according to an embodiment. Specific details for implementing the invention

[0009] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0010] Where in this specification it is stated that one element is "connected" to another element, the elements may be directly connected to each other or connected through one or more intervening elements.

[0011] Terms such as "first," "second," etc., as used in this specification are used to distinguish different components and do not limit the order, importance, functional differences, or physical arrangement of the components. Different numbers may be used for the same component depending on the embodiment.

[0012] Figure 1a is a diagram schematically showing the structure of a deep neural network (DNN).

[0013] Referring to FIG. 1a, the main structure of the artificial intelligence operation may include sequential matrix multiplication operations based on a Deep Neural Network (DNN). The Deep Neural Network (DNN) may include an input layer (IL), first to third hidden layers (HL1 to HL3), and an output layer (OL). The number of hidden layers included in the Deep Neural Network (DNN) may be examples.

[0014] The input layer (IL) can receive multidimensional external input data from the outside. Each input node (IND) included in the input layer (IL) is activated according to each dimensional component of the external input data, and the external input data is transmitted to the first hidden layer (HL1) to act as an initial stage of deep neural network (DNN) computation. The first to third hidden layers (HL1~HL3) can be placed between the input layer (IL) and the output layer (OL). Each of the first to third hidden layers (HL1~HL3) includes one or more nodes (ND) and can receive data output from the previous layer as input, generate a new feature representation by applying weight operations and a non-linear activation function, and transmit it to the subsequent layer. The output layer (OL) can output the result that the artificial intelligence model has finally predicted or classified. The output layer may include one or more output nodes (ONDs) depending on the purpose of the task, and generally, probabilistic output data for each class or result can be produced by applying an output-specific activation function such as a softmax or sigmoid function.

[0015] Figure 1b is a diagram illustrating the operation of each node of a deep neural network (DNN).

[0016] Referring to FIG. 1b, each node (ND) (or artificial neuron) included in the first to third hidden layers (HL1 to HL3) serves as a computational unit of a deep neural network (DNN). By summing (103) the results of applying parameters (102) to inputs (101) output from the previous layer and applying an activation function (104) to the summed result, a node operation result (y) to be transmitted as an input to a subsequent layer can be generated. Through this process, the node (ND) transforms the inputs (101) step by step, and the deep neural network (DNN) can contribute to extracting useful features from external input data and producing final output data.

[0017] FIG. 2 is a block diagram illustrating a memory device (100) capable of performing deep neural network operation according to an embodiment.

[0018] Referring to FIG. 2, the memory device (100) can operate under the control of an external device, for example, a controller. Specifically, the memory device (100) can store program data (PD) received from the controller by performing a program operation in response to an external signal (CTR) received from the controller. Additionally, the memory device (100) can output read data (RD) to the controller by performing a read operation in response to an external signal (CTR) received from the controller. Additionally, the memory device (100) can perform a deep neural network operation in response to an external signal (CTR) received from the controller.

[0019] The memory device (100) may include peripheral circuits (110) and a memory cell array (120).

[0020] The peripheral circuit (110) can perform program operations and read operations for the memory cell array (120).

[0021] Additionally, the peripheral circuit (110) can perform deep neural network operation based on external input data (DIN) input from the controller and parameters read from the memory cell array (120). The parameters can be stored in the memory cell array (120) through a program operation before the deep neural network operation is performed.

[0022] The peripheral circuit (110) may include a control circuit (111), a voltage generation circuit (112), a decoder (113), a plurality of page buffers (114), a fail bit counter (115), a pass / fail determination circuit (116), an input circuit (117), and an output circuit (118).

[0023] The control circuit (111) can control the various operations of the internal circuits of the memory device (100) in response to an external signal (CTR) to perform internal operations of the memory device (100), such as a program operation, a read operation, an erase operation, and a deep neural network operation. The control circuit (111) can selectively re-perform an internal operation in response to a pass / fail result (PF) received from the pass / fail determination circuit (116) in a predetermined internal operation (e.g., a program operation, a read operation, an erase operation, etc.).

[0024] The voltage generation circuit (112) can generate various internal voltages and output the internal voltages to the internal circuits of the memory device (100). For example, the voltage generation circuit (112) can output a read voltage used in a read operation to a decoder (113).

[0025] The decoder (113) can be connected to the memory cell array (120) via row lines (RL). The decoder (113) can apply internal voltages transmitted from the voltage generation circuit (112) to the row lines (RL). The row lines (RL) may include one or more drain select lines, a plurality of word lines, and one or more source select lines connected to each of the memory blocks (MB1 to MBk), as described below.

[0026] A plurality of page buffers (114) can be connected to memory blocks (MB1~MBk) included in the memory cell array (120) through bit lines (BL1~BLm). A plurality of page buffers (114) may include page buffers (PB1~PBm) each connected to the bit lines (BL1~BLm).

[0027] Multiple page buffers (114) can receive and store program data (PD) to be stored in the memory cell array (120) from the input circuit (117).

[0028] Additionally, a plurality of page buffers (114) can store read data (RD) read from the memory cell array (120) before outputting it to the output circuit (118).

[0029] Additionally, the multiple page buffers (114) can transmit the result of a verification operation, i.e., verification data (VD), performed to verify the completion of an internal operation after an internal operation (e.g., program operation, erase operation, etc.) is performed on a target area of ​​the memory cell array (120) to a fail bit counter (115).

[0030] Additionally, one or more of the multiple page buffers (114) can perform multiplication operations on the inputs (x) received from the input circuit (117) and the parameters read from the memory cell array (120) during a deep neural network operation, and output the multiplication results (m) to the fail bit counter (115).

[0031] The fail bit counter (115) can output a count result (CNT) by performing a counting operation to count the number of fail bits in the verification data (VD) transmitted from the plurality of page buffers (114). For example, the fail bit counter (115) can count the number of fail bits equal to a predetermined value in the verification data (VD) which is the result of a verification operation for an erase operation. As another example, the fail bit counter (115) can count the number of fail bits equal to a predetermined value in the verification data (VD) which is the result of a verification operation for a program operation. Depending on the embodiment, the count result (CNT) can be output in a digital or analog manner (i.e., a voltage or current signal).

[0032] Additionally, the fail bit counter (115) can receive multiplication results (m) from one or more of the multiple page buffers (114) during a deep neural network operation, count the number of multiplication results that are equal to a predetermined value, and output a count result (CNT). The fail bit counter (115) can count the number of multiplication results that are equal to a predetermined value among the multiplication results input to the same node of the deep neural network (DNN). Thus, during a deep neural network operation, the count result (CNT) can correspond to the result of performing a sum operation on the multiplication results input to a corresponding node (ND).

[0033] The pass / fail determination circuit (116) receives a count result (CNT) from the fail bit counter (115) and can output a pass / fail result (PF) to the control circuit (111) by determining whether the count result (CNT) is a pass or a fail by comparing it with a predetermined reference value. For example, in an erasure operation, if the count result (CNT) is less than or equal to the reference value, the pass / fail determination circuit (116) can output a pass / fail result (PF) of a first value (e.g., "1") indicating that the erasure operation is a pass. On the other hand, if the count result (CNT) is greater than the reference value, the pass / fail determination circuit (116) can output a pass / fail result (PF) of a second value (e.g., "0") indicating that the erasure operation is a fail. When the control circuit receives a pass / fail result (PF) indicating that the erasure operation is a fail from the pass / fail determination circuit (116), it can re-perform the erasure operation. A predetermined reference value can be set according to the control of the control circuit.

[0034] Additionally, the pass / fail determination circuit (116) can receive a count result (CNT) from the fail bit counter (115) during a deep neural network operation, compare the count result (CNT) with a predetermined reference value, and output a pass / fail result (PF) to the input circuit (117). Thus, during a deep neural network operation, the pass / fail result (PF) can correspond to the result of performing an activation operation (i.e., applying an activation function) on the result of performing a sum operation at a corresponding node (ND), i.e., the node operation result (y) of the corresponding node (ND).

[0035] According to an embodiment, the memory device (100) may further include fail bit counters corresponding to the number of nodes included in each hidden layer and pass / fail determination circuits corresponding to the number.

[0036] The input circuit (117) receives program data (PD) to be stored in the memory cell array (120) in the program operation from the controller and can transfer the program data (PD) to a plurality of page buffers (114).

[0037] Additionally, the input circuit (117) can operate as an input layer (IL) of a deep neural network (DNN). Specifically, in a deep neural network operation, the input circuit (117) receives external input data (DIN) from a controller and can transmit the external input data (DIN) to one or more of the multiple page buffers (114) as inputs (x) transmitted from the input layer (IL) to the first hidden layer (HL1). The one or more page buffers to which the inputs (x) are transmitted can be determined according to the input connection structure between the nodes of the input layer (IL) and the first hidden layer (HL1) of the deep neural network (DNN).

[0038] Additionally, the input circuit (117) can transmit the pass / fail result (PF) received from the pass / fail determination circuit (116) to one or more of the page buffers (114) as inputs (x) transmitted from the previous hidden layer to the subsequent hidden layer in a deep neural network operation.

[0039] The output circuit (118) receives read data (RD) read from the memory cell array (120) from a plurality of page buffers (114) and can output the read data (RD) to the controller.

[0040] Additionally, the output circuit (118) can output to the controller as final output data (DOUT) during deep neural network operation. The final output data (DOUT) may include a pass / fail result (PF) received from the pass / fail determination circuit (116). The output circuit (118) can operate as an output layer (OL) of the deep neural network (DNN).

[0041] The memory cell array (120) may include a plurality of memory blocks (MB1 to MBk). Each of the memory blocks (MB1 to MBk) may include memory cells. Each of the memory blocks (MB1 to MBk) may be connected to row lines (RL) and bit lines (BL1 to BLm). Each of the memory blocks (MB1 to MBk) may be selected for program operation and read operation through the control of the row lines (RL) and bit lines (BL1 to BLm). Each memory block may be a unit in which an erase operation is performed.

[0042] According to an embodiment, the memory device (100) may be a NAND flash memory device. NAND flash memory is a non-volatile storage medium and may have the characteristic of retaining data even when the power is cut off. NAND flash memory can store data by adjusting the charge amount of a floating gate transistor to vary the threshold voltage state of each memory cell. NAND flash memory may be suitable for large-capacity data storage due to its high integration density and low cost structure. In addition, based on its parallel accessibility and non-volatile characteristics, NAND flash memory can be effectively utilized for artificial intelligence processing, such as deep neural network computation operations.

[0043] According to an embodiment, the memory device (100) may include various types of memory such as NOR Flash memory, Resistive Random Access Memory (RRAM), Phase-Change Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), or Spin Transfer Torque Random Access Memory (STT-RAM).

[0044] According to an embodiment, the deep neural network implemented by the memory device (100) may be a Binary Neural Network (BNN), but the embodiments of the present invention are not limited thereto. For example, the deep neural network implemented by the memory device (100) may be an artificial neural network in which inputs or weights are represented by multiple bits.

[0045] According to the present invention, by implementing a deep neural network in a memory device (100), costs can be reduced compared to when deep neural network computation operations are performed on a processor such as a CPU and a GPU. In addition, according to the present invention, the processing speed of the artificial intelligence of a mobile device can be improved compared to when neural network computation is performed on a server and computation results are obtained from the server. In addition, according to the present invention, the accuracy of neural network computation operations can be prevented from degrading due to cell current volatility and page buffer sensing errors. In addition, according to the present invention, the number of hidden layers and the number of nodes per hidden layer can be efficiently expanded.

[0046] FIG. 3 is a circuit diagram illustrating a memory block (MB) according to an embodiment. Each of the memory blocks (MB1 to MBk) of FIG. 3 can be configured similarly to the memory block (MB) of FIG. 2.

[0047] Referring to FIG. 3, a memory block (MB) can be connected to a peripheral circuit (110) through drain select lines (DSL1, DSL2), source select lines (SSL1, SSL2), word lines (WL1~WLn), bit lines (BL1~BLm), and source line (SL).

[0048] A memory block (MB) may contain strings (ST11~ST1m, ST21~ST2m). Each of the strings (ST11~ST1m, ST21~ST2m) may extend along the vertical direction (Z direction). Within the memory block (MB), m strings may be arranged in the row direction (X direction). Although FIG. 2 is illustrated as having two strings arranged in the column direction (Y direction), this is for convenience of explanation and three or more strings may be arranged in the column direction (Y direction).

[0049] Strings (ST11~ST1m, ST21~ST2m) can be configured identically. For example, string (ST11) may include a source select transistor (SST), memory cells (MC1~MCn), and a drain select transistor (DST) connected in series between a source line (SL) and a bit line (BL1). The source of the source select transistor (SST) may be connected to the source line (SL), and the drain of the drain select transistor (DST) may be connected to the bit line (BL1). Memory cells (MC1~MCn) may be connected in series between the source select transistor (SST) and the drain select transistor (DST). According to an embodiment, a plurality of source select transistors may be connected in series between the source line (SL) and the memory cell (MC1). According to an embodiment, a plurality of drain select transistors may be connected in series between the bit line (BL1) and the memory cell (MCn).

[0050] Source select transistors located at the same position in the vertical direction can be configured as follows. Specifically, the gates of source select transistors of strings arranged in the same row can be connected to the same source select line. For example, the gates of source select transistors of strings (ST11–ST1m) in the first row can be connected to the source select line (SSL1). For example, the gates of source select transistors of strings (ST21–ST2m) in the second row can be connected to the source select line (SSL2).

[0051] According to an embodiment, source selection transistors of strings of two or more rows may be commonly connected to a single source selection line. For example, source selection transistors of strings of the first and second rows (ST11~ST1m, ST21~ST2m) may be commonly connected to a single source selection line, and source selection transistors of strings of the third and fourth rows may be commonly connected to a single source selection line.

[0052] Drain select transistors located at the same position in the vertical direction can be configured as follows. Specifically, the gates of the drain select transistors of strings arranged in the same row can be connected to the same drain select line. For example, the gates of the drain select transistors of the strings (ST11–ST1m) of the first row can be connected to the drain select line (DSL1). For example, the gates of the drain select transistors of the strings (ST21–ST2m) of the second row can be connected to the drain select line (DSL2).

[0053] Strings arranged in the same column can be connected to the same bit line. For example, strings in the first column (ST11, ST21) can be connected to bit line (BL1). For example, strings in the mth column (ST1m, ST2m) can be connected to bit line (BLm).

[0054] The gates of memory cells located at the same position in the vertical direction can be connected to the same word line. For example, in strings (ST11~ST1m, ST21~ST2m), memory cells located at the same position in the vertical direction as memory cell (MC1) can be connected to word line (WL1).

[0055] Among the memory cells, memory cells connected to the same word line in the same row can form a single memory region. For example, memory cells connected to word line (WL1) in the first row can form a single memory region (MR11). For example, memory cells connected to word line (WL1) in the second row can form a single memory region (MR12). For example, memory cells connected to word line (WL2) in the first row can form a single memory region (MR21). Depending on the number of rows, each word line can be connected to multiple memory regions. Memory cells forming a single memory region can be accessed simultaneously.

[0056] According to an embodiment, the memory block (MB) may be further connected to one or more dummy word lines other than the word lines (WL1 to WLn). In this case, the memory block (MB) may further include dummy memory cells connected to the dummy word lines.

[0057] When a predetermined read voltage is applied to a memory cell through a selected word line among the word lines (WL1~WLn), the memory cell may be turned on / off according to the threshold voltage. Specifically, a memory cell having a threshold voltage lower than the read voltage may be turned on in response to the read voltage, and a memory cell having a threshold voltage higher than the read voltage may be turned off. When the memory cell is turned on, it changes the state of a precharged bit line (i.e., the voltage level of the bit line or the current flowing through the bit line), and a page buffer connected to the bit line may determine whether the threshold voltage of the memory cell is lower or higher than the read voltage by sensing the state of the bit line. For example, the page buffer may store the sensing result as "1" (or "0") when it is determined that the memory cell has a threshold voltage lower than the read voltage, and store the sensing result as "0" (or "1") when it is determined that the memory cell has a threshold voltage higher than the read voltage. Accordingly, a read operation for memory cells connected to a selected word line can be performed by determining the threshold voltage of each memory cell based on one or more read voltages.

[0058] FIG. 4 is a circuit diagram illustrating a page buffer (PB) according to an embodiment. Each of the page buffers (PB1 to PBm) of FIG. 2 can be configured similarly to the page buffer (PB).

[0059] Referring to FIG. 4, the page buffer (PB) may include a bitline selection circuit (401), a precharge circuit (402), a plurality of latches (403 to 405), and a multiplication circuit (406). The page buffer (PB) may be connected to a corresponding bitline (BL) among bitlines (BL1 to BLm).

[0060] The bitline selection circuit (401) can be configured to form a data path by connecting the bitline (BL) and the intermediate node (CN) under the control of the control circuit (111).

[0061] The precharge circuit (402) is connected to an intermediate node (CN) and can be configured to precharge the intermediate node (CN) under the control of the control circuit (111). The precharge circuit (402) can precharge the bitline (BL) through the intermediate node (CN) to perform a sensing operation.

[0062] Multiple latches (403 to 405) are connected to an intermediate node (CN) and, under the control of the control circuit (111), can store data to be stored in a memory cell connected to a bitline (BL) and data read from a memory cell connected to a bitline (BL). Additionally, among the multiple latches (403 to 405), a pre-designated first latch (403) can store an input (x) on which a multiplication operation is to be performed in a deep neural network operation. Additionally, among the multiple latches (403 to 405), a pre-designated second latch (404) can store a parameter (p) on which a multiplication operation is to be performed with the input (x) in a deep neural network operation.

[0063] The multiplication circuit (406) is connected to an intermediate node (CN) and can perform a multiplication operation in a deep neural network operation under the control of the control circuit (111). The multiplication circuit (406) can perform a multiplication operation (416) by receiving an input (x) stored in the first latch (403) and a parameter (p) stored in the second latch (404).

[0064] According to an embodiment, the multiplication circuit (406) may be implemented to perform an AND operation or an XNOR operation, but embodiments of the present invention are not limited thereto.

[0065] According to an embodiment, the input of program data (PD) into the page buffer (PB) and the output of read data (RD) from the page buffer (PB) can be performed through at least one of a plurality of latches (403 to 405), and the latch can be configured in various ways depending on the implementation method.

[0066] FIG. 5a is a circuit diagram illustrating a fail bit counter (115) and a pass / fail determination circuit (116) according to an embodiment. The number of components in FIG. 5a may be examples. FIG. 5b is a table (501) illustrating a pass / fail result according to a reference signal according to an embodiment.

[0067] Referring to FIG. 5a, the fail bit counter (115) may include a judgment circuit (510) and a mirror circuit (520).

[0068] The judgment circuit (510) can supply a summation current (ISUM) to the common node (NDC) corresponding to the number of "0" bits among the data (i.e., verification data (VD) or multiplication results (m)) received from one or more of the page buffers (114). Depending on the structure of the page buffer (PB), the fail bit may have a value of "0".

[0069] Specifically, the judgment circuit (510) may include fail bit judgment circuits (511 to 514). The fail bit judgment circuits (511 to 514) may each be connected to one or more of the page buffers (114). Each of the fail bit judgment circuits (511 to 514) may optionally supply current to the common node (NDC) according to the value of the data received from the corresponding page buffer. The current flowing from the fail bit judgment circuits (511 to 514) may be accumulated in the common node (NDC) as an summation current (ISUM).

[0070] For example, the fail bit determination circuit (511) may include a PMOS transistor (PM). The PMOS transistor (PM) may receive data (D1) transmitted from a corresponding page buffer at its gate. In response to data (D1) being "0", the PMOS transistor (PM) may supply current (IFAIL) to the common node (NDC). The amount of current (IFAIL) may be determined according to the ratio (W / L) of the channel width and channel length of the PMOS transistor (PM). The fail bit determination circuits (512–514) may be configured and operated similarly to the fail bit determination circuit (511).

[0071] The mirror circuit (520) can be configured to replicate the summing current (ISUM) flowing through the common node (NDC) as a replicating current (ISUMC) flowing from the judgment node (NDP) to the ground node. The replicating current (ISUMC) can correspond to the count result (CNT) of FIG. 2.

[0072] The pass / fail judgment circuit (116) can supply a reference current (IREF) corresponding to a reference value to a judgment node (NDP) in response to a reference signal (V<2:0>) corresponding to a predetermined reference value. The pass / fail judgment circuit (116) may include unit circuits (531 to 533). The unit circuits (531 to 533) can receive each bit constituting the reference signal (V<2:0>). Each of the unit circuits (531 to 533) can optionally supply a current to the judgment node (NDP) in response to a corresponding bit signal. The unit circuits (531 to 533) may be configured to supply currents of different multipliers of the current (IFAIL) flowing through the activated fail bit judgment circuit to the judgment node (NDP), respectively.

[0073] For example, unit circuits (531–533) may each include PMOS transistors (PM1–PM3). The PMOS transistor (PM1) is a bit signal (V <0> ) receives ) at the gate, and the PMOS transistor (PM2) receives the bit signal (V <1> ) receives the gate, and the PMOS transistor (PM3) receives the bit signal (V <2> ) can be received as a gate. For the ratio (W / L) of the channel width to the channel length of each fail bit judgment circuit, the PMOS transistor (PM1) can be configured to have a ratio corresponding to 0.5 times, the PMOS transistor (PM2) can be configured to have a ratio corresponding to 1 time, and the PMOS transistor (PM3) can be configured to have a ratio corresponding to 2 times.

[0074] Accordingly, referring to table (501), for example, when only unit circuits (531, 533) are activated in response to a reference signal (V<2:0>), a reference current (IREF) corresponding to 2.5 times the current (IFAIL) flowing through the activated fail bit judgment circuit can be supplied to the judgment node (NDP).

[0075] The decision node (NDP) can output the result of comparing the reference current (IREF) and the replication current (ISUMC) as a pass / fail result (PF). The decision node (NDP) outputs "1" as the pass / fail result (PF) when the replication current (ISUMC) is smaller than the reference current (IREF), and outputs "0" as the pass / fail result (PF) when the replication current (ISUMC) is larger than the reference current (IREF).

[0076] Table (501) illustrates the number of fail bits for which the pass / fail result (PF) is output as "1" for exemplary values ​​of reference current (IREF). For example, when a reference current (IREF) corresponding to 2.5 times the current (IFAIL) flowing through the activated fail bit judgment circuit is supplied to the judgment node (NDP), if the number of fail bits counted in the fail bit counter (115) is 3, the pass / fail result (PF) is output as "0", and if the number of fail bits counted in the fail bit counter (115) is 2, the pass / fail result (PF) can be output as "1".

[0077] Accordingly, in a deep neural network operation, the fail bit determination circuits (511–514) receive the multiplication results (m) from the corresponding page buffers, and by determining whether each of the multiplication results (m) matches "0", they can output a replication current (ISUMC) corresponding to the number of "0s" in the multiplication results (m). Since the number of "0s" in the multiplication results (m) is in a complementary relationship with respect to the total number of multiplication results (m) with respect to the number of "1s" in the multiplication results (m), consequently, the operation of the fail bit counter (115) can reflect the sum operation at each node (ND) in the deep neural network operation.

[0078] And in the deep neural network operation, the pass / fail determination circuit (116) can output a pass / fail result (PF) of "1" when the replication current (ISUMC) output from the fail bit counter (115) is smaller than the reference current (IREF) (i.e., when the sum result is greater than a predetermined reference value), and output a pass / fail result (PF) of "0" when the replication current (ISUMC) is greater than the reference current (IREF) (i.e., when the sum result is smaller than the reference value). Consequently, the pass / fail determination circuit (116) can perform an activation operation on the sum result in the deep neural network operation to non-linearly transform the sum result and output a node operation result (y) of each node (ND).

[0079] If the fail bit has a value of "0" depending on the structure of the page buffer (PB), the fail bit counter (115) counts the number of "0"s and outputs the corresponding replication current (ISUMC) as the count result (CNT). Then, the pass / fail determination circuit (116) can be configured to compare the replication current (ISUMC) with the reference current (IREF). As such, the embodiment of FIG. 5a is processed in a complementary manner based on complement rather than a method of outputting a direct sum result, but the pass / fail result (PF) finally output can accurately reflect the actual sum operation result and the activation operation result.

[0080] According to an embodiment, when the fail bit has a value of "1", the fail bit counter (115) may be configured to count the number of "1"s, unlike the embodiment of FIG. 5a, and it is obvious that the count result (CNT) output from the fail bit counter (115) will reflect the result of performing a sum operation on the multiplication results (m).

[0081] FIGS. 6 and 7 are drawings for explaining the operation of a deep neural network operation of a memory device (100) according to an embodiment. In FIGS. 6 and 7, the memory device (100) can implement a deep neural network (DNN1) in which an input layer (IL) includes four input nodes (IND1~IND4), a first hidden layer (HL1) includes first to fourth nodes (ND1~ND4), and a second hidden layer (HL2) includes fifth to eighth nodes (ND5~ND8).

[0082] Referring to FIG. 6, parameters (b, w1, w2, w3) corresponding to the input connections of the first node (ND1) may each be stored in memory cells (C1~C4) connected to the word line (WLn). The memory cells (C1~C4) may have threshold voltages corresponding to the parameters (b, w1, w2, w3) through a program operation. The parameters (b, w1, w2, w3) may include a bias (b) and weights (w1, w2, w3).

[0083] The input circuit (117) may include selection circuits (61 to 64). The selection circuits (61 to 64) may each receive external inputs (x1 to x4) and each receive a pass / fail result (PF). Each of the selection circuits (61 to 64) may output one of the corresponding external input and pass / fail result (PF) under the control of the control circuit (111).

[0084] Specifically, each of the selection circuits (61 to 64) can output a corresponding external input to perform operations of the first hidden layer (HL1) and output a pass / fail result (PF) to perform operations of the hidden layer after the first hidden layer (HL1).

[0085] Page buffers (PB1 to PB4) can each be connected to selection circuits (61 to 64). Each of the page buffers (PB1 to PB4) can receive and store the output of the corresponding selection circuit among the selection circuits (61 to 64).

[0086] According to an embodiment, the output path from the selection circuits (61–64) to the page buffers (PB1–PB4) may be controlled differently from what is illustrated according to the input connection structure between the input layer (IL) and the nodes of the plurality of hidden layers.

[0087] According to an embodiment, selection circuits (61 to 64) can receive program data (PD) of FIG. 2 as external inputs (x1 to x4) and output it to page buffers (PB1 to PB4).

[0088] To specifically describe the operation corresponding to the first node (ND1) of the first hidden layer (HL1), the selection circuits (61 to 64) can each transmit external inputs (x1 to x4) to page buffers (PB1 to PB4) under the control of the control circuit (111). Each of the external inputs (x1 to x4) can be stored in the first latch (403) included in the corresponding page buffer. The external inputs (x1 to x4) can be included in the external input data (DIN) of FIG. 2.

[0089] Additionally, a read operation can be performed on the memory cells (C1 to C4). Specifically, by applying a read voltage to the word line (WLn), the parameters (b, w1, w2, w3) stored in the memory cells (C1 to C4) can be read into the page buffers (PB1 to PB4) respectively through the bit lines (BL1 to BL4). Each of the parameters (b, w1, w2, w3) can be stored in the second latch (404) included in the corresponding page buffer.

[0090] Page buffers (PB1~PB4) can perform multiplication operations on external inputs (x1~x4) and parameters (b, w1, w2, w3), respectively, and output multiplication results (m1~m4).

[0091] The fail bit counter (115) can receive multiplication results (m1 to m4) and output a count result (CNT) by performing a counting operation on the multiplication results (m1 to m4). The count result (CNT) can correspond to the result of a sum operation performed on the multiplication results (m1 to m4).

[0092] The pass / fail determination circuit (116) can output a pass / fail result (PF) as "1" when the sum result is greater than a predetermined reference value based on the count result (CNT) output from the fail bit counter (115), and output a pass / fail result (PF) as "0" when the sum result is not greater than the reference value. The pass / fail result (PF) may be the node operation result (y) of the first node (ND1) as the result of performing an activation operation on the sum result.

[0093] The pass / fail result (PF) output from the pass / fail judgment circuit (116) can be transmitted to the input circuit (117).

[0094] Next, referring to FIG. 7, weights (w4~w7) corresponding to input connections from the first node (ND1) to the fifth to eighth nodes (ND5~ND8) may be stored in memory cells (C11~C14) connected to the word line (WLn-1).

[0095] For the operation of the second hidden layer (HL2), the selection circuits (61 to 64) can each transmit the node operation result (y) of the first node (ND1), that is, the pass / fail result (PF) received from the pass / fail determination circuit (116), to the page buffers (PB1 to PB4) as an input (x5) transmitted from the first node (ND1) to the fifth to eighth nodes (ND5 to ND8) under the control of the control circuit (111).

[0096] Additionally, a read operation can be performed on the memory cells (C11~C14). Specifically, by applying a read voltage to the word line (WLn-1), parameters (w4~w7) stored in the memory cells (C11~C14) can be read to the page buffers (PB1~PB4) respectively through the bit lines (BL1~BL4).

[0097] Page buffers (PB1~PB4) can each perform multiplication operations on the input (x5) and parameters (w4~w7). Subsequent operations of the second hidden layer (HL2) can be performed similarly to those described for the first hidden layer (HL1).

[0098] According to an embodiment, in the case of a structure that is not a Fully Connected Deep Neural Network (FC DNN), weights corresponding to paths that are not actually connected may be stored as "0" in memory cells. Accordingly, the memory device (100) can operate to implement both a Fully Connected Deep Neural Network and a Deep Neural Network other than a Fully Connected Deep Neural Network.

[0099] FIG. 8 is a diagram illustrating the deep neural network operation of a memory device (100) according to an embodiment.

[0100] Referring to FIG. 8, the memory device (100) can implement a deep neural network (DNN2) in which the input layer (IL) includes three input nodes (IND1~IND3) and the first hidden layer (HL1) includes three first to third nodes (ND1~ND3).

[0101] The input circuit (117) may include selection circuits (81 to 83). The selection circuits (81 to 83) may each receive external inputs (x1 to x3) and pass / fail results (PF1 to PF3). The output of selection circuit (81) may be connected to page buffers (PB1, PB4, PB7), the output of selection circuit (82) may be connected to page buffers (PB2, PB5, PB8), and the output of selection circuit (83) may be connected to page buffers (PB3, PB6, PB9). Each of the selection circuits (81 to 83) may output one of the corresponding external inputs and pass / fail results to the corresponding page buffers under the control of the control circuit (111).

[0102] Specifically, each of the selection circuits (81 to 83) can output a corresponding external input to perform operations of the first hidden layer (HL1) and output a corresponding pass / fail result to perform operations of the hidden layer after the first hidden layer (HL1). According to an embodiment, the output path from the selection circuits (81 to 83) to the page buffers (PB1 to PB9) may be controlled differently from the illustration depending on the connection structure between the input layer (IL) and the nodes of the plurality of hidden layers.

[0103] According to an embodiment, selection circuits (81 to 83) can receive program data (PD) of FIG. 2 as external inputs (x1 to x3) and output it to page buffers (PB1 to PB9).

[0104] Additionally, the memory device (100) may include fail bit counters (801 to 803) and pass / fail determination circuits (811 to 813).

[0105] Each of the fail bit counters (801–803) can receive multiplication results from a set of corresponding page buffers. For example, fail bit counter (801) can receive multiplication results (m1–m3) from page buffers (PB1–PB3), fail bit counter (802) can receive multiplication results (m4–m6) from page buffers (PB4–PB6), and fail bit counter (803) can receive multiplication results (m7–m9) from page buffers (PB7–PB9). Each of the fail bit counters (801–803) operates similarly to fail bit counter (115) with respect to the received multiplication results, and fail bit counters (801–803) can each output count results (CNT1–CNT3).

[0106] Pass / fail determination circuits (811~813) are each connected to fail bit counters (801~803) and can each receive count results (CNT1~CNT3) from the fail bit counters (801~803). Each of the pass / fail determination circuits (811~813) operates similarly to the pass / fail determination circuit (116) for the corresponding count result, and the pass / fail determination circuits (811~813) can each output pass / fail results (PF1~PF3).

[0107] Memory cells (C1~C9) connected to the word line (WLn) can store weights (w11, w21, w31, w12, w22, w32, w13, w23, w33) corresponding to the input connections of the first to third nodes (ND1~ND3). Specifically, memory cells (C1~C3) can store weights (w11, w21, w31) corresponding to the input connections of the first node (ND1), memory cells (C4~C6) can store weights (w12, w22, w32) corresponding to the input connections of the second node (ND2), and memory cells (C7~C9) can store weights (w13, w23, w33) corresponding to the input connections of the third node (ND3).

[0108] To specifically describe the operations performed in the first hidden layer (HL1), selection circuits (81 to 83) can transmit external inputs (x1 to x3) to page buffers (PB1 to PB9) under the control of the control circuit (111). Specifically, selection circuit (81) transmits external input (x1) to page buffers (PB1, PB4, PB7), selection circuit (82) transmits external input (x2) to page buffers (PB2, PB5, PB8), and selection circuit (83) transmits external input (x3) to page buffers (PB3, PB6, PB9).

[0109] Additionally, a read operation can be performed on the memory cells (C1 to C9). Specifically, by applying a read voltage to the word line (WLn), the weights (w11, w21, w31, w12, w22, w32, w13, w23, w33) stored in the memory cells (C1 to C9) can be read into the page buffers (PB1 to PB9) respectively through the bit lines (BL1 to BL9).

[0110] Each of the page buffers (PB1~PB9) performs a multiplication operation on the received external input and weight, and the page buffers (PB1~PB9) can output the multiplication results (m1~m9).

[0111] The operation corresponding to the first node (ND1) can be implemented through page buffers (PB1~PB3) that perform multiplication operations and output multiplication results (m1~m3), a fail bit counter (801) that performs summation operations on the multiplication results (m1~m3) and outputs a count result (CNT1), and a pass / fail determination circuit (811) that performs activation operations on the count result (CNT1). The pass / fail result (PF1) can correspond to the node operation result (y1) of the first node (ND1).

[0112] Additionally, the operation corresponding to the second node (ND2) can be implemented through page buffers (PB4~PB6) that perform multiplication operations and output multiplication results (m4~m6), a fail bit counter (802) that performs summation operations on the multiplication results (m4~m6) and outputs a count result (CNT2), and a pass / fail determination circuit (812) that performs activation operations on the count result (CNT2). The pass / fail result (PF2) can correspond to the node operation result (y2) of the second node (ND2).

[0113] Additionally, the operation corresponding to the third node (ND3) can be implemented through page buffers (PB7~PB9) that perform multiplication operations and output multiplication results (m7~m9), a fail bit counter (803) that performs summation operations on the multiplication results (m7~m9) and outputs a count result (CNT3), and a pass / fail determination circuit (813) that performs activation operations on the count result (CNT3). The pass / fail result (PF3) can correspond to the node operation result (y3) of the third node (ND3).

[0114] The pass / fail results (PF1~PF3) can be transferred to the input circuit (117) for operations to be performed in the next hidden layer of the first hidden layer (HL1).

[0115] FIG. 9 is a block diagram illustrating a memory device (900) capable of performing deep neural network operation according to an embodiment.

[0116] Referring to FIG. 9, compared to memory device (100), memory device (900) may further include majority check circuits (MJC1 to MJCp). The remaining circuit configurations of memory device (900) may be configured similarly to those described with reference to FIG. 2.

[0117] Each of the majority check circuits (MJC1~MJCp) can be connected to a corresponding page buffer (or a corresponding page buffer group) among the page buffers (PB1~PBm). Each of the majority check circuits (MJC1~MJCp) can output a final multiplication result by performing a majority check operation on the multiplication results received from the corresponding page buffers.

[0118] Specifically, the majority check circuit (MJC1) can determine the final multiplication result (mf1) based on the number of multiplication results having the same value by comparing the values ​​of the multiplication results (M1) received from the corresponding page buffers. Similarly, the majority check circuit (MJCp) can determine the final multiplication result (mfp) based on the number of multiplication results having the same value by comparing the values ​​of the multiplication results (Mp) received from the corresponding page buffers. For example, the multiplication results (Mp) may include eight multiplication results (mp1 to mp8). If five or more of the multiplication results (mp1 to mp8) have the same value, the majority check circuit (MJCp) can output that value as the final multiplication result (mfp).

[0119] The fail bit counter (115) receives final multiplication results (mf1 to mfp) from majority check circuits (MJC1 to MJCp), performs a summation operation on the final multiplication results (mf1 to mfp) similarly to what is described with reference to FIG. 2, and can output a count result (CNT) as a result of the summation operation.

[0120] Although not shown, the fail bit counter (115) can receive verification data (VD) from a plurality of page buffers (114) as described with reference to FIG. 2 and perform a counting operation on the verification data (VD).

[0121] Therefore, the majority check circuits (MJC1~MJCp) can provide a stable result by referring to the majority of multiplication results even if errors exist in some multiplication results, and thus the reliability of the deep neural network operation can be improved.

[0122] FIG. 10 is a diagram illustrating the deep neural network operation of a memory device (900) according to an embodiment.

[0123] Referring to FIG. 10, the same weight (w1) can be stored in memory cells (C1~C8) connected to word lines (WLn) and bit lines (BL1~BL8). Additionally, the same weight (w2) can be stored in memory cells (C9~C16) connected to word lines (WLn) and bit lines (BL9~BL16).

[0124] Additionally, an external input (x1) can be input to page buffers (PB1~PB8) connected to bit lines (BL1~BL8) respectively through an unillustrated input circuit (117). The page buffers (PB1~PB8) can form a single page buffer group. Furthermore, an external input (x2) can be input to page buffers (PB9~PB16) connected to bit lines (BL9~BL16) respectively through the input circuit (117). The page buffers (PB9~PB16) can form a single page buffer group.

[0125] By applying a read voltage to the word line (WLn), the same weight (w1) stored in the memory cells (C1~C8) can be read to the page buffers (PB1~PB8) through the bit lines (BL1~BL8), and at the same time, the same weight (w2) stored in the memory cells (C9~C16) can be read to the page buffers (PB9~PB16) through the bit lines (BL9~BL16).

[0126] Page buffers (PB1~PB8) can each perform multiplication operations on an external input (x1) and a weight (w1). Additionally, page buffers (PB9~PB16) can each perform multiplication operations on an external input (x2) and a weight (w2).

[0127] A majority check circuit (MJC1) can receive multiplication results (m11~m18) included in the multiplication results (M1) of FIG. 9 from page buffers (PB1~PB8) and output a final multiplication result (mf1) by performing a majority check operation on the multiplication results (m11~m18). Additionally, a majority check circuit (MJC2) can receive multiplication results (m21~m28) and output a final multiplication result (mf2) by performing a majority check operation on the multiplication results (m21~m28).

[0128] The fail bit counter (115) and the pass / fail determination circuit (116) can operate similarly to the above.

[0129] FIG. 11 is a block diagram illustrating a computing device (1100) that performs deep neural network computation operations according to an embodiment.

[0130] The computing device (1100) may include a controller (1110) and a memory device (1120).

[0131] The controller (1110) can store parameters (PRM), such as weights and biases required for deep neural network operation, in a memory device (1120) before performing deep neural network operation.

[0132] According to an embodiment, the parameter (PRM) may be stored in advance in a memory device (1120) by an external device during the manufacturing process or initial setup stage.

[0133] According to an embodiment, the controller (1110) can control that some of the bitlines (BL1 to BLm) are not used in deep neural network operation. For example, the controller (1110) can store dummy values ​​in memory cells connected to some bitlines. For example, the controller (1110) can store weights corresponding to the input connections of the first node of the first hidden layer (HL1) in memory cells connected to the first bitlines, weights corresponding to the input connections of the second node of the first hidden layer (HL1) in memory cells connected to the second bitlines spaced apart from the first bitlines, and weights corresponding to the input connections of the third node of the first hidden layer (HL1) in memory cells connected to the third bitlines spaced apart from the second bitlines. At this time, the controller (1110) can store dummy values ​​in memory cells connected to bitlines between the first bitlines and the second bitlines and between the second bitlines and the third bitlines.

[0134] The controller (1110) can control the memory device (1120) to perform deep neural network operation by transmitting external input data (DIN) to the memory device (1120). The external input data (DIN) may be provided from an external host device or application processor (AP).

[0135] The memory device (1120) can perform a deep neural network operation based on stored parameters (PRM) and external input data (DIN) under the control of the controller (1110), and output output data (DOUT) to the controller (1110) as a result of the deep neural network operation.

[0136] The memory device (1120) may include a structure similar to, for example, the memory device (100) shown in FIG. 2 or the memory device (900) shown in FIG. 9.

[0137] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Furthermore, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and thus the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention. Explanation of the symbols

[0138] 100: Memory device 110: Peripheral circuit 111: Control circuit 112: Voltage generation circuit 113: Decoder 114: Page buffers 115: Fail beat counter 116: Pass / Fail Judgment Circuit 117: Input circuit 118: Output circuit 120: Memory cell array MB1~MBk: Memory blocks

Claims

Claim 1 A memory cell array comprising memory cells connected to word lines and bit lines, wherein the memory cells are NAND flash memory cells; and a plurality of page buffers configured to store first values ​​read from first memory cells connected to a first word line among the word lines through the bit lines in a deep neural network operation, and to perform multiplication operations on the inputs and the first values, respectively. Claim 2 A memory device according to claim 1, wherein each of the plurality of page buffers comprises: a first latch configured to store a corresponding input among the inputs; a second latch configured to store a corresponding first value among the first values; and a multiplication circuit configured to perform a multiplication operation on the corresponding input stored in the first latch and the corresponding first value stored in the second latch. Claim 3 A memory device according to claim 1, further comprising a fail bit counter configured to output a count result by performing a counting operation to count the number of fail bits in the verification data, wherein the fail bit counter outputs the count result by performing the counting operation on the multiplication results output from one or more first page buffers among the plurality of page buffers in the deep neural network operation, and wherein the count result corresponds to the result of performing an sum operation on the multiplication results. Claim 4 A memory device according to claim 3, further comprising a pass / fail determination circuit configured to output a pass / fail result of the internal operation based on the count result received from the fail bit counter, wherein the pass / fail determination circuit outputs the pass / fail result for the count result in the deep neural network operation, and the pass / fail result corresponds to the result of performing an activation operation on the result of the sum operation. Claim 5 In claim 4, the memory device further comprises a control circuit configured to control a read operation for the first memory cells to perform an operation of the first hidden layer of the deep neural network in the deep neural network operation, and to control a read operation for the second memory cells connected to the second word line among the word lines to perform an operation of the second hidden layer of the deep neural network, wherein the first memory cells store parameters corresponding to the input connections of the nodes of the first hidden layer, and the second memory cells store parameters corresponding to the input connections of the nodes of the second hidden layer. Claim 6 A memory device according to claim 5, further comprising, in the deep neural network operation, an input circuit configured to transmit external inputs received from the outside to the plurality of page buffers as inputs transmitted from the input layer of the deep neural network to the first hidden layer, and to transmit the pass / fail result received from the pass / fail determination circuit to at least one page buffer selected among the plurality of page buffers as an input transmitted from the first hidden layer to the second hidden layer, wherein the at least one page buffer is selected based on at least one input connection from the first hidden layer to the second hidden layer. Claim 7 A memory device according to claim 6, further comprising: a second fail bit counter configured to output a second count result by performing a counting operation on second multiplication results output from one or more second page buffers among the plurality of page buffers in the deep neural network operation; and a second pass / fail determination circuit configured to output a second pass / fail result as a result of performing the activation operation on the second count result in the deep neural network operation, wherein the input circuit transmits the second pass / fail result received from the second pass / fail determination circuit to at least one selected second page buffer among the plurality of page buffers as a second input transmitted from the first hidden layer to the second hidden layer. Claim 8 A memory cell array comprising memory cells connected to word lines and bit lines, wherein the memory cells are NAND flash memory cells; a plurality of page buffers configured to store first values ​​read from first memory cells connected to a first word line among the word lines through the bit lines in a deep neural network operation, and to perform multiplication operations on the inputs and the first values, respectively; and a plurality of majority check circuits each connected to a plurality of page buffer groups into which the plurality of page buffers are divided, wherein each of the plurality of majority check circuits performs a majority check operation on multiplication results received from one or more corresponding page buffers included in the corresponding page buffer group in the deep neural network operation, and outputs a final multiplication result. Claim 9 A memory device according to claim 8, wherein one or more page buffers included in the same page buffer group among the plurality of page buffer groups each perform multiplication operations on the same input and the same first value. Claim 10 A memory device according to claim 8, wherein each of the plurality of page buffers comprises: a first latch configured to store a corresponding input among the inputs; a second latch configured to store a corresponding first value among the first values; and a multiplication circuit configured to perform a multiplication operation on the corresponding input stored in the first latch and the corresponding first value stored in the second latch. Claim 11 In claim 8, the memory device further comprises a fail bit counter configured to output a count result by performing a counting operation to count the number of fail bits in the verification data, wherein the fail bit counter outputs the count result by performing the counting operation on the final multiplication results output from the plurality of majority check circuits in the deep neural network operation, and the count result corresponds to the result of performing an sum operation on the final multiplication results. Claim 12 A memory device according to claim 11, further comprising a pass / fail determination circuit configured to output a pass / fail result of the internal operation based on the count result received from the fail bit counter, wherein the pass / fail determination circuit outputs the pass / fail result for the count result in the deep neural network operation, and the pass / fail result corresponds to the result of performing an activation operation on the result of the sum operation. Claim 13 In claim 12, the memory device further comprises a control circuit configured to control a read operation for the first memory cells to perform an operation of the first hidden layer of the deep neural network in the deep neural network operation, and to control a read operation for the second memory cells connected to the second word line among the word lines to perform an operation of the second hidden layer of the deep neural network, wherein the first memory cells store parameters corresponding to the input connections of the nodes of the first hidden layer, and the second memory cells store parameters corresponding to the input connections of the nodes of the second hidden layer. Claim 14 A memory device according to claim 13, further comprising, in the deep neural network operation, an input circuit configured to transmit external inputs received from the outside to the plurality of page buffers as inputs transmitted from the input layer of the deep neural network to the first hidden layer, wherein the input circuit transmits the same external input to one or more page buffers included in the same page buffer group among the plurality of page buffer groups. Claim 15 A memory device according to claim 14, wherein the input circuit transmits the pass / fail result received from the pass / fail determination circuit to at least one selected page buffer among the plurality of page buffers as an input transmitted from the first hidden layer to the second hidden layer. Claim 16 A memory device comprising memory cells connected to word lines and bit lines, wherein the memory cells are NAND flash memory cells; and a computation device comprising a controller configured to control the memory device to perform a deep neural network computation operation by storing first parameters corresponding to input connections of nodes of a first hidden layer of a deep neural network in first memory cells connected to a first word line among the word lines, and transmitting external inputs to the memory device, wherein the memory device further comprises a plurality of page buffers configured to store the first parameters read from the first memory cells through the bit lines, store the external inputs, and perform multiplication operations on the external inputs and the first parameters, respectively, in the deep neural network computation operation. Claim 17 In claim 16, the memory device further comprises a fail bit counter configured to receive verification data from the plurality of page buffers, which is the result of a verification operation performed to determine whether the internal operation is completed after the internal operation is performed on the target memory cells, and to output a count result by performing a counting operation to count the number of fail bits in the verification data, wherein the fail bit counter outputs the count result by performing a counting operation on the multiplication results output from one or more first page buffers among the plurality of page buffers in the deep neural network operation, and the count result corresponds to the result of performing an sum operation on the multiplication results. Claim 18 In claim 17, the memory device further comprises a pass / fail determination circuit configured to output a pass / fail result of the internal operation based on the count result received from the fail bit counter, wherein the pass / fail determination circuit outputs the pass / fail result for the count result in the deep neural network operation, and the pass / fail result corresponds to the result of performing an activation operation on the result of the sum operation. Claim 19 In paragraph 18, the controller is a computing device that stores second parameters corresponding to input connections of nodes of the second hidden layer of the deep neural network in second memory cells connected to the second word line among the word lines. Claim 20 In claim 19, the computing device further comprises a control circuit configured to control a read operation for the first memory cells to perform an operation of the first hidden layer and to control a read operation for the second memory cells to perform an operation of the second hidden layer in the above deep neural network operation. Claim 21 In claim 19, the memory device further comprises an input circuit configured to transmit the pass / fail result received from the pass / fail determination circuit in the deep neural network operation to at least one page buffer selected among the plurality of page buffers as an input transmitted from the first hidden layer to the second hidden layer, wherein the at least one page buffer is selected based on at least one input connection from the first hidden layer to the second hidden layer.

Images