Semiconductor devices and related methods

Abstract

For example, a semiconductor device may include a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate may include a first substrate surface and a second substrate surface facing each other, an outer substrate wall between the first substrate surface and the second substrate surface, and an inner substrate wall defining a cavity between the first substrate surface and the second substrate surface. The device stack may be located within the cavity and may include a first electronic device and a second electronic device stacked on the first electronic device. The first internal interconnect may be coupled to the substrate and the device stack. The encapsulant may cover the inner substrate wall and the device stack and fill the cavity. Other examples and related methods are disclosed herein.

Description

Technology Field

[0001] This application is a partial continuation of (pending) U.S. Application No. 16 / 429,553, filed on June 3, 2019, under the title “Semiconductor Devices and Related Methods” (Document No. MCK-63846US01). This application also claims the benefit of (pending) U.S. Application No. 62 / 902,473, filed on September 19, 2019, under the title “Semiconductor Devices AND Related Methods” (Document No. CK-018PR). Application No. 16 / 429,553 and Application No. 62 / 902,473 are incorporated herein by reference in their entirety.

[0002] The present disclosure generally relates to electronic devices, more specifically to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0004] Conventional semiconductor packages and methods for forming semiconductor packages are inadequate, for example, because they result in excessive costs, reduced reliability, relatively low performance, or package sizes that are too large. Additional limitations and disadvantages of conventional and traditional methods will become apparent to those skilled in the art by comparing these methods with reference to the present invention and the drawings. The problem to be solved

[0006] The present disclosure generally relates to electronic devices, more specifically to semiconductor devices and methods for manufacturing semiconductor devices. means of solving the problem

[0008] A semiconductor device according to the present invention may include: a substrate having a first substrate surface, a second substrate surface opposite to the first substrate surface, an outer substrate wall between the first substrate surface and the second substrate surface, and an inner substrate wall defining a cavity between the first substrate surface and the second substrate surface; a device stack having a first electronic device and a second electronic device stacked on the first electronic device and located within the cavity; a first internal interconnect coupled to the substrate and the device stack; a second internal interconnect coupled to the first electronic device and the second electronic device; and an encapsulant covering the inner substrate wall and the device stack and filling the cavity.

[0009] Here, the substrate includes a substrate shelf adjacent to a first edge of the substrate; the substrate shelf includes an internal terminal on a first substrate surface; and the encapsulant may cover the first substrate surface, leaving the substrate shelf and the internal terminal exposed.

[0010] And the above encapsulant includes a recessed sidewall at an interface with the substrate shelf; said recessed sidewall may be inclined at an acute angle with respect to the first substrate surface.

[0011] Additionally, it further includes a vertical interconnect connected to a first internal terminal on a first substrate surface, wherein the vertical interconnect extends through an encapsulant and can be exposed at the top of the encapsulant.

[0012] Additionally, at least one side of the device stack may not be bounded by a substrate.

[0013] Additionally, the device stack further includes a stack cap at the top, wherein the stack cap has a cap thermal expansion coefficient; the device stack has a device thermal expansion coefficient; the encapsulant has an encapsulant thermal expansion coefficient; and the cap thermal expansion coefficient may be closer to the device thermal expansion coefficient than to the encapsulant thermal expansion coefficient.

[0014] In addition, the thermal expansion coefficient of the cap may be substantially the same as the thermal expansion coefficient of the device.

[0015] Additionally, the device stack may further include a stack cap on the top of the device stack, wherein the stack cap is exposed on the top of the encapsulant; and the device stack may be exposed on the bottom surface of the encapsulant.

[0016] Additionally, the substrate includes a first external interconnect and a second external interconnect, wherein the substrate includes a first shelf of the substrate adjacent to a first edge of the substrate and a first external terminal on a second substrate surface below the first shelf; the substrate includes a second shelf of the substrate adjacent to a second edge of the substrate and a second external terminal on a second substrate surface below the second shelf; the encapsulant covers the first substrate surface and leaves the first shelf of the substrate and the second shelf of the substrate exposed; the first external interconnect is coupled to the first external terminal below the first shelf outside the footprint of the encapsulant; and the second external interconnect can be coupled to the second external terminal below the second shelf outside the footprint of the encapsulant.

[0017] In addition, the method according to the present invention may comprise: (a) a step of receiving a substrate, wherein the substrate has a first substrate surface, a second substrate surface opposite to the first substrate surface, an outer substrate wall between the first substrate surface and the second substrate surface, and an inner substrate wall defining a cavity between the first substrate surface and the second substrate surface; (b) a step of providing a device stack within the cavity, wherein the device stack has a first electronic device and a second electronic device stacked on the first electronic device; (c) a step of providing a first internal interconnect coupled to the substrate and the device stack; (d) a step of providing a second internal interconnect coupled to the first electronic device and the second electronic device; and (e) a step of providing an encapsulant that covers the inner substrate wall and the device stack and fills the cavity.

[0018] Herein, the method includes the step of providing a vertical interconnect coupled to a first internal terminal on a first substrate surface before providing an encapsulant, wherein the vertical interconnect extends through the encapsulant and may be exposed on the upper surface of the encapsulant.

[0019] And it may include the step of providing a stack cap on the upper surface of the device stack.

[0020] Additionally, the substrate includes a first substrate shelf adjacent to a first edge of the substrate, and a first external terminal on a second substrate surface below the first shelf; the substrate includes a second substrate shelf adjacent to a second edge of the substrate, and a second external terminal on a second substrate surface below the second shelf; the encapsulant covers the first substrate surface and leaves the first substrate shelf and the second substrate shelf exposed; the method may further include the steps of: providing a first external interconnect coupled to the first external terminal on the lower part of the first shelf outside the footprint of the encapsulant; and providing a second external interconnect coupled to the second external terminal on the lower part of the second shelf outside the footprint of the encapsulant.

[0021] In addition, a semiconductor device according to the present invention may include a base substrate having a first surface and an internal base terminal on the first surface; a first module on the base substrate, wherein the first module comprises a first substrate surface; a second substrate surface opposite to the first substrate surface; an outer sidewall of the substrate between the first substrate surface and the second substrate surface; and an inner sidewall of the substrate defining a cavity between the first substrate surface and the second substrate surface; a first electronic device; a device stack comprising a second electronic device stacked on the first electronic device; a first internal interconnect coupled to the substrate and the device stack; and a first encapsulant covering the inner sidewall of the substrate and the device stack and filling the cavity, a second module on the first module; and a second encapsulant on the base substrate and in contact with the horizontal plane of the first module and the second module.

[0022] Here, it may further include a module interconnect located within the second in-capsule and coupled with the internal base terminal and substrate of the first module.

[0023] And the substrate of the first module includes a substrate shelf adjacent to a first edge of the substrate; the substrate shelf includes an internal terminal on the first substrate surface; the first encapsulant covers the first substrate, leaving the substrate shelf and the internal terminal exposed; and the module interconnect can be coupled with the internal terminal.

[0024] Additionally, the first incapsulant includes a recessed sidewall at an interface with the first substrate shelf; and the recessed sidewall may be inclined at an acute angle with respect to the first substrate surface.

[0025] Additionally, the first module includes a vertical interconnect coupled to a first internal terminal on the first substrate surface; the vertical interconnect extends through the first encapsulant and is exposed on the upper surface of the first encapsulant; and the module interconnect can be coupled to the substrate through the vertical interconnect.

[0026] In addition, the first module may include a stack cap on the upper surface of the device stack.

[0027] Additionally, it may further include an external interconnect located within the second in-capsulant that contacts the upper surface of the base substrate and the lower surface of the substrate of the first module. Brief explanation of the drawing

[0029] FIGS. 1a and FIGS. 1b are cross-sectional views illustrating an exemplary semiconductor device. FIGS. 2a to 2h are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 3 is a cross-sectional view illustrating an exemplary semiconductor device. FIGS. 4a to 4h are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 5 is a cross-sectional view illustrating an exemplary semiconductor device. FIGS. 6a to 6c are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 7 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 8 is a cross-sectional view illustrating an exemplary semiconductor device. FIGS. 9a to 9g are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 10 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 11 is a cross-sectional view illustrating an exemplary semiconductor device. FIGS. 12a to 12d are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 13 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 14 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 15 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 16 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 17 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 18 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 19 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 20 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 21 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 22 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 23 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 24 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 25 is a cross-sectional view illustrating an exemplary semiconductor device. FIG. 26 is a cross-sectional view illustrating an exemplary semiconductor device. Specific details for implementing the invention

[0030] The following discussion provides various examples of semiconductor devices and methods for manufacturing semiconductor devices. Since these examples are non-limiting, the scope of the appended claims should not be limited to the specific examples disclosed. In the following discussion, the phrases "example" and "e.g." are non-limiting.

[0031] The drawings illustrate the general configuration, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the present disclosure. Additionally, the components in the drawings are not necessarily drawn in proportion. For example, to enhance understanding of the examples discussed in the present disclosure, the dimensions of some components in the drawings may be exaggerated compared to others. The same reference numerals in different drawings indicate the same components.

[0032] The term "or" means one or more items in a list combined by "or". For example, "x or y" means any one of the three component sets of {(x), (y), (x, y)}. As another example, "x, y or z" means any one of the seven component sets of {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}.

[0033] The terms “comprises,” “comprising,” “includes,” or “including” are “open-ended” terms that specify the existence of the mentioned features but do not exclude the existence or addition of one or more other features.

[0034] Terms such as "first," "second," etc., may be used herein to describe various components, and these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, the first component discussed in this disclosure may be referred to as the second component without departing from the teachings of this disclosure.

[0035] Unless otherwise specified, the term “coupled” may be used to describe two components in direct contact with each other or two components indirectly connected by one or more other components. For example, if component A is coupled to component B, component A may be in direct contact with component B or indirectly connected to component B by an interposed component C. Similarly, the terms “over” or “on” may be used to describe two components in direct contact with each other or two components indirectly connected by one or more other components.

[0036] In one example, a semiconductor device may include a substrate, a device stack, first and second internal interconnects, and an encapsulant. The substrate may include a first substrate surface and a second substrate surface located opposite each other, an outer substrate wall between the first substrate surface and the second substrate surface, and an inner substrate wall defining a cavity between the first substrate surface and the second substrate surface. The device stack may be located within the cavity and includes a first electronic device and a second electronic device stacked on the first electronic device. The first internal interconnect may be coupled to the substrate and the device stack. The second internal interconnect may be coupled to the first electronic device and the second electronic device. The encapsulant may cover the inner substrate wall and the device stack and fill the cavity.

[0037] In one example, the method may include: (a) receiving a substrate having a first substrate surface, a second substrate surface opposite to the first substrate surface, an outer substrate wall between the first substrate surface and the second substrate surface, and an inner substrate wall defining a cavity between the first substrate surface and the second substrate surface; (b) providing a device stack having a first electronic device and a second electronic device stacked on the first electronic device within the cavity; (c) providing a first internal interconnect coupled to the substrate and the device stack; (d) providing a second internal interconnect coupled to the first electronic device and the second electronic device; and (e) providing an encapsulant that covers the inner substrate wall and the device stack and fills the cavity.

[0038] Other examples are incorporated into the present disclosure. Such examples can be found in the drawings, claims, or description of the present disclosure.

[0039] FIGS. 1a and FIGS. 1b are cross-sectional views illustrating exemplary semiconductor devices (100, 100'). In the present disclosure, the reference numeral for the semiconductor device (100) or its components may also refer to the semiconductor device (100') or its corresponding components.

[0040] In the example illustrated in FIG. 1, the semiconductor device (100) may include a substrate (110), a device stack (120), an internal interconnect (130), an encapsulant (140), and an external interconnect (150). In some examples, the semiconductor device (100) may include or be referred to as a module (101).

[0041] The substrate (110) may include a cavity (111), an internal terminal (112), and an external terminal (113). The device stack (120) may include a plurality of electronic devices (121, 122, 123, 124). Additionally, each of the plurality of electronic devices (121, 122, 123, 124) may include a device terminal (121a, 122a, 123a, 124a).

[0042] The substrate (110), internal interconnect (130), encapsulant (140), and external interconnect (150) may include or be referred to as a semiconductor package, and the semiconductor package may protect the device stack (120) from external components or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (120).

[0043] FIGS. 2a to 2h are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 2a is a cross-sectional view illustrating a semiconductor device (100) in the initial manufacturing stage.

[0044] In the example illustrated in FIG. 2a, a substrate (110) may be attached to the top of a carrier (10). Although FIG. 2a is illustrated as having only one substrate (110) attached to the carrier (10), multiple substrates (110) may be arranged on the carrier (10) for the simultaneous production of multiple modules (101). In some examples, multiple substrates (110) may be singulated from a larger strip or substrate and arranged on the carrier (10) after singulation to leave a gap between adjacent substrates (110). In some examples, multiple substrates (110) may be attached to the carrier (10) before singulation, still in the form of a strip or a larger substrate, without a gap between adjacent substrates (110).

[0045] The carrier (10) may include a base layer (11) and a separable layer (12). In some examples, the base layer (11) may include a metal, glass, or semiconductor material. In some examples, the carrier (10) or the base layer (11) may include a rectangular shape, such as a panel or strip, or a disc shape, such as a wafer. The separable layer (12) may include a temporary adhesive tape or film, a revalpha tape, a thermal release tape, an adhesive tape, or an adhesive film. In some examples, the separable layer (12) may be removed by heating, chemical materials, light irradiation, or physical force.

[0046] A substrate (110) may include a cavity (111), a substrate dielectric structure (114), and a substrate conductive structure (115). The substrate cavity (111) may be defined as an inner wall (110i) of the substrate dielectric structure (114). The substrate dielectric structure (114) may include one or more dielectrics, and the substrate conductive structure (115) may include one or more conductors stacked or embedded between dielectrics corresponding to the substrate dielectric structure (114). The substrate conductive structure (115) may include substrate terminals, such as an internal terminal (112) and an external terminal (113), which are electrically connected to each other by internally penetrating the substrate (110) by a substrate conductor (115a).

[0047] In some examples, the substrate dielectric structure (114) may include or be referred to as one or more dielectrics, dielectric materials, dielectric layers, passivation layers, insulating layers, or protective layers. In some examples, the substrate dielectric structure (114) may include electrical insulating materials such as polymers, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), bismaleimide triazine (BT), molding materials, phenolic resin, epoxy, silicone, or acrylate polymers. In some examples, the substrate dielectric structure (114) may be formed by various processes such as spin coating, spray coating, printing, oxidation, PVD (Physical Vapor Deposition), CVD (Chemical Vapor Deposition), MOCVD (MetalOrganic Chemical Vapor Deposition), ALD (Atomic Layer Deposition), LPCVD (Low Pressure Chemical Vapor Deposition), or PECVD (Plasma-Enhanced Chemical Vapor Deposition). Each dielectric or layer of the substrate dielectric structure (114) may have a thickness range of about 1 μm to about 20 μm.

[0048] In some examples, the substrate conductive structure (115) may include or be referred to as one or more conductors, conductive materials, conductive paths, conductive layers, redistribution layers (RDL), wiring layers, trace patterns, or circuit patterns. In some examples, the substrate conductive structure (115) may include various conductive materials such as copper, gold, or silver. The substrate conductive structure (115) may be formed by various processes such as sputtering, electroless plating, electroplating, PVD, CVD, MODVD, ALD, LPCVD, or PECVD. Each conductor or layer of the substrate conductive structure (115) may have a thickness range of about 5 µm to about 50 µm.

[0049] In some examples, the substrate (110) may include a multi-layed printed circuit board (multi-layed PCB), a pre-formed substrate, a redistribution layer (RDL) substrate, an interposer, a lead frame, or a micro lead frame. In some examples, the thickness of the substrate (110) may range from about 90 µm to about 110 µm.

[0050] In some examples, the cavity (111) is formed within the substrate (110) and may be formed to penetrate the substrate (110). For example, the cavity (111) may be formed by removing a portion of the substrate (110). In some examples, the cavity (111) may be formed by cutting a portion of the substrate (110) using a laser or a blade. In some examples, by forming the cavity (111) in the substrate (110), the substrate (110) may be formed as a roughly rectangular frame having an empty space. In some examples, the substrate (110) may include an open parallel frame, and the cavity (111) may be bordered by the substrate (110) on both parallel sides, but may not be open or bordered by the substrate (110) elsewhere. The width of the cavity (111) may range from about 8500 µm to about 9500 µm. In some examples, the cavity (111) may provide a space in which a device stack (120) can be seated. Additionally, the cavity (111) may serve to reduce the size, particularly the height, of the semiconductor device (100).

[0051] In some examples, the internal terminal (112) may include or be referred to as a pad, bond pad, circuit pattern, wiring layer, or metal layer. The internal terminal (112) may include an electrically conductive material such as, for example, aluminum, copper, aluminum alloy, or copper alloy. For example, the internal terminal (112) may be formed by an electroplating or a PVD (physical vapor deposition) process. The internal terminal (112) may be formed on a first surface (top surface) (110a) of the substrate (110) and exposed to the top of the substrate (110). In some examples, the internal terminal (112) may be provided as an electrical contact to provide electrical signals of the substrate (110) to the device stack (120) or electrical signals of the device stack (120) to the substrate (110).

[0052] In some examples, the external terminal (113) may be referred to as a pad, circuit pattern, wiring layer, or metal layer. The external terminal (113) may include an electrically conductive material, such as, for example, a metal material, aluminum, copper, an aluminum alloy, or a copper alloy. For example, the external terminal (113) may be formed by an electroplating or a PVD (physical vapor deposition) process. The external terminal (113) may be formed on a second surface (bottom surface) (110b) of the substrate (110) and exposed to the bottom of the substrate (110). In some examples, the external terminal (113) may be provided as an electrical contact to provide electrical signals of the substrate (110) to external electronic components, or to provide electrical signals of external electronic components to the substrate (110).

[0053] In some examples, the substrate (110) may be a redistribution layer ("RDL") substrate. The RDL substrate may include one or more conductive redistribution layers and one or more dielectric layers. The one or more conductive redistribution layers and one or more dielectric layers may be formed layer by layer on an electronic device to which the RDL substrate is electrically coupled (a) or on a carrier that may be removed wholly or at least partially after the electronic device and the RDL substrate are coupled together. The RDL substrate may be manufactured layer by layer as a wafer-level substrate on a circular wafer in a wafer-level process or as a panel-level substrate on a rectangular or square panel carrier in a panel-level process. The RDL substrate may be formed by an additional build-up process that may include one or more conductive layers alternately stacked with one or more dielectric layers, and the one or more conductive layers are defined as each conductive redistribution pattern or trace that constitutes (a) a fan-out electrical trace outside the footprint of the electronic device or (b) a fan-in electrical trace within the footprint of the electronic device. The conductive pattern can be formed using a plating process, for example, an electroplating process or an electroless plating process. The conductive pattern may include an electrically conductive material, for example, copper or other plating-compatible metals. The location of the conductive pattern can be created using a photo-patterning process, for example, a photoresist material and a photolithography process to form a photolithographic mask. The dielectric layer of the RDL substrate can be patterned by a photo-patterning process, which may include a photolithographic mask to which light is exposed to a photo-pattern of a desired shape, such as vias within the dielectric layer. The dielectric layer can be made of a photo-definable organic dielectric material, for example, polyimide (PI), benzocyclobutene (BCB), or polybenzoxazole (PBO).These dielectric materials may be ejected in liquid form or otherwise coated, rather than attached as a pre-formed film. To allow for the proper formation of the desired photo-defined shape, these photo-definable dielectric materials may be filler-free, meaning they may omit structural reinforcement or be free of strands, weaves, or other particles that could interfere with light during the photo-patterning process. In some examples, this filler-free characteristic of the filler-free dielectric material may allow for a reduction in the thickness of the resulting dielectric layer. Although the aforementioned photo-definable dielectric material may be an organic material, in other examples, the dielectric material of the RDL substrate may comprise one or more inorganic dielectric layers. Some examples of inorganic dielectric layers may comprise silicon nitride (Si3N4), silicon oxide (SiO2), or SiON. The inorganic dielectric layer may be formed by growing the inorganic dielectric layer using an oxidation or nitridation process instead of using the photo-defined organic dielectric material. These inorganic dielectric layers may be filler-free, without strands, weaves, or other dissimilar inorganic particles. In some examples, the RDL substrate may omit a permanent core structure or carrier, such as a dielectric material comprising, for example, bismalede triazine (BT) or FR4, and this type of RDL substrate may be referred to as a coreless substrate. Other substrates in the present invention may also include an RDL substrate.

[0054] In some examples, the substrate (110) may be a pre-formed substrate. The pre-formed substrate may be manufactured before being attached to an electronic device and may include a dielectric layer between each conductive layer. The conductive layer may include copper and may be formed using a plating process. The dielectric layer may be a relatively thick, non-photodefinable layer that can be attached as a pre-formed film rather than being a liquid, and may include a resin having fillers such as strands, weaves, or other inorganic particles for rigidity or structural support. Because the dielectric layer is non-photodefinable, shapes such as vias or openings may be formed using a drill or a laser. In some examples, the dielectric layer may include prepreg material or ABF (Ajinomoto Buildup Film). A preformed substrate may comprise a permanent core structure or carrier, such as a dielectric material including, for example, bismalede triazine (BT) or FR4, and the dielectric layer and conductive layer may be formed on the permanent core structure. In other examples, the preformed substrate may be a coreless substrate that omits the permanent core structure, and the dielectric layer and conductive layer may be formed on a sacrificial carrier that is removed after the dielectric layer and conductive layer are formed and before the electronic device is attached. The preformed substrate may be referred to as a printed circuit board (PCB) or a laminate substrate. Such a preformed substrate may be formed through a semi-additive or modified-semi-additive process. Other substrates in the present invention may also include a preformed substrate.

[0055] FIG. 2b is a cross-sectional view illustrating a semiconductor device (100) in the next stage of manufacturing. In the example illustrated in FIG. 2b, a device stack (120) may be formed in the cavity (111). The device stack (120) may include a first electronic device (121), a second electronic device (122), a third electronic device (123), and a fourth electronic device (124). Although FIG. 2b illustrates the device stack (120) as including four electronic devices (121, 122, 123, 124), this does not limit the invention. In some examples, the device stack (120) may be composed of four or more electronic devices or fewer electronic devices. In some examples, a first electronic device (121) may be attached to the upper surface of a carrier (10) within a cavity (111), and a second electronic device (122) may be attached to cover most of the upper surface of the first electronic device (121) using an adhesive member (20) to expose a portion of the upper surface of the first electronic device (121) including a device terminal (121a). A third electronic device (123) may be attached to cover most of the upper surface of the second electronic device (122) using an adhesive member (20) to expose a portion of the upper surface of the second electronic device (122) including a device terminal (122a), and a fourth electronic device (124) may be attached to cover most of the upper surface of the third electronic device (123) using an adhesive member (20) to expose a portion of the upper surface of the third electronic device (123) including a device terminal (123a). In some examples, the device stack (120) may be stacked in an offset structure, such as in a stepped, staggered, or zigzag shape. In some examples, the offset structure may align the electronic devices (121-124) such that each device terminal (121a, 122a, 123a, 124a) is exposed toward the same side of the semiconductor device (100).The height of the device stack (120) may be in the range of about 110 to 130 μm.

[0056] In some examples, when the device stack (120) is in the cavity (111), the upper surface of the first electronic device (121) may be lower than the upper surface of the substrate (110). In some examples, the upper surface of the second electronic device (122) may also be lower than the upper surface of the substrate (110). In some examples, the upper surface of the third electronic device (123) or the fourth electronic device (124) may be higher than the upper surface of the substrate (110). In some examples, most of the device stack (120) may be lower than the upper surface of the substrate (110). In some examples, the thickness of each of the second to fourth electronic devices (122-124) may be the same. In some examples, the thickness of the first electronic device (121) may be formed to be thicker than the thickness of the other electronic devices (122-124) to provide increased structural support or integrity of the device stack (120). In some examples, even though the thickness of the first electronic device (121) is thicker than the thickness of the second electronic device (122), the integrated circuit of the first electronic device (121) may be the same as the integrated circuit of the second electronic device (122).

[0057] In some examples, the first through fourth electronic devices (121, 122, 123, 124) may include or be referred to as semiconductor packages such as semiconductor dies, semiconductor chips, or chip-scale packages. The electronic devices (121, 122, 123, 124) may include semiconductor materials such as silicon (Si), for example. The electronic devices (121, 122, 123, 124) may include passive electronic circuit elements or active electronic circuit elements such as transistors. In some examples, the electronic devices (121, 122, 123, 124) may include electrical circuits such as digital signal processors (DSPs), microprocessors, network processors, power management processors, audio processors, RF circuits, wireless baseband system-on-chip (SoC) processors, sensors, and application-specific integrated circuits (ASICs). Each electronic device (121, 122, 123, 124) may include a device terminal (121a, 122a, 123a, 124a). In some examples, each device terminal (121a, 122a, 123a, 124a) may include or be referred to as a die pad, a bond pad, a bump, or an electrical contact for providing an electrical signal from the electronic device (121, 122, 123, 124) to the substrate (110) or an adjacent electronic device (121, 122, 123, 124), or for providing an electrical signal from the substrate (110) or an adjacent electronic device (121, 122, 123, 124) to the electronic device (121, 122, 123, 124).

[0058] FIG. 2c is a cross-sectional view illustrating a semiconductor device (100) in the next stage of manufacturing. In the example illustrated in FIG. 2c, an internal interconnect (130) can electrically connect the substrate (110) to each electronic device (121, 122, 123, 124) or device stack (120). In some examples, one or more internal interconnects (130) can connect one or more device terminals (121a, 122a, 123a, 124a) to one or more device terminals (121a, 122a, 123a, 124a).

[0059] In some examples, one or more internal interconnects (130) may connect an internal terminal (112) of a substrate (110) and one or more device terminals (121a, 122a, 123a, 124a). In some examples, a first end of the internal interconnect (130) may be coupled to an internal terminal (112) of a substrate (110), and a second end of the internal interconnect (130) may be coupled to a device stack (120) within a cavity (111), for example, and the height of the first end may be higher than the height of the second end of the internal interconnect (130).

[0060] In some examples, the internal interconnect (130) may include or be referred to as a wire, a conductive wire, or a bonding wire. The internal interconnect (130) may include, for example, a metal material, an electrically conductive material such as gold, silver, aluminum, or copper. In some examples, the internal interconnect (130) may be joined by wire bonding. The internal interconnect (130) may provide electrical coupling between the substrate (110) and the device stack (130) or between each electronic device (121, 122, 123, 124).

[0061] FIGS. 2d and FIGS. 2e are cross-sectional views illustrating a semiconductor device (100) in the next stage of manufacturing. In the example illustrated in FIG. 2d, an encapsulant (140) may encapsulate the device stack (120) and the internal interconnect (130). Additionally, the encapsulant (140) may also be provided between the inner wall (110i) of the substrate (110) and the device stack (120) to fill the cavity (111). As illustrated in FIG. 2d, the encapsulant (140) may overmold the device stack (120) and the internal interconnect (130), and as illustrated in FIG. 2e, it may be ground thinly. In some examples, grinding may be omitted by adjusting the height of the encapsulant (140) during the forming process.

[0062] In some examples, as illustrated in relation to the semiconductor device (100) of FIG. 1a, the outer wall (110s) of the substrate (110) may remain uncovered by the encapsulant (140) or may be substantially coplanar with the encapsulant (140). This configuration may be attributed to the pre-singulation option described above for arranging a plurality of substrates (110) on a carrier (10), and there is no gap between adjacently arranged substrates (110).

[0063] In some examples, as illustrated in relation to the semiconductor device (110') of FIG. 1b, the outer walls (110s) of the substrate (110) may be covered by an encapsulant (140'). This configuration may be attributed to the post-singulation option described above for arranging a plurality of substrates (110) on a carrier (10), such that a space exists between adjacently arranged substrates (110), and this space is filled by an encapsulant (140').

[0064] In some examples, the encapsulant (140) may include or be referred to as a protective material, dielectric, mold compound, or package body. The encapsulant (140) may include various encapsulating or molding materials (e.g., resin, polymer composite material, polymer having filler, epoxy resin, epoxy resin having filler, epoxy acrylate having filler, silicone resin, combinations thereof, equivalents thereof). The encapsulant (140) may be formed by various methods, e.g., a compression molding process, a liquid encapsulant molding process, a vacuum lamination process, a paste printing process, or a film-assisted molding process. The height of the encapsulant (140) may be in the range of about 100 μm to about 200 μm. The encapsulant (140) may protect the device stack (120) and internal interconnect (130) from the external environment.

[0065] FIG. 2f is a cross-sectional view illustrating a semiconductor device (100) in the next stage of manufacturing. In the example illustrated in FIG. 2f, a carrier (10) located on the lower surface of a substrate (110) may be removed. In some examples, when the carrier (10) is removed, the lower surface of the substrate (110b) is exposed from the encapsulant (140). In some examples, when the carrier (10) is removed, the lower surface of the electronic device (121) or the lower surface of the device stack (120) is exposed from the encapsulant (140). In some examples, when the carrier (10) is removed, the lower surface of the substrate (110b) may be coplanar with the lower surface of the device stack (120) or the lower surface of the encapsulant (140). In some examples, the carrier (10) may be separated from the substrate (110) as the separable layer (12) loses its adhesion due to heat, chemical, or irradiation. In some examples, the carrier (10) may be separated from the substrate (110) by a physical force. Thus, the second surface (bottom surface) (110b) of the substrate (110) and the bottom surface (120b) of the device stack (120) may be exposed.

[0066] FIGS. 2g and FIGS. 2h are a cross-sectional view and a plan view illustrating a semiconductor device (100) in the next stage of manufacturing. In the example illustrated in FIG. 2g, an external interconnect (150) may be connected to an external terminal (113) of a substrate (110). The external interconnect (150) may include a conductive bump, ball, or pillar (such as a post or wire) and may include, for example, a solder body, a copper body, or a solder cap. The external interconnect (150) may include tin (Sn), silver (Ag), lead (Pb), copper (Cu), Sn-Pb, Sn37-Pb, Sn95-Pb, Sn-Pb-Ag, Sn-Cu, Sn-Ag, Sn-Au, Sn-Bi, or Sn-Ag-Cu. The external interconnect (150) can be formed, for example, by a ball drop process, a screen printing process, or an electroplating process. The height of the external interconnect (150) may be in the range of about 20 μm to 50 μm. The external interconnect (150) can provide an electrical connection path between the semiconductor device (100) and an external component. Additionally, after the external interconnect (150) is connected, a singulation process can be performed to separate the arranged substrates (110) from each other. Accordingly, the semiconductor device (100) can be completed as shown in FIG. 2h.

[0067] FIG. 3 is a cross-sectional view illustrating an exemplary semiconductor device (200). In the example illustrated in FIG. 3, the semiconductor device (200) may include a module (101) from the semiconductor device (100) of FIG. 1, a module stack (290) having the module (201), and external interconnects (150, 250). The semiconductor device (200) may be formed to have a module stack including the module (101, 201).

[0068] The first module (101) may include a substrate (110), a device stack (120), an internal interconnect (130), and an encapsulant (140). The second module (201) may include a substrate (210), a device stack (220), an internal interconnect (230), an encapsulant (240), and a vertical interconnect (260). The substrate (210) may include a cavity (211), an internal terminal (212), and an external terminal (213). The device stack (220) may include a plurality of devices (221, 222, 223, 224). Additionally, each of the plurality of devices (221, 222, 223, 224) may include a device terminal (221a, 222a, 223a, 224a).

[0069] In some examples, the module (201) may include components, features, materials, or forming processes that correspond similarly to those of the module (101) described above. For example, the items (210, 211, 212, 213, 220, 221, 221a, 222, 222a, 223, 223a, 224, 224a, 230, 240, 250) of the module (201) described above may each correspond to or be similar to the items (110, 111, 112, 113, 120, 121, 121a, 122, 122a, 123, 123a, 124, 124a, 130, 140, 150) of the module (101) described above. The module (201) also includes a vertical interconnect (260) coupled to an internal terminal (212) of the substrate (210).

[0070] In some examples, the substrate (210), internal interconnect (230), encapsulant (240), and external interconnect (250) may include or be referred to as a semiconductor package, and the semiconductor package may protect the device stack (220) from external components or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (220). In some examples, the module (201) may include or be referred to as a semiconductor package. In some examples, the semiconductor device (200) in which the modules (101, 201) are stacked may include or be referred to as a Package On Package (POP) device.

[0071] FIGS. 4a through 4h are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 4a is a cross-sectional view illustrating a semiconductor device (200) in the initial manufacturing stage.

[0072] In the example illustrated in FIG. 4a, a substrate (210) may be attached to the upper part of a carrier (10), and a vertical interconnect (260) may be attached to or formed on the substrate (210). Although FIG. 4a is illustrated as having only one substrate (210) attached to the carrier (10), multiple substrates (210) may be arranged side by side on the carrier (10) for the simultaneous production of multiple modules (101). The carrier (10) may include a base layer (11) and a separable layer (12).

[0073] The substrate (210) may include a cavity (211), an internal terminal (212), and an external terminal (213). The internal terminal (212) and the external terminal (213) may be electrically connected to each other by internally penetrating the substrate (210) through a substrate conductor or an internal circuit. The cavity (211) may pass through the substrate (210) completely.

[0074] A vertical interconnect (260) may be coupled to or formed on an internal terminal (212) of a substrate (210). In some examples, the vertical interconnect (260) may include components, features, materials, or forming processes similar to those of the interconnect (150) described above. In some examples, the height of the vertical interconnect (260) may be in the range of about 50 µm to about 100 µm. The vertical interconnect (260) may provide an electrical connection path between the first module (101) and the second module (201). In some examples, the vertical interconnect (260) may provide terminals formed to allow stacking of modules.

[0075] FIG. 4b is a cross-sectional view illustrating a semiconductor device (200) in the next stage of manufacturing. In the example illustrated in FIG. 4b, a device stack (220) may be formed in a cavity (211), and an internal interconnect (230) may be formed. The device stack (220) may include electronic devices (221, 222, 223, 224). Although FIG. 4b illustrates the device stack (220) as including four electronic devices (221, 222, 223, 224), this does not limit the invention. In some examples, the device stack (220) may be composed of four or more electronic devices or a smaller number of electronic devices. In some examples, a first electronic device (221) may be attached to the upper surface of a carrier (10) within a cavity (211), and a second electronic device (222) may be attached to the upper surface of the first electronic device (221) using an adhesive member (20) to expose a portion of the upper surface of the first electronic device (221) including a device terminal (221a). A third electronic device (223) may be attached to the upper surface of the second electronic device (222) using an adhesive member (20) to expose a portion of the upper surface of the second electronic device (222) including a device terminal (222a), and a fourth electronic device (224) may be attached to the upper surface of the third electronic device (223) using an adhesive member (20) to expose a portion of the upper surface of the third electronic device (223) including a device terminal (223a). In some examples, the internal interconnect (230) may electrically connect the substrate (210) to one or more respective electronic devices (221, 222, 223, 224) or connect one or more device terminals (221a, 222a, 223a, 224a) to one another.In some examples, the device stack (220) may be stacked obliquely, such as in a stepped shape, with the corresponding device terminals (221a, 222a, 223a, 224a) of adjacent electronic devices (221, 222, 223, 224) exposed toward the same side of the semiconductor device (200). The height of the device stack (220) may be in the range of about 110 μm to 130 μm.

[0076] FIG. 4c is a cross-sectional view illustrating a semiconductor device (200) in the next stage of manufacturing. In the example illustrated in FIG. 4c, an encapsulant (240) may encapsulate the device stack (220), internal interconnect (230), and vertical interconnect (260). Additionally, the encapsulant (240) may also be formed between the device stack (220) and the substrate (210) within the cavity (211). In some examples, the encapsulant (240) may be overmolded with the device stack (220), internal interconnect (230), and external interconnect (260), and then the top surface may be ground. The height of the encapsulant (240) may be in the range of about 100 μm to 200 μm. The encapsulant (240) can protect the device stack (220), internal interconnect (230), and vertical interconnect (260) from the external environment.

[0077] FIG. 4d is a cross-sectional view illustrating a semiconductor device (200) in the next stage of manufacturing. In the example illustrated in FIG. 4d, a carrier (10) located at the bottom of the substrate (210) can be removed. Accordingly, the second surface (bottom surface) (210b) of the substrate (210) and the bottom surface of the device stack (220) can be exposed to the outside.

[0078] FIG. 4e is a cross-sectional view illustrating a semiconductor device (200) in the next stage of manufacturing. In the example illustrated in FIG. 4e, the vertical interconnect (260) may be exposed through each opening (241) or via of the encapsulant (240). In some examples, the opening (241) may be formed by removing a portion of the encapsulant (240) by a sawing process, a grinding process, a laser process, or an etching process. In some examples, the vertical interconnect (260) is partially extended through the encapsulant (240) such that the top of the vertical interconnect (260) is lower than or sits down relative to the top surface of the encapsulant (240). In some examples, the vertical interconnect (260) extends completely through the encapsulant (240) such that the top of the vertical interconnect (260) is substantially flat with the top surface of the encapsulant (240) or protrudes past the top surface of the encapsulant (240). In some examples, the via (241) contacts or coincides with the shape or sidewall of the vertical interconnect (260), regardless of whether it partially or completely penetrates the top surface of the encapsulant (240).

[0079] FIG. 4f is a cross-sectional view illustrating a semiconductor device (200) in the next stage of manufacturing. In the example illustrated in FIG. 4f, an external interconnect (250) may be connected to an external terminal (213) of a substrate (210).

[0080] FIG. 4g is a cross-sectional view illustrating an exemplary semiconductor device (200). In the example illustrated in FIG. 4g, the semiconductor device (200) may include modules (101, 201) stacked together. Although two modules are shown stacked, this does not limit the invention. In some examples, the semiconductor device (500) may have two or more or fewer modules stacked together. The modules (201, 101) may be stacked so that vertical interconnects (260, 150) are electrically connected to each other. In some examples, the vertical interconnects (260) formed in the module (201) and the interconnects (150) of the module (101) may be melted or reflowed together to electrically connect the modules to each other. Although the semiconductor device (200) is illustrated as including modules (101, 201), there may be examples in which other modules or other electronic devices of the present invention can replace one or more of these modules (101, 201).

[0081] FIG. 4h is a cross-sectional view illustrating an exemplary semiconductor device. In the example illustrated in FIG. 4h, the semiconductor device (200') may include a semiconductor device (200), a base substrate (310), an encapsulant (340), a base interconnect (350), and an underfill (345). The vertical interconnect (260) is illustrated as a pillar that is one or an option of the vertical interconnect (260) described in FIG. 4h, but may include any of the options of other interconnects (260). In this example, the top of the vertical interconnect (260) is substantially coplanar with the top surface of the encapsulant (240). In some examples, the semiconductor device (200') including the packaged semiconductor device (200) may include or be referred to as a Package-In-Package (PIP) device.

[0082] In some examples, the base substrate (310) may include components, features, materials, or forming processes that correspond similarly to those of the substrate (110) described above. In this example, the substrate (310) does not include a cavity such as the cavity (111) of the substrate (110). In some examples, the encapsulant (340) may include components, features, materials, or forming processes that correspond similarly to those of the encapsulant (140) described above.

[0083] In some examples, the underfill (345) may be provided between the module (201) and the substrate (310) or between the modules (101, 201). In some examples, the underfill (345) may cover the sidewalls of the module (101). In some examples, the top surface of the module (101) or the top of the sidewalls of the module (101) may remain uncovered by the underfill (345). In some examples, the underfill (345) may be omitted or may be considered as part of the encapsulant (340). In some examples, the underfill (345) and the encapsulant (340) may comprise separate material layers. In some examples, the underfill (345) may be similar to the encapsulant (340), or the underfill (345) and the encapsulant (340) may comprise the same material layer. In some examples, the underfill (345) may be referred to as a dielectric, insulating paste, or non-conductive paste. In some examples, the underfill (345) may be a dielectric without resin or inorganic filler. In some examples, the underfill (345) may be inserted using capillary action between the substrate (310) and the module (201) or between the module (201) and the module (101). In some examples, the underfill (345) may be applied before joining the substrate (310) and the module (201) or before joining the module (201) and the module (101). Other examples of the invention may include an underfill similar to the underfill (345) between or around each substrate or module.

[0084] FIG. 5 is a cross-sectional view illustrating an exemplary semiconductor device (300). In the example illustrated in FIG. 5, the semiconductor device (300) may include a base substrate (310), a module stack (390), an encapsulant (340), and a base interconnect (350). The module stack (390) may include a stack of two or more modules as described in the present invention, such as a stack of modules (101). The base substrate (310) may include an internal base terminal (312) and an external base terminal (313). In some examples, the semiconductor device (300) including a package of modules (101) may include or be referred to as a Package-In-Package (PIP) device.

[0085] FIGS. 6a to 6c are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 6a is a cross-sectional view illustrating a semiconductor device (300) in the initial manufacturing stage.

[0086] In the example illustrated in FIG. 6a, a base substrate (310) may be provided. In some examples, the base substrate (310) may include components, features, materials, or forming processes that correspond similarly to those of the substrate (110) described above. For example, the base substrate (310) may include a substrate conductive structure (315), an internal base terminal (312), an external base terminal (313), and a substrate conductor (315a), which may correspond similarly to the substrate conductive structure (115), internal terminal (112), external terminal (113), and substrate conductor (115a) of the substrate (110). In this example, the base substrate (310) does not include a cavity such as the cavity (111) of the substrate (110).

[0087] FIG. 6b is a cross-sectional view illustrating a semiconductor device (300) in the next stage of manufacturing. In the example illustrated in FIG. 6b, a module stack (390) may be added to the module (101) stacked on the base substrate (310), and a module interconnect (330) may electrically connect the base substrate (310) and the module stack (390). The module stack (390) may be attached to the upper surface of the base substrate (310) using adhesive so that the second side (110b) of the substrate (110) faces upward. Thus, the external terminal (113) of the substrate (110) may be exposed. In some examples, the module (101) may be stacked in a zigzag pattern on the upper surface of the base substrate (310). Although FIG. 6b illustrates a semiconductor device (300) comprising four modules (101), this does not limit the invention. In some examples, the semiconductor device (300) may comprise four or more or fewer modules (101). Although FIG. 6b illustrates a semiconductor device (300) comprising modules (101) and a module stack (390), there may be examples in which other modules or electronic devices of the invention can replace one or more of these modules (101).

[0088] A module interconnect (330) may be electrically connected between an external terminal (113) of a module (101) and an internal base terminal (312) of a base substrate (310) or between external terminals (113) of other modules (101). In some examples, the module interconnect (330) may be referred to as a wire, a conductive wire, or a bond wire. The module interconnect (330) may include an electrically conductive material, such as a metal material, gold, silver, aluminum, or copper. In some examples, the module interconnect (330) may be electrically connected between an external terminal (113) of a module (101) and an internal base terminal (312) of a base substrate (310) by wire bonding. The module interconnect (330) may provide an electrical connection between the module (101) and the base substrate (310) or between other modules (101).

[0089] FIG. 6c is a cross-sectional view illustrating a semiconductor device (300) in the next stage of manufacturing. In the example illustrated in FIG. 6c, the encapsulant (340) may cover the module stack (390), the module interconnect (330), and the base substrate (310). The base interconnect (350) may be connected to an external base terminal (313) of the base substrate (310). In some examples, the encapsulant (340) may include components, features, materials, or forming processes similar to those of the encapsulant (140) described above. The encapsulant (340) may protect the module stack (390) and the module interconnect (330) from the external environment.

[0090] In some examples, the base interconnect (350) may include corresponding components, features, materials, or forming processes similar to those of the interconnect (150) described above. The base interconnect (350) may provide an electrical connection path between the semiconductor device (300) and an external component such as a motherboard or PCB board.

[0091] The modules of the module stack (390) may have different orientations relative to one another. In some examples, the modules of the module stack (390) may be connected to different sides or margins of the base substrate (310) via module interconnects (330).

[0092] The base substrate (310) may include base margins (316, 317) that are not covered by the space occupied by the module stack (390). The base margins (316, 317) of the base substrate (310) may each be adjacent to the module stack sides (396, 397) of the module stack (390). In some examples, the modules of the module stack (390) may include the respective module terminals (113) of their respective substrates (110) on the upper surface of their respective modules. In this example, the modules (101) of the module stack (390) may include modules (3011, 3012, 3013, 3014) stacked on top of the base substrate (310). Modules (3011, 3013) are oriented in a first direction such that their respective module terminals (113) are adjacent to or closer to the module stack side (396) or base margin (316) than to the module stack side (397) or base margin (317). Conversely, modules (3012, 3014) are oriented in a second direction such that their respective module terminals (113) are adjacent to or closer to the module stack side (397) or base margin (317) than to the module stack side (396) or base margin (316). A module interconnect (330) extends from the module terminals (113) of modules (3011, 3013) to the base margin (316) of an adjacent substrate (310). Conversely, the module interconnect (330) extends from the module terminal (113) of the module (3012, 3014) to the base margin (317) of the adjacent substrate (310).

[0093] These different orientations of the modules in the module stack (390) allow for more uniform distribution of signals around the base substrate (310) compared to a scenario where all modules have the same orientation and are coupled to the same base margin or substrate (310). These different orientations of the modules in the module stack (390) allow for shorter and faster signal paths for the module interconnect (330) compared to a scenario where all modules have the same orientation and part of the module interconnect (330) needs to be routed to the base margin of a more distant substrate (310) instead.

[0094] FIG. 7 is a cross-sectional view illustrating an exemplary semiconductor device (300'). In the example illustrated in FIG. 7, the semiconductor device (300') may include a base substrate (310), a module stack (390'), a module interconnect (330), an encapsulant (340), and a base interconnect (350). In some examples, the semiconductor device (300') may include corresponding components, features, materials, or forming processes similar to those of the semiconductor device (300) described above. In some examples, the modules may be stacked in an offset structure so that the corresponding external terminals (113) of adjacent modules (101) are exposed. For example, the module stack (390) illustrated in FIG. 5 and 6 includes an offset structure of modules in an alternating or zigzag pattern, and the module stack (390') illustrated in FIG. 7 includes an offset structure of modules in a stepped form.

[0095] FIG. 8 is a cross-sectional view illustrating an exemplary semiconductor device (400). In the example illustrated in FIG. 8, the semiconductor device (400) may include a substrate (110), a device stack (420), an internal interconnect (130), an encapsulant (440a, 440b), and an interconnect (450a, 450b).

[0096] The device stack (420) may include a plurality of electronic devices (421, 422, 423, 424). Additionally, each of the plurality of electronic devices (421, 422, 423, 424) may include a device terminal (421a, 422a, 423a, 424a).

[0097] FIGS. 9a through 9g are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 9a is a cross-sectional view illustrating a semiconductor device (400) in the initial manufacturing stage.

[0098] In the example illustrated in FIG. 9a, a substrate (110) and electronic devices (421, 422) may be attached to the top of a carrier (10). The substrate (110) may include a cavity (111), an internal terminal (112), and an external terminal (113). In some examples, the electronic devices (421, 422) may include corresponding components, features, materials, or forming processes similar to those of the electronic devices (121, 122, 123, 124) described above. The electronic devices (421, 422) may each include device terminals (421a, 422a). The electronic devices (421, 422) may be stacked sequentially within the cavity (111). In some examples, the first electronic device (421) may be attached to the upper surface of the carrier (10) within the cavity (111), and the second electronic device (422) may be attached to the upper surface of the first electronic device (421) using an adhesive (20) such that a portion of the upper surface of the first electronic device (421), including the device terminal (421a), is exposed. Additionally, the electronic devices (421, 422) may be formed such that the sum of the heights of the first and second electronic devices (421, 422) is smaller than the height of the substrate (110).

[0099] FIG. 9b is a cross-sectional view illustrating a semiconductor device (400) in the next stage of manufacturing. In the example illustrated in FIG. 9b, the interconnect (450a) may be electrically connected to an internal terminal (112) on the first surface (110a) of the substrate (110). The internal interconnect (130) may electrically connect the substrate (110) and the device terminals (421a, 422a) of the electronic devices (421, 422), or electrically connect the device terminals (421a, 422a) to each other. In some examples, the interconnect (450a) may include components, features, materials, or forming processes similar to those of the interconnects (150, 260) described above.

[0100] FIG. 9c is a cross-sectional view illustrating a semiconductor device (400) in the next stage of manufacturing. In the example illustrated in FIG. 9c, the encapsulant (440a) may encapsulate electronic devices (421, 422) and internal interconnects (130). Additionally, the encapsulant (440a) may cover a first surface (top surface) (110a) of the substrate (110) and encapsulate a portion of the interconnects (450a). The encapsulant (440a) may also be formed between the substrate (110) and electronic devices (421, 422) within the cavity (111). In some examples, the encapsulant (440a) may include components, features, materials, or forming processes similar to those of the encapsulant (140) described above. The height of the encapsulant (440a) may be in the range of about 120 µm to 150 µm. The encapsulant (440a) can protect the device (421, 422) and the internal interconnect (130) from the external environment.

[0101] FIG. 9d is a cross-sectional view illustrating a semiconductor device (400) in the next stage of manufacturing. In the example illustrated in FIG. 9d, a carrier (10) located at the bottom of a substrate (110) may be removed. The substrate (110) may be flipped so that the second side (bottom) (110b) of the substrate faces upward. With the carrier (10) removed, an electronic device (423) may be stacked on an electronic device (421), and thus the electronic devices (422, 423) are stacked on the opposite side of the electronic device (421). The electronic device (423) protrudes from the encapsulant (440a) and has a side wall and a top surface (a surface away from the electronic device (421)) exposed from the encapsulant (440a).

[0102] In some examples, an electronic device (424) may be stacked on an electronic device (423) as part of a device stack (420). Each electronic device (423, 424) may include a device terminal (423a, 424a). In some examples, a third electronic device (423) may be attached to the top of a first electronic device (421) using an adhesive (20), and a fourth electronic device (424) may be attached to the top of a third electronic device (423) using an adhesive (20) so as to expose a portion of the top surface of the third electronic device (423) including the device terminal (423a). The device stack (420) can be stacked such that the device terminals (421a, 422a) of the first and second electronic devices (421, 422) face a first direction, and the device terminals (423a, 424a) of the third and fourth electronic devices (423, 424) face a second direction opposite to the first direction.

[0103] FIG. 9e is a cross-sectional view illustrating a semiconductor device (400) in the next stage of manufacturing. In the example illustrated in FIG. 9e, an interconnect (450b) may be electrically connected to an external terminal (113) of a substrate (110). An internal interconnect (130) may electrically connect the substrate (110) to the device terminals (423a, 424a) of electronic devices (423, 424), or electrically connect the device terminals (423a, 424a) to each other. In some examples, the interconnect (450b) may include components, features, materials, or forming processes similar to those of the interconnects (150, 260, 450a) described above. In some examples, the interconnect (450b) may provide an electrical connection path between the semiconductor device (400) and another semiconductor device or package stacked on the semiconductor device (400).

[0104] FIG. 9f is a cross-sectional view illustrating a semiconductor device (400) in the next stage of manufacturing. In the example illustrated in FIG. 9f, the encapsulant (400b) may encapsulate electronic devices (423, 424), internal interconnects (130), and interconnects (450b). In some examples, the encapsulant (440b) may include components, features, materials, or forming processes similar to those of the encapsulant (440a) described above. The encapsulant (440b) may come into contact with the encapsulant (440a) and may cover a second surface (110b) of the substrate (110). The height of the encapsulant (440b) may be in the range of about 120 μm to 150 μm. The encapsulant (440b) can protect the electronic devices (423, 424), internal interconnect (130), and external interconnect (450b) from the external environment.

[0105] FIG. 9g is a cross-sectional view illustrating a semiconductor device (400) in the next stage of manufacturing. In the example illustrated in FIG. 9g, the interconnect (450b) may be exposed by forming an opening or via (441) in the encapsulant (440b), respectively. In some examples, the opening (441) may be formed by removing a portion of the encapsulant (440b) by a sawing process, a grinding process, a laser process, or an etching process. In some examples, the interconnect (450b) is partially extended through the encapsulant (440b) such that the top of the interconnect (450b) is lower than or lower than the top surface of the encapsulant (440b) relative to the top surface of the encapsulant (440b). In some examples, the interconnect (450b) extends completely through the encapsulant (440b) such that the top of the interconnect (450b) is substantially flush with the top surface of the encapsulant (440b) or protrudes past the top surface of the encapsulant (440b). In some examples, the via (441) contacts or matches the shape or sidewall of the interconnect (450b), regardless of whether it partially or completely penetrates the top surface of the encapsulant (440b).

[0106] FIG. 10 is a cross-sectional view illustrating an exemplary semiconductor device (500). In the example illustrated in FIG. 10, the semiconductor device (500) may include a module stack (590) in which semiconductor devices (400) are stacked together. In some examples, the semiconductor device (400) may be manufactured by the method illustrated in FIG. 9a through 9g. Each semiconductor device (400) stacked together may be referred to as a module. Although three modules (400) are shown stacked together, this does not limit the invention. In some examples, the semiconductor device (500) may have three or more modules stacked together or fewer modules stacked together. The modules (400) may be stacked such that interconnects (450a, 450b) are electrically connected to each other. In some examples, the interconnect (450b) formed in the opening (441) of the module (400) and the interconnect (450a) formed on the first surface of the substrate of another module may be melted or reflowed together to electrically connect the modules (400) to each other. Although the semiconductor device (500) is illustrated as including the module (400), there may be examples in which other modules or electronic devices of the present disclosure may replace one or more of such modules (400).

[0107] FIG. 11 is a cross-sectional view illustrating an exemplary semiconductor device. In the example illustrated in FIG. 11, the semiconductor device (600) may include a substrate (610), a device stack (120), an internal interconnect (130), an encapsulant (140), and an external interconnect (150). In some examples, the semiconductor device (600) may include or be referred to as a module (601).

[0108] The substrate (610) may include a substrate ledge portion (6101) and a substrate vertical portion (6102). The substrate ledge portion (6101) may include a ledge (615). Additionally, the substrate (610) may include a cavity (611), an internal terminal (612), and an external terminal (613). The device stack (120) may include a plurality of devices (121, 122, 123, 124). Additionally, each of the plurality of devices (121, 122, 123, 124) may include a device terminal (121a, 122a, 123a, 124a).

[0109] The substrate (610), internal interconnect (130), encapsulant (140), and external interconnect (150) may include or be referred to as a semiconductor package, and the semiconductor package may protect the device stack (120) from external components or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (120).

[0110] FIGS. 12a to 12d are cross-sectional views illustrating an exemplary method for manufacturing an exemplary semiconductor device. FIG. 12a is a cross-sectional view illustrating a semiconductor device (600) in the initial manufacturing stage.

[0111] In the example illustrated in FIG. 12a, the substrate (610) may be formed or attached to the upper portion of the carrier (10). The substrate (610) may include a cavity (611). In some examples, the cavity (611) may include an aperture (610d1) having a first width (d1) and penetrating the first surface (610a) and the second surface (610b) of the substrate (610), and an aperture (610d2) formed thereafter having a second width (d2) and penetrating a portion of the substrate (610). The first width (d1) may be smaller than the second width (d2) (d1 <d2). 일부 예에서, 제1너비(d1)는 기판 렛지부(6101)에 의해 규정되거나 경계가 정해지고, 제2너비(d2)는 기판 수직부(6102)에 의해 규정되거나 경계가 정해질 수 있다. 일부 예에서, 캐비티(611)는 제2너비(d2)를 갖는 어퍼처(610d2)를 하고, 제1너비(d1)를 갖는 어퍼처(610d1)를 형성함으로써 형성될 수 있다. 일부 예에서, 캐비티(611)는 레이저, 블레이드 또는 펀치 툴을 사용하여 형성될 수 있다. 일부 예에서, 기판 렛지부(6101)와 기판 수직부(6102)는 일원화된 기판과 같이 별개의 기판이 서로 결합될 수 있다. 일부 예에서, 기판 렛지부(6101)(어퍼처(610d1)가 있거나 또는 없는) 또는 기판 수직부(6102)(어퍼처(610d2)가 있거나 또는 없는) 중 첫번째 하나가 먼저 형성될 수 있고, 두번째 하나는 첫번째 하나에 형성될 수 있다. 일부 예에서, 캐비티(611)는 디바이스 스택(120)이 안착될 수 있는 공간을 제공할 수 있다.

[0112] A substrate (610) may include a substrate ledge portion (6101) having a ledge (615) and a substrate vertical portion (6102). The substrate ledge portion (6101) may be defined as the lower part of the substrate (610) and may include a ledge (615) that protrudes laterally toward the cavity (611) more than the substrate vertical portion (6102). The substrate vertical portion (6102) may be defined as the upper part of the substrate (610) and may be located on the substrate ledge portion (6101).

[0113] In some examples, the substrate (610) may include an internal terminal (612) and an external terminal (613). The internal terminal (612) may be formed in the ledge (615). In some examples, the internal terminal (612) or the external terminal (613) may include a corresponding component, feature, material, or forming process similar to that of the internal terminal (112) or the external terminal (113) described above. In some examples, the internal terminal (612) may be provided as an electrical contact for routing an electrical signal of the substrate (610) to the device stack (120) or routing an electrical signal of the device stack (120) to the substrate (610).

[0114] External terminals (613) may be formed on a first surface (top surface) (610a) and a second surface (bottom surface) (610b) of a substrate (610). External terminals (613) located on the first surface (610a) and external terminals (613) located on the second surface (610b) may be electrically connected to each other by internally penetrating the substrate (610) through a substrate conductor or internal circuit. Additionally, external terminals (613) may be electrically connected to internal terminals (612) by internally penetrating the substrate (610) through a substrate conductor or internal circuit. In some examples, external terminals (613) may be provided as electrical contacts for routing electrical signals from the substrate (610) to an external component such as a motherboard or PCB board, or for routing electrical signals from an external component such as a motherboard or PCB board to the substrate (610).

[0115] FIG. 12b is a cross-sectional view illustrating a semiconductor device (600) in the next stage of manufacturing. In the example illustrated in FIG. 12b, a device stack (120) is formed within a cavity (611), and an internal interconnect (130) can electrically connect the substrate (610) and the device stack (120) or the respective electronic devices (121, 122, 123, 124). In some examples, the device stack (120) may be formed lower than the height of the substrate (610).

[0116] In some examples, the internal interconnect (130) can electrically connect an internal terminal (612) on a ledge (615) of a substrate (610) to any of the device terminals (121a, 122a, 123a, 124a) of an electronic device (121, 122, 123, 124). In some examples, merging of the ledge (615) can reduce the size, particularly the height, of the semiconductor device (600). In some examples, the internal interconnect (130) can electrically couple the device terminals (121a, 122a, 123a, 124a) to each other.

[0117] FIG. 12c is a cross-sectional view illustrating a semiconductor device (600) in the next stage of manufacturing. In the example illustrated in FIG. 12c, the encapsulant (140) may encapsulate the device stack (120) and the internal interconnect (130). In some examples, the encapsulant (140) may be formed within a cavity (611) and may expose a first surface (610a) of the substrate (610) to the outside. The encapsulant (140) may protect the device stack (120) and the internal interconnect (130) from the external environment.

[0118] FIG. 12d is a cross-sectional view illustrating a semiconductor device (600) in the next stage of manufacturing. In the example illustrated in FIG. 12d, the carrier (10) located on the lower part of the substrate (610) may be removed, and the external interconnect (150) may be connected to the external terminal (613). In some examples, the carrier (10) may be separated from the substrate (610), and the external terminal (613) located on the second side (610b) of the substrate (610) may be exposed. The external interconnect (150) may provide an electrical connection path between the semiconductor device (600) and an external component such as a motherboard or a PCB board.

[0119] FIG. 13 is a cross-sectional view illustrating an exemplary semiconductor device (700). In the example illustrated in FIG. 13, the semiconductor device (700) may include a module stack (790) in which modules (601) are stacked together, an interface structure (730), and an external interconnect (150). In some examples, the semiconductor device (700) may be formed by stacking the modules (601) of FIG. 12 and FIG. 13. Although four modules (601) are illustrated, this does not limit the invention. In other examples, the semiconductor device (700) may be formed by stacking four or more or fewer modules (601). Although the semiconductor device (700) is illustrated as including modules (601), there may be examples in which other modules or other electronic devices of the invention can replace one or more of these modules (601).

[0120] Modules (601) can be joined together and electrically connected to each other through an interface structure (730). In some examples, the interface structure (730) may include a conductive adhesive such as an anisotropic conductive film (AFC). The conductive adhesive (760) may include an insulating layer and conductive particles, such as metal particles or metal-coated polymer particles, dispersed within the insulating layer. In some examples, the conductive adhesive (730) may be interposed between modules (601) and subjected to heating and pressure, and external terminals (613) may be electrically connected to each other by the conductive particles. Parts of the conductive adhesive (730) that do not have external terminals (613) may be electrically insulated from each other by the insulating layer. In some examples, the conductive adhesive (730) or its conductive particles may include or be referred to as an interconnect. The external interconnect (150) may be connected to the external terminal (613) of the bottommost module of the semiconductor device (700). The interconnect structure (730) may include examples in which it includes an interconnect similar to the interconnect (150) in addition to or instead of a conductive adhesive to combine other modules of the semiconductor device (700).

[0121] FIG. 14 is a cross-sectional view illustrating an exemplary semiconductor device (700'). In the example illustrated in FIG. 14, the semiconductor device (700') may include a base substrate (310), a module stack (790) in which modules (601) are stacked, a conductive adhesive (730), an encapsulant (340), and an external interconnect (350). The base substrate (310) may include an internal base terminal (312) on a first surface (top surface) and an external base terminal (313) on a second surface (bottom surface) opposite to the first surface. In some examples, the semiconductor device (700') including a package of modules (601) may include or be referred to as a Package-In-Package (PIP) device.

[0122] In some examples, the semiconductor device (700') may be formed by stacking modules (601) on a base substrate (310). In some examples, the modules (601) may be stacked together using a conductive adhesive (730). In some examples, the modules (601) may be stacked together using an interconnect (150). An encapsulant (340) may encapsulate the module (601) on top of the base substrate (310), and an external interconnect (350) may be electrically connected to an external base terminal (313) of the base substrate (310). Although the semiconductor device (700') is illustrated as comprising modules (601), there may be examples in which other modules or other electronic devices of the present invention may replace one or more of these modules (601).

[0124] FIG. 15 is a cross-sectional view illustrating an exemplary semiconductor device (800). In the example illustrated in FIG. 15, the semiconductor device (800) may include a substrate (110), a device stack (120), an internal interconnect (130), an encapsulant (840), and an external interconnect (150). In some examples, the semiconductor device (800) may include a module (801) or be referred to as the module (801). In some examples, the module (801) may include corresponding components, features, materials, or forming processes similar to other modules described in the present disclosure.

[0125] The substrate (110) may include a shelf (116). The shelf (116) may be positioned toward the edge or end of the substrate (110) where the encapsulant (840) is not formed. Since the shelf (116) is not encapsulated by the encapsulant (840), it may protrude to one side of the semiconductor device (800). An internal terminal (112) located on the shelf (116) may be exposed on the first surface (110a) of the substrate (110).

[0126] In some examples, the encapsulant (840) may include corresponding components, features, materials, or forming processes similar to those of the encapsulant (140) described above. The encapsulant (840) may include a recessed sidewall (846). The encapsulant (840) may encapsulate the device stack (120) and the internal interconnect (130). The encapsulant (840) may also be formed between the device stack (120) and the substrate (110) in the cavity (111). In some examples, the encapsulant (840) may encapsulate only a portion of the first face (110a) of the substrate (110) so that the recessed sidewall (846) is located inside the footprint of the substrate (110). The encapsulant (840) may expose a portion of the first surface (110a) of the substrate (110). In some examples, the encapsulant (840) may completely encapsulate the first surface (110a) of the substrate (110), and then a portion of the encapsulant (840) may be removed to form a recessed sidewall (846). In some examples, a portion of the encapsulant (840) may be removed by an etching process. Since the encapsulant (840) encapsulates only a portion of the first surface (110a) of the substrate (110), the substrate (110) may include a shelf (116). The recessed sidewall (846) may be perpendicular to the first surface (110a) of the substrate (110). The encapsulant (840) can protect the substrate (110), device stack (120), and internal interconnect (130) from the external environment.

[0127] The substrate (110), internal interconnect (130), encapsulant (840), and external interconnect (150) may include or be referred to as a semiconductor package and may protect the device stack (120) from external components or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (120).

[0128] FIG. 16 is a cross-sectional view illustrating an exemplary semiconductor device (900). In the example illustrated in FIG. 16, the semiconductor device (900) may include a substrate (110), a device stack (120), an internal interconnect (130), an encapsulant (940), and an external interconnect (150). In some examples, the semiconductor device (900) may include a module (901) or be referred to as the module (901). In some examples, the module (901) may include corresponding components, features, materials, or forming processes similar to other modules described in the present disclosure.

[0129] The substrate (110) may include a shelf (116). The shelf (116) may be positioned toward an edge or end of the substrate (110) where the encapsulant (940) is not formed. Since the shelf (116) is not encapsulated by the encapsulant (940), it may protrude toward one side of the semiconductor device (900). An internal terminal (112) located on the shelf (116) may be exposed on a first surface (110a) of the substrate (110).

[0130] In some examples, the encapsulant (940) may include corresponding components, features, materials, or forming processes similar to those of the previously described encapsulant (140). The encapsulant (940) may include a recessed sidewall (946). The encapsulant (940) may encapsulate the device stack (120) and the internal interconnect (130). The encapsulant (940) may also be formed between the device stack (120) and the substrate (110) in the cavity (111). In some examples, the encapsulant (940) may encapsulate only a portion of the first face (110a) of the substrate (110) so that the recessed sidewall (946) is located inside the footprint of the substrate (110). The encapsulant (940) may expose a portion of the first surface (110a) of the substrate (110). In some examples, the encapsulant (940) may completely encapsulate the first surface (110a) of the substrate (110), and then a portion of the encapsulant (940) may be removed to form a recessed sidewall (946). In some examples, a portion of the encapsulant (940) may be removed using a laser. The recessed sidewall (946) may be formed obliquely with respect to the first surface (110a) of the substrate (110). In some examples, the angle (α) formed between the first surface (110a) of the substrate (110) and the recessed sidewall (946) may be an acute angle. The encapsulant (940) can protect the substrate (110), device stack (120), and internal interconnect (130) from the external environment.

[0131] The substrate (110), internal interconnect (130), encapsulant (940), and external interconnect (150) may include or be referred to as a semiconductor package and may protect the device stack (120) from external components or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (120).

[0132] FIG. 17 is a cross-sectional view illustrating an exemplary semiconductor device (1000). In the example illustrated in FIG. 17, the semiconductor device (1000) may include a base substrate (310), a module (801), a module interconnect (1030), an encapsulant (340), and a base interconnect (350). In some examples, the semiconductor device (1000) including the stacked module (801) may include or refer to a Package-In-Package (PIP) device. In some examples, the module semiconductor device (1000) may include corresponding components, features, materials, or forming processes similar to those of other semiconductor devices described in this disclosure.

[0133] In some examples, the semiconductor device (1000) may be formed by stacking a module (801) on a base substrate (310). The module (801) may be attached to the upper surface of the base substrate (310) using an adhesive member that causes the substrate (110) to face downward. The module (801) may be stacked on the upper surface of the base substrate (310), for example in a stepped or zigzag shape, to expose an internal terminal (112) located on a protrusion (116) of an adjacent module (801). In some examples, the module interconnect (1030) may include corresponding components, features, materials, or forming processes similar to those of the previously described module interconnect (330). The module interconnect (1030) may be electrically connected between the internal terminal (112) of the module (801) and the internal base terminal (312) of the base substrate (310), or between the internal terminals (112) of the module (801). In some examples, the module interconnect (1030) may be electrically connected to the internal terminal (112) located outside the recessed sidewall (846). Because the module interconnect (1030) is connected to the internal terminal (112) located on the shelf (116), the height of the semiconductor device (1000) may be reduced. The module interconnect (1030) may provide electrical coupling between the module (801) and the base substrate (310), or between the modules (801). In some examples, the module interconnect (1030) may be formed so as not to exceed the height of the top module (801), and the top module (801) may be exposed on the upper side of the encapsulant (340).

[0134] The encapsulant (340) can encapsulate the module (801) and the module interconnect (1030). In some examples, the encapsulant (340) may include corresponding components, features, materials, or forming processes similar to those of the previously described encapsulant (140). The encapsulant (340) can protect the module (801) and the module interconnect (1030) from the external environment.

[0135] FIG. 18 is a cross-sectional view illustrating an exemplary semiconductor device (1000'). In the example illustrated in FIG. 18, the semiconductor device (1000') may include a base substrate (310), a module (901), a module interconnect (1030), an encapsulant (340), and a base interconnect (350). In some examples, the semiconductor device (1000') may include corresponding components, features, materials, or forming processes similar to the previously described semiconductor device (1000).

[0136] In some examples, a semiconductor device (1000') comprising a stacked module (901) may include or be referred to as a Package-In-Package (PIP) device. In some examples, the module semiconductor device (1000') may include corresponding components, features, materials, or forming processes similar to those of other semiconductor devices described in this disclosure.

[0137] In some examples, the semiconductor device (1000) may be formed by stacking a module (901) on a base substrate (310). The module (901) may be attached to the upper surface of the base substrate (310) using an adhesive member that causes the substrate (110) to face downward. The module (901) may be stacked on the upper surface of the base substrate (310), for example in a stepped or zigzag shape, to expose an internal terminal (112) located on a protrusion (116) of an adjacent module (901).

[0138] In some examples, the module interconnect (1030) may include corresponding components, features, materials, or forming processes similar to those of the previously described module interconnect (330). The module interconnect (1030) may be electrically connected between the internal terminal (112) of the module (901) and the internal base terminal (312) of the base substrate (310), or between the internal terminals (112) of the module (901). In some examples, the module interconnect (1030) may be electrically connected to the internal terminal (112) located outside the recessed sidewall (946). Because the module interconnect (1030) is connected to the internal terminal (112) located on the shelf (116), the height of the semiconductor device (1000) may be reduced. The module interconnect (1030) may provide electrical coupling between the module (901) and the base substrate (310), or between the modules (901). In some examples, the module interconnect (1030) may be formed so as not to exceed the height of the top module (901), and the top module (901) may be exposed on the upper side of the encapsulant (340).

[0139] FIG. 19 is a cross-sectional view illustrating an exemplary semiconductor device (1100). In the example illustrated in FIG. 19, the semiconductor device (1100) may include a substrate (110), a device stack (120), an internal interconnect (130), an encapsulant (1140), an external interconnect (150), and a vertical interconnect (1160). In some examples, the semiconductor device (1100) may include a module (1101) or be referred to as the module (1101). In some examples, the module (1101) may include corresponding components, features, materials, or forming processes similar to other modules described in the present disclosure.

[0140] The vertical interconnect (1160) may be electrically connected to an internal terminal (112) of the substrate (110). The vertical interconnect (1160) may be exposed on the upper surface of the encapsulant (1140). In some examples, the upper surface of the vertical interconnect (1160) may be substantially coplanar with the upper surface of the encapsulant (1140). In some examples, the vertical interconnect (1160) may include or refer to a metal pillar, a conductive pillar, a copper pillar, a copper post, a vertical wire bond, a through-mold-via, a solder ball, or a copper core solder ball. In some examples, after the encapsulant (1140) is formed on the substrate (110), the vertical interconnect (1160) may be formed to pass through the encapsulant (1140). In some examples, after a vertical interconnect (1160) is formed on an internal terminal (112) of a substrate (110), an encapsulant (1140) may encapsulate the vertical interconnect (1160). The vertical interconnect (1160) may comprise an electrically conductive material or a metal material, such as, for example, gold, silver, aluminum, or copper. Additionally, the height of the vertical interconnect (1160) may be the same as the encapsulant (1140) formed on a first side (110a) of the substrate (110). The vertical interconnect (1160) may provide an electrical coupling between the substrate (110) and an external device.

[0141] In some examples, the encapsulant (1140) may include corresponding components, features, materials, or forming processes similar to those of the encapsulant (140) described above. The encapsulant (1140) may encapsulate the device stack (120), the internal interconnect (130), and the vertical interconnect (1160). The encapsulant (1140) may also be formed between the device stack (120) and the substrate (110) in the cavity (111). The encapsulant (1140) may expose the upper surface of the vertical interconnect (1160). The encapsulant (1140) may protect the substrate (110), the device stack (120), the internal interconnect (130), and the vertical external interconnect (1160) from the external environment. 110.

[0142] The substrate (110), internal interconnect (130), encapsulant (1140), external interconnect (150), and vertical interconnect (1160) may include or be referred to as a semiconductor package and may protect the device stack (120) from external elements or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (120).

[0143] FIG. 20 is a cross-sectional view illustrating an exemplary semiconductor device (1200). In the example illustrated in FIG. 20, the semiconductor device (1200) may include a base substrate (310), a module (1101), a module interconnect (1230), an encapsulant (340), and a base interconnect (350). In some examples, the semiconductor device (1200) including the stacked module (1101) may include or be referred to as a Package-In-Package (PIP) device. In some examples, the module semiconductor device (1200) may include corresponding components, features, materials, or forming processes similar to other semiconductor devices described in this disclosure.

[0144] In some examples, a module (1101) may be formed by stacking it on a base substrate (310) of a semiconductor device (1200). The module (1101) may be attached to the upper surface of the base substrate (310) using an adhesive member that causes the substrate (110) to face downward. In some examples, the module (1101) may be stacked on the upper surface of the base substrate (310) in a stepped or zigzag shape to expose the vertical interconnect (1160) of adjacent modules (1101).

[0145] In some examples, the module interconnect (1230) may include corresponding components, features, materials, or forming processes similar to the module interconnect (330) described above. The module interconnect (1230) may be electrically connected between the vertical interconnect (1160) of the module (1101) and the internal base terminal (312) of the base substrate (310), or between the vertical interconnect (1160) of the stacked module (1101). The module interconnect (1230) may provide electrical coupling between the module (1101) and the base substrate (310), or between the modules (1101).

[0146] The encapsulant (340) can encapsulate the module (1101) and the module interconnect (1230) and protect them from the external environment.

[0148] FIG. 21 is a cross-sectional view illustrating an exemplary semiconductor device (1300). In the example illustrated in FIG. 21, the semiconductor device (1300) may include a substrate (1310), a device stack (120), an internal interconnect (130), and an encapsulant (1340). In some examples, the semiconductor device (1300) may include a module (1301) or be referred to as the module (1301). In some examples, the module (1300) may include corresponding components, features, materials, or forming processes similar to other modules described in the present disclosure.

[0149] In some examples, the substrate (1310) may include corresponding components, features, materials, or forming processes similar to the substrate (110) described above. For example, the substrate (1310) may include a cavity (1311), an internal terminal (1312), and an external terminal (1313), which may be correspondingly similar to the cavity (111), internal terminal (112), and external terminal (113) of the substrate (110). In this example, the cavity (1311) may be formed on one side of the substrate (1310).

[0150] A substrate (1310) may be located on the side of a semiconductor device (1300). In some examples, the substrate (1310) may include or refer to a partial substrate or a side substrate, wherein at least one side of the device stack (120) is bounded by the substrate (1310) and at least one side of the device stack (120) is not bounded by the substrate (1310). For example, the substrate (1310) may be formed in an open rectangular or ('U') shape, which allows at least one side of the rectangular frame of the substrate (110) shown in FIG. 2h to be omitted. In some examples, the substrate (1310) may be formed asymmetrically. Since the substrate (1310) has a smaller width than the substrate (110) shown in FIG. 2h, the semiconductor device (1300) can be reduced in size.

[0151] A cavity (1311) may be formed to penetrate the substrate (1310). For example, the cavity (1311) may be formed by removing a portion of the substrate (1310). In some examples, the cavity (1311) may be formed by cutting a portion of the substrate (1310) using a laser or a blade. In some examples, the cavity (1311) may provide a space in which a device stack (120) can be mounted.

[0152] In some examples, the encapsulant (1340) may include corresponding elements, features, materials, or forming processes similar to the previously described encapsulant (140). The encapsulant (1340) may encapsulate the device stack (120) and the internal interconnect (130). The encapsulant (1340) may also be formed between the device stack (120) and the substrate (1310) in a cavity (1311).

[0153] The substrate (1310), internal interconnect (130), and encapsulant (1340) may include or be referred to as a semiconductor package and may protect the device stack (120) from external elements or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (120).

[0154] FIG. 22 is a cross-sectional view illustrating an exemplary semiconductor device (1400). In the example illustrated in FIG. 22, the semiconductor device (1400) may include a base substrate (310), a module (1301), a module interconnect (330), an encapsulant (340), and a base interconnect (350). In some examples, the semiconductor device (1400) may include corresponding elements, features, materials, or forming processes similar to the previously described semiconductor device (300). In some examples, the semiconductor device (1400) including a package of modules (1301) may include or be referred to as a Package-In-Package (PIP) device. In some examples, the module semiconductor device (1400) may include corresponding elements, features, materials, or forming processes similar to other previously described semiconductor devices.

[0155] In some examples, the semiconductor device (1400) may be formed by stacking a module (1301) on a base substrate (310). The module (1301) may be attached to the upper surface of the base substrate (310) using an adhesive member so that the substrate (1310) faces upward. In some examples, the module (1301) may be stacked on the upper surface of the base substrate (310) in a stepped or zigzag shape to expose the external terminal (1313) of an adjacent module (1301).

[0156] The module interconnect (330) can be electrically connected between the external terminal (1313) of the module (1301) and the internal base terminal (312) of the base substrate (310), or between the external terminal (1313) of the stacked module (1301). The module interconnect (330) can provide electrical coupling between the module (1301) and the base substrate (310), or between the stacked modules (1301).

[0157] FIG. 23 is a cross-sectional view illustrating an exemplary semiconductor device (1500). In the example illustrated in FIG. 23, the semiconductor device (1500) may include a substrate (110), a device stack (120), an internal interconnect (130), an encapsulant (1540), an external interconnect (150), and a stack cap (1570). In some examples, the semiconductor device (1500) may include a module (1501) or be referred to as the module (1501). In some examples, the module (1501) may include corresponding components, features, materials, or forming processes similar to other modules described in the present disclosure.

[0158] A stack cap (1570) may be mounted on a device stack (120). In some examples, the stack cap (1570) may be attached to the upper side of a fourth electronic device (124) located at the top of the device stack (120) using an adhesive member. The stack cap (1570) may be exposed on the upper side of the encapsulant (1540). In some examples, the upper surface of the stack cap (1570) may be coplanar with the upper surface of the encapsulant (1540). Additionally, the width of the stack cap (1570) may be smaller than the width of the device stack (120). In some examples, the stack cap (1570) may be positioned in the center of the fourth electronic device (124) to expose a device terminal (124a) located on the side of the fourth electronic device (124). In some examples, the stack cap (1570) may include an insert die, a dummy die, or a silicon die, or may be referred to as an insert die. The stack cap (1570) may include a semiconductor material, for example, silicon (Si). In some examples, the coefficient of thermal expansion of the stack cap (1570) is closer to the coefficient of thermal expansion of the electronic devices (121-124) in the device stack (120) than to the coefficient of thermal expansion of the encapsulant (1540). In some examples, the coefficient of thermal expansion of the stack cap (1570) may be substantially the same as the coefficient of thermal expansion of the electronic devices (121-124) in the device stack (120). In some examples, the stack cap (1570) may suppress warping caused by the difference in the coefficient of thermal expansion between the device stack (120) and the encapsulant (1540). In some examples, the stack cap (1570) may provide a heat dissipation path for the device stack (120).

[0159] In some examples, the encapsulant (1540) may include corresponding components, features, materials, or forming processes similar to the previously described encapsulant (140). The encapsulant (1540) may encapsulate the device stack (120), internal interconnect (130), and stack cap (1570). In some examples, the encapsulant (1540) may expose the top surface of the stack cap (1570). The encapsulant (1540) may protect the substrate (110), device stack (120), internal interconnect (130), and stack cap (1570) from the external environment.

[0160] In some examples, the module (1501) may be stacked on a base substrate (310) to form a stacked module semiconductor device, which may be similar to other stacked module semiconductor devices described in the present disclosure.

[0161] FIG. 24 is a cross-sectional view illustrating an exemplary semiconductor device (1600). In the example illustrated in FIG. 24, the semiconductor device (1600) may include a substrate (110), a device stack (120), an internal interconnect (130), an encapsulant (1640), an external interconnect (150), and a stack cap (1570). In some examples, the semiconductor device may include or be referred to as a module (1601). In some examples, the module (1601) may include corresponding components, features, materials, or forming processes similar to other modules described in the present disclosure.

[0162] The encapsulant (1640) can encapsulate the device stack (120), internal interconnect (130), and stack cap (1570). The encapsulant (1640) may include a side wall (1646). In some examples, the encapsulant (1640) may completely encapsulate the upper portion of the substrate (110), and the edge or corner of the encapsulant (1640) may be removed to form the side wall (1646). A portion of the encapsulant (1640) may be removed using a laser. The side wall (1646) may be inclined with respect to the first surface (110a) of the substrate (110). In some examples, the angle formed between the first surface (110a) of the substrate (110) and the side wall (1646) may be an acute angle.

[0163] The substrate (110), internal interconnect (130), encapsulant (1640), and stack cap (1570) may include or be referred to as a semiconductor package and may protect the device stack (120) from external elements or environmental exposure. Additionally, the semiconductor package may provide electrical coupling between the external components and the device stack (120).

[0164] In some examples, the module (1601) may be stacked on a base substrate (310) to form a stacked module semiconductor device, which may be similar to other stacked module semiconductor devices described in the present disclosure.

[0165] FIG. 25 is a cross-sectional view illustrating an exemplary semiconductor device (1700). In the example illustrated in FIG. 25, the semiconductor device (1700) may include a substrate (110), a device stack (120), an internal interconnect (130), an encapsulant (1740), an external interconnect (150), and a stack cap (1570). In some examples, the semiconductor device (1600) may include a module (1701) or be referred to as the module (1701). In some examples, the module (1701) may include corresponding components, features, materials, or forming processes similar to other modules described in the present disclosure.

[0166] The substrate (110) may include a shelf (1716). The shelf (1716) may be located at opposite ends of the substrate (110), and the encapsulant (1740) may leave the shelf (1716) exposed. Since the shelf (1716) is not encapsulated by the encapsulant (1740), the shelf (1716) may protrude to the opposite side of the semiconductor device (1700). An internal terminal (112) located on the shelf (1716) may be exposed on the first surface (110a) of the substrate (110). In some examples, an external interconnect (150) may be coupled to an external terminal (113) under each shelf (1716) of the substrate (110) outside the vertical footprint defined by the perimeter of the encapsulant (1740).

[0167] The encapsulant (1740) may include a recessed sidewall (1746). In some examples, the encapsulant (1740) may encapsulate only a portion of the first surface (110a) of the substrate (110) so that the recessed sidewall (1746) may be located inside the substrate (110). The encapsulant (1740) may expose a portion of the first surface (110a) of the substrate (110). In some examples, the encapsulant (1740) may completely encapsulate the first surface (110a) of the substrate (110) and then remove a portion of the encapsulant (1740) located at the edge of the substrate (110) to form the recessed sidewall (1746). The portion of the encapsulant (1740) may be removed using a laser. The recessed sidewall (1746) may be formed at an angle with respect to the first surface (110a) of the substrate (110). In some examples, the angle formed between the first surface (110a) of the substrate (110) and the recessed sidewall (1746) may be an acute angle.

[0168] FIG. 26 is a cross-sectional view illustrating an exemplary semiconductor device (1800). In the example illustrated in FIG. 26, the semiconductor device (1800) may include a base substrate (310), a module (1701), an encapsulant (1840), and a base interconnect (350). In some examples, the semiconductor device (1800) including a package of the module (1701) may include or be referred to as a Package-In-Package (PIP) device. In some examples, the module semiconductor device (1800) may include corresponding components, features, materials, or forming processes similar to other semiconductor devices described in this disclosure, such as the semiconductor device (300).

[0169] In some examples, the semiconductor device (1800) may be formed by stacking modules (1701) on a base substrate (310). Modules (1701) may be stacked such that external interconnects (150) are electrically connected to internal base terminals (312) of the base substrate (310). In some examples, modules (1701) may be stacked on the base substrate (310) in a straight vertical shape instead of a stepped or zigzag shape. In some examples, modules (1701) may be stacked so that external interconnects (150) are positioned on a shelf (1716) of an adjacent module (1701) and external interconnects (150) are electrically connected to internal terminals (112) of the adjacent module (1701). In some examples, the module (1701) may be stacked such that the device stack (120) contacts the stack cap (1570) of an adjacent module (1701). In some examples, the external interconnect (150) may be applied to the interconnect modules (1701) together or to the base substrate (210) and may be referred to as a module interconnect because it can perform a function similar to a module interconnect (330) without wire bonding (e.g., FIG. 3, 7).

[0170] While the present invention includes reference to specific embodiments, those skilled in the art will understand that various modifications may be made and equivalents substituted without departing from the scope of the invention. Additionally, modifications to the disclosed examples may be made without departing from the scope of the invention. Accordingly, the present invention is not limited to the disclosed examples but is intended to include all examples falling within the scope of the appended claims.

Claims

Claim 1 A semiconductor device comprising: a base substrate having a first surface and an internal base terminal on the first surface; a first module substrate coupled to the internal base terminal and comprising a module dielectric structure, a module conductive structure, a first substrate surface, a second substrate surface opposite to the first substrate surface, and a substrate sidewall between the first substrate surface and the second substrate surface; a device stack coupled to the module conductive structure and comprising a first electronic device and a second electronic device stacked on the first electronic device; an encapsulant surrounding the device stack and in contact with the substrate sidewall; and an insert comprising a non-electrically functional semiconductor material within the encapsulant, wherein the upper surface of the insert is coplanar with the upper surface of the encapsulant. Claim 2 In claim 1, the insert comprises silicon, forming a semiconductor device. Claim 3 A semiconductor device according to claim 1, wherein the base substrate comprises a base conductive structure; and further comprises a third electronic device on the first surface of the base substrate and coupled to the base conductive structure. Claim 4 In claim 3, the insert is a semiconductor device located on a first surface of the third electronic device. Claim 5 A semiconductor device according to claim 1, wherein the base substrate comprises a base conductive structure; and the first electronic device and the second electronic device are coupled to the base conductive structure through the module conductive structure. Claim 6 A semiconductor device according to claim 5, wherein the module conductive structure is coupled to the base conductive structure through an interconnect between the base substrate and the first module substrate. Claim 7 A semiconductor device according to claim 1, wherein the encapsulant is on the first surface of the base substrate and covers the side of the first module substrate. Claim 8 In claim 7, the semiconductor device, wherein the encapsulant extends between the base substrate and the first module substrate. Claim 9 A method for manufacturing a semiconductor device, comprising: providing a base substrate having a first surface and an internal base terminal on the first surface; and providing a first module substrate coupled to the internal base terminal, wherein the first module substrate is: Modular genetic structure; Module challenge structure; First substrate surface; A second substrate surface opposite to the first substrate surface; and A method for manufacturing a semiconductor device comprising: a substrate sidewall between the first substrate surface and the second substrate surface; a step of providing a device stack including a first electronic device and a second electronic device stacked on the first electronic device, the device stack including a substrate sidewall between the first substrate surface and the second substrate surface; a step of providing an insert including a non-electrical functional semiconductor material; and a step of providing an encapsulant surrounding the device stack and in contact with the substrate sidewall, wherein the insert is within the encapsulant and the upper surface of the insert is coplanar with the upper surface of the encapsulant. Claim 10 In claim 9, the method of manufacturing a semiconductor device wherein the insert comprises silicon. Claim 11 A method for manufacturing a semiconductor device according to claim 9, wherein the base substrate comprises a base conductive structure; and a third electronic device is provided on the first surface of the base substrate and is coupled to the base conductive structure. Claim 12 A method for manufacturing a semiconductor device according to claim 11, wherein the insert is on a first surface of the third electronic device. Claim 13 A method for manufacturing a semiconductor device according to claim 9, wherein the base substrate comprises a base conductive structure; and the first electronic device and the second electronic device are coupled to the base conductive structure through the module conductive structure. Claim 14 A method for manufacturing a semiconductor device according to claim 13, wherein the module conductive structure is coupled to the base conductive structure through an interconnect between the base substrate and the first module substrate. Claim 15 A method for manufacturing a semiconductor device according to claim 9, wherein the encapsulant is on the first surface of the base substrate and covers the side of the first module substrate. Claim 16 A method for manufacturing a semiconductor device according to claim 15, wherein the encapsulant extends between the base substrate and the first module substrate. Claim 17 A semiconductor device comprising: a base substrate including a first surface and a base conductive structure; a module substrate including a module conductive structure located on the first surface of the base substrate; a first electronic device coupled to the module conductive structure through a first interconnect; an encapsulant located on the first surface of the base substrate and covering a side of the module substrate; a second interconnect located within the encapsulant and coupled to the module conductive structure and the base conductive structure; and a semiconductor insert located on the first surface of the base substrate and in contact with the encapsulant. Claim 18 In claim 17, the semiconductor insert comprises silicon, forming a semiconductor device. Claim 19 In claim 17, the semiconductor device comprises a second electronic device coupled to the base conductive structure, wherein the semiconductor insert is on the second electronic device. Claim 20 In claim 19, the encapsulant is a semiconductor device located between the second electronic device and the first surface of the base substrate.

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