Low-power communication in single-line bus devices

Abstract

Low-power communication in a single-line bus device is initiated. The single-line bus device includes a master circuit and a plurality of slave circuits configured to perform forward and reverse communication with forward and reverse data symbols over a single-line bus. In the invention, for each reverse data symbol, the master circuit first applies a higher bus voltage to the single-line bus to provide each slave circuit with an opportunity to harvest power, and then makes the single-line bus into a three-state so that each slave circuit can communicate with the master circuit. Specifically, when the single-line bus is in a three-state, each slave circuit may represent different values ​​in the reverse data symbol by lowering the single-line bus to a lower bus voltage or maintaining the single-line bus at a higher bus voltage. The combination of opportunistic charging and low-power data encoding enables each slave circuit to be power self-sufficient with a smaller footprint.

Description

Technology Field

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 627,272 filed on January 31, 2024, the full contents of said application’s disclosure are incorporated herein by reference.

[0003] Technology field

[0004] The technology of the present disclosure generally relates to communication of a single-line communication bus of an electronic device. Background Technology

[0005] Mobile communication devices are becoming increasingly common in modern society. The proliferation of these devices is partly driven by the many features currently available on them. The improved processing capabilities of these devices signify that they have evolved from simple communication tools into sophisticated mobile multimedia centers that provide an enhanced user experience.

[0006] To provide a new dimension of user experience, state-of-the-art wireless communication devices (e.g., smartphones) are equipped with various electrical circuits that support various applications and enable diverse user experiences. Additionally, wireless communication devices utilize various communication buses to enable inter-circuit and intra-circuit communication. For example, a 2-wire Radio Frequency Front End (RFFE) bus allows transceiver circuit(s) to communicate with power amplifier circuits, power management circuits, and / or antenna circuits. A multi-wire high-bandwidth memory bus can enable time-sensitive direct access to memory circuits, and a multi-wire General Purpose Input / Output (GPIO) bus can connect communication to external peripheral devices.

[0007] However, not all communication requires multi-wire buses such as RFFE buses, memory buses, and GPIO buses. In some cases, a single-wire serial bus may be sufficient or even desirable for performing low-speed and / or low-bandwidth communication between certain types of circuits (e.g., antenna tuners, sensors, and switches).

[0008] The embodiment disclosed in the detailed description relates to low-power communication in a single-line bus device. The single-line bus device comprises a master circuit and a plurality of slave circuits, which are configured to perform forward (i.e., master-slave) and reverse (i.e., slave-master) communication over the single-line bus with forward (i.e., master-slave) and reverse (i.e., slave-master) data symbols. In the above, for each reverse data symbol, the master circuit first applies a higher bus voltage to the single-line bus to provide each slave circuit with an opportunity to harvest power, and then makes the single-line bus into a three-state so that each slave circuit can communicate with the master circuit. Specifically, when the single-line bus is in a three-state, each slave circuit may indicate a different value in the reverse data symbol by pulling the single-line bus down to a lower bus voltage or maintaining the single-line bus at a higher bus voltage. The combination of opportunistic charging and low-power data encoding enables each slave circuit to be power self-sufficient with a reduced footprint.

[0009] In one embodiment, a single-line bus device is provided. The single-line bus device includes a master circuit. The master circuit is coupled to a single-line bus consisting of a single line. The master circuit is configured to apply a higher bus voltage to the single-line bus during a first interval for each of a plurality of reverse data symbols, and then make the single-line bus three-state for a second interval. Additionally, the single-line bus device includes multiple slave circuits. Each of the multiple slave circuits is connected to the single-line bus. Each of the multiple slave circuits is configured to lower the single-line bus to a lower bus voltage during a second interval for each of the multiple reverse data symbols, thereby communicating a first value to the master circuit. Each of the multiple slave circuits is also configured to maintain the single-line bus at a higher bus voltage during a second interval for each of the multiple reverse data symbols, thereby communicating a second value different from the first value to the master circuit.

[0010] In another embodiment, a wireless device is provided. The wireless device includes a master circuit. The master circuit is coupled to a single-line bus consisting of a single line. The master circuit is configured to apply a higher bus voltage to the single-line bus during a first interval for each of a plurality of reverse data symbols, and then make the single-line bus three-state for a second interval. The wireless device also includes a plurality of slave circuits. Each of the multiple slave circuits is connected to the single-line bus. Each of the multiple slave circuits is configured to lower the single-line bus to a lower bus voltage during a second interval for each of the multiple reverse data symbols, thereby communicating a first value to the master circuit. Each of the multiple slave circuits is also configured to maintain the single-line bus at a higher bus voltage during a second interval for each of the multiple reverse data symbols, thereby communicating a second value different from the first value to the master circuit.

[0011] In another embodiment, a method for configuring a single-line bus device is provided. The method comprises the step of coupling a master circuit to a single-line bus composed of a single line. The method also comprises the step of configuring the master circuit to apply a higher bus voltage to the single-line bus during a first interval for each of multiple reverse data symbols, and then to make the single-line bus three-state for a second interval. The method also comprises the step of coupling each of multiple slave circuits to the single-line bus. The method also comprises the step of configuring each of the multiple slave circuits to lower the single-line bus to a lower bus voltage during a second interval for each of the multiple reverse data symbols, thereby communicating a first value to the master circuit. The method also comprises the step of configuring each of the multiple slave circuits to maintain the single-line bus at a higher bus voltage during a second interval for each of the multiple reverse data symbols, thereby communicating a second value different from the first value to the master circuit.

[0012] A person skilled in the art will be able to understand the scope of the present disclosure and implement additional embodiments thereof after reading the following detailed description related to the attached drawings. Brief explanation of the drawing

[0013] The accompanying drawings included in and constituting part of this specification serve to illustrate various aspects of the present disclosure and, together with the detailed description, explain the principles of the present disclosure. FIG. 1a is a schematic diagram of an exemplary conventional single-wire bus device configured so that a master circuit communicates with slave circuit(s) through a single-wire bus. FIG. 1b is a schematic diagram providing an exemplary example of one or more bus telegrams communicating from a master circuit to slave circuit(s) through the single-line bus of FIG. 1a. FIG. 1c is a schematic diagram providing an exemplary example of one or more bus telegrams communicating from slave circuit(s) to master circuit through the single-line bus of FIG. 1a. FIG. 1d is a schematic diagram providing an exemplary example of a bus symbol modulated based on voltage pulse-width modulation (PWM) to represent a voltage PWM value "1". FIG. 1e is a schematic diagram providing an exemplary example of a bus symbol modulated based on voltage PWM to represent a voltage PWM value "0". FIG. 1f is a schematic diagram providing an exemplary detail of some technical challenges associated with the master circuit and slave circuit(s) in a conventional single-line bus device of FIG. 1. Figure 1g is a graph illustrating the cumulative voltage drop problem in the slave circuit(s) of Figure 1f. FIG. 2 is a schematic diagram of an exemplary single-line bus device, wherein the master circuit and slave circuit(s) are configured to perform reverse communication using the low-power waveform of the present disclosure. FIGS. 3a and FIGS. 3b are schematic diagrams providing detailed examples of low-power waveforms for performing reverse communication in a single-line bus device of FIG. 2. FIG. 4 is a schematic diagram providing an exemplary example of the slave circuit(s) of FIG. 2. Figure 5 is a schematic diagram illustrating the daisy chain topology of a single-line bus device. FIG. 6 is a schematic diagram of an exemplary user element (e.g., a wireless device), and the single-line bus device of FIG. 2 and FIG. 5 may be provided. FIG. 7 is a flowchart of an exemplary process for configuring the single-line bus device of FIG. 2 and FIG. 5. Specific details for implementing the invention

[0014] The embodiments presented below provide information necessary to enable a person skilled in the art to carry out the embodiments, while illustrating the best manner of carrying out the embodiments. By reading the description below in conjunction with the accompanying drawings, a person skilled in the art will understand the concepts of the present disclosure and recognize applications of these concepts that are not specifically addressed herein. These concepts and applications should be understood to fall within the scope of the present disclosure and the appended claims.

[0015] Although terms such as first, second, etc. may be used herein to describe various elements, it will be understood that these elements should not be limited by these terms. These terms are used solely to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure. The term "and / or" as used herein includes any and all combinations of one or more of the associated enumerated items.

[0016] When an element such as a layer, region, or substrate is referred to as being "on" or extending "on" another element, it will be understood that this may be directly on or directly extending onto another element, or that intervening elements may also exist. In contrast, when an element is referred to as being "directly" on or extending "on" another element, no intervening elements exist. Likewise, when an element such as a layer, region, or substrate is referred to as being "on" or extending "up" another element, it will be understood that this may be directly on or directly extending onto another element, or that intervening elements may also exist. In contrast, when an element is referred to as being "directly" on or extending "up" another element, no intervening elements exist. Furthermore, when an element is referred to as being "connected" or "joined" to another element, it should be understood that it may be directly connected or joined to the other element, or that intervening elements exist. In contrast, when an element is referred to as being "directly connected" or "directly joined" to another element, no intervening elements exist.

[0017] Relative terms such as "below," "above," "upper," "lower," "horizontal," or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region as shown in the drawings. These terms and those discussed above should be understood as intended to include different orientations of the element in addition to the orientations shown in the drawings.

[0018] The terms used herein are merely for describing specific embodiments and are not intended to limit the disclosure. As used herein, the singular forms “one,” “one,” and “the above” are intended to also include the plural forms unless otherwise indicated in the context. It should also be understood that, as used herein, the terms “comprises,” “comprising,” “includes,” and / or “including” define the presence of the mentioned features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, parts, elements, components, and / or groups thereof.

[0019] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art to which this disclosure pertains. Terms used herein should be interpreted as having meanings consistent with the context of this disclosure and the relevant technical field, and it will be further understood that they should not be interpreted in an ideal or overly formal sense unless explicitly defined herein as such.

[0020] The embodiment disclosed in the detailed description relates to low-power communication in a single-line bus device. The single-line bus device comprises a master circuit and a plurality of slave circuits, which are configured to perform forward (i.e., master-slave) and reverse (i.e., slave-master) communication over the single-line bus with forward (i.e., master-slave) and reverse (i.e., slave-master) data symbols. In the above, for each reverse data symbol, the master circuit first applies a higher bus voltage to the single-line bus to provide each slave circuit with an opportunity to harvest power, and then makes the single-line bus into a three-state so that each slave circuit can communicate with the master circuit. Specifically, when the single-line bus is in a three-state, each slave circuit may indicate a different value in the reverse data symbol by pulling the single-line bus down to a lower bus voltage or maintaining the single-line bus at a higher bus voltage. The combination of opportunistic charging and low-power data encoding enables each slave circuit to be power self-sufficient with a reduced footprint.

[0021] Before discussing the single-line bus device of the present disclosure starting from FIG. 2, a brief overview of a conventional single-line bus device is first provided in relation to FIG. 1a to 1g to help understand the basic operation of the conventional single-line bus and the technical problems to be solved herein.

[0022] In this regard, FIG. 1a is a schematic diagram of an exemplary conventional single-line bus device (10) in which a master circuit (12) is configured to communicate with a plurality of slave circuits (14(1) to 14(M)) through a single-line bus (16) connected to a master port (18). As such, the master circuit (12) and the slave circuits (14(1) to 14(M)) can only communicate with each other alternately (e.g., in a time-division method).

[0023] The master circuit (12) is configured such that bus telegram communication is always initiated via the single-line bus (16) by communicating bus telegram(s) to one or more of the slave circuits (14(1) to 14(M)). As such, the conventional single-line bus device (10) is also known as a "master-slave bus architecture." The slave circuits (14(1) to 14(M)) can provide data payload(s) to the master circuit (12) via the single-line bus (16) in response to receiving bus telegram(s) from the master circuit (12). Hereinafter, the bus telegram(s) communicated from the master circuit (12) to the slave circuits (14(1) to 14(M)) are referred to as "forward bus telegram(s)," and the data payload(s) communicated from the slave circuits (14(1) to 14(M)) to the master circuit (12) are referred to as "reverse bus telegram(s)."

[0024] FIG. 1b is a schematic diagram providing exemplary examples of one or more bus telegrams (20, 22) that are communicated from a master circuit (12) to any of the slave circuits (14(1)–14(M)) via the single-line bus (16) of FIG. 1a. Each bus telegram (20, 22) begins with an SOS sequence (24) followed by a bus command sequence (26). The bus command sequence (26) includes a write command frame (28) and a write data frame (30). The write command frame (28) includes a command field (32) (indicated as "CMD") encoded with the binary value "100" representing a register-write operation. The write data frame (30) includes a write data period (34). The write data period (34) includes one or more write data symbols T modulated to transmit data to the slave circuits (14(1)–14(M)) during a register-write operation. S It may include. In this regard, the bus telegram (20, 22) may be an example of a forward bus telegram(s). In the context of the present disclosure, write data symbol T Sis also referred to as a forward data symbol.

[0025] The SOS sequence (24) always precedes the bus command sequence (26) and is always communicated from the master circuit (12) to the slave circuit (14(1)–14(M)). The bus telegram (22) following the bus telegram (20) can be separated from the bus telegram (20) by a fast charging period (36) starting at time T1 and ending at time T2 (T2 > T1), and an idle period (38) starting at time T2 and ending at time T3 (T3 > T2). Collectively, the duration between times T1 and T3 is also referred to as the suspension period (T3-T1).

[0026] The fast charging period (36) is configured so that each of the slave circuits (14(1)–14(M)) can draw a higher charging current through the single-line bus (16) and harvest power from the higher charging current. In this regard, the single-line bus (16) is said to be in a fast charging state during the fast charging period (36). The idle period (38) may be an inactive period during which the master circuit (12) and the slave circuits (14(1)–14(M)) can be disabled to help conserve power. Accordingly, the single-line bus (16) is said to be in an idle state during the idle period (38).

[0027] Each bus command sequence (26) of the bus telegrams (20, 22) includes a slave address field (40), followed by a bus park period (42), and then four ACK symbols (T S An acknowledgment (ACK) symbol field (44) containing ) follows. The slave address field (40) can be used to address slave circuits (14(1)–14(M)). The bus park period (42) can be used to switch between forward and reverse communication modes. ACK symbol (T S) can be used for up to four of the slave circuits (14(1) to 14(M)) to acknowledge the reception of each data carried during the write data period (34). ACK symbol (T S ) are each symbol duration (T S Given that it is associated with and communicates immediately before the fast charging period (36), each slave circuit (14(1)–14(M)) receives four ACK symbols (T) from the end of the bus park period (42). S By counting four ACKs communicated in ), the time T1 to start the fast charging period (36) can be determined. In the context of the present disclosure, the ACK symbol T in the ACK symbol field (44) S is a type of reverse data symbol.

[0028] Each of the slave circuits (14(1) to 14(M)) is uniquely identified by its own unique slave identification (USID). As such, when the slave address field (40) contains the USID of any one of the slave circuits (14(1) to 14(M)), the bus command sequence (26) in the bus telegram (20, 22) may be a unicast command sequence directed to any one of the slave circuits (14(1) to 14(M)). When the slave address field (40) contains a group slave identification (GSID) corresponding to a subset of the slave circuits (14(1) to 14(M)), the bus command sequence (26) in the bus telegram (20, 22) may be a multicast command sequence directed to a subset of the slave circuits (14(1) to 14(M)). Additionally, when the slave address field (40) includes a broadcast slave identification (BSID), the bus command sequence (26) in the bus telegram (20, 22) may be a broadcast command sequence directed to all slave circuits (14(1) to 14(M)).

[0029] FIG. 1c is a schematic diagram providing an exemplary illustration of one or more bus telegrams (46, 48) communicating from slave circuits (14(1)–14(M)) to a master circuit (12) via the single-line bus (16) of FIG. 1a. Common elements between FIG. 1b and FIG. 1c are illustrated therein with common element numbers and will not be described again herein.

[0030] Each of the bus telegrams (46, 48) contains a bus command sequence (26). The bus command sequence (26) contains a read command frame (50) and a read data frame (52) separated by a bus park period (42). The read command frame (50) contains a command field (32) (indicated as "CMD") encoded with the binary value "010" to indicate a register-read operation. The read data frame (52) contains one or more read data symbols T modulated to carry a data payload to the master circuit (12) during a register-read operation. S It includes a read data period (54) that includes. The master circuit (12) first communicates a read command frame (50) to a slave circuit (14(1)–14(M)) identified by the slave address field (40) to initiate a register-read operation. Then, the master circuit (12) becomes a 3-state during the bus park period (42) sandwiched between the read command frame (50) and the read data frame, thereby transferring control of the single-line bus (16) to the slave circuit (14(1)–14(M)). Subsequently, the slave circuit (14(1)–14(M)) receives one or more read data symbols (T) during the read data period (54). S A data payload can be started to be transmitted via ). In this regard, the bus telegram (46, 48) may be an example of both forward and reverse bus telegram(s). In the context of the present disclosure, read data symbol T S is another type of reverse data symbol.

[0031] Referring again to FIG. 1a, the master circuit (12) is configured to suspend bus telegram communication over the single-line bus (16) during the suspension period (T3-T1). Accordingly, the master circuit (12) and the slave circuits (14(1) to 14(M)) are configured not to communicate bus telegram(s) and data payload(s) from time T1 to T3. In this regard, the single-line bus (16) can be said to be in a suspension mode between time T1 and T3. During the suspension period (T3-T1), the master circuit (12) suspends the single-line bus (16) to a high voltage level V HIGH (V HIGH Bus voltage V (> 0 V) BUS In this way, the slave circuits (14(1) to 14(M)) each draw charging current through the single-line bus (16) and can harvest power from the master circuit (12).

[0032] In addition to the suspension period (T3-T1), the write data symbol T of the write data period (34) S and the read data symbol T of the read data period (54) S As shown in FIGS. 1D and 1E, the high voltage level V HIGH and low voltage level V LOW Between (V LOW < V HIGH ) Bus voltage V BUS It can be modulated by toggling. FIG. 1d shows a bus symbol T modulated based on voltage PWM to represent a voltage PWM value "1". S This is a schematic diagram providing an exemplary example of.

[0033] Bus symbol T S is, write data symbol T S , read data symbol T S , and ACK symbol T SIt may be either one, and is modulated based on a predefined low voltage section (56) and a predefined high voltage section (58) configured according to a predefined configuration ratio. To indicate a voltage PWM value "1", the predefined low voltage section (56) is shorter than the predefined high voltage section (58). For example, bus symbol T S It may include 16 digital control oscillators (DCOs), and the predefined configuration ratio between the predefined low voltage interval (56) and the predefined high voltage interval (58) is 25% to 75% (or 1 to 3). In a non-limiting example, the DCOs are derived from a clock running in the master circuit (12). Thus, the predefined low voltage interval (56) lasts for 4 DCOs, and the predefined high voltage interval (58) lasts for 12 DCOs.

[0034] In this regard, the bus symbol T is used to indicate a voltage PWM value of "1". S To modulate, the bus voltage V BUS First, for a predefined low voltage interval (56), the low voltage level V LOW After being authorized as (V BUS = V LOW ), for a predefined high voltage interval (58), high voltage level V HIGH It is authorized as (V HIGH > V LOW ).

[0035] FIG. 1e shows a voltage PWM symbol T modulated to represent a voltage PWM value "0". S This is a schematic diagram providing an exemplary example of. The common elements of FIG. 1d and FIG. 1e are illustrated therein with their common element numbers and are not described again here.

[0036] To indicate a voltage PWM value of "0", the predefined low voltage interval (56) is longer than the predefined high voltage interval (58). Based on the same example of FIG. 1d, the predefined low voltage interval (56) lasts for 12 DCOs, and the predefined high voltage interval (58) lasts for 4 DCOs. Thus, the bus symbol T to indicate a voltage PWM value of "0" S To modulate, the bus voltage V BUS First, for a predefined low voltage interval (56), the low voltage level V LOW After being authorized as (V BUS = V LOW ), for a predefined high voltage interval (58), high voltage level V HIGH It is authorized as (V BUS = V HIGH ).

[0037] FIG. 1f is a schematic diagram illustrating in exemplary detail some technical problems associated with the master circuit (12) and slave circuits (14(1)–14(M)) in the conventional single-line bus device (10) of FIG. 1a. Common elements of FIG. 1a and FIG. 1f are illustrated therein with common element numbers and are not described again here.

[0038] Each slave circuit (14(1)–14(M)) may be configured to include an input node (60), a slave bus driver (62), a switch (64), and a power harvesting circuit (66). Specifically, the input node (60) is connected to a single-line bus (16), the switch (64) is connected to the input node (60), and the power harvesting circuit (66) is connected to the switch (64). The power harvesting circuit (66) includes a resistor R (resistance value R (e.g., 200 Ω)) and a holding capacitor C HOLD (Capacitance C HOLDIt can be implemented as a resistor-capacitor (RC) circuit including (e.g., 470 nF). Each of the slave circuits (14(1)–14(M)) also includes a slave bypass capacitor C coupled between the input node (60) and ground (GND). SBYP (Capacitance C SBYP Includes (e.g., 20 pF).

[0039] The master circuit (12) includes an output node (68), a master bus driver (70), and a master bypass capacitor C MBYP (Capacitance C MBYP It may include (e.g., 20 pF). The output node (68) is coupled to the single-line bus (16), and the master bypass capacitor C MBYP It is coupled between the output node (68) and GND. In the present invention, the master bus driver (70) is configured to initiate forward and reverse communication with each of the slave circuits (14(1)–14(M)) using the bus telegrams (20, 22) of FIG. 1b and the bus telegrams (46, 48) of FIG. 1c. The master bus driver (70) is also configured to enable and disable fast charging during the fast charging period (36).

[0040] The slave bus driver (62) is configured to close the switch (64) during the suspension period (T3-T1) to connect the power harvesting circuit (66) to the input node (60). In this way, each of the slave circuits (14(1)–14(M)) has a bus current I BUS Draw out, and retain capacitor C HOLD local voltage V CAP It can be charged. In addition to the suspension period (T3-T1), the slave bus driver (62) opens the switch (64) to disconnect the power harvesting circuit (66) from the input node (60). As a result, the retaining capacitor C HOLD It will be discharged to supply power to the slave bus driver (62).

[0041] The performance index of the power harvesting circuit (66) is the RC time constant τ (τ = R × C HOLD It can be defined by ), which maintains capacitor C up to a specific percentage (e.g., 63.2%) of the maximum capacitance. HOLD It indicates the time required to charge. As can be understood, the shorter the RC time constant τ, the faster the power harvesting circuit (66) can harvest energy. In this regard, it may be desirable to shorten the RC time constant τ by reducing the resistance R and / or capacitance CHOLD. Unfortunately, the capacitance C HOLD Reducing it can cause several technical challenges.

[0042] In a conventional single-line bus device (10), the master circuit reads the data symbol T S and ACK symbol T S Bus voltage V on the single-line bus (16) at the start of each BUS It is configured to apply. Each of the slave circuits (14(1) to 14(M)) is configured to apply the bus voltage V BUS Read data symbol T by maintaining S and ACK symbol T S It is required that any one of them represent a logic 0 "0" (e.g., binary "0"). Each of the slave circuits (14(1)–14(M)) reads the data symbol T S and ACK symbol T S To represent a logic 1 "1" (e.g., binary "1") in either one, a single-line bus (16) is connected to a higher bus voltage V BUSH (V BUSH > V BUS It is additionally required to pull it up to ).

[0043] Master bypass capacitor C MBYP and slave bypass capacitor C SBYP Each can have a capacitance of 20 pF, and the single-line bus (16) also has an equivalent capacitance C BUSGiven that it may have a total of 350 pF capacitance, the slave bus driver (62) must overcome a total of 350 pF capacitance to represent a logic "1" to the master circuit (12). Retaining capacitor C in each of the slave circuits (14(1)–14(M)). HOLD Each of the slave circuits (14(1)–14(M)) must have a capacitance (e.g., 470 pF) large enough to store enough power to overcome a total capacitance of 350 pF, which will inevitably increase the footprint of the slave circuits (14(1)–14(M)). In this regard, the first technical problem to be solved herein is the holding capacitor C HOLD It helps to reduce the footprint of the slave circuit (14(1)~14(M)) by reducing the capacitance.

[0044] Also, retaining capacitor C HOLD The 470 pF capacitance will significantly increase the RC time constant of the power harvesting circuit (66), thereby hindering the power harvesting circuit (66)'s ability to rapidly harvest power as needed. Consequently, the power harvesting circuit (66) may experience a cumulative voltage drop in a continuous bus telegram.

[0045] FIG. 1g is a graph illustrating the cumulative voltage drop problem experienced by each of the slave circuits (14(1)–14(M)) of FIG. 1f. Specifically, FIG. 1g shows the local voltage V in two consecutive (also called back-to-back) bus write telegrams, such as the bus telegrams (20, 22) of FIG. 1b. CAP The cumulative drop of is illustrated. Common elements between FIG. 1b, FIG. 1f, and FIG. 1g are indicated or referenced by common element numbers in those figures and are not described again in this specification.

[0046] During each writing telegram, maintain capacitor C HOLD Because it supplies power to the slave bus driver (62), the local voltage V CAPA drop occurs in. During the high-speed charging period (36) in each writing telegram, the capacitor C is maintained. HOLD is bus current I BUS It is charged by. During the first 500 seconds of the bus telegram (before the fast charging period (36)), capacitor C is retained. HOLD is a power harvesting circuit (66), master bypass capacitor C MBYP , slave bypass capacitor C SBYP and bus capacitance C BUS Due to the large RC time constant, it is not charged much. During the fast charging period (36), the capacitor C is retained. HOLD It is only partially charged due to the large RC time constant of the power harvesting circuit (66). As a result, the retaining capacitor C HOLD over time, the local voltage V CAP It may experience a cumulative drop. As shown herein, the cumulative drop can be as much as 100 mV.

[0047] Accumulated voltage drop can have an adverse effect on the slave circuits (14(1) to 14(M)). Specifically, the local voltage V CAP Due to the cumulative drop of, each slave circuit (14(1) to 14(M)) has a bus voltage V BUS higher bus voltage V BUSH When attempting to raise it, there is already a shortage of 100 mV. As a result, the slave circuits (14(1)–14(M)) signal a logic "1" to the master circuit (12) via the bus voltage V BUS Local voltage V sufficient to raise CAP It may not have. Also, the local voltage V CAPSince is the primary power source for the slave circuits (14(1) to 14(M)), the cumulative drop means that there is less voltage margin for each slave circuit (14(1) to 14(M)) to operate. Thus, the second technical problem to be solved herein is to reduce the power consumption of the slave circuits (14(1) to 14(M)) so that the local voltage V CAP It reduces the demand for, and therefore maintains capacitor C HOLD By reducing the capacitance of, the local voltage V CAP It makes it possible to reduce the cumulative drop in.

[0048] In this regard, FIG. 2 is a schematic diagram of an exemplary single-line bus device (72) configured according to an embodiment of the present disclosure to solve the previously identified technical problems associated with the conventional single-line bus device of FIG. 1a and FIG. 1f. In the above, the single-line bus device (72) comprises a master circuit (74) and multiple slave circuits (76(1)–76(M)). In one embodiment, the slave circuits (76(1)–76(M)) are coupled in parallel to the master circuit (74) via a single-line bus (78). As described in detail below, the single-line bus device (72) is based on a low-power waveform designed to reduce the amount of energy that each of the slave circuits (76(1)–76(M)) must locally store, the read data symbol T in the bus telegram (46, 48) of FIG. 1c S and the ACK symbol T in the bus telegram (20, 22) of FIG. 1b S It is configured to communicate reverse data symbols such as. As a result, each of the slave circuits (76(1)–76(M)) is configured to have a much smaller holding capacitor C HOLD Local voltage V supplied by (e.g., 1nF) CAP Sufficient power can be supplied by the smaller holding capacitor C in the slave circuit (76(1) to 76(M)). HOLDBy using it, the footprint of the slave circuit (76(1) to 76(M)) can be reduced and the accumulated voltage drop can be mitigated as shown in FIG. 1g.

[0049] In one embodiment, each slave circuit (76(1)–76(M)) may be configured to include an input node (80), a slave bus driver (82), a switch (84), and a power harvesting circuit (86). Specifically, the input node (80) is connected to a single-line bus (78), the switch (84) is connected to the input node (80), and the power harvesting circuit (86) is connected to the switch (84). The power harvesting circuit (86) includes a resistor R (resistance value R (e.g., 200 Ω)) and a holding capacitor C HOLD (Capacitance C HOLD It can be implemented as an RC circuit including (e.g., 1 nF). Each of the slave circuits (76(1) to 76(M)) also includes a slave bypass capacitor C coupled between the input node (80) and GND. SBYP (Capacitance C SBYP Includes (e.g., having 20 pF).

[0050] The master circuit (74) includes an output node (88), a master bus driver (90), and a master bypass capacitor C MBYP (Capacitance C MBYP It may include (e.g., having 20 pF). The output node (88) is coupled to the single-line bus (78), and the master bypass capacitor C MBYPIt is coupled between the output node (88) and GND. In the present invention, the master bus driver (90) is configured to initiate forward and reverse communication with each of the slave circuits (14(1)–14(M)) using the bus telegrams (20, 22) of FIG. 1b and the bus telegrams (46, 48) of FIG. 1c. The master bus driver (90) is also configured to enable and disable fast charging during the fast charging period (36). Unlike the master bus driver (70) of the conventional single-wire bus device (10) of FIG. 1f, the master bus driver (90) is additionally configured to initiate a low-power waveform at the start of each reverse data symbol.

[0051] The slave bus driver (82) is configured to close the switch (84) during the suspension period (T3-T1) to connect the power harvesting circuit (86) to the input node (80). In this way, each of the slave circuits (76(1)–76(M)) draws the bus current IBUS to the retaining capacitor CHOLD to the local voltage V CAP It can be charged. In addition to the suspension period (T3-T1), the slave bus driver (82) opens the switch (84) to disconnect the power harvesting circuit (86) from the input node (60). As a result, the retaining capacitor C HOLD It will be discharged to supply power to the slave bus driver (82).

[0052] Unlike the slave bus driver (62) of FIG. 1f, the slave bus driver (82) is configured to communicate in reverse data symbols using a low-power waveform, which will be discussed further below with reference to FIG. 3a and FIG. 3b are schematic diagrams providing detailed examples of low-power waveforms for performing reverse communication in the single-line bus device (72) of FIG. 2. Common elements of FIG. 3a and FIG. 3b are illustrated therein with common element numbers and are not described again here.

[0053] FIG. 3a illustrates a low-power waveform, and accordingly, each of the slave circuits (76(1) to 76(M)) of FIG. 2 transmits reverse read data symbol T to the master circuit (74) via a single-line bus (78). S logic "0" or reverse ACK symbol T S It can be used to indicate a negative acknowledgment (NAK). In this document, logic "0" and NAK are collectively referred to as the "first value".

[0054] Here, the low-power waveform is divided into a first section INT1 and a second section INT2. During the first section INT1, the master circuit (74) first applies a higher bus voltage V on the single-line bus (78). BUSH Apply a higher bus voltage V BUSH Immediately after applying (e.g., after 1 clock cycle), the master circuit (74) activates the fast charging period (92) so that each of the slave circuits (76(1)–76(M)) maintains capacitor C HOLD It allows for opportunistic recharging. Accordingly, each of the slave circuits (76(1) to 76(M)) closes the switch (84) to reduce the bus current I BUS Capacitor C that maintains HOLD It can be recharged. Before ending the first section INT1, the master circuit (74) disables the fast charging period (92), and each of the slave circuits (76(1) to 76(M)) opens the switch (84) in turn.

[0055] The master circuit (74) is configured to make the single-line bus (78) into a 3-state during the second section INT2, which means the single-line bus (78) has a higher bus voltage V BUSH It is maintained as such. Each slave bus driver (82) of the slave circuit (76(1) to 76(M)) has a higher bus voltage V during the second interval INT2. BUSH A single-line bus (78) is maintained to display a logic "0" (e.g., binary "0") or NAK to the master circuit (74).

[0056] FIG. 3b illustrates a low-power waveform, and accordingly, each of the slave circuits (76(1) to 76(M)) of FIG. 2 reads the reverse reading data symbol T through the single-line bus (78). S The logic "1" or reverse ACK symbol T S The ACK can be used to display the master circuit (74). In this specification, logic “1” and ACK are collectively referred to as “second value”.

[0057] In this specification, during the second interval INT2, the slave bus driver (82) of each slave circuit (76(1) to 76(M)) connects the single-line bus (78) to a higher bus voltage V BUSH lower bus voltage V from BUSL (V BUSL < V BUSH It is configured to be pulled down to ) to indicate a logic "1" (e.g., binary "1") or ACK. As can be understood, the single-wire bus (78) is lowered to a higher bus voltage V, as in a conventional single-wire bus device (10). BUSH Conversely to raising it to, the lower bus voltage V BUSL By lowering it, the amount of energy that each slave circuit (76(1)–76(M)) must locally store can be significantly reduced, so a much smaller holding capacitor C can be used to help reduce the footprint of the slave circuits (76(1)–76(M)). HOLD It becomes possible to use (e.g., 1nF). In addition, a smaller holding capacitor C HOLD This can also significantly reduce the RC time constant of the power harvesting circuit (86). As a result, the power harvesting circuit (86) can quickly harvest sufficient power to mitigate or even eliminate the accumulated voltage drop shown in FIG. 1g.

[0058] In particular, the slave bus driver (82) has a lower bus voltage V on the single-line bus (78) only during part of the second section INT2. BUSLIt may be necessary to apply. The single-line bus (78) is maintained in state 3 during the remainder of the second section INT2, and the lower bus voltage V BUSL Maintains the single-line bus (78) current reverse data symbol T S At lower bus voltage V BUSL Given that it was pulled down to, the master circuit (74) immediately follows the reverse data symbol T S During the first section INT1, a higher bus voltage V on the single-line bus (78) BUSH It is necessary to re-authorize it.

[0059] Referring again to FIG. 2, each of the slave circuits (76(1) to 76(M)) maintains capacitor C during the fast charging period (92). HOLD To enable opportunistic recharging, each of the slave circuits (76(1)–76(M)) is coupled in series with a smaller fast charging resistor R1 (e.g., 1 Ω) and a fast charging switch SW FC It additionally includes. During the fast charging period (92), the slave bus driver (82) of each slave circuit (76(1) to 76(M)) is the fast charging switch SW FC Close the capacitor C that each slave circuit (76(1) to 76(M)) maintains during the fast charging period (92). HOLD It allows for opportunistic recharging. Each slave bus driver (82) of the slave circuit (76(1) to 76(M)) uses a high-speed charging switch SW during periods other than the high-speed charging period (92). FC Opens.

[0060] FIG. 4 is a schematic diagram providing an exemplary illustration of the slave circuits (76(1) to 76(M)) of FIG. 2. Common elements of FIG. 2 and FIG. 4 are illustrated therein with common element numbers and are not described again here.

[0061] In one embodiment, the slave bus driver (82) includes an n-type field-effect transistor (NFET) (94), a data transmitter (96), and a data receiver (98). The NFET (94) is at a local voltage V CAP Driven by, during the second section INT2, the single-line bus (78) at a lower bus voltage V BUSL It pulls down to communicate logic "1" or ACK to the master circuit (74).

[0062] In particular, a smaller holding capacitor C in the slave circuit (76(1) to 76(M)). HOLD By using this, the setup time of the slave circuits (76(1)–76(M)) can be reduced. As a result, the slave circuits (76(1)–76(M)) can be rearranged based on a daisy-chain topology. FIG. 5 is a schematic diagram of a single-line bus device (72A) in which the slave circuits (76(1)–76(M)) are coupled to a master circuit (74) based on a daisy-chain topology. Common elements of FIG. 2 and FIG. 5 are illustrated therein with common element numbers and are not described again here.

[0063] The single-line bus device (72) of FIG. 2 and the single-line bus device (72A) of FIG. 5 may be provided to a user element (e.g., a wireless device) to support the aforementioned embodiment. In this regard, FIG. 6 is a schematic diagram of an exemplary user element (100) to which the single-line bus device (72) of FIG. 2 and the single-line bus device (72A) of FIG. 5 may be provided.

[0064] Here, the user element (100) may be any type of user element, such as a mobile terminal, a smartwatch, a tablet, a computer, a navigation device, an access point, and a similar wireless communication device that supports wireless communication such as cellular, wireless local area communication (WLAN), Bluetooth, and local area communication. The user element (100) generally includes a control system (102), a baseband processor (104), a transmitting circuit (106), a receiving circuit (108), an antenna switching circuit (110), a plurality of antennas (112), and a user interface circuit (114). In a non-limiting example, the control system (102) may be, for example, a field programmable gate array (FPGA). In this regard, the control system (102) may include at least a microprocessor(s), an embedded memory circuit(s), and a communication bus interface(s). The receiving circuit (108) receives radio frequency signals from one or more base stations through the antenna (112) and the antenna switching circuit (110). A low-noise amplifier and a filter work together to amplify the received signal for processing and to remove broadband interference. Then, a down-conversion and digitization circuit (not shown) down-converts the filtered received signal into an intermediate or baseband frequency signal and then digitizes it into one or more digital streams using an analog-to-digital converter(s) (ADC).

[0065] A baseband processor (104) processes a digitized received signal to extract information or data bits transmitted in the received signal. This processing typically includes demodulation, decoding, and error correction operations, which will be discussed in more detail below. The baseband processor (104) is generally implemented in one or more digital signal processors (DSPs) and application-specific integrated circuits (ASICs).

[0066] For transmission, a baseband processor (104) receives digitized data from a control system (102) that may represent voice, data, or control information, and encodes it for transmission. The encoded data is output to a transmission circuit (106), where digital-to-analog converter(s) (DAC) convert the digitally encoded data into an analog signal, and a modulator modulates the analog signal into a carrier signal of a desired transmission frequency or frequencies. A power amplifier amplifies the modulated carrier signal to a level suitable for transmission and transmits the modulated carrier signal to an antenna (112) through an antenna switching circuit (110). Multiple antennas (112) and duplicated transmission and reception circuits (106, 108) may provide spatial diversity. Details regarding modulation and processing will be understood by those skilled in the art.

[0067] In one embodiment, the single-line bus device (72) and the single-line bus device (72A) may be provided to the antenna switching circuit (110) to enable communication between the antenna switching circuit (110) and the antenna (112). In another embodiment, the single-line bus device (72) and the single-line bus device (72A) may also be used to enable communication between the antenna switching circuit (110), the transmitting circuit (106) and / or the receiving circuit (108).

[0068] The single-line bus device (72) of FIG. 2 and the single-line bus device (72A) of FIG. 5 can be configured according to a process. In this regard, FIG. 7 is a flowchart of an exemplary process (200) for configuring the single-line bus device (72) of FIG. 2 and the single-line bus device (72A) of FIG. 5.

[0069] In the present invention, the process (200) includes the step (step 202) of coupling the master circuit (74) to a single-line bus (78) consisting of a single line. The process (200) also includes the reverse data symbol T SIn each case, a higher bus voltage V on the single-line bus (78) during the first section INT1. BUSH After applying, the process includes a step (step 204) of configuring the master circuit (74) to make the single-line bus (78) a 3-state during the second interval INT2. The process (200) also includes a step (step 206) of coupling each of the slave circuits (76(1) to 76(N)) to the single-line bus (78). The process (200) also includes the reverse data symbol T S In each of the two sections INT2, the single-line bus (78) at a lower bus voltage V BUSL The process includes the step (step 208) of configuring each of the slave circuits (76(1)–76(N)) so as to pull down to thereby communicate a first value "1" or ACK to the master circuit (74). The process also includes the reverse data symbol T S During the second section (INT2) in each of the two sections, the single-line bus (78) has a lower bus voltage V BUSL The method includes the step (step 210) of configuring each of the slave circuits (76(1) to 76(N)) so as to bring down the first value "1" or ACK and thereby communicate a second value "0" or NAK different from the first value to the master circuit (74).

[0070] Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the following claims.

Claims

Claim 1 A single-line bus device comprising: a master circuit coupled to a single-line bus composed of a single line and configured to apply a higher bus voltage to the single-line bus during a first period and then make the single-line bus into a three-state during a second period at each of a plurality of reverse data symbols; and a plurality of slave circuits each coupled to the single-line bus, wherein each of the plurality of slave circuits is: In each of the plurality of reverse data symbols above, the single-line bus is lowered to a lower bus voltage during the second interval, thereby communicating a first value to the master circuit; A single-line bus device configured to maintain the single-line bus at the higher bus voltage during the second interval in each of the plurality of reverse data symbols, thereby communicating a second value different from the first value to the master circuit. Claim 2 In claim 1, the plurality of reverse data symbols includes a plurality of read data symbols; and each of the plurality of slave circuits additionally: In each of the plurality of read data symbols, the single-line bus is lowered to the lower bus voltage during the second interval, thereby communicating the binary number "1" as the first value to the master circuit; A single-line bus device configured to maintain the single-line bus at the higher bus voltage during the second interval in each of the plurality of read data symbols, thereby communicating the binary zero "0" as the second value to the master circuit. Claim 3 In paragraph 1, the plurality of reverse data symbols include a plurality of acknowledgment (ACK) symbols; and each of the plurality of slave circuits additionally: In each of the plurality of ACK symbols, the single-line bus is lowered to the lower bus voltage during the second interval, thereby communicating an ACK to the master circuit as the first value; A single-line bus device configured to maintain the single-line bus at the higher bus voltage during the second interval in each of the plurality of ACK symbols, thereby communicating a negative acknowledgment (NAK) as the second value to the master circuit. Claim 4 A single-line bus device according to claim 1, wherein when any one of the plurality of slave circuits lowers the single-line bus to the lower bus voltage at one immediately preceding the plurality of reverse data symbols, the master circuit is additionally configured to reapply the higher bus voltage to the single-line bus at the beginning of each of the plurality of reverse data symbols. Claim 5 A single-line bus device according to claim 1, wherein the master circuit is further configured to activate a high-speed charging period during the first interval at each of the plurality of reverse data symbols, so that each of the plurality of slave circuits can harvest power from the master circuit during the high-speed charging period. Claim 6 A single-line bus device according to claim 5, wherein the master circuit is further configured to: activate the fast charging period in each of the plurality of slave circuits after starting the first section in each of the plurality of reverse data symbols; and deactivate the fast charging period in each of the plurality of slave circuits before ending the first section in each of the plurality of reverse data symbols. Claim 7 A single-line bus device according to claim 5, wherein each of the plurality of slave circuits comprises: a holding capacitor coupled to the single-line bus through a switch, wherein the holding capacitor is closed during the high-speed charging period so that the holding capacitor can be charged by a bus current drawn from the master circuit through the single-line bus; and a slave bus driver comprising an n-type field-effect transistor (NFET) configured to lower the single-line bus to the lower bus voltage during the second period, thereby communicating the first value to the master circuit. Claim 8 A single-line bus device according to claim 1, wherein the plurality of slave circuits are coupled in parallel to the single-line bus. Claim 9 A single-line bus device according to claim 1, wherein the plurality of slave circuits are connected to the single-line bus in a daisy-chain manner. Claim 10 A wireless device comprising: a master circuit coupled to a single-line bus consisting of a single line and configured to apply a higher bus voltage to the single-line bus during a first interval and then make the single-line bus into a three-state during a second interval for each of a plurality of reverse data symbols; and a plurality of slave circuits each coupled to the single-line bus, wherein each of the plurality of slave circuits is: In each of the plurality of reverse data symbols above, the single-line bus is lowered to a lower bus voltage during the second interval, thereby communicating a first value to the master circuit; A wireless device configured to maintain the single-line bus at the higher bus voltage during the second interval in each of the plurality of reverse data symbols, thereby communicating a second value different from the first value to the master circuit. Claim 11 In paragraph 10, the plurality of reverse data symbols includes a plurality of read data symbols; and each of the plurality of slave circuits additionally: In each of the plurality of read data symbols, the single-line bus is lowered to the lower bus voltage during the second interval, thereby communicating the binary number "1" as the first value to the master circuit; A wireless device configured to maintain the single-line bus at the higher bus voltage during the second interval in each of the plurality of read data symbols, thereby communicating the binary zero "0" as the second value to the master circuit. Claim 12 In paragraph 10, the plurality of reverse data symbols include a plurality of acknowledgment (ACK) symbols; and each of the plurality of slave circuits additionally: In each of the plurality of ACK symbols, the single-line bus is lowered to the lower bus voltage during the second interval, thereby communicating an ACK to the master circuit as the first value; A wireless device configured to maintain the open-circuit bus at the higher bus voltage during the second interval in each of the plurality of ACK symbols, thereby communicating a negative acknowledgment (NAK) as the second value to the master circuit. Claim 13 A wireless device according to claim 10, wherein, when any one of the plurality of slave circuits lowers the single-line bus to the lower bus voltage at one immediately preceding the plurality of reverse data symbols, the master circuit is further configured to reapply the higher bus voltage to the single-line bus at the beginning of each of the plurality of reverse data symbols. Claim 14 A wireless device according to claim 10, wherein the master circuit is further configured to activate a high-speed charging period during the first interval at each of the plurality of reverse data symbols, so that each of the plurality of slave circuits can harvest power from the master circuit during the high-speed charging period. Claim 15 A wireless device according to claim 14, wherein the master circuit is further configured to: activate the fast charging period in each of the plurality of slave circuits after starting the first section in each of the plurality of reverse data symbols; and deactivate the fast charging period in each of the plurality of slave circuits before ending the first section in each of the plurality of reverse data symbols. Claim 16 A wireless device according to claim 14, wherein each of the plurality of slave circuits comprises a slave bus driver comprising: a holding capacitor coupled to the open-circuit bus via a switch—the switch being closed during the fast charging period so that the holding capacitor can be charged by a bus current drawn from the master circuit via the open-circuit bus—and an n-type field-effect transistor (NFET) configured to lower the open-circuit bus to the lower bus voltage during the second period, thereby communicating the first value to the master circuit. Claim 17 A wireless device according to claim 10, wherein the plurality of slave circuits are coupled in parallel to the single-line bus. Claim 18 A wireless device according to claim 10, wherein the plurality of slave circuits are daisy-chained to the single-line bus. Claim 19 A method for configuring a single-line bus device, comprising: a step of coupling a master circuit to a single-line bus composed of a single line; a step of configuring the master circuit such that, for each of a plurality of reverse data symbols, a higher bus voltage is applied to the single-line bus during a first period, and then the single-line bus is made into a three-state during a second period; a step of coupling each of a plurality of slave circuits to the single-line bus; a step of configuring each of the plurality of slave circuits such that, for each of the plurality of reverse data symbols, the single-line bus is lowered to a lower bus voltage during the second period, thereby communicating a first value to the master circuit; and a step of configuring each of the plurality of slave circuits such that, for each of the plurality of reverse data symbols, the single-line bus is maintained at the higher bus voltage during the second period, thereby communicating a second value different from the first value to the master circuit. Claim 20 A method according to claim 19, further comprising the step of connecting the plurality of slave circuits to the single-line bus in a daisy-chain manner.

Images