Display device and electronic device

Abstract

The present invention relates to a display device and an electronic device, comprising: a display panel including a display area and a non-display area; a first data driving circuit disposed in a non-display area on one side of the display area; and a first distribution circuit disposed in a non-display area between the first data driving circuit and the display area. The first data driving circuit includes a gamma circuit that generates a plurality of grayscale voltages, wherein the first data driving circuit includes a first data processing circuit that processes a first digital image data and a first data output circuit that converts the first digital image data from the first data processing circuit into a first analog image signal based on a plurality of grayscale voltages from the gamma circuit and provides it to the first distribution circuit, wherein the first data output circuit is disposed in a non-display area between the first data processing circuit and the first distribution circuit, and the gamma circuit includes a master gamma circuit that generates a gamma reference voltage based on a reference voltage and divides the gamma reference voltage to generate a plurality of grayscale voltages, and a first slave gamma circuit that divides the gamma reference voltage from the master gamma circuit to generate a plurality of grayscale voltages, wherein the first slave gamma circuit is disposed in a non-display area between the first data processing circuit and the first data output circuit.

Description

Technology Field

[0001] The present invention relates to a display device, and more specifically to a display device and an electronic device in which outputs from a data output circuit can be stably supplied to a distribution circuit and the length of the data output circuit can be reduced. Background Technology

[0002] Organic light-emitting diode displays have self-luminous properties and, unlike liquid crystal displays, do not require a separate light source, which can reduce thickness and weight. In addition, organic light-emitting diode displays exhibit high-quality characteristics such as low power consumption, high brightness, and high response speed, so they are attracting attention as next-generation display devices for TVs, monitors, and portable electronic devices. The problem to be solved

[0003] The present disclosure aims to provide a display device and an electronic device in which outputs from a data output circuit can be stably supplied to a distribution circuit and the length of the data output circuit can be reduced.

[0004] The problems of the present invention are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0005] A display device according to one embodiment for achieving the above-mentioned purpose comprises: a display panel including a display area and a non-display area; a first data driving circuit disposed in a non-display area on one side of the display area; and a first distribution circuit disposed in a non-display area between the first data driving circuit and the display area. The first data driving circuit includes a gamma circuit that generates a plurality of grayscale voltages, wherein the first data driving circuit includes a first data processing circuit that processes a first digital image data and a first data output circuit that converts the first digital image data from the first data processing circuit into a first analog image signal based on a plurality of grayscale voltages from the gamma circuit and provides it to the first distribution circuit, wherein the first data output circuit is disposed in a non-display area between the first data processing circuit and the first distribution circuit, and the gamma circuit includes a master gamma circuit that generates a gamma reference voltage based on a reference voltage and divides the gamma reference voltage to generate a plurality of grayscale voltages, and a first slave gamma circuit that divides the gamma reference voltage from the master gamma circuit to generate a plurality of grayscale voltages, wherein the first slave gamma circuit is disposed in a non-display area between the first data processing circuit and the first data output circuit.

[0006] In addition, an electronic device according to one embodiment for achieving the above-mentioned purpose comprises a display device including a display screen, wherein the display device comprises: a display panel including a display area and a non-display area; a first data driving circuit disposed in a non-display area on one side of the display area; and a first distribution circuit disposed in a non-display area between the first data driving circuit and the display area. The first data driving circuit includes a gamma circuit that generates a plurality of grayscale voltages, wherein the first data driving circuit includes a first data processing circuit that processes a first digital image data and a first data output circuit that converts the first digital image data from the first data processing circuit into a first analog image signal based on a plurality of grayscale voltages from the gamma circuit and provides it to the first distribution circuit, wherein the first data output circuit is disposed in a non-display area between the first data processing circuit and the first distribution circuit, and the gamma circuit includes a master gamma circuit that generates a gamma reference voltage based on a reference voltage and divides the gamma reference voltage to generate a plurality of grayscale voltages, and a first slave gamma circuit that divides the gamma reference voltage from the master gamma circuit to generate a plurality of grayscale voltages, wherein the first slave gamma circuit is disposed in a non-display area between the first data processing circuit and the first data output circuit.

[0007] Specific details of other embodiments are included in the detailed description and drawings. Effects of the invention

[0008] According to one embodiment of the display device and electronic device, outputs from a data output circuit can be stably supplied to a distribution circuit, and the length of the data output circuit can be reduced.

[0009] For example, according to one embodiment, slave gamma circuits are not placed between the circuit blocks of the data output circuit but are respectively placed adjacent to both edges of the data output circuit, so that the output terminals of the data output circuit and the input terminals of the distribution circuit can be connected without separate fan-out lines. Accordingly, outputs from the data output circuit can be reliably supplied to the distribution circuit.

[0010] In addition, since the slave gamma circuits are not placed between the circuit blocks of the data output circuit but are positioned adjacent to each of the two edges of the data output circuit, the length of the data output circuit can be reduced. Therefore, exposure can be performed in a single shot during the photolithography process for forming the data output circuit.

[0011] Meanwhile, the effects obtainable from the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by those skilled in the art to which the present invention belongs from the description below. Brief explanation of the drawing

[0012] FIG. 1 is an exploded perspective view showing a display device according to one embodiment. FIG. 2 is a block diagram showing a display device according to one embodiment. FIG. 3 is an equivalent circuit diagram of a first subpixel according to one embodiment. FIG. 4 is a layout diagram showing an example of a display panel according to one embodiment. Figure 5 is a detailed configuration diagram of the first data driving circuit of Figure 4. FIG. 6 is a block diagram of an electronic device according to one embodiment. FIGS. 7, FIGS. 8 and FIGS. 9 are schematic diagrams of electronic devices according to various embodiments. Specific details for implementing the invention

[0013] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0014] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0015] Although terms such as "first," "second," etc., are used to describe various components, it goes without saying that these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it goes without saying that the first component mentioned below may also be the second component within the technical scope of the present invention.

[0016] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0017] Specific embodiments will be described below with reference to the attached drawings.

[0018] FIG. 1 is an exploded perspective view showing a display device according to one embodiment. FIG. 2 is a block diagram showing a display device according to one embodiment.

[0019] Referring to FIGS. 1 and 2, a display device (10) according to one embodiment is a device for displaying video or still images. The display device (10) according to one embodiment can be applied to portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation systems, and ultra mobile PCs (UMPCs). For example, the display device (10) according to one embodiment can be applied to a television, laptop, monitor, billboard, or display unit of the Internet of Things (IOT). Alternatively, the display device (10) according to one embodiment can be applied to a smart watch, a watch phone, or a head-mounted display (HMD) for implementing virtual reality and augmented reality.

[0020] A display device (10) according to one embodiment includes a display panel (100), a heat dissipation layer (200), a circuit board (300), a timing control circuit (400), and a power supply circuit (500).

[0021] The display panel (100) may be formed in a planar shape similar to a rectangle. For example, the display panel (100) may have a planar shape similar to a rectangle having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corners where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet in the display panel (100) may be formed rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display panel (100) is not limited to a rectangle and may be formed similarly to other polygons, circles, or ellipses. The planar shape of the display device (10) may follow the planar shape of the display panel (100), but the embodiments of the present specification are not limited thereto.

[0022] The display panel (100) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of light emission control lines (EL), and a plurality of data lines (DL), a scan driving unit (610), a light emission driving unit (620), and a data driving unit (800). As shown in FIG. 2, the display panel (100) may be divided into a display area (DAA) that displays an image and a non-display area (NDA) that does not display an image.

[0023] Multiple pixels (PX) may be placed in a display area (DAA). Multiple pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) may extend in the first direction (DR1) and be placed in the second direction (DR2). Multiple data lines (DL) may extend in the second direction (DR2) and be placed in the first direction (DR1).

[0024] A plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of control scan lines (GCL), and a plurality of bias scan lines (GBL). A plurality of light emission control lines (EL) include a plurality of first light emission control lines (EL1) and a plurality of second light emission control lines (EL2).

[0025] A plurality of pixels (PX) include a plurality of sub-pixels (SP1, SP2, SP3). The plurality of sub-pixels (SP1, SP2, SP3) include a plurality of pixel transistors as shown in FIG. 3, and the plurality of pixel transistors are formed by a semiconductor process and can be placed on a semiconductor substrate. For example, the plurality of pixel transistors of the data driving unit (800) may be formed as CMOS (Complementary Metal Oxide Semiconductor), but the embodiments of the present specification are not limited thereto.

[0026] Each of the plurality of subpixels (SP1, SP2, SP3) can be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines (GCL), one of the plurality of bias scan lines (GBL), one of the plurality of first light emission control lines (EL1), one of the plurality of second light emission control lines (EL2), and one of the plurality of data lines (DL). Each of the plurality of subpixels (SP1, SP2, SP3) receives a data voltage of the data line (DL) according to the write scan signal of the write scan line (GWL), and can emit light from the light-emitting element according to the data voltage.

[0027] The scan drive unit (610), light-emitting drive unit (620), and data drive unit (800) can be placed in the non-display area (NDA).

[0028] The scan driving unit (610) includes a plurality of scan transistors, and the light-emitting driving unit (620) includes a plurality of light-emitting transistors. The plurality of scan transistors and the plurality of light-emitting transistors are formed by a semiconductor process and can be formed on a semiconductor substrate. For example, the plurality of scan transistors and the plurality of light-emitting transistors can be formed by CMOS, but the embodiments of the present specification are not limited thereto.

[0029] The scan driving unit (610) may include a write scan signal output unit (611), a control scan signal output unit (612), and a bias scan signal output unit (613). Each of the write scan signal output unit (611), the control scan signal output unit (612), and the bias scan signal output unit (613) may receive a scan timing control signal (SCS) from the timing control circuit (400). The write scan signal output unit (611) may generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (400) and output them sequentially to the write scan lines (GWL). The control scan signal output unit (612) may generate control scan signals according to the scan timing control signal (SCS) and output them sequentially to the control scan lines (GCL). The bias scan signal output unit (613) may generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (EBL).

[0030] The light-emitting driver (620) includes a first light-emitting control driver (621) and a second light-emitting control driver (622). Each of the first light-emitting control driver (621) and the second light-emitting control driver (622) can receive a light-emitting timing control signal (ECS) from the timing control circuit (400). The first light-emitting control driver (621) can generate first light-emitting control signals according to the light-emitting timing control signal (ECS) and output them sequentially to the first light-emitting control lines (EL1). The second light-emitting control driver (622) can generate second light-emitting control signals according to the light-emitting timing control signal (ECS) and output them sequentially to the second light-emitting control lines (EL2).

[0031] The data driving unit (800) includes a plurality of data transistors, and the plurality of data transistors are formed by a semiconductor process and can be formed on a semiconductor substrate. For example, the plurality of data transistors can be formed by CMOS, but the embodiments of the present specification are not limited thereto.

[0032] The data driver (800) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (400). The data driver (800) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SP1, SP2, SP3) are selected by the write scan signal of the scan driver (610), and data voltages can be supplied to the selected subpixels (SP1, SP2, SP3).

[0033] The heat dissipation layer (200) may overlap with the display panel (100) in a third direction (DR3), which is the thickness direction of the display panel (100). The heat dissipation layer (200) may be placed on one side of the display panel (100), for example, on the back side. The heat dissipation layer (200) serves to dissipate heat generated from the display panel (100). The heat dissipation layer (200) may include a metal layer such as graphite, silver (Ag), copper (Cu), or aluminum (Al), which has high thermal conductivity.

[0034] The circuit board (300) can be electrically connected to a plurality of pads (PDs in FIG. 4) of the pad portion (PDA in FIG. 4) of the display panel (100) using a conductive adhesive member such as an anisotropic conductive film. The circuit board (300) may be a flexible printed circuit board having a flexible material or a flexible film. Although FIG. 1 illustrates the circuit board (300) unfolded, the circuit board (300) may be bent. In this case, one end of the circuit board (300) may be placed on the back surface of the display panel (100) and / or the back surface of the heat dissipation layer (200). The other end of the circuit board (300) may be connected to a plurality of pads (PDs in FIG. 4) of the pad portion (PDA in FIG. 4) of the display panel (100) using a conductive adhesive member. One end of the circuit board (300) can be the opposite end of the other end of the circuit board (300).

[0035] The timing control circuit (400) can receive digital video data and timing signals from an external source. The timing control circuit (400) can generate a scan timing control signal (SCS), a light emission timing control signal (ECS), and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the scan driver (610) and the light emission timing control signal (ECS) to the light emission driver (620). The timing control circuit (400) can output the digital video data and the data timing control signal (DCS) to the data driver (800).

[0036] The power supply circuit (500) can generate a plurality of panel driving voltages according to the power supply voltage from an external source. For example, the power supply circuit (500) can generate a first driving voltage (VSS), a second driving voltage (VDD), and a third driving voltage (VINT) and supply them to the display panel (100). The first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) will be described later in conjunction with FIG. 3.

[0037] The timing control circuit (400) and the power supply circuit (500) can each be formed as an integrated circuit (IC) and attached to one side of the circuit board (300). In this case, the scan timing control signal (SCS), light emission timing control signal (ECS), digital video data (DATA), and data timing control signal (DCS) of the timing control circuit (400) can be supplied to the display panel (100) through the circuit board (300). Additionally, the first driving voltage (VSS), the second driving voltage (VDD), and the third driving voltage (VINT) of the power supply circuit (500) can be supplied to the display panel (100) through the circuit board (300).

[0038] Alternatively, the timing control circuit (400) and the power supply circuit (500) may each be placed in the non-display area (NDA) of the display panel (100), similar to the scan driver (610), light-emitting driver (620), and data driver (800). In this case, the timing control circuit (400) may include a plurality of timing transistors, and each of the power supply circuits (500) may include a plurality of power transistors. The plurality of timing transistors and the plurality of power transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate. For example, the plurality of timing transistors and the plurality of power transistors may be formed by CMOS, but the embodiments of this specification are not limited thereto. The timing control circuit (400) and the power supply circuit (500) may each be placed between the data driver (800) and the pad unit (PDA of FIG. 4).

[0039] FIG. 3 is an equivalent circuit diagram of a first subpixel according to one embodiment.

[0040] Referring to FIG. 3, the first subpixel (SP1) can be connected to a write scan line (GWL), a control scan line (GCL), a bias scan line (EBL), a first light emission control line (EL1), a second light emission control line (EL2), and a data line (DL). Additionally, the first subpixel (SP1) can be connected to a first driving voltage line (VSL) to which a first driving voltage (VSS) corresponding to a low potential voltage is applied, a second driving voltage line (VDL) to which a second driving voltage (VDD) corresponding to a high potential voltage is applied, and a third driving voltage line (VIL) to which a third driving voltage (VINT) corresponding to an initialization voltage is applied. That is, the first driving voltage line (VSL) may be a low potential voltage line, the second driving voltage line (VDL) may be a high potential voltage line, and the third driving voltage line (VIL) may be an initialization voltage line. In this case, the first driving voltage (VSS) may be a lower voltage than the third driving voltage (VINT). The second driving voltage (VDD) may be a higher voltage than the third driving voltage (VINT).

[0041] The first subpixel (SP1) includes a plurality of transistors (T1 to T6), a light-emitting element (LE), a first capacitor (CP1), and a second capacitor (CP2).

[0042] The light-emitting element (LE) emits light according to the driving current (Ids) flowing through the channel of the first transistor (T1). The amount of light emitted by the light-emitting element (LE) may be proportional to the driving current (Ids). The light-emitting element (LE) may be placed between the fourth transistor (T4) and the first driving voltage line (VSL). The first electrode of the light-emitting element (LE) may be connected to the drain electrode of the fourth transistor (T4), and the second electrode may be connected to the first driving voltage line (VSL). The first electrode of the light-emitting element (LE) may be an anode electrode, and the second electrode of the light-emitting element (LE) may be a cathode electrode. The light-emitting element (LE) may be an organic light-emitting diode comprising a first electrode, a second electrode, and an organic light-emitting layer placed between the first electrode and the second electrode, but the embodiments of this specification are not limited thereto. For example, the light-emitting element (LE) may be an inorganic light-emitting element comprising a first electrode, a second electrode, and an inorganic semiconductor disposed between the first electrode and the second electrode, in which case the light-emitting element (LE) may be a micro light-emitting diode.

[0043] The first transistor (T1) may be a driving transistor that controls the source-drain current (Ids, hereinafter referred to as “driving current”) flowing between the source electrode and the drain electrode according to the voltage applied to the gate electrode. The first transistor (T1) includes a gate electrode connected to the first node (N1), a source electrode connected to the drain electrode of the sixth transistor (T6), and a drain electrode connected to the second node (N2).

[0044] The second transistor (T2) may be placed between one electrode of the first capacitor (CP1) and the data line (DL). The second transistor (T2) is turned on by a write scan signal of the write scan line (GWL) to connect one electrode of the first capacitor (CP1) to the data line (DL). As a result, the data voltage of the data line (DL) can be applied to one electrode of the first capacitor (CP1). The second transistor (T2) includes a gate electrode connected to the write scan line (GWL), a source electrode connected to the data line (DL), and a drain electrode connected to one electrode of the first capacitor (CP1).

[0045] The third transistor (T3) may be placed between the first node (N1) and the second node (N2). The third transistor (T3) is turned on by a write control signal of the write control line (GCL) to connect the first node (N1) to the second node (N2). As a result, when the gate electrode and the source electrode of the first transistor (T1) are connected, the first transistor (T1) can operate like a diode. The third transistor (T3) includes a gate electrode connected to the write control line (GCL), a source electrode connected to the second node (N2), and a drain electrode connected to the first node (N1).

[0046] The fourth transistor (T4) can be connected between the second node (N2) and the third node (N3). The fourth transistor (T4) is turned on by a first light emission control signal of the first light emission control line (EL1) to connect the second node (N2) to the third node (N3). As a result, the driving current of the first transistor (T1) can be supplied to the light emission element (LE). The fourth transistor (T4) includes a gate electrode connected to the first light emission control line (EL1), a source electrode connected to the second node (N2), and a drain electrode connected to the third node (N3).

[0047] The fifth transistor (T5) may be placed between the third node (N3) and the third driving voltage line (VIL). The fifth transistor (T5) is turned on by a bias scan signal of the bias scan line (EBL) to connect the third node (N3) to the third driving voltage line (VIL). As a result, the third driving voltage (VINT) of the third driving voltage line (VIL) can be applied to the first electrode of the light-emitting element (LE). The fifth transistor (T5) includes a gate electrode connected to the bias scan line (EBL), a source electrode connected to the third node (N3), and a drain electrode connected to the third driving voltage line (VIL).

[0048] The sixth transistor (T6) may be placed between the source electrode of the first transistor (T1) and the second driving voltage line (VDL). The sixth transistor (T6) is turned on by a second light emission control signal of the second light emission control line (EL2) to connect the source electrode of the first transistor (T1) to the second driving voltage line (VDL). As a result, the second driving voltage (VDD) of the second driving voltage line (VDL) may be applied to the source electrode of the first transistor (T1). The sixth transistor (T6) includes a gate electrode connected to the second light emission control line (EL2), a source electrode connected to the second driving voltage line (VDL), and a drain electrode connected to the source electrode of the first transistor (T1).

[0049] The first capacitor (CP1) is formed between the first node (N1) and the drain electrode of the second transistor (T2). The first capacitor (CP1) includes one electrode connected to the drain electrode of the second transistor (T2) and another electrode connected to the first node (N1).

[0050] A second capacitor (CP2) is formed between the gate electrode of the first transistor (T1) and the second driving voltage line (VDL). The second capacitor (CP2) includes one electrode connected to the gate electrode of the first transistor (T1) and another electrode connected to the second driving voltage line (VDL).

[0051] The first node (N1) is the contact point of the gate electrode of the first transistor (T1), the drain electrode of the third transistor (T3), the other electrode of the first capacitor (CP1), and the one electrode of the second capacitor (CP2). The second node (N2) is the contact point of the drain electrode of the first transistor (T1), the source electrode of the third transistor (T3), and the source electrode of the fourth transistor (T4). The third node (N3) is the contact point of the drain electrode of the fourth transistor (T4), the source electrode of the fifth transistor (T5), and the first electrode of the light-emitting element (LE).

[0052] Each of the first to sixth transistors (T1 to T6) may be a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET). For example, each of the first to sixth transistors (T1 to T6) may be a P-type MOSFET, but the embodiments of this specification are not limited thereto. Each of the first to sixth transistors (T1 to T6) may be an N-type MOSFET. Alternatively, among the first to sixth transistors (T1 to T6), some of the transistors may be P-type MOSFETs and the remaining transistors may be N-type MOSFETs.

[0053] In FIG. 3, the first subpixel (SP1) is illustrated as including six transistors (T1 to T6) and two capacitors (CP1, CP2), but the equivalent circuit diagram of the first subpixel (SP1) is not limited to that shown in FIG. 3.

[0054] In addition, the equivalent circuit diagram of the second subpixel (SP2) and the equivalent circuit diagram of the third subpixel (SP3) may be substantially the same as the equivalent circuit diagram of the first subpixel (SP1) described in conjunction with FIG. 3. Therefore, the description of the equivalent circuit diagram of the second subpixel (SP2) and the equivalent circuit diagram of the third subpixel (SP3) is omitted in this specification.

[0055] FIG. 4 is a layout diagram showing an example of a display panel according to one embodiment.

[0056] Referring to FIG. 4, a display area (DAA) of a display panel (100) according to one embodiment includes a plurality of pixels (PX) arranged in a matrix form. A pixel (PX) may include a first sub-pixel (SP1), a second sub-pixel (SP2), and a third sub-pixel (SP3) arranged adjacently.

[0057] In the non-display area (NDA) of a display panel (100) according to one embodiment, a scan driving unit (610), a light-emitting driving unit (620), a data driving unit (800)(800), a first distribution circuit (710), a second distribution circuit (720)(720), a gamma circuit, and a pad unit (PDA) may be disposed.

[0058] The scan drive unit (610) may be positioned on the first side of the display area (DAA), and the light-emitting drive unit (620) may be positioned on the second side of the display area (DAA). For example, the scan drive unit (610) may be positioned on one side of the first direction (DR1) of the display area (DAA), and the light-emitting drive unit (620) may be positioned on the other side of the first direction (DR1) of the display area (DAA). That is, the scan drive unit (610) may be positioned on the left side of the display area (DAA), and the light-emitting drive unit (620) may be positioned on the right side of the display area (DAA). However, the embodiments of this specification are not limited thereto, and the scan drive unit (610) and the light-emitting drive unit (620) may be positioned on both the first side and the second side of the display area (DAA).

[0059] The pad portion (PDA) may include a plurality of pads (PDs) connected to pads or bumps of the circuit board (300) through a conductive adhesive member. The pad portion (PDA) may be positioned at the edge of the display panel adjacent to the scan driver (610).

[0060] The data driving unit (800) may include a first data driving circuit (810) and a second data driving circuit (820).

[0061] The first data driving circuit (810) may be placed in the non-display area (NDA) on the third side (e.g., the lower side) of the display area (DAA). For example, the first data driving circuit (810) may be placed on one side of the second direction (DR2) of the display area (DAA). The first data driving circuit (810) may include a first data processing circuit (811) and a first data output circuit (812).

[0062] The first data processing circuit (811) can process the first digital image data signals from the timing control circuit (400) and provide them to the first data output circuit (812).

[0063] The first data output circuit (812) can convert the first image data signal processed from the first data processing circuit (811) into an analog signal and provide it to the first distribution circuit (710). For example, the first analog image signals from the first data output circuit (812) can be provided to the first distribution circuit (710).

[0064] The second data driving circuit (820) may be placed in the non-display area (NDA) on the fourth side (e.g., upper side) of the display area (DAA). For example, the second data driving circuit (820) may be placed on the other side of the second direction (DR2) of the display area (DAA). The second data driving circuit (820) may include a second data processing circuit (821) and a second data output circuit (822).

[0065] The second data processing circuit (821) can process the second digital image data signals from the timing control circuit (400) and provide them to the second data output circuit (822).

[0066] The second data output circuit (822) can convert the second image data signal processed from the second data processing circuit (821) into an analog signal and provide it to the second distribution circuit (720). For example, the second analog image signals from the second data output circuit (822) can be provided to the second distribution circuit (720).

[0067] The first distribution circuit (710) may be placed in a non-display area (NDA) between the display area (DAA) and the first data driving circuit (810). For example, the first distribution circuit (710) may be placed in a non-display area (NDA) between the display area (DAA) and the first data output circuit (812). The first distribution circuit (710) may divide the first analog video signals from the first data output circuit (812) in a time-division manner and provide them to a plurality of first data lines. For example, the data lines (DL) may be divided into a plurality of first data lines and a plurality of second data lines, and the first distribution circuit (710) may divide the first analog video signals in a time-division manner and provide them sequentially to the plurality of first data lines. The number of channels (e.g., output channels) of the first distribution circuit (710) may be equal to the number of first data lines, and the number of channels (e.g., output channels) of the first data output circuit (812) may be smaller than the number of channels (e.g., output channels) of the first distribution circuit (710). The first distribution circuit (710) may include, for example, a demultiplexer.

[0068] The second distribution circuit (720) may be placed in the non-display area (NDA) between the display area (DAA) and the second data driving circuit (820). For example, the second distribution circuit (720) may be placed in the non-display area (NDA) between the display area (DAA) and the second data output circuit (822). The second distribution circuit (720) may divide the second analog video signals from the second data output circuit (822) in a time-division manner and provide them to a plurality of second data lines. For example, the second distribution circuit (720) may divide the second analog video signals in a time-division manner and provide them sequentially to a plurality of second data lines. The number of channels (e.g., output channels) of the second distribution circuit (720) may be equal to the number of second data lines, and the number of channels (e.g., output channels) of the second data output circuit (822) may be smaller than the number of channels (e.g., output channels) of the second distribution circuit (720). The second distribution circuit (720) may include, for example, a demultiplexer.

[0069] The gamma circuit (900) can divide the gamma reference voltage to generate a plurality of grayscale voltages and provide the generated plurality of grayscale voltages (e.g., grayscale voltages of 0 to 255 grayscale levels) to the data driving unit (800). For example, the gamma circuit (900) can provide the plurality of grayscale voltages to the first data output circuit (812) and the second data output circuit (822). The first data output circuit (812) can select a grayscale voltage corresponding to the first digital image data signal from the gamma circuit (900) and output the selected grayscale voltage as the first analog image signal. Similarly, the second data output circuit (822) can select a grayscale voltage corresponding to the second digital image data signal from the gamma circuit (900) and output the selected grayscale voltage as the second analog image signal. Here, the gamma circuit (900) can generate a plurality of red grayscale voltages for red image data, a plurality of green grayscale voltages for green image data, and a plurality of blue grayscale voltages for blue image data.

[0070] The gamma circuit (900) may include a master gamma circuit (910) and a plurality of slave gamma circuits (921, 922, 923, 924, 925, 926).

[0071] The master gamma circuit (910) can generate a gamma reference voltage based on a reference voltage from the power supply circuit (500), and divide the generated gamma reference voltage to generate a plurality of grayscale voltages (e.g., grayscale voltages of 0 to 255 grayscale levels). The grayscale voltages from the master gamma circuit (910) can be supplied to the first data output circuit (812) of the first data driving circuit (810) and the second data output circuit (822) of the second data driving circuit (820). Additionally, the gamma reference voltage from the master gamma circuit (910) can be provided to a plurality of slave gamma circuits (921, 922, 923, 924, 925, 926). The master gamma circuit (910) can be placed in the non-display area (NDA) between the pad section (PDA) and the scan driving section (610). The master gamma circuit (910) can be connected to the power supply circuit (500) on the circuit board (300) through the pads (PD) of the pad section (PDA).

[0072] A plurality of slave gamma circuits (921, 922, 923, 924, 925, 926) may include a first slave gamma circuit (921), a second slave gamma circuit (922), a third slave gamma circuit (923), a fourth slave gamma circuit (924), a fifth slave gamma circuit (925), and a sixth slave gamma circuit (926).

[0073] Each slave gamma circuit (921, 922, 923, 924, 925, 926) can receive a gamma reference voltage from the master gamma circuit (910). Each slave gamma circuit (921, 922, 923, 924, 925, 926) can divide the gamma reference voltage to generate multiple grayscale voltages (e.g., grayscale voltages of 0 to 255 grayscale levels). For example, the first slave gamma circuit (921) divides the gamma reference voltage from the master gamma circuit (910) to generate a plurality of grayscale voltages (e.g., grayscale voltages of levels 0 to 255), the second slave gamma circuit (922) divides the gamma reference voltage from the master gamma circuit (910) to generate a plurality of grayscale voltages (e.g., grayscale voltages of levels 0 to 255), the third slave gamma circuit (923) divides the gamma reference voltage from the master gamma circuit (910) to generate a plurality of grayscale voltages (e.g., grayscale voltages of levels 0 to 255), and the fourth slave gamma circuit (924) divides the gamma reference voltage from the master gamma circuit (910) to generate a plurality of grayscale voltages (e.g., grayscale to A gradation voltage of 255 gradation levels is generated, and the 5th slave gamma circuit (925) divides the gamma reference voltage from the master gamma circuit (910) to generate a plurality of gradation voltages (e.g., gradation voltages of 0 to 255 gradation levels), and the 6th slave gamma circuit (926) divides the gamma reference voltage from the master gamma circuit (910) to generate a plurality of gradation voltages (e.g., gradation voltages of 0 to 255 gradation levels).

[0074] The first slave gamma circuit (921), the second slave gamma circuit (922), and the third slave gamma circuit (923) can be connected to the master gamma circuit (910) and the first data output circuit (812). Grayscale voltages from the first slave gamma circuit (921), grayscale voltages from the second slave gamma circuit (922), and grayscale voltages from the third slave gamma circuit (923) can be supplied to the first data output circuit (812). The first data output circuit (812) can output first analog video signals based on the grayscale voltages from the first to third slave gamma circuits (921, 922, 923).

[0075] The first slave gamma circuit (921) may be placed in the non-display area (NDA) between the first data processing circuit (811) and the first data output circuit (812). The length of the first slave gamma circuit (921) (e.g., the size of the first slave gamma circuit (921) in the second direction (DR2)) may be smaller than the length of the second slave gamma circuit (922) (e.g., the size of the second slave gamma circuit (922) in the second direction (DR2)). The width of the first slave gamma circuit (921) (e.g., the size of the first slave gamma circuit (921) in the first direction (DR1)) may be smaller than the width of the second slave gamma circuit (922) (e.g., the size of the second slave gamma circuit (922) in the first direction (DR1)).

[0076] The second slave gamma circuit (922) may be placed in a non-display area (NDA) adjacent to one edge of the first data processing circuit (811). For example, the second slave gamma circuit (922) may be placed in a non-display area (NDA) between one edge of the first data processing circuit (811) and the pad portion (PDA).

[0077] The third slave gamma circuit (923) may be placed in a non-display area (NDA) adjacent to the other edge of the first data processing circuit (811). For example, the third slave gamma circuit (923) may be placed in a non-display area (NDA) between the other edge of the first data processing circuit (811) and the edge of the display panel (100). The length of the third slave gamma circuit (923) (e.g., the size of the third slave gamma circuit (921) in the second direction (DR2)) may be the same as the length of the second slave gamma circuit (922) (e.g., the size of the second slave gamma circuit (922) in the second direction (DR2)). The width of the third slave gamma circuit (923) (e.g., the size of the third slave gamma circuit (923) in the first direction (DR1)) may be the same as the width of the second slave gamma circuit (922) (e.g., the size of the second slave gamma circuit (922) in the first direction (DR1)).

[0078] The area of ​​the first slave gamma circuit (921), the area of ​​the second slave gamma circuit (922), and the area of ​​the third slave gamma circuit (923) may be the same as each other.

[0079] The fourth slave gamma circuit (924), the fifth slave gamma circuit (925), and the sixth slave gamma circuit (926) can be connected to the master gamma circuit (910) and the second data output circuit (822). The grayscale voltages from the fourth slave gamma circuit (924), the grayscale voltages from the fifth slave gamma circuit (925), and the grayscale voltages from the sixth slave gamma circuit (926) can be supplied to the second data output circuit (822). The second data output circuit (822) can output second analog video signals based on the grayscale voltages from the fourth to sixth slave gamma circuits (924, 925, 926).

[0080] The fourth slave gamma circuit (924) may be placed in the non-display area (NDA) between the second data processing circuit (821) and the second data output circuit (822). The length of the fourth slave gamma circuit (924) (e.g., the size of the fourth slave gamma circuit (924) in the second direction (DR2)) may be smaller than the length of the fifth slave gamma circuit (925) (e.g., the size of the fifth slave gamma circuit (925) in the second direction (DR2)). The width of the fourth slave gamma circuit (924) (e.g., the size of the fourth slave gamma circuit (924) in the first direction (DR1)) may be smaller than the width of the fifth slave gamma circuit (925) (e.g., the size of the fifth slave gamma circuit (925) in the first direction (DR1)).

[0081] The fifth slave gamma circuit (925) may be placed in a non-display area (NDA) adjacent to one edge of the second data processing circuit (821). For example, the fifth slave gamma circuit (925) may be placed in a non-display area (NDA) between one edge of the second data processing circuit (821) and the pad portion (PDA).

[0082] The sixth slave gamma circuit (926) may be placed in a non-display area (NDA) adjacent to the other edge of the second data processing circuit (821). For example, the sixth slave gamma circuit (926) may be placed in a non-display area (NDA) between the other edge of the second data processing circuit (821) and the edge of the display panel (100). The length of the sixth slave gamma circuit (926) (e.g., the size of the sixth slave gamma circuit (926) in the second direction (DR2)) may be the same as the length of the fifth slave gamma circuit (925) (e.g., the size of the fifth slave gamma circuit (925) in the second direction (DR2)). The width of the sixth slave gamma circuit (926) (e.g., the size of the sixth slave gamma circuit (926) in the first direction (DR1)) may be the same as the width of the fifth slave gamma circuit (925) (e.g., the size of the fifth slave gamma circuit (925) in the first direction (DR1)).

[0083] The area of ​​the fourth slave gamma circuit (924), the area of ​​the fifth slave gamma circuit (925), and the area of ​​the sixth slave gamma circuit (926) may be the same as each other.

[0084] According to one embodiment, the first data output circuit (812) may be positioned between the second slave gamma circuit (922) and the third slave gamma circuit (923) without being separated into a plurality of circuit blocks. In other words, the second slave gamma circuit (922) and the second slave gamma circuit (922) are not positioned between the circuit blocks of the first data output circuit (812) but are positioned adjacent to each of the two edges of the first data output circuit (812). Accordingly, the first data output circuit (812) and the first distribution circuit (710) may be positioned to face each other directly. Therefore, the output terminals of the first data output circuit (812) and the input terminals of the first distribution circuit (710) can be connected without separate fan-out lines. Thus, outputs from the first data output circuit (812) can be reliably supplied to the first distribution circuit (710). In the same way, outputs from the second data output circuit (822) can be reliably supplied to the second distribution circuit (720).

[0085] Additionally, according to one embodiment, as described above, the second slave gamma circuit (922) and the second slave gamma circuit (922) are not placed between the circuit blocks of the first data output circuit (812) but are respectively placed adjacent to both edges of the first data output circuit (812), so that the length of the first data output circuit (812) in the direction toward the first data output circuit (812) in the display area (DAA) (e.g., the second direction) can be reduced. For example, the length of the first data output circuit (812) can be reduced instead of the width of the first data output circuit (812) (e.g., the size of the first data output circuit (812) in the first direction) increasing. Accordingly, the length of the first data output circuit (812) can be reduced while maintaining the area of ​​the first data output circuit (812). Therefore, exposure can be performed in a single shot during the photolithography process to form the first data output circuit (812). In the same way, exposure can be performed in a single shot during the photolithography process to form the second data output circuit (822).

[0086] Additionally, according to one embodiment, a first slave gamma circuit (921) is disposed between the first data processing circuit (811) and the first data output circuit (812), and accordingly, an auxiliary circuit (503) may be further disposed in the area between the first data processing circuit (811) and the first data output circuit (812). For example, the auxiliary circuit (503) may include at least one of a regulator capable of generating various power sources required for driving the display panel (100), a decoupling circuit connected to driving lines connected to subpixels (SP1, SP2, SP3) for noise reduction of the display panel (100), and a bias circuit for supplying power to the gamma circuit. In the same manner, an auxiliary circuit may be further disposed in the area between the second data processing circuit (821) and the second data output circuit (822).

[0087] Figure 5 is a detailed configuration diagram of the first data driving circuit of Figure 4.

[0088] The first data driving circuit may include a plurality of channel circuits (e.g., data channel circuits) (DCH1, DCH2, DCHn), as shown in FIG. 5.

[0089] Multiple channel circuits (DCH1, DCH2, DCHn) can output multiple data voltages (Vd1, Vd2, Vdn). For example, the first channel circuit (DCH1) can output a first data voltage (Vd1), the second channel circuit (DCH2) can output a second data voltage (Vd2), and the nth channel circuit (DCHn) can output an nth data voltage (Vdn). Here, n can be a natural number greater than 2.

[0090] Multiple channel circuits (DCH1, DCH2, DCHn) can be connected to multiple first data lines in a time-division manner through a first distribution circuit (710). For example, a first data voltage (Vd1) from the first channel circuit (DCH1), a second data voltage (Vd2) from the second channel circuit (DCH2), and an nth data voltage (Vdn) from the nth channel circuit (DCHn) can be provided to the first distribution circuit.

[0091] Each channel circuit (DCH1, DCH2, DCHn) may include the aforementioned first data processing circuit (811) and first data output circuit (812).

[0092] The first data processing circuit (811) may include a shift register (SHR; e.g., a data shift register), a sampling latch (SAL; e.g., a data sampling latch), and a holding latch (HOL; e.g., a data holding latch).

[0093] The first data output circuit (812) may include a level shifter (LVS; e.g., a data level shifter), a digital-to-analog converter (DAC; e.g., a data digital-to-analog converter), and a buffer (BUF; e.g., a data buffer). Here, the buffer (BUF) may be connected to the first data line through the first distribution circuit (710).

[0094] The shift register (SHR) receives a source shift clock and a source start pulse from the timing control circuit (400), and can sequentially generate multiple sampling signals while shifting the source start pulse for every one cycle of the source shift clock.

[0095] The sampling latch (SAL) can sequentially store a plurality of first digital image data signals in response to a plurality of sampling signals sequentially supplied from the shift register (SHR).

[0096] The holding latch (HOL) can receive and store a first digital image data signal from the sampling latch (SAL) in response to a source output enable signal, and can also output the sampled first digital image data signal that was stored during the previous period. The first digital image data signal output from the holding latch (HOL) can be provided to a digital-to-analog converter (DAC) through a level shifter (LVS).

[0097] A level shifter (LVS) can convert the level of a first digital image data signal from a holding latch (HOL) and provide it to a digital-to-analog converter (DAC). For example, the level shifter (LVS) can convert the level of the first digital image data signal so that the first digital image data signal has a level capable of driving the transistors of the digital-to-analog converter (DAC).

[0098] A digital-to-analog converter (DAC) can provide a first analog video signal corresponding to a bit value of a first digital video data signal supplied from a holding latch (HOL) through a level shifter (LVS). For example, the digital-to-analog converter (DAC) can select a grayscale voltage corresponding to a bit value of the first digital video data signal from the holding latch (HOL) from at least one of a master gamma circuit (910), a first slave gamma circuit (921), a second slave gamma circuit (922), and a third slave gamma circuit (923), and output the selected grayscale voltage as a first analog video signal.

[0099] For example, among the plurality of channel circuits (DCH1, DCH2, DCHn) of the first data driving circuit (810), the digital-to-analog converter (DAC) of the first channel circuit (DCH1) outputs a first analog video signal based on the grayscale voltages from the master gamma circuit (910), and among the plurality of channel circuits (DCH1, DCH2, DCHn) of the first data driving circuit (810), the digital-to-analog converter (DCA) of the second channel circuit (DCH2) outputs a first analog video signal based on the grayscale voltages from the first slave gamma circuit (921), and among the plurality of channel circuits (DCH1, DCH2, DCHn) of the first data driving circuit (810), the digital-to-analog converter of the third channel circuit outputs a first analog video signal based on the grayscale voltages from the second slave gamma circuit (922), and the plurality of channels of the first data driving circuit (810) The digital-to-analog converter of the fourth channel circuit among the circuits (DCH1, DCH2, DCHn) can output a first analog video signal based on the grayscale voltages from the third slave gamma circuit (923).

[0100] The buffer (BUF) receives a grayscale voltage (e.g., an analog video signal) from a digital-to-analog converter (DAC) and can amplify and output this grayscale voltage. For example, the buffer (BUF) can amplify the grayscale voltage and output a data voltage. The data voltage from the buffer (BUF) can be provided to the first data line (DL) through the first distribution circuit (710). The buffer (BUF) may include an amplifier.

[0101] The second data driving circuit (820) may have the same configuration as the first data driving circuit (810) described above. For example, the second data driving circuit (820) may include n channel circuits as shown in FIG. 5, a shift register provided in each channel circuit, a sampling latch provided in each channel circuit, a holding latch provided in each channel circuit, a level shifter provided in each channel circuit, a digital-to-analog converter provided in each channel circuit, and a buffer provided in each channel circuit. For a description of the shift register, sampling latch, holding latch, level shifter, digital-to-analog converter, and buffer of the second data driving circuit, refer to FIG. 5 and the related description described above.

[0102] At this time, the digital-to-analog converter of the second data driving circuit (820) can provide a second analog video signal corresponding to the bit value of the second digital video data signal supplied from the holding latch through a level shifter. For example, the digital-to-analog converter of the second data driving circuit (820) can select a grayscale voltage corresponding to the bit value of the second digital video data signal from the holding latch of the second data driving circuit (820) from at least one of the master gamma circuit (910), the fourth slave gamma circuit (924), the fifth slave gamma circuit (925), and the sixth slave gamma circuit (926), and output the selected grayscale voltage as the second analog video signal.

[0103] For example, among the plurality of channel circuits of the second data driving circuit (820), the digital-to-analog converter of the first channel circuit outputs a second analog video signal based on the grayscale voltages from the master gamma circuit (910), the digital-to-analog converter of the second channel circuit among the plurality of channel circuits of the second data driving circuit (820) outputs a second analog video signal based on the grayscale voltages from the fourth slave gamma circuit (924), the digital-to-analog converter of the third channel circuit among the plurality of channel circuits of the second data driving circuit (820) outputs a second analog video signal based on the grayscale voltages from the fifth slave gamma circuit (925), and the digital-to-analog converter of the fourth channel circuit among the plurality of channel circuits of the second data driving circuit (820) outputs a second analog video signal based on the grayscale voltages from the sixth slave gamma circuit (926).

[0104] The display device (10) according to the embodiment can be applied to various electronic devices. An electronic device according to one embodiment includes the display device (10) described above and may further include a module or device having other additional functions in addition to the display device (10).

[0105] FIG. 6 is a block diagram of an electronic device according to one embodiment.

[0106] Referring to FIG. 6, an electronic device (50) according to one embodiment may include a display module (11), a processor (12), a memory (13), and a power module (14). The electronic device (50) may further include an input module (14), a non-image output module (15) and / or a communication module (16).

[0107] The electronic device (50) can output various information in the form of images through the display module (11). When the processor (12) executes an application stored in memory (13), the image information provided by the application can be provided to the user through the display module (11). The power module (14) may include a power supply module, such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power necessary for the operation of the electronic device (50). The input module (14) can provide input information to the processor (12) and / or the display module (11). The non-image output module (15) can receive information other than images received from the processor (12), such as sound, haptics, light emission, etc., and provide this information to the user. The communication module (16) is a module responsible for the transmission and reception of information between the electronic device (50) and an external device, and may include a receiving unit and a transmitting unit.

[0108] At least one of each component of the electronic device (50) described above may be included in a display device according to the embodiments described above. Additionally, some of the individual modules functionally included in one module may be included in the display device, while others may be provided separately from the display device. For example, the display device may include a display module (11), and the processor (12), memory (13), and power module (14) may be provided in the form of other devices within the electronic device (50) that are not the display device.

[0109] FIGS. 7, FIGS. 8, and FIGS. 9 are schematic diagrams of electronic devices according to various embodiments. FIGS. 7 through 9 illustrate examples of various electronic devices to which a display device (10) according to embodiments is applied.

[0110] FIG. 7 illustrates examples of electronic devices, including a smartphone (10_1a), a tablet PC (10_1b), a laptop (10_1c), a TV (10_1d), and a desktop monitor (10_1e).

[0111] The smartphone (10_1a) may include an input module, such as a touch sensor, and a communication module in addition to the display module (11). The smartphone (10_1a) can process information received through the communication module or other input modules and display information through the display module of the display device.

[0112] In the case of a tablet PC (10_1b), laptop (10_1c), TV (10_1d), and desk monitor (10_1e), it also includes a display module and an input module similar to a smartphone (10_1a), and may additionally include a communication module depending on the case.

[0113] FIG. 8 illustrates a case where an electronic device including a display module is applied to a wearable electronic device. The wearable electronic device may be smart glasses (10_2a), a head-mounted display (10_2b), a smart watch (10_2c), etc.

[0114] Smart glasses (10_2a) and a head-mounted display (10_2b) may include a display module that emits a display image and a reflector that reflects the emitted display screen to provide it to the user's eyes, thereby providing a virtual reality or augmented reality screen to the user.

[0115] The smart watch (10_2c) includes a bio-sensor as an input device and can provide bio-information recognized through the bio-sensor to the user through a display module.

[0116] FIG. 9 illustrates a case where an electronic device including a display module is applied to a vehicle. For example, the electronic device (10_3) may be applied to the instrument panel, center fascia, etc. of a vehicle, or may be applied to a Center Information Display (CID) placed on the dashboard of a vehicle or a room mirror display that replaces a side mirror.

[0117] A person skilled in the art to which this specification pertains will understand that this specification may be implemented in other specific forms without altering its technical concept or essential features. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. The scope of this specification is defined by the claims set forth below rather than by the detailed description above, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts should be interpreted as being included within the scope of this specification.

[0118] Meanwhile, the present specification and drawings disclose preferred embodiments of the present specification. Although specific terms have been used, they are used only in a general sense to facilitate the explanation of the technical content of the present specification and to aid in understanding the invention, and are not intended to limit the scope of the present specification. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, other variations based on the technical concept of the present specification are possible. Explanation of the symbols

[0119] 100: Display panel 710: First distribution circuit 720: 2nd distribution circuit 810: First data driving circuit 820: 2nd data driving circuit 811: First data processing circuit 812: First data output circuit 821: 2nd data processing circuit 822: Second data output circuit 921: 1st slave gamma circuit 922: 2nd slave gamma circuit 923: 3rd slave gamma circuit 924: 4th slave gamma circuit 925: 5th slave gamma circuit 926: 6th Slave Gamma Circuit PDA: Pad part PD: pad 910: Master Gamma Circuit 900: Gamma circuit 800: Data drive unit 610: Scan drive unit 620: Light-emitting driving unit

Claims

Claim 1 A display panel including a display area and a non-display area; a first data driving circuit disposed in a non-display area on one side of the display area; a first distribution circuit disposed in a non-display area between the first data driving circuit and the display area; A display device comprising a gamma circuit that generates multiple grayscale voltages, wherein the first data driving circuit includes a first data processing circuit that processes first digital image data and a first data output circuit that converts the first digital image data from the first data processing circuit into a first analog image signal based on the multiple grayscale voltages from the gamma circuit and provides it to the first distribution circuit, wherein the first data output circuit is disposed in a non-display area between the first data processing circuit and the first distribution circuit, and the gamma circuit includes a master gamma circuit that generates a gamma reference voltage based on a reference voltage and divides the gamma reference voltage to generate multiple grayscale voltages, and a first slave gamma circuit that divides the gamma reference voltage from the master gamma circuit to generate multiple grayscale voltages, wherein the first slave gamma circuit is disposed in a non-display area between the first data processing circuit and the first data output circuit. Claim 2 A display device according to claim 1, wherein the gamma circuit further comprises a second slave gamma circuit and a third slave gamma circuit that divide the gamma reference voltage from the master gamma circuit to generate a plurality of grayscale voltages. Claim 3 In claim 2, the second slave gamma circuit is a display device placed in a non-display area adjacent to one edge of the first data output circuit. Claim 4 In claim 3, the third slave gamma circuit is a display device placed in a non-display area adjacent to the other edge of the first data output circuit. Claim 5 In claim 4, the first data output circuit is a display device placed in a non-display area between the second slave gamma circuit and the second slave gamma circuit. Claim 6 A display device according to claim 5, wherein the length of the first slave gamma circuit is smaller than the length of the second slave gamma circuit, and the width of the first slave gamma circuit is larger than the width of the second slave gamma circuit. Claim 7 A display device according to claim 6, wherein the area of ​​the first slave gamma circuit, the area of ​​the second slave gamma circuit, and the area of ​​the third slave gamma circuit are the same. Claim 8 A display device according to claim 5, further comprising an auxiliary circuit disposed in a non-display area between the first data processing circuit and the first data output circuit. Claim 9 A display device according to claim 1, further comprising: a second data driving circuit disposed in a non-display area on the other side of the display area; and a second distribution circuit disposed in a non-display area between the second data driving circuit and the display area. Claim 10 A display device according to claim 9, wherein the second data driving circuit comprises: a second data processing circuit for processing second digital image data; and a second data output circuit for converting the second digital image data from the second data processing circuit into a second analog image signal based on a plurality of grayscale voltages from the gamma circuit and providing it to the second distribution circuit. Claim 11 In claim 10, the second data output circuit is a display device placed in a non-display area between the second data processing circuit and the second distribution circuit. Claim 12 A display device according to claim 11, wherein the gamma circuit further comprises a fourth slave gamma circuit that divides the gamma reference voltage from the master gamma circuit to generate a plurality of grayscale voltages. Claim 13 In claim 12, the fourth slave gamma circuit is a display device placed in a non-display area between the second data processing circuit and the second data output circuit. Claim 14 In claim 13, the display device further comprises a fifth slave gamma circuit and a sixth slave gamma circuit that divide the gamma reference voltage from the master gamma circuit to generate a plurality of grayscale voltages. Claim 15 In claim 14, the fifth slave gamma circuit is a display device placed in a non-display area adjacent to one edge of the second data output circuit. Claim 16 In claim 15, the sixth slave gamma circuit is a display device placed in a non-display area adjacent to the other edge of the second data output circuit. Claim 17 In claim 16, the second data output circuit is a display device placed in a non-display area between the fifth slave gamma circuit and the sixth slave gamma circuit. Claim 18 A display device according to claim 17, wherein the length of the fourth slave gamma circuit is smaller than the length of the fifth slave gamma circuit, and the width of the fourth slave gamma circuit is larger than the width of the fifth slave gamma circuit. Claim 19 A display device including a screen, wherein the display device comprises: a display panel including a display area and a non-display area; a first data driving circuit disposed in a non-display area on one side of the display area; and a first distribution circuit disposed in a non-display area between the first data driving circuit and the display area. An electronic device comprising a gamma circuit that generates multiple grayscale voltages, wherein the first data driving circuit includes a first data processing circuit that processes first digital image data and a first data output circuit that converts the first digital image data from the first data processing circuit into a first analog image signal based on the multiple grayscale voltages from the gamma circuit and provides it to the first distribution circuit, wherein the first data output circuit is disposed in a non-display area between the first data processing circuit and the first distribution circuit, and the gamma circuit includes a master gamma circuit that generates a gamma reference voltage based on a reference voltage and divides the gamma reference voltage to generate multiple grayscale voltages, and a first slave gamma circuit that divides the gamma reference voltage from the master gamma circuit to generate multiple grayscale voltages, wherein the first slave gamma circuit is disposed in a non-display area between the first data processing circuit and the first data output circuit. Claim 20 In claim 19, the electronic device comprises a smartphone, tablet, laptop, TV, desk monitor, smart glasses, smart watch, head-mounted display, and vehicle.

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