Post thermal annealing method for SiO2 thin films fabricated through plasma enhanced chemical vapor deposition, and SiO2 thin films therefrom

Abstract

The present invention relates to a post-heat treatment method for a silicon dioxide thin film prepared by plasma-enhanced chemical vapor deposition and a silicon dioxide thin film produced thereby. According to the present invention, when a silicon dioxide (SiO2) thin film prepared by a plasma-enhanced chemical vapor deposition (PECVD) process is post-heat treated under specific conditions, a silicon dioxide thin film with improved dielectric properties can be provided. Furthermore, an IGZO thin-film transistor utilizing the obtained silicon dioxide thin film exhibits excellent electrical characteristics and excellent stability, such as low off-current, a large on / off ratio, a low sub-threshold swing, high field-effect mobility, and a threshold voltage close to 0 V.

Description

Technology Field

[0001] The present invention relates to a post-heat treatment method for a silicon dioxide thin film prepared by plasma-enhanced chemical vapor deposition and a silicon dioxide thin film produced according to the same. Background Technology

[0002] Silicon dioxide (SiO2) thin films are widely used in the semiconductor industry for memory devices, displays, logic circuits, and more. Plasma-enhanced chemical vapor deposition (PECVD), a common method used for manufacturing SiO2 thin films, offers advantages such as ease of control, high reproducibility, and a low thermal budget. PECVD not only enables high deposition rates and low process temperatures but also prevents defect formation and dopant diffusion, thereby producing high-quality thin films with significant technical advantages.

[0003] Meanwhile, dielectric properties are a key parameter of Si-based devices that determines device performance indicators such as leakage current density, charge density, and interface characteristics. Various strategies, including post-heat treatment, low-temperature sintering, and calcination, have been used to improve the dielectric properties of SiO2 thin films. These methods can improve structural properties by reducing defect states and densifying the dielectric film.

[0004] In particular, post-heat treatment is a simple and effective method to restore the intrinsic dielectric properties of SiO2 thin films, which can be affected by unintended physical / chemical interactions during the manufacturing process. High-quality SiO2 thin films can be formed by strengthening the Si-O bond structure through the release of trapped charges at the interface. Meanwhile, gate dielectric thin films play a crucial role in device performance and charge transfer because they come into direct contact with the active channel and influence interface properties.

[0005] In this invention, high-quality SiO2 thin films were demonstrated via PECVD, and the effect of annealing after heat treatment on the dielectric properties of the SiO2 thin films was investigated through JE and CV analysis at various processing temperatures and atmospheres. The mechanism of the improvement in dielectric properties induced by annealing after heat treatment was investigated through compositional analysis of the Si-O bonding state of the thin film. Subsequently, IGZO TFTs with SiO2 insulating films were fabricated, and the effect of the improved interface properties on device performance and electrical stability was investigated. Finally, the effect of the improved dielectric properties of the SiO2 thin film was confirmed by analyzing the charge transfer characteristics of the device through temperature-dependent field-effect mobility (μ) measurements. The problem to be solved

[0006] The present invention provides a silicon dioxide (SiO2) thin film with improved dielectric properties and a method for manufacturing the same by post-heat treating a silicon dioxide (SiO2) thin film prepared according to a plasma chemical vapor deposition (PECVD) process under specific conditions, and by utilizing the silicon dioxide thin film in the manufacture of an IGZO thin film transistor, the invention aims to provide an IGZO thin film transistor that exhibits excellent electrical properties and excellent stability, such as low off-current, a large on / off ratio, a low sub-threshold swing, high field-effect mobility, and a threshold voltage close to 0 V.

[0007] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0008] The present specification provides a method for post-heat treatment of a SiO2 thin film, comprising: a) performing post-heat treatment of the silicon dioxide (SiO2) thin film one or more times in a vacuum chamber; and b) washing the silicon dioxide thin film obtained in step a and removing surface residues by UV-ozone treatment.

[0009] For example, the silicon dioxide (SiO2) thin film of step a above may be prepared by plasma-enhanced chemical vapor deposition (PECVD) using one or more of silane (SiH4), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), and hydrogen (H2) as reactant precursors.

[0010] For example, the post-heat treatment of step a above may be performed one or more times under conditions in a temperature range of 200 to 400 ℃.

[0011] For example, the post-heat treatment of step a above may be performed for 1 hour in a temperature range of 200 to 400 ℃ and under a 99% nitrogen (N2) atmosphere or for 1 hour in the above temperature range and under a 99% oxygen (O2) atmosphere.

[0012] For example, the washing in step b above may be performed by washing with acetone and isopropyl alcohol for 10 minutes each.

[0013] For example, the UV-ozone treatment of step b above may be performed for 20 to 40 minutes.

[0014] In addition, the present specification describes a SiO2 thin film post-heat treated according to the above method, wherein the SiO2 thin film may have improved dielectric properties by reducing charge impurities and mitigating defects due to the post-heat treatment.

[0015] For example, the above SiO2 thin film may have a reduced RMS (root mean square) value of surface roughness compared to before post-heat treatment.

[0016] In addition, the present specification provides a method for manufacturing an IGZO thin film transistor, comprising: c) a step of preparing the SiO2 thin film; d) a step of depositing an IGZO thin film by performing high-frequency magnetron sputtering using an IGZO target on the SiO2 thin film under a temperature condition of 20 to 25 ℃; and e) a step of forming Al source / drain electrodes by electron beam deposition after performing patterning on the IGZO thin film through wet etching.

[0017] In addition, the present specification provides an IGZO thin film transistor manufactured according to the above method, wherein the thickness of the SiO2 thin film in the thin film transistor is in the range of 70 to 90 nm, the thickness of the IGZO thin film is in the range of 8 to 12 nm, and the thickness of the Al source / drain electrode is in the range of 70 to 80 nm.

[0018] For example, the thin-film transistor is 3 to 7.5 cm 2 V -1 s -1 Temperature-dependent field-effect mobility (μ) in the range, threshold voltage (V) in the range of -7 to -1 V. th ), 1 X 10 3 Up to 1 x 10 8 On / off ratio in the range and 0.4 to 1.23 Vdec -1 It may represent the sub-threshold swing (SS) of the range.

[0019] For example, the thin-film transistor above has a threshold voltage (Threshold Voltage, V) in the PBS test and NBS test, respectively. th The movement may stabilize within 7.2 V. Effects of the invention

[0020] According to the present invention, when a silicon dioxide (SiO2) thin film prepared by a plasma chemical vapor deposition (PECVD) process is subjected to post-heat treatment under specific conditions, a silicon dioxide thin film with improved dielectric properties can be provided.

[0021] In addition, the IGZO thin-film transistor utilizing the silicon dioxide thin film obtained above exhibits excellent electrical characteristics and excellent stability, such as low off-current, large on / off ratio, low sub-threshold swing, high field-effect mobility, and a threshold voltage close to 0 V. Brief explanation of the drawing

[0022] Figure 1 shows optical images of a silicon dioxide thin film deposited on a 4-inch wafer according to an embodiment of the present invention. Figure 2 shows a schematic diagram of fabricating an IGZO-TFT using a silicon dioxide thin film according to an embodiment of the present invention. Figure 3 shows (a) JE and (b) CV characteristics of a PECVD-based SiO2 thin film deposited using N2O or NO gas according to an embodiment of the present invention, (c) JE and (d) CV characteristics of a PECVD-based SiO2 thin film annealed at 300 °C in various atmospheres, and (e) JE and (f) CV characteristics of a PECVD-based SiO2 thin film annealed at temperatures of 200, 300, and 400 °C. FIG. 4 shows (a) FT-IR spectrum, (b), (c) O1s and Si2p spectra, and (d), (e) AFM images of a NO-based SiO2 thin film upon deposition and N2 annealing according to an embodiment of the present invention. FIG. 5 shows, according to an embodiment of the present invention, (a) a transfer curve of an IGZO TFT using a PECVD-based SiO2 insulating film based on N2O or NO gas, (b) a transfer curve of an IGZO TFT using a substitute gas-based SiO2 dielectric film before and after N2 annealing, (c) log(on / off current ratio), (d) field-effect mobility in the linear region, and (e) V th and (f) SS, and the above statistical distribution was obtained from 15 IGZO-TFTs in which NO-based SiO2 insulating films were deposited and N2 annealed. FIG. 6 shows, according to an embodiment of the present invention, (a) an Arrhenius plot according to measurement temperature (90-300 K), (b) activation energy according to gate voltage of an IGZO TFT with a deposited NO-based SiO2 insulating film and N2 annealed, (c) DOS as a function of energy below the conduction band, and (d) interface trap density (D) of an IGZO TFT with a deposited NO-based SiO2 insulating film and N2 annealed. it It represents a comparison. FIG. 7 shows, according to an embodiment of the present invention, (a) transfer characteristics of an IGZO TFT using an NO-based SiO2 insulating film before N2 annealing as a function of stress time during PBS and (b) NBS, (c) transfer characteristics after N2 annealing according to stress time during PBS and (d) NBS, (e) ΔV of deposition and N2 annealing according to stress time for PBS and (f) NBS. th This represents a comparison. Specific details for implementing the invention

[0023] Hereinafter, embodiments of the present invention are described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. However, the present invention may be embodied in various different forms and is not limited to the embodiments disclosed below. Furthermore, in order to clearly disclose the present invention in the drawings, parts unrelated to the present invention have been omitted, and identical or similar reference numerals in the drawings indicate identical or similar components.

[0024] The purpose and effects of the present invention may be naturally understood or become clearer from the following description, and the purpose and effects of the present invention are not limited to the description below alone.

[0025] The objectives, features, and advantages of the present invention will become clearer through the following detailed description. Furthermore, in describing the present invention, if it is determined that a detailed description of known technology related to the present invention may unnecessarily obscure the essence of the invention, such detailed description will be omitted. Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

[0027] Today, silicon dioxide thin films are widely used in the semiconductor industry for memory devices, displays, and logic circuits. Plasma-Enhanced Chemical Vapor Deposition (PECVD), a common method used for silicon dioxide thin films, is a technology capable of producing high-quality films with significant technical advantages by enabling high deposition rates and low process temperatures, as well as preventing defect formation and dopant diffusion.

[0028] Meanwhile, the inventors confirmed through experiments that the dielectric properties of a silicon dioxide (SiO2) thin film prepared in a plasma-enhanced chemical vapor deposition (PECVD) process are improved when subjected to post-heat treatment under specific conditions, and that excellent electrical properties and stability can be secured when applied to an IGZO thin-film transistor, thereby completing the present invention.

[0030] Hereinafter, a post-heat treatment method for a silicon dioxide thin film prepared by plasma-enhanced chemical vapor deposition according to the present invention and a silicon dioxide thin film produced thereby will be described in more detail.

[0032] Post-heat treatment method for silicon dioxide thin films and SiO₂ for thin-film transistors 2 pellicle

[0033] A post-heat treatment method for a SiO2 thin film according to one embodiment of the present invention may include: a) a step of performing post-heat treatment on a silicon dioxide (SiO2) thin film one or more times in a vacuum chamber; and b) a step of washing the silicon dioxide thin film obtained in step a and removing surface residues by UV-ozone treatment.

[0035] First, a silicon dioxide (SiO2) thin film is subjected to post-heat treatment one or more times in a vacuum chamber (step a).

[0036] The silicon dioxide (SiO2) thin film in this step may be grown by plasma-enhanced chemical vapor deposition (PECVD). Specifically, silicon dioxide thin films are widely used in the semiconductor industry, such as memory devices, displays, and logic circuits, and may be manufactured by the PECVD method using one or more precursors selected from silane (SiH4), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), and hydrogen (H2). On the other hand, the silicon dioxide thin film used in the present invention may be manufactured using nitrous oxide (N2O) or nitric oxide (NO), in which case the growth rate of the silicon dioxide (SiO2) thin film can be increased while reducing the possibility of carbon contamination due to high reactivity and oxidation characteristics.

[0037] In detail, the silicon dioxide (SiO2) thin film of step a above can be grown by plasma-enhanced chemical vapor deposition (PECVD) using one or more of silane (SiH4), nitrous oxide (NO2), nitric oxide (NO), and hydrogen (H2) as reactant precursors. In addition, the PECVD process can be performed with a chamber internal pressure in the range of 0.3 to 0.4 Torr, a deposition temperature in the range of 220 to 280 °C, a frequency of 13.56 MHz, and an output of 100 W, and in detail, it can be performed by setting the chamber internal pressure to 0.38 Torr and the deposition temperature to 250 °C.

[0038] Meanwhile, post-thermal annealing is performed to improve the dielectric properties of silicon dioxide thin films produced through the PECVD process, and can be performed one or more times, specifically two times, in a vacuum chamber. Meanwhile, the post-thermal annealing process can be performed in the chamber after the aforementioned PECVD process without any additional equipment, which is advantageous in terms of economic efficiency.

[0039] Specifically, the post-heat treatment can be performed for 1 hour in a vacuum chamber at a temperature range of 200 to 400 ℃, specifically at a temperature of 300 ℃ under a 99% nitrogen (N2) atmosphere, or for 1 hour in the above temperature range under a 99% oxygen (O2) atmosphere. When the post-heat treatment is performed under the above temperature range and atmosphere conditions, the dielectric properties of the silicon dioxide thin film can be further improved, and since the heat treatment is performed under relatively low temperature conditions, the cost is low and the process is simple, thereby ensuring economic feasibility.

[0041] Next, the silicon dioxide thin film obtained in step a is washed and UV-ozone treated to remove surface residue (step b).

[0042] The above steps correspond to a process for improving device performance by removing impurities from the surface of a silicon dioxide thin film, and specifically, the cleaning can be performed by washing with acetone and isopropyl alcohol for 10 minutes each, and then UV-ozone treatment to remove surface residues can be performed for 20 to 40 minutes, specifically for 30 minutes.

[0044] The SiO2 thin film for a thin film transistor according to an embodiment of the present invention, which is post-heat treated according to the method described above, may have improved dielectric properties that determine device performance indicators such as leakage current density, charge density, and interface characteristics, as charge impurities are reduced and defects are mitigated due to the post-heat treatment. In addition, the root mean square (RMS) value of the surface roughness of the SiO2 thin film may be reduced compared to before the post-heat treatment.

[0046] IGZO thin film transistor and method for manufacturing the same

[0047] Meanwhile, a method for manufacturing an IGZO thin film transistor according to another embodiment of the present invention may include: c) a step of preparing the SiO2 thin film; d) a step of depositing an IGZO thin film by performing high-frequency magnetron sputtering using an IGZO target on the SiO2 thin film under a temperature condition of 20 to 25 ℃; and e) a step of forming Al source / drain electrodes by electron beam deposition after performing patterning on the IGZO thin film through wet etching.

[0049] First, prepare a thin SiO2 film (step c).

[0050] The above SiO2 thin film may be prepared by growing it by plasma-enhanced chemical vapor deposition (PECVD) using one or more of silane (SiH4), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), and hydrogen (H2) as reactant precursors, followed by the post-heat treatment described above, and the specific manufacturing method is as described above. Meanwhile, the thickness of the prepared SiO2 thin film may be in the range of 70 to 90 nm, specifically 80 nm.

[0052] Next, an IGZO thin film is deposited by performing high-frequency magnetron sputtering using an IGZO target on the SiO2 thin film under temperature conditions of 20 to 25 ℃ (step d).

[0053] The above step can be performed by depositing an IGZO thin film by performing high-frequency magnetron sputtering using an IGZO target on the SiO2 thin film under room temperature conditions, specifically under temperature conditions of 20 to 25 ℃, and specifically, the IGZO target may be a target of In : Ga : Zn = 1 : 1 : 1, and the thickness of the IGZO thin film deposited through the above process may be in the range of 8 to 12 nm, specifically 10 nm.

[0055] Next, patterning of the IGZO thin film is performed through wet etching, and then Al source / drain electrodes are formed by electron beam deposition (step e).

[0056] The above step is performed to pattern the IGZO thin film according to a pre-designed shape and then to form Al source / drain electrodes using an electron beam method, and specifically, the thickness of the Al source / drain electrodes deposited in the above step may be in the range of 70 to 80 nm, specifically 75 nm.

[0058] An IGZO thin-film transistor according to one embodiment of the present invention manufactured according to the method described above is 3 to 7.5 cm 2 V -1 s -1 Temperature-dependent field-effect mobility (μ) in the range, specifically 4.3 cm 2 V -1 s -1 Temperature-dependent field-effect mobility (μ), threshold voltage in the range of -7 to -1 V (V th ), more specifically, a threshold voltage of -5V (V th ), 1 X 10 3 Up to 1 x 10 8 The on / off ratio of the range, specifically 3 x 10 6 The on / off ratio and 0.4 to 1.23 Vdec -1 The sub-threshold swing (SS) of the range, specifically 1.23 Vdec -1 It can represent the sub-threshold swing (SS).

[0059] In addition, the thin-film transistor has a threshold voltage (Threshold Voltage, V) at each of the PBS test and NBS test. th The movement can be stabilized within 7.2 V.

[0061] Examples

[0062] The present invention is capable of various modifications and may take various forms, and specific embodiments are illustrated and described in detail below. However, this is not intended to limit the invention to the specific disclosed forms, and it should be understood that the invention includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0064] Preparation Examples 1 and 2 (SiO 2 Post-heat treatment of thin films)

[0065] The highly doped p-type substrate was washed with 10% hydrofluoric acid and then dried with N2 gas. Next, the chamber internal pressure was set to 0.38 Torr and the deposition temperature to 250 °C, and a PECVD process was performed at a frequency of 13.56 MHz and an output of 100 W, wherein SiH4, N2O (Preparation Example 1), NO (Preparation Example 2), and H2 were used as reactant precursors in combination, respectively.

[0066] Next, the SiO2 thin film prepared by the above method was post-heat treated in a vacuum chamber at 200 to 400 °C in an atmosphere of 99% nitrogen (N2) and 99% oxygen (O2) for 1 hour each.

[0067] Next, the fabricated silicon dioxide (SiO2) thin film was washed with acetone and isopropyl alcohol for 10 minutes each, and surface residues were removed by UV-ozone treatment for 30 minutes (see Fig. 1).

[0069] Example 1

[0070] A SiO2 thin film obtained from the above preparation example was prepared, and a 10 nm thick IGZO thin film was deposited on an 80 nm thick SiO2 thin film by high-frequency magnetron sputtering using an IGZO (In : Ga : Zn = 1 : 1 : 1) target under room temperature conditions. Next, IGZO channel patterning was performed by wet etching, and then 75 nm thick Al source / drain electrodes were formed by electron beam deposition to complete the IGZO thin film transistor (see Fig. 2).

[0072] [Experiment 1: SiO 2 [Verification of Electrical Properties of Thin Films]

[0073] Figures 3 (a) and (b) show the electrical characteristics of N2O and NO-based SiO2 thin films, respectively. According to JE measurements, the deposited N2O and NO-based SiO2 thin films were 1.18 x 10⁻¹⁰, respectively. -11 and 6 x 10 -11 A cm -2 It exhibited current densities of . In addition, the deposited N2O and NO-based SiO2 thin films showed current densities of 38 and 42 nF cm⁻¹, respectively, in CV measurements. -2 The capacitance was shown. Relatively high leakage current density and capacitance were obtained when N2O was replaced with NO during the fabrication of PECVD-based SiO2 thin films. For alternative gas-based SiO2 thin films to be practically applied in industry, they must have electrical properties similar to or better than those of existing gas-based SiO2 thin films. Therefore, post-heat treatment was performed under various process conditions to improve the dielectric properties of the proposed SiO2 thin film.

[0074] As can be seen in Fig. 3 (c), the annealed SiO2 thin film has a lower value of 1.5 × 10⁻¹⁰ than the deposited thin film. -12 A cm -2The leakage current was shown. Based on the JE curve, we confirmed that the current of the PECVD-based SiO2 thin film was significantly suppressed in a similar manner regardless of the annealing atmosphere. These results are due to the reduction of charge impurities that can affect the dielectric quality of the SiO2 thin film after thermal annealing.

[0075] Figure 3 (d) shows the CV characteristics of SiO2 thin films fabricated after thermal annealing in various atmospheres. Unlike the JE curve, the CV characteristics of the thin film were affected by the heat treatment atmosphere. The capacitance of the PECVD-based SiO2 thin film after N2 annealing was 37.7 nF cm⁻¹. -2 The decrease confirmed that thermal annealing in an N2 atmosphere provides the greatest recovery compatible with the recovery of thermally grown SiO2 thin films.

[0076] Figure 3 (e) shows the optimal annealing temperature in an N2 atmosphere. As a result of thermal annealing at 200 °C, the leakage current density was lower than before annealing but higher than that obtained at 300 °C and 400 °C. Similar currents were obtained when the thin film was annealed at 300 °C and 400 °C. These results indicate that the effect of N2 annealing on JE characteristics is limited at 400 °C.

[0077] As shown in Fig. 3 (f), thermal annealing at 200 °C yields a higher capacitance (39.3 nF cm) than that obtained at 300 °C and 400 °C. -2 ...was able to obtain ). It is highly likely that similar capacitance values ​​were obtained when the thin film was annealed at 300 ℃ and 400 ℃. These results indicate that the improvement in the dielectric properties of the thin film saturates after 300 ℃. Based on these results, 300 ℃ was selected as the optimal temperature for post-thermal annealing in an N2 atmosphere.

[0079] [Experiment 2: SiO 2 [Investigation of Mechanism for Improving Dielectric Properties of Thin Films]

[0080] We investigated the mechanism by which the dielectric properties of PECVD-based SiO2 thin films are improved after N2 annealing. Figure 4 (a) shows the FTIR profiles of NO-based SiO2 thin films before and after N2 annealing. The peak associated with the asymmetric stretching vibration of Si-O-Si bonds is at 1060 cm⁻¹. -1 It was observed, and its strength increased after N2 annealing. These results indicate an increase in the amount or strength of Si-O bonds as well as the Si-O bond angle after thermal annealing. Furthermore, surface diffusion induced by N2 annealing generates tensile stress in the SiO2 thin film, thereby relieving compressive stress and reducing the formation of micropores. The subsequent rearrangement of trapped charges affects the dielectric properties of NO-based SiO2 thin films.

[0081] Figure 4 (b) shows the O1s spectrum of the proposed SiO2 thin film before and after N2 annealing. Before annealing, the Si-O-Si peak was observed at 532.88 eV. After N2 annealing, the binding energy of this peak shifted to 532.43 eV and the intensity increased accordingly, confirming the rearrangement of trapped charges in the NO-based SiO2 thin film. It is estimated that annealing after heat treatment in an N2 atmosphere can effectively relax defect states (or remove charge impurities) and restore the intrinsic dielectric properties of the NO-based SiO2 thin film.

[0082] Figure 4 (c) shows the Si2p spectrum of the prepared SiO2 thin film. Here, Si is the Si oxidation state. 4+Only a single chemical structure decomposing into was observed. This peak was observed at 103.73 eV before N2 annealing and shifted to 103.38 eV as the intensity increased after N2 annealing. Additionally, the full width at half maximum (FWHM) decreased from 1.98 to 1.60 eV, indicating that a dense and complete surface morphology was formed after N2 annealing. The Si2p binding energy associated with SiO2 is known to vary depending on the oxygen composition. Generally, stoichiometric SiO2 films, characterized by Si atoms surrounded by four O atoms, exhibit a binding energy of 103.3 eV. The peak observed at 103.38 eV confirms that the intrinsic material properties of the NO-based SiO2 film were restored after optimal thermal annealing.

[0083] Figures 4 (d) and (e) show the AFM results of the SiO2 thin film before and after annealing, respectively. The RMS (root mean square) values ​​of surface roughness were 0.583 and 0.443 nm, respectively, and decreased after annealing. This is a result of the decomposition of defect states due to the surface diffusion of atoms caused by thermal energy during the annealing process.

[0085] [Experiment 3: Verification of IGZO TFT Transfer Characteristics]

[0086] Figure 5 (a) shows the transfer characteristics of IGZO TFTs fabricated from N2O and NO-based SiO2 dielectric thin films. The IGZO TFT fabricated from the NO-based SiO2 thin film is 4.3 cm 2 V -1 s -1 μ, -5V threshold voltage (V th ), 3 X 10 6 The on / off ratio and 1.23 Vdec -1 It exhibited a sub-threshold swing (SS). In contrast, the IGZO TFT fabricated with an N2O-based SiO2 thin film showed 6.8 cm. 2 V -1 s -1 μ of, V of -3V th, 1.58 X 10 8 The on / off ratio of, and 0.49 Vdec -1 The SS of was represented. These values ​​indicate that using conventional gas-based SiO2 dielectric films is advantageous for improving the device performance of IGZO TFTs. In particular, V in IGZO TFTs fabricated with alternative gas-based SiO2 dielectric thin films th The shift to negative, and the off-current and SS were relatively high.

[0087] Figure 5 (b) compares the transfer characteristics of an IGZO TFT fabricated with an NO-based SiO2 insulating film annealed at 300 °C in an N2 atmosphere and a TFT fabricated with a deposited NO-based SiO2 dielectric film. In this study, post-thermal treatment was performed on the gate dielectric layer prior to IGZO sputtering to maintain the material properties of the channel thin film, and the effect of the enhanced dielectric properties of the NO-based SiO2 thin film on the device performance of the IGZO TFT was compared and analyzed. In the IGZO TFT fabricated with the NO-based SiO2 thin film with enhanced dielectric properties, the interface characteristics between the gate dielectric and the channel layer were improved, resulting in the off-state current, V th The on / off ratio was significantly improved. It is estimated that the reduction in defect states of the gate dielectric thin film or the improvement in interface characteristics suppresses leakage current and significantly improves SS, thereby enhancing IGZO TFT performance.

[0088] To further investigate the reliability of the proposed method, key parameters on / off ratio, μ, and V were obtained from 15 IGZO TFTs fabricated with different batches of deposited and N2-annealed SiO2 thin films at different times. th and SS were analyzed.

[0089] As can be seen in Figs. 5 (c) to (f), the average on / off ratio is 4.4, 4.1 cm 2 V -1 s -1μ of, V of -5.3 V th , 1.0 Vdec -1 SS was observed in IGZO TFTs fabricated from NO-based SiO2 insulating films deposited thereon. In contrast, an average on / off ratio of 6.4 and 6.1 cm⁻¹ were observed. 2 V -1 s -1 μ of, V of -1.8 V th and 0.7 Vdec -1 SS of was observed in IGZO TFTs fabricated from N2-annealed NO-based SiO2 dielectric thin films. These results indicate that the performance of the IGZO TFTs was significantly enhanced by a chemically clean interface and suppressed defect states between the gate dielectric and channel thin films. Thermal annealing affects the trapped charge density and the interface trap density (D it By reducing ), charge transfer was effectively promoted, and high-performance IGZO TFTs were realized. Thus, the N2-annealed SiO2 dielectric film showed excellent potential to replace existing gas-based SiO2 thin films due to improved interface characteristics and charge transport characteristics, thereby enabling similar or higher device performance in IGZO TFTs.

[0091] [Experiment 4: Investigation of the Effect of Enhanced Dielectric Properties on IGZO TFT Charge Transfer Characteristics]

[0092] We performed temperature-dependent μ measurements to investigate the effect of enhanced dielectric properties on the charge transfer characteristics of IGZO TFTs. Figure 6 (a) shows the Arrhenius plots of IGZO TFTs fabricated with NO-based SiO2 insulating films with or without N2 annealing at measurement temperatures ranging from 90 to 300 K. An increase in μ was observed as the measurement temperature increased, indicating that thermally activated transport is dominant in IGZO TFTs.

[0093] Fig. 6 (b) shows the activation energy (E) determined from the slope of the Arrhenius plot for the thermally activated μ according to Equation 1. a Shows ).

[0095] (Equation 1)

[0097] Here, k is the Boltzmann constant and T is the temperature. E a represents the minimum energy required for charge carriers to move through defect states to a transition level. The Fermi level decreased as it shifted toward the band edge as the applied gate voltage increased. Of the IGZO TFT fabricated from the deposited SiO2 insulating film E a was measured at 47.6 meV, and the IGZO TFT fabricated from an N2-annealed SiO2 insulating film E a It was measured at 38.1 meV. Low E a indicates that the Fermi level has shifted significantly to the edge of the non-local band, resulting in improved charge transition. To further investigate the effect of the improvement in dielectric properties on device performance, as shown in Equation 2 below E a The DOS of the IGZO TFT was determined using [this].

[0099] (Equation 2)

[0101] Here N(E) is the bandgap DOS and d ε is the effective thickness of the deposited layer. As can be seen in Fig. 6 (c), the DOS of the IGZO TFT increased exponentially in the conduction band. Most charge carriers in the IGZO TFT are in the tail state, and a small number of charges can move to the transition energy level. Therefore, the shift in the Fermi level is determined by the distribution of the tail state, which has an exponential energy distribution. The DOS of the IGZO TFT fabricated from the deposited SiO2 insulating film ranged from 47.6 to 117.0 meV (9.32 × 10⁻¹⁰) below the conduction band. 18 - 6.41 X 10 19 eV -1 cm -3The range was ), and the IGZO TFT fabricated from N2-annealed SiO2 insulating film was 38.0 ~ 107.8 meV (5.33 Х 10⁻⁶ 18 - 3.17 X 10 19 eV -1 cm -3 The range was ). A relatively low DOS was achieved in IGZO TFTs fabricated from NO-based SiO2 insulating films annealed at 300°C in an N2 atmosphere, which indicates that enhanced dielectric or interfacial properties can affect the topological properties of a disordered system and thus affect charge transfer properties.

[0102] Fig. 6 (d) shows an IGZO TFT fabricated on a NO-based SiO2 insulating film regardless of N2 annealing. D it Shows the value. This characteristic is an essential factor in identifying the interface characteristics between the channel and the dielectric layer. D it was determined from the SS of the thin film using the following Equation 3.

[0104] (Equation 3)

[0106] IGZO TFT fabricated from deposited SiO2 dielectric thin films D it is 4.62 X 10 12 cm -2 eV -1 It was determined, and the IGZO TFT fabricated from the N2-annealed SiO2 dielectric thin film is 1.59 x 10 12 cm -2 eV -1 It was decided as. D it The reduction in [variable] is consistent with the improvement in interface characteristics between the IGZO channel and the NO-based SiO2 insulating film by N2 annealing, supporting the improvement in device performance and charge transfer characteristics.

[0108] [Experiment 5: Verification of the effect of improved interface characteristics on device stability]

[0109] To verify the effect of improved interface characteristics on device stability, positive bias stress (PBS) and negative bias stress (NBS) tests were performed to investigate the effect of N2 annealing on the electrical stability of IGZO TFTs fabricated with NO-based SiO2 insulating films.

[0110] Figures 7 (a) and (b) show the transfer characteristics of IGZO TFTs fabricated with deposited NO-based SiO2 insulating films after applying PBS and NBS for 20,000 seconds, respectively. V th It shifted positively under PBS and negatively under NBS. Generally, under PBS, V th The positive shift of is attributed to charge trapping at the interface between the channel and the dielectric layer or charge injection into the gate dielectric layer. On the other hand, V under NBS th The negative shift of is attributed to charge trapping at the interface or oxygen vacancies acting as shallow donor states.

[0111] Figures 7 (c) and (d) show the respective transfer characteristics of IGZO TFTs fabricated from NO-based SiO2 dielectric thin films annealed in N2 for 20,000 seconds in PBS and NBS. The IGZO TFTs exhibit relatively small ΔV in both PBS and NBS. th It showed [this], which can be attributed to the suppression of charge trapping due to the recovery of the intrinsic dielectric properties of the PECVD-based SiO2 thin film. V of approximately 13.3 V was observed in the IGZO TFT fabricated with the NO-based SiO2 dielectric thin film deposited after the PBS test. th Although migration was observed, when the device was fabricated with an N2-annealed NO-based SiO2 dielectric thin film, V of 6.0 V th Movement was achieved (Fig. 7 (e)).

[0112] In addition, V in IGZO TFTs fabricated with NO-based SiO2 insulating films deposited after NBS testing thWhile it shifted negatively to -7.2 V, in the device fabricated with an N2-annealed NO-based SiO2 insulating film, V was -3 V. th Only movement was observed (Fig. 7 (f)). V under prolonged electrical bias stress th The instability of movement was significantly suppressed in IGZO TFTs fabricated from N2-annealed NO-based SiO2 thin films. This improvement in electrical stability indicates that the interfacial properties were enhanced in IGZO TFTs using PECVD-based SiO2 thin films, where the trap state for charge capture was effectively reduced by N2 annealing, thereby improving dielectric properties.

[0114] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by these embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

Claims

Claim 1 a) a step of performing post-heat treatment on a silicon dioxide (SiO2) thin film one or more times in a vacuum chamber; and b) a step of washing the silicon dioxide thin film obtained in step a and removing surface residues by UV-ozone treatment; comprising a method for post-heat treatment of a SiO2 thin film. Claim 2 A method for post-heat treatment of a SiO2 thin film according to claim 1, wherein the silicon dioxide (SiO2) thin film of step a is prepared by plasma-enhanced chemical vapor deposition (PECVD) using one or more of silane (SiH4), carbon dioxide (CO2), nitrous oxide (N2O), nitric oxide (NO), and hydrogen (H2) as reactant precursors. Claim 3 A method for post-heat treatment of a SiO2 thin film according to claim 1, wherein the post-heat treatment of step a is performed one or more times under conditions in a temperature range of 200 to 400 ℃. Claim 4 A method for post-heat treatment of a SiO2 thin film according to claim 3, wherein the post-heat treatment of step a is performed for 1 hour in a temperature range of 200 to 400 ℃ and under a 99% nitrogen (N2) atmosphere or for 1 hour in the said temperature range and under a 99% oxygen (O2) atmosphere. Claim 5 A post-heat treatment method for a SiO2 thin film according to claim 1, wherein the washing in step b is performed by washing with acetone and isopropyl alcohol for 10 minutes each. Claim 6 A post-heat treatment method for a SiO2 thin film according to claim 1, wherein the UV-ozone treatment of step b is performed for 20 to 40 minutes. Claim 7 A SiO2 thin film for a thin film transistor, wherein the SiO2 thin film is post-heat-treated according to the method of claim 1, and the dielectric properties are improved by reducing charge impurities and mitigating defects due to the post-heat treatment. Claim 8 In claim 7, the SiO2 thin film is a SiO2 thin film for a thin film transistor in which the RMS (root mean square) value of the surface roughness is reduced compared to before post-heat treatment. Claim 9 c) a step of preparing a SiO2 thin film according to claim 7; d) a step of depositing an IGZO thin film by performing high-frequency magnetron sputtering using an IGZO target on the SiO2 thin film under temperature conditions of 20 to 25 ℃; and e) a step of forming Al source / drain electrodes by electron beam deposition after performing patterning on the IGZO thin film through wet etching; comprising a method for manufacturing an IGZO thin film transistor. Claim 10 An IGZO thin film transistor manufactured according to the method of claim 9, wherein the thickness of the SiO2 thin film in the thin film transistor is in the range of 70 to 90 nm, the thickness of the IGZO thin film is in the range of 8 to 12 nm, and the thickness of the Al source / drain electrode is in the range of 70 to 80 nm. Claim 11 In claim 10, the thin-film transistor is 3 to 7.5 cm 2 V -1 s -1 Temperature-dependent field-effect mobility (μ) in the range, threshold voltage (V) in the range of -7 to -1 V. th ), 1 X 10 3 Up to 1 x 10 8 On / off ratio of the range and 0.4 to 1.2 Vdec -1 IGZO thin-film transistor exhibiting a sub-threshold swing (SS) of the range. Claim 12 In claim 10, the thin-film transistor has a threshold voltage (Threshold Voltage, V) at each of the PBS test and the NBS test. th IGZO thin-film transistor with a movement stabilized within 7.2 V.

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