Device and Method for Thermal Distribution Switching Control in Phase-Shift Full-Bridge Converters

Abstract

The present invention relates to a heat dissipation switching control device and method, and more specifically, to a heat dissipation switching control device and method for a phase-shifted full-bridge converter. According to one embodiment of the present invention, the present invention can evenly distribute switch losses, reduce the maximum temperature applied to the switch, extend the lifespan of the power semiconductor switch, and simplify the design of the switch heat sink.

Description

Technology Field

[0001] The present invention relates to a thermal dissipation switching control device and method, and more specifically, to a thermal dissipation switching control device and method of a phase-shifted full-bridge converter. Background Technology

[0003] A phase-shifted full-bridge converter can be implemented using a center-tap high-frequency transformer, an output-side inductor, four switches on the primary side relative to the high-frequency transformer, and two switching elements on the secondary side relative to the high-frequency transformer.

[0004] Phase-shifted full-bridge converters can convert power with high efficiency under high-frequency switching because the switches located in the full-bridge can be turned on with zero-voltage switching. Phase-shifted full-bridge converters are used in numerous applications, such as power supplies for data centers and power supplies of several kW.

[0005] However, in a phase-shifted full-bridge converter, the switching losses applied when the switches located in the leading leg and the lagging leg of the primary side are turned off are different, so there is a problem where the thermal balance between the switches located in the leading leg and the lagging leg is disrupted during high-frequency switching.

[0006] In addition, since the dead time required for zero-voltage switching in the switches located in the leading leg and the lagging leg is different in the phase-shifted full-bridge converter, there is a problem in that the switch located in one leg does not perform zero-voltage switching when the same dead time is applied.

[0007] Conventional methods switch the roles of the leading leg and the lagging leg for the primary switches at regular intervals, but there are limitations in solving the problem as the temperature of the switches continuously fluctuates within a certain band.

[0008] To solve these problems, it is necessary to provide a thermal dissipation switching control device and method for a phase-shifted full-bridge converter.

[0009] The background technology of the present invention is disclosed in Korean Registered Patent No. 10-2708036. The problem to be solved

[0011] The present invention provides a thermal dissipation switching control device and method for a phase-shifted full-bridge converter that continuously switches the roles of the leading leg and the lagging leg. means of solving the problem

[0013] According to one aspect of the present invention, a thermal dissipation switching control device for a phase-shifted full-bridge converter is provided.

[0014] A thermal dissipation switching control device of a phase-shifted full-bridge converter according to one embodiment of the present invention may include a full-bridge unit that converts an input DC voltage into an AC signal, a transformer unit that transmits the AC signal to the secondary side of a transformer and steps up or steps down the voltage, a rectifier unit that converts the AC signal into a DC signal, rectifies it to remove ripple, and generates an output voltage, a signal generation unit that calculates an error between the output voltage and a reference output voltage and generates a control signal to correct the error, and generates a PWM signal by comparing the control signal with a Ramp signal, and a divided complementary modulation unit that controls a full-bridge switch by including a dead time in the PWM signal and generating a gate signal.

[0015] According to another aspect of the present invention, a thermal dissipation switching control method for a phase-shifted full-bridge converter is provided.

[0016] A thermal dissipation switching control method for a phase-shifted full-bridge converter according to one embodiment of the present invention may include the steps of: converting an input DC voltage into an AC signal; transmitting the AC signal to the secondary side of a transformer and stepping up or stepping down the voltage; converting the AC signal into a DC signal and rectifying it to remove ripple and generating an output voltage; calculating an error between the output voltage and a reference output voltage; generating a control signal to correct the error and comparing the control signal with a Ramp signal to generate a PWM signal; and controlling a full-bridge switch by including a dead time in the PWM signal and generating a gate signal. Effects of the invention

[0018] According to one embodiment of the present invention, the present invention can evenly distribute switch losses.

[0019] According to one embodiment of the present invention, the present invention can reduce the maximum temperature applied to the switch and extend the lifespan of the power semiconductor switch.

[0020] According to one embodiment of the present invention, the present invention can simplify the design of a heat sink for a switch.

[0021] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the composition of the invention described in the description or claims of the present invention. Brief explanation of the drawing

[0023] FIGS. 1 and 2 are drawings showing a thermal dissipation switching control device of a phase-shifted full-bridge converter according to an embodiment of the present invention. FIGS. 3 to 6 are control circuit diagrams of a thermal dissipation switching control device of a phase-shifted full-bridge converter according to embodiments of the present invention. FIG. 7 is a flowchart illustrating a thermal dissipation switching control method of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIGS. 8 to 11 are drawings showing the operation of a phase-shifted full-bridge converter according to an embodiment of the present invention divided into 12 states. FIG. 12 is a diagram showing the voltage gain in DCM and CCM operation of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIG. 13 is a diagram showing the dead time required for the leading leg switch and the lagging leg switch of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIG. 14 is a diagram showing the turn-off switching loss occurring at the primary side switch of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIG. 15 is a diagram showing an experimental apparatus and a power stack of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIG. 16 is a diagram showing the CCM operation experimental waveform of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIG. 17 is a diagram showing the DCM operation experimental waveform of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIG. 18 is a drawing showing the measurement efficiency curve of a phase-shifted full-bridge converter according to one embodiment of the present invention. FIG. 19 is a diagram showing a switch row of a phase-shifted full-bridge converter according to one embodiment of the present invention. Specific details for implementing the invention

[0024] The present invention is susceptible to various modifications and may have various embodiments; therefore, specific embodiments are illustrated in the drawings and described in detail. However, this is not intended to limit the present invention to specific embodiments, and it should be understood that it includes all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention. In describing the present invention, detailed descriptions of related prior art are omitted if it is determined that such detailed descriptions may unnecessarily obscure the essence of the invention. Furthermore, singular expressions used in this specification and claims should generally be interpreted as meaning "one or more" unless otherwise stated.

[0025] Throughout the specification, when it is stated that a part is "connected (connected, in contact, combined)" with another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other members interposed between them. Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components.

[0026] The terms used herein are merely for describing specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0027] The present invention will be described below with reference to the attached drawings. However, the present invention can be implemented in various different forms and is not limited to the embodiments described herein. For example, in addition to a phase-shifted full-bridge converter, it can also be utilized in a phase-shifted resonant full-bridge converter or an inductor-inductor-capacitor (LLC) converter. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals.

[0029] FIGS. 1 and 2 are drawings illustrating a thermal dissipation switching control device of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0030] Referring to FIG. 1, the thermal dissipation switching control device of a phase shift full bridge (PSFB) converter includes a full bridge section (110), a transformer section (120), a rectifier section (130), a signal generation section (140), and a divided complementary modulation section (150).

[0031] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0032] The full bridge section (110) converts the input direct current (DC) voltage into a high-frequency alternating current (AC) signal.

[0033] The full bridge section (110) is a transformer It is the primary side of, the input power supply, full bridge circuit, and leakage inductance It includes. Here, the full bridge circuit is a full bridge switch , , and Includes

[0034] The full bridge section (110) supplies a DC voltage from the input power source to the full bridge switching element and converts the input DC voltage into a high-frequency AC signal in the full bridge circuit.

[0035] Leakage inductance in the full bridge section (110) It transfers energy during the switching process and enables ZVS. Self-inductance in the full bridge section (110) It stores energy and maintains the magnetic properties of the transformer.

[0036] The transformer section (120) is a transformer The high-frequency AC signal on the primary side of the transformer It transmits to the secondary side and steps up or steps down the voltage.

[0037] The rectifier (130) converts the secondary AC signal into a DC signal and rectifies it to remove ripple and outputs the voltage Creates.

[0038] The rectifier section (130) is a transformer It is the secondary side of, and the center-tapped rectifier and output inductor Includes

[0039] Here, the center-tap rectifier is a switch and Includes

[0040] The rectifier section (130) converts the secondary AC signal into a DC signal in the center tap rectifier.

[0041] The rectifier section (130) removes ripple remaining in the DC signal after rectification in the output filter and supplies stable DC power to the load. Output inductance in the rectifier section (130) It smooths the current and output capacitance It removes voltage ripple.

[0042] The signal generating unit (140) is an output voltage and reference output voltage Calculate the error and generate a control signal to correct the error, and compare the generated control signal with the Ramp signal to generate a PWM signal.

[0043] The signal generation unit (140) includes a feedback circuit and a PWM signal unit.

[0044] The signal generation unit (140) outputs the voltage in the feedback circuit. Detects in real-time and reference output voltage The error of the output voltage is calculated by comparing it with the. The signal generation unit (140) generates a control signal to correct the error in the PI controller.

[0045] The PWM signal section includes a ramp signal generator, a comparator, and an RS flip-flop.

[0046] The signal generation unit (140) generates a Ramp signal from a Ramp signal generator. The signal generation unit (140) generates a PWM signal by comparing the control signal generated from the PI controller and the Ramp signal in a comparator.

[0047] The signal generation unit (140) stabilizes the switching signal based on the signal of the comparator in the RS flip-flop.

[0048] The divided complementary modulation unit (150) generates a new PWM signal including dead time in the PWM signal and generates a gate signal to control the full bridge switch.

[0049] The divided complementary modulation unit (150) includes a dead-time control circuit and a gate driver.

[0050] The divided complementary modulation unit (150) generates a PWM signal including dead time to reduce switching loss in the dead-time control circuit and maintain ZVS.

[0051] The divided complementary modulation unit (150) generates a gate signal suitable for each switch based on the PWM signal from the gate driver.

[0052] The generated gate signal is transmitted to the full-bridge switch to control the switching timing.

[0054] Referring to FIG. 2, the divided complementary modulation unit (150) includes a data analysis unit (210), a modulation signal generation unit (220), and a signal operation unit (230).

[0055] The data analysis unit (210) collects data and analyzes the state of the switch using the collected data.

[0056] The data analysis unit (210) collects data, analyzes the switching mode based on the collected data, calculates the dead time, and transmits it to the modulation signal generation unit (220).

[0057] The data is the input voltage , output voltage Includes the back.

[0058] The data analysis unit (210) determines the load status of the switch by determining whether it is a heavy load or a light load based on the collected data. That is, the data analysis unit (210) determines whether the switching mode is currently CCM (Continuous Conduction Mode) or DCM (Discontinuous Conduction Mode).

[0059] The data analysis unit (210) calculates the dead time corresponding to the load state or switching mode of the switch and determines the dead time setting value.

[0060] The data analysis unit (210) is dead time if the load state of the switch is CCM. Apply only, and if the switch's load status is DCM, additional dead time Apply.

[0061] DCM requires additional dead time to meet the ground leg's ZVS.

[0062] The calculated dead time setting value is used to generate a switching signal in the modulation signal generation unit (220).

[0063] The modulation signal generation unit (220) generates a switching signal based on the state of the switch.

[0064] The modulation signal generation unit (220) generates a switching signal using a split complementary modulation method and alternately changes the role of each switch.

[0065] The modulation signal generation unit (220) generates a gate signal of the switch and alternates roles.

[0066] The modulation signal generation unit (220) generates a gate signal by using logic gates and inserting a pulse of 0.5 duty cycle. For example, the logic gates may include AND gates and OR gates.

[0067] Here, the input values ​​are the clock signal and the existing signal received from the data analysis unit (210), and the output value is the gate signal.

[0068] The clock signal is , the existing signal is , , the gate signal is , , , It may include the back.

[0069] The modulation signal generation unit (220) in split complementary modulation A gate driving signal for the nth primary side switch is generated by applying OR logic to the first pulse and the second pulse.

[0070] The first pulse is It is generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse.

[0071] The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch It is generated by applying an AND gate to the gate driving signal for the nth primary side switch.

[0072] The second pulse is It is generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse.

[0073] The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch It is generated by applying an OR gate to the gate driving signal for the nth primary side switch.

[0074] For example, in two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0075] For example, The first pulse of is and It can be generated by applying AND logic to. Here, is using an AND gate and Creates from.

[0076] For example, The second pulse of is and It can be generated by applying AND logic to. Here, is using an OR gate and Creates from.

[0077] For example, , and is in the above two switching cycles You can create it by following the same steps as the method for creating it.

[0078] The modulation signal generation unit (220) amplifies the gate signal to generate a gate driving signal.

[0079] The modulation signal generation unit (220) generates a switching signal by applying a dead time setting value calculated by the data analysis unit (210) to the gate driving signal to satisfy the ZVS condition.

[0080] The modulation signal generation unit (220) switches the roles of the leading leg and the ground leg according to an odd switching period or an even switching period.

[0081] Odd switching cycles are switches and switch It operates as a true-state leg and the switch and switch It operates as a ground leg.

[0082] The even switching cycle is the switch and switch It operates as a true-state leg and the switch and switch It operates as a ground leg.

[0083] The generated switching signal is transmitted to the signal operation unit (230).

[0084] The signal operation unit (230) controls the operation by transmitting a switching signal to the switch.

[0085] The signal operation unit (230) transmits the generated switching signal to the switch of the PSFB converter to control the switch operation.

[0086] The signal operation unit (230) controls each switch to turn on and off at a set timing.

[0087] The signal operation unit (230) can maintain the ZVS condition by applying a dead time when transmitting the switching signal.

[0089] FIGS. 3 to 6 are control circuit diagrams of a thermal dissipation switching control device of a phase-shifted full-bridge converter according to embodiments of the present invention.

[0090] FIG. 3 is a basic circuit diagram of the present invention, in which the secondary side of a phase-shifted full-bridge converter according to one embodiment of the present invention is a current distribution circuit.

[0091] Referring to Fig. 3, in a phase-shifted full-bridge converter, the input power supplies a DC voltage to the full-bridge switching element.

[0092] A full bridge converts the input DC voltage into a high-frequency AC signal.

[0093] leakage inductance It transfers energy during the switching process and enables ZVS. Self-inductance It stores energy and maintains the magnetic properties of the transformer.

[0094] A transformer transmits high-frequency AC signals from the primary side to the secondary side and steps up or steps down the voltage.

[0095] A center-tap rectifier converts the secondary AC signal into a DC signal.

[0096] The output filter removes ripple remaining in the DC signal after rectification and supplies stable DC power to the load. Output inductance It smooths the current and output capacitance It eliminates voltage ripple. The generated voltage is the load It is delivered as.

[0097] The feedback circuit outputs the voltage Detects in real-time and reference output voltage Calculate the error in the output voltage by comparing it with.

[0098] The PI controller generates a control signal to correct the error.

[0099] The PWM signal section includes a ramp signal generator, a comparator, and an RS flip-flop.

[0100] The ramp signal generator generates a ramp signal.

[0101] The comparator generates a PWM signal by comparing the control signal and the Ramp signal generated by the PI controller.

[0102] The RS flip-flop stabilizes the switching signal based on the comparator signal.

[0103] The dead-time control circuit generates a PWM signal including dead time to reduce switching losses and maintain ZVS. While the PWM signal can be implemented analogously as described above, the same PWM signal can also be implemented digitally.

[0104] The gate driver generates a gate signal suitable for each switch based on the PWM signal.

[0105] The generated gate signal is transmitted to the full-bridge switch to control the switching timing.

[0106] Referring to Fig. 3, the transformer The primary side is a full bridge circuit and leakage inductance Includes

[0107] Here, the full bridge circuit is a full bridge switch , , and Includes

[0108] transformer The secondary side is a center-tap rectifier and an output inductor Includes

[0109] Here, the center-tap rectifier is a switch and Includes

[0110] Referring to Fig. 3, the switch is , the body diode of the switch is , the parasitic capacitance of the switch is Igo am.

[0111] transformer The honorific of Is is, represents the number of turns in the primary winding and represents the number of turns in the secondary winding, and am.

[0112] Magnetizing inductance , leakage inductance is , output inductance is , output capacitance is , the resistive load is , the input voltage is , the output voltage is , the reference output voltage is , the primary side voltage of the transformer is , the input current is , switch The current flowing through is , the current flowing through the leakage inductance is The current flowing through the self-inductance is , the current flowing through the output inductance is am.

[0113] in split complementary modulation This is the gate driving signal for the i-th primary side switch. Here am.

[0114] in conventional modulation This is the gate driving signal for the first-side switch.

[0115] is the switching frequency It operates as For the nth primary side switch It is a clock signal with a phase shift of that amount.

[0116] is a non-inverting clock signal, is an inverted clock signal.

[0117] is a ramp signal and PI is proportional-integral control.

[0118] Conventional modulation methods and It operates with two diagonal switch pairs. The switch pairs are controlled by two gate driving signals. The switch pairs have the same duty cycle Dead time identical to It is driven by a gate driving signal having. The two signals are in phase There is a difference of that much.

[0119] However, the split complementary modulation method of the present invention is variable duty cycle It is driven by a complementary gate driving signal having. The gate driving signal is separated by an additional gate driving signal having a duty cycle pulse width of 0.5. It is driven by the same gate driving signal, but It has a phase difference. That is, each leg alternately operates as a leading leg and a lagging leg during every switching cycle.

[0120] The circuit operates in Continuous Conduction Mode (CCM) under heavy load conditions and naturally switches to Discontinuous Conduction Mode (DCM) under light load conditions.

[0121] The PSFB converter provides additional dead time during the switching cycle for the complete ZVS turn-on of the ground leg switch in the DCM. This is necessary.

[0122] Split complementary modulation changes the switching order of the primary side switches during the switching cycle, and odd switching cycle and even switching cycles The switching order and dead time differ at this point. Here is a discrete time index.

[0123] Therefore, the dead-time sequence of the primary switch is an odd switching period and even switching cycles It appears differently from each other.

[0124] Referring to FIG. 3, the gate portion of the divided complementary modulation unit (150) is a portion that implements a thermal dispersion switching control method by applying the divided complementary modulation method of the present invention to an analog circuit, and can also be implemented digitally.

[0125] In two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0126] The first pulse of is Gate driving signal and a 0.5 duty cycle pulse It can be generated by applying AND logic to. Here, is using an AND gate and Creates from.

[0127] The second pulse of is Gate driving signal and It can be generated by applying AND logic to. Here, is using an OR gate and Creates from.

[0128] Here, and is the full bridge switch number.

[0129] For example, in two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0130] For example, The first pulse of is and It can be generated by applying AND logic to. Here, is using an AND gate and Creates from.

[0131] For example, The second pulse of is and It can be generated by applying AND logic to. Here, is using an OR gate and Creates from.

[0132] , and is in the above two switching cycles You can create it by following the same steps as the method for creating it.

[0133] For example, in two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0134] For example, The first pulse of is and It can be generated by applying AND logic to. Here, is using an AND gate and Creates from.

[0135] For example, The second pulse of is and It can be generated by applying AND logic to. Here, is using an OR gate and Creates from.

[0136] For example, in two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0137] For example, The first pulse of is and It can be generated by applying AND logic to it.

[0138] For example, The second pulse of is and It can be generated by applying AND logic to it.

[0139] For example, in two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0140] For example, The first pulse of is and It can be generated by applying AND logic to it.

[0141] For example, The second pulse of is and It can be generated by applying AND logic to it.

[0142] The present invention establishes three assumptions to analyze the steady-state operation of a converter.

[0143] First, all switches inside It is considered ideal, and the body diode included in each switch inside Parasitic capacitors related to inside Only considers.

[0144] The parasitic capacitor value here is , is. That is, ~ The parasitic capacitor is the same and and The parasitic capacitor is the same.

[0145] Second, output capacitor is set to a sufficiently large value so that the output voltage ripple is negligibly small, and the output capacitor voltage It remains constant during one switching cycle.

[0146] Third, transformer It includes self-inductance and leakage inductance.

[0148] FIG. 4 is a control circuit diagram of a phase-shifted full-bridge resonant converter with a resonant capacitor added in a phase-shifted full-bridge converter according to another embodiment of the present invention.

[0149] Referring to FIG. 4, the phase-shifted full-bridge resonant converter is a phase-shifted full-bridge converter of the present invention. This is the added form.

[0150] Referring to Fig. 4, the phase-shifted full-bridge resonant converter is for each switching interval The current waveform is resonant rather than linear.

[0151] Referring to FIG. 4, the switching control method of the phase-shifted full-bridge resonant converter is the same as the switching control method of the secondary side of the phase-shifted full-bridge converter of the present invention, which is the same as the switching control method of the current distribution circuit.

[0152] The resonant full bridge section (410) converts the input DC voltage into a resonant high-frequency AC signal.

[0153] The resonant full bridge section (410) is a transformer It is the primary side of and includes an input power supply, a full bridge circuit, and a resonant circuit. Here, the full bridge circuit is a full bridge switch , , and It includes, and the resonant circuit is a resonant capacitor and resonant inductor Includes

[0154] The resonant full bridge section (410) supplies a DC voltage from the input power source to the full bridge switching element, and converts the input DC voltage into a resonant high-frequency AC signal through the resonant circuit in the full bridge circuit.

[0155] Resonant inductor in the resonant full bridge section (410) is a resonant capacitor It forms resonance together to smooth current changes and plays an auxiliary role in enabling more stable implementation of ZVS.

[0156] Also, leakage inductance It transfers energy during the switching process, and self-inductance It stores energy to maintain the magnetic properties of the transformer.

[0157] The resonant transformer section (420) is a transformer The resonant high-frequency AC signal on the primary side of the transformer It transmits to the secondary side and steps up or steps down the voltage.

[0158] The signal passing through the resonant circuit is converted into a smoother current waveform on the secondary side of the transformer and transmitted to the rectifier.

[0159] The resonant rectifier section (430) converts the secondary side resonant high-frequency AC signal of the transformer into a DC signal, rectifies it to remove ripple, and outputs the voltage Creates.

[0160] The resonant rectifier section (430) is a transformer It is the secondary side of, and the center-tapped rectifier and output inductor Includes

[0161] Here, the center-tap rectifier is a switch and Includes rectifier diode and Includes

[0162] The resonant rectifier section (430) converts the secondary AC signal from the center-tap rectifier into a DC signal.

[0163] The resonant rectifier section (430) removes ripple remaining in the DC signal after rectification in the output filter and supplies stable DC power to the load. Output inductance in the resonant rectifier section (430) It smooths the current and output capacitance It removes voltage ripple.

[0164] The phase-shifted full-bridge resonant converter utilizes a resonant circuit to transmit a smoother current waveform even in the resonant rectifier section (430), and can provide a more stable DC voltage by reducing output ripple.

[0165] The signal generating unit (140) is an output voltage and reference output voltage Calculate the error and generate a control signal to correct the error, and compare the generated control signal with the Ramp signal to generate a PWM signal.

[0166] The signal generation unit (140) includes a feedback circuit and a PWM signal unit.

[0167] The signal generation unit (140) outputs the voltage in the feedback circuit. Detects in real-time and reference output voltage The error of the output voltage is calculated by comparing it with the. The signal generation unit (140) generates a control signal to correct the error in the PI controller.

[0168] The PWM signal section includes a ramp signal generator, a comparator, and an RS flip-flop.

[0169] The signal generation unit (140) generates a Ramp signal from a Ramp signal generator. The signal generation unit (140) generates a PWM signal by comparing the control signal generated from the PI controller and the Ramp signal in a comparator.

[0170] The signal generation unit (140) stabilizes the switching signal based on the signal of the comparator in the RS flip-flop.

[0171] The divided complementary modulation unit (150) generates a new PWM signal including dead time in the PWM signal and generates a gate signal to control the full bridge switch.

[0172] The divided complementary modulation unit (150) includes a dead-time control circuit and a gate driver.

[0173] The divided complementary modulation unit (150) generates a PWM signal including dead time to reduce switching loss in the dead-time control circuit and maintain ZVS.

[0174] The divided complementary modulation unit (150) generates a gate signal suitable for each switch based on the PWM signal from the gate driver.

[0175] The generated gate signal is transmitted to the full-bridge switch to control the switching timing.

[0177] FIG. 5 is a control circuit diagram in which the secondary side of a phase-shifted full-bridge converter according to another embodiment of the present invention is a diode rectifier.

[0178] Referring to FIG. 5, power transfer is possible by changing the secondary side of the phase-shifted full-bridge converter of the present invention from a current distribution circuit to a diode rectifier.

[0179] Referring to FIG. 5, the switching control method of the phase-shifted full-bridge converter of the present invention is the same even when the secondary side of the phase-shifted full-bridge converter is a diode rectifier.

[0180] Referring to Fig. 5, when the secondary side of the phase-shifted full-bridge converter is a diode rectifier, the secondary output current is compared to when a current distribution circuit is used. It has the effect of changing to twice the amount and changing the voltage to twice the amount.

[0181] Therefore, when the secondary side of a phase-shifted full-bridge converter is a diode rectifier, it can be utilized in applications with medium-voltage output.

[0182] The full bridge section (110) converts the input DC voltage into a high-frequency AC signal.

[0183] The full bridge section (110) is a transformer It is the primary side of, the input power supply, full bridge circuit, and leakage inductance It includes. Here, the full bridge circuit is a full bridge switch , , and Includes

[0184] The full bridge section (110) supplies a DC voltage from the input power source to the full bridge switching element and converts the input DC voltage into a high-frequency AC signal in the full bridge circuit.

[0185] Leakage inductance in the full bridge section (110) It transfers energy during the switching process and enables ZVS. Self-inductance in the full bridge section (110) It stores energy and maintains the magnetic properties of the transformer.

[0186] The transformer section (120) is a transformer The high-frequency AC signal on the primary side of the transformer It transmits to the secondary side and steps up or steps down the voltage.

[0187] The diode rectifier section (530) is a transformer Converts the secondary AC signal to a DC signal and removes ripple to output voltage Creates.

[0188] The diode rectifier section (530) is a transformer It is the secondary side and includes a diode bridge rectifier and an output filter.

[0189] Here, the diode bridge rectifier is a diode , , and Includes

[0190] The diode rectifier section (530) converts the secondary AC signal from the diode bridge rectifier into a DC signal.

[0191] The diode rectifier section (530) is a transformer When an AC signal is applied to the secondary side of the diode , or , It alternately conducts power and supplies electricity to the load.

[0192] The diode rectifier section (530) removes ripple remaining in the DC signal after rectification in the output filter and supplies stable DC power to the load. Output inductance in the rectifier section (130) It smooths the output current and output capacitance It removes voltage ripple.

[0193] The signal generating unit (140) is an output voltage and reference output voltage Calculate the error and generate a control signal to correct the error, and compare the generated control signal with the Ramp signal to generate a PWM signal.

[0194] The signal generation unit (140) includes a feedback circuit and a PWM signal unit.

[0195] The signal generation unit (140) outputs the voltage in the feedback circuit. Detects in real-time and reference output voltage The error of the output voltage is calculated by comparing it with the. The signal generation unit (140) generates a control signal to correct the error in the PI controller.

[0196] The PWM signal section includes a ramp signal generator, a comparator, and an RS flip-flop.

[0197] The signal generation unit (140) generates a Ramp signal from a Ramp signal generator. The signal generation unit (140) generates a PWM signal by comparing the control signal generated from the PI controller and the Ramp signal in a comparator.

[0198] The signal generation unit (140) stabilizes the switching signal based on the signal of the comparator in the RS flip-flop.

[0199] The divided complementary modulation unit (150) generates a new PWM signal including dead time in the PWM signal and generates a gate signal to control the full bridge switch.

[0200] The divided complementary modulation unit (150) includes a dead-time control circuit and a gate driver.

[0201] The divided complementary modulation unit (150) generates a PWM signal including dead time to reduce switching loss in the dead-time control circuit and maintain ZVS.

[0202] The divided complementary modulation unit (150) generates a gate signal suitable for each switch based on the PWM signal from the gate driver.

[0203] The generated gate signal is transmitted to the full-bridge switch to control the switching timing.

[0205] FIG. 6 is a control circuit diagram in which the secondary side of a phase-shifted full-bridge converter according to another embodiment of the present invention is a voltage doubling circuit.

[0206] Referring to FIG. 6, power transfer is possible by changing the secondary side of the phase-shifted full-bridge converter of the present invention from a current distribution circuit to a voltage distribution circuit.

[0207] Referring to FIG. 6, the switching control method of the phase-shifted full-bridge converter of the present invention is the same even when the secondary side of the phase-shifted full-bridge converter is a voltage doubling circuit.

[0208] Referring to Fig. 6, when the secondary side of the phase-shifted full-bridge converter is a voltage doubling circuit, the secondary output current is compared to when a current doubling circuit is used. It has the effect of changing by a factor of two and changing the voltage by four times.

[0209] Therefore, when the secondary side of a phase-shifted full-bridge converter is a voltage doubling circuit, it can be utilized in applications requiring high-voltage output.

[0210] The full bridge section (110) converts the input DC voltage into a high-frequency AC signal.

[0211] The full bridge section (110) is a transformer It is the primary side of, the input power supply, full bridge circuit, and leakage inductance It includes. Here, the full bridge circuit is a full bridge switch , , and Includes

[0212] The full bridge section (110) supplies a DC voltage from the input power source to the full bridge switching element and converts the input DC voltage into a high-frequency AC signal in the full bridge circuit.

[0213] Leakage inductance in the full bridge section (110) It transfers energy during the switching process and enables ZVS. Self-inductance in the full bridge section (110) It stores energy and maintains the magnetic properties of the transformer.

[0214] The transformer section (120) is a transformer The high-frequency AC signal on the primary side of the transformer It transmits to the secondary side and steps up or steps down the voltage.

[0215] The voltage distribution rectifier section (630) is a transformer Converts the secondary AC signal into a DC signal, rectifies it to remove ripple, and outputs the voltage Creates.

[0216] The voltage distribution rectifier section (630) is a transformer It is the secondary side and includes a voltage doubling rectifier and an output filter capacitor.

[0217] Here, the voltage doubler rectifier is a diode , and capacitor , It includes and performs voltage doubling rectification using the secondary side AC signal.

[0218] The voltage doubling rectifier section (630) is a diode , They take turns communicating.

[0219] For example, the voltage doubling rectifier section (630) is when the transformer secondary side is bipolar. While attaining enlightenment When charging, and the transformer's secondary side is negative polarity Ga attained enlightenment Charges.

[0220] The voltage doubling rectifier section (630) removes ripple from the DC signal converted by the voltage doubling rectifier, and the output filter capacitor Using the load It supplies stable DC power to.

[0221] Output filter capacitor It removes voltage ripple from the DC signal.

[0222] The signal generating unit (140) is an output voltage and reference output voltage Calculate the error and generate a control signal to correct the error, and compare the generated control signal with the Ramp signal to generate a PWM signal.

[0223] The signal generation unit (140) includes a feedback circuit and a PWM signal unit.

[0224] The signal generation unit (140) outputs the voltage in the feedback circuit. Detects in real-time and reference output voltage The error of the output voltage is calculated by comparing it with the. The signal generation unit (140) generates a control signal to correct the error in the PI controller.

[0225] The PWM signal section includes a ramp signal generator, a comparator, and an RS flip-flop.

[0226] The signal generation unit (140) generates a Ramp signal from a Ramp signal generator. The signal generation unit (140) generates a PWM signal by comparing the control signal generated from the PI controller and the Ramp signal in a comparator.

[0227] The signal generation unit (140) stabilizes the switching signal based on the signal of the comparator in the RS flip-flop.

[0228] The divided complementary modulation unit (150) generates a new PWM signal including dead time in the PWM signal and generates a gate signal to control the full bridge switch.

[0229] The divided complementary modulation unit (150) includes a dead-time control circuit and a gate driver.

[0230] The divided complementary modulation unit (150) generates a PWM signal including dead time to reduce switching loss in the dead-time control circuit and maintain ZVS.

[0231] The divided complementary modulation unit (150) generates a gate signal suitable for each switch based on the PWM signal from the gate driver.

[0232] The generated gate signal is transmitted to the full-bridge switch to control the switching timing.

[0234] FIG. 7 is a flowchart illustrating a thermal dissipation switching control method of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0235] Referring to FIG. 7, the phase-shifted full-bridge converter, as shown in FIGs. 3 to 6, has a secondary side that is a current distribution circuit, a diode rectifier, or a voltage distribution circuit, or on the primary side This includes an added phase-shifted full-bridge resonant converter.

[0236] In step S705, the heat dissipation switching control unit converts the input DC voltage into a high-frequency AC signal.

[0237] Here, the high-frequency AC signal can be a resonant high-frequency AC signal when it is a phase-shifted full-bridge resonant converter.

[0238] In step S710, the heat dissipation switching control device sends the high-frequency AC signal on the primary side to the transformer It transmits to the secondary side and steps up or steps down the voltage.

[0239] In step S715, the heat dissipation switching controller converts the secondary side AC signal into a DC signal, rectifies it to remove ripple, and outputs the voltage Creates.

[0240] In step S720, the heat dissipation switching control unit outputs the voltage and reference output voltage Calculate the error of.

[0241] In step S725, the heat dissipation switching control device generates a control signal to correct the error, and generates a PWM signal by comparing the generated control signal with the Ramp signal.

[0242] In step S730, the thermal dissipation switching control device controls the full bridge switch by including a dead time in the PWM signal and generating a gate signal.

[0243] The heat dissipation switching control device collects data in real time.

[0244] The data is the input voltage , input current , frequency of the modulated signal and phase It may include the back.

[0245] The heat dissipation switching control device determines the load status of the switch based on the collected data.

[0246] The heat dissipation switching control device determines whether the switching mode of the switch is CCM or DCM.

[0247] If the switching mode is CCM (Continuous Conduction Mode), it is a heavy load, and if it is DCM (Discontinuous Conduction Mode), it is a light load.

[0248] The heat dissipation switching control device calculates the dead time corresponding to the determined load state or switching mode and determines the dead time setting value.

[0249] The heat dissipation switching control device has dead time if the switch load state is CCM. Apply only, and if the switch's load status is DCM, additional dead time Apply.

[0250] The thermal dissipation switching control device uses logic gates and generates gate signals by inserting pulses of 0.5 duty cycles.

[0251] For example, logic gates can include AND gates and OR gates.

[0252] Here, the input values ​​are the clock signal and the existing signal received from the data analysis unit (210), and the output value is the gate signal.

[0253] The clock signal is , the existing signal is , , the gate signal is , , , It may include the back.

[0254] The thermal dispersion switching control device in split complementary modulation The gate driving signal for the i-th primary switch is generated by applying OR logic to the first pulse and the second pulse. Here, in divided complementary modulation The gate drive signal for the i-th primary side switch is It can be represented as.

[0255] The first pulse is It is generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse. Here, The gate driving signal is It can be represented as, and the 0.5 duty cycle pulse is It can be expressed as. Here, , and represents the full bridge switch number.

[0256] The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch It is generated by applying an AND gate to the gate driving signal for the i-th primary side switch. Here, in the basic modulation The gate drive signal for the i-th primary side switch is It can be represented as, and in basic modulation The gate drive signal for the i-th primary side switch is It can be represented as.

[0257] The second pulse is It is generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse. Here, The gate driving signal is It can be represented as.

[0258] The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch It is generated by applying an OR gate to the gate driving signal for the nth primary side switch.

[0259] For example, in two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0260] For example, The first pulse of is and It can be generated by applying AND logic to. Here, is using an AND gate and Creates from.

[0261] For example, The second pulse of is and It can be generated by applying AND logic to. Here, is using an OR gate and Creates from.

[0262] For example, , and is in the above two switching cycles You can create it by following the same steps as the method for creating it.

[0263] The thermal dissipation switching control device amplifies the gate signal to generate a gate driving signal.

[0264] The heat dissipation switching control device generates a switching signal by applying a calculated dead-time set value to the gate drive signal.

[0265] The heat dissipation switching control device switches the roles of the leading leg and the ground leg according to the odd or even switching cycle.

[0266] Odd switching cycles are switches and switch It operates as a true-state leg and the switch and switch It operates as a ground leg.

[0267] The even switching cycle is the switch and switch It operates as a true-state leg and the switch and switch It operates as a ground leg.

[0268] The heat dissipation switching control device transmits the generated switching signal to the switch of the PSFB converter to control the switch operation.

[0269] Since the present invention requires additional AND gates and OR gates to implement divided complementary switching modulation, development costs can be reduced by implementing the AND gates and OR gates using an Application-Specific Integrated Circuit (ASIC).

[0270] In order to maintain thermal balance between the leading leg and the lagging leg switches, the switching signal in the split complementary switching modulation is updated after an even switching cycle is completed.

[0271] The divided complementary modulation of the present invention can be implemented in a digital control environment by using analog control logic based on an ASIC and comparing the phase shift value with an up / down counter.

[0273] FIGS. 8 to 11 are diagrams showing the operation of a phase-shifted full-bridge converter according to one embodiment of the present invention divided into 12 states.

[0274] Referring to FIGS. 8 to 11, It represents 12 states during.

[0275] Referring to FIGS. 8 and 9, the state of the Continuous Conduction Mode (CCM) operation is analyzed.

[0276] Referring to FIGS. 10 and FIGS. 11, the state of the discontinuous conduction mode (DCM) operation is analyzed.

[0277] Referring to Figures 8 and 10, this is the theoretical waveform of a PSFB converter with split complementary modulation applied.

[0278] Referring to FIGS. 8 and FIGS. 10, in two switching cycles Is The first pulse of and It can be generated by applying OR logic to the second pulse.

[0279] In two switching cycles The first pulse of is and It can be generated by applying AND logic to. Here, is using an AND gate and Creates from.

[0280] In two switching cycles The second pulse of is and It can be generated by applying AND logic to. Here, is using an OR gate and Creates from.

[0281] , and is in the above two switching cycles You can create it by following the same steps as the method for creating it.

[0283] FIG. 8 is a diagram showing the theoretical waveform of a phase-shifted full-bridge converter under heavy load conditions according to one embodiment of the present invention.

[0284] Figure 8(a) shows the result of applying conventional phase shift modulation, and Figure 8(b) shows the result of applying the split complementary modulation of the present invention.

[0285] Referring to FIG. 8, the switching signal of the present invention can be created by applying a pulse width of 0.5 in the middle between the switching signals. In the present invention, the loss generated when the primary side switch is turned off occurs equally for each switch during two switching cycles.

[0286] Referring to Fig. 8, in split complementary modulation The other side It represents the gate driving signal of the second side switch. is the phase during effective power transfer, represents the phase during commutation.

[0288] FIG. 9 is a diagram showing the divided complementary modulation operation state of a phase-shifted full-bridge converter under heavy load conditions according to one embodiment of the present invention.

[0289] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0290] Figure 9 (a) shows state 1, Figure 9 (b) shows state 2, Figure 9 (c) shows state 3, Figure 9 (d) shows state 4, Figure 9 (e) shows state 5, Figure 9 (f) shows state 6, Figure 9 (g) shows state 7, Figure 9 (h) shows state 8, Figure 9 (i) shows state 9, Figure 9 (j) shows state 10, Figure 9 (k) shows state 11, and Figure 9 (l) shows state 12.

[0291] Referring to FIG. 9(a), state 1 is [ , ] and, switch is time Turning off at It flows. Capacitor Silver is discharged and capacitor is an inductor It is charged using the energy stored in it.

[0292] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time is increasing linearly and It is converted (commutated).

[0293] The equation of state can be expressed as shown in Equation 1 below.

[0294] [Mathematical Formula 1]

[0295]

[0296] Here, And, , , , am.

[0297] Referring to Fig. 9(b), state 2 is [ , ] and, is time at It is the same as. Power is transferred from the input side to the output side.

[0298] The equation of state can be expressed as Equation 2 below.

[0299] [Mathematical Formula 2]

[0300]

[0301] Referring to Fig. 9(c), state 3 is [ , ] and, switch time Turning off at It flows. Capacitor It is charged and the capacitor is an inductor It is discharged using the energy stored in it.

[0302] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time It decreases linearly.

[0303] The equation of state can be expressed as Equation 3 below.

[0304] [Mathematical Formula 3]

[0305]

[0306] Referring to Fig. 9(d), state 4 is [ , ] and, switch is time Turning off at It flows. Capacitor Silver is discharged and capacitor is an inductor It is charged using the energy stored in it.

[0307] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time is decreasing linearly and and It is converted (commutated).

[0308] The equation of state can be expressed as Equation 4 below.

[0309] [Mathematical Formula 4]

[0310]

[0311] Referring to Fig. 9(e), state 5 is [ , ] and, is time at It is the same as. Power is transferred from the input side to the output side.

[0312] The equation of state can be expressed as Equation 5 below.

[0313] [Mathematical Formula 5]

[0314]

[0315] Referring to (f) in Fig. 9, state 6 is [ , ] and, switch is time Turning off at It flows. Capacitor Silver is discharged and capacitor is an inductor It is charged using the energy stored in it.

[0316] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time It increases linearly.

[0317] The state equation can be expressed as Equation 6 below.

[0318] [Mathematical Formula 6]

[0319]

[0320] Referring to (g) in Fig. 9, state 7 is [ , ] and, switch time Turning off at It flows. Capacitor is discharged and the capacitor silver inductor It is charged using the energy stored in it.

[0321] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time is increasing linearly and It is converted (commutated).

[0322] The state equation can be expressed as shown in Equation 7 below.

[0323] [Mathematical Formula 7]

[0324]

[0325] Referring to (h) in Fig. 9, state 8 is [ , ] and, is time at It is the same as. Power is transferred from the input side to the output side.

[0326] The state equation can be expressed as shown in Equation 8 below.

[0327] [Mathematical Formula 8]

[0328]

[0329] Referring to (i) in Fig. 9, state 9 is [ , ] and, switch is time Turning off at It flows. Capacitor is charged and capacitor is an inductor It is discharged using the energy stored in it.

[0330] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time It decreases linearly.

[0331] The state equation can be expressed as shown in Equation 9 below.

[0332] [Mathematical Formula 9]

[0333]

[0334] Referring to (j) in Fig. 9, state 10 is [ , ] and, switch time Turning off at It flows. Capacitor is discharged and the capacitor silver inductor It is charged using the energy stored in it.

[0335] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time is decreasing linearly and and It is converted (commutated).

[0336] The equation of state can be expressed as shown in mathematical equation 10 below.

[0337] [Mathematical Formula 10]

[0338]

[0339] Referring to (k) in Fig. 9, state 11 is [ , ] and, is time at It is the same as. Power is transferred from the input side to the output side.

[0340] The equation of state can be expressed as shown in Equation 11 below.

[0341] [Mathematical Formula 11]

[0342]

[0343] Referring to (l) in Fig. 9, state 12 is [ , ] and, switch time Turning off at It flows. Capacitor is discharged and the capacitor silver inductor It is charged using the energy stored in it.

[0344] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time It increases linearly.

[0345] The equation of state can be expressed as shown in Equation 12 below.

[0346] [Mathematical Formula 12]

[0347]

[0349] FIG. 10 is a diagram showing the theoretical waveform of a phase-shifted full-bridge converter under light load conditions according to one embodiment of the present invention.

[0350] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0351] Figure 10 (a) shows the result of applying conventional phase shift modulation, and Figure 10 (b) shows the result of applying the split complementary modulation of the present invention.

[0352] Referring to FIG. 10, since the effect of turn-off loss is greater under light load, the present invention more clearly shows that switching loss occurs equally per switch during two switching cycles.

[0353] Referring to Fig. 10, indicates the falling phase. A switch operating with a leading leg is dead time This is applied, and the switch operating with the ground leg is dead time and additional dead time This applies.

[0355] FIG. 11 is a diagram showing the divided complementary modulation operation state of a phase-shifted full-bridge converter under light load conditions according to one embodiment of the present invention.

[0356] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0357] Figure 11 (a) shows state 1, Figure 11 (b) shows state 2, Figure 11 (c) shows state 3, Figure 11 (d) shows state 4, Figure 11 (e) shows state 5, Figure 11 (f) shows state 6, Figure 11 (g) shows state 7, Figure 11 (h) shows state 8, Figure 11 (i) shows state 9, Figure 11 (j) shows state 10, Figure 11 (k) shows state 11, and Figure 11 (l) shows state 12.

[0358] Referring to FIG. 11 (a), state 1 is [ , ] and, switch is time Turning off at It flows. Capacitor Silver is discharged and capacitor is an inductor It is charged using the energy stored in it.

[0359] is time Because it conducts first in It turns on in ZVS state. At this time is increasing linearly It conducts power. Power is transferred from the input side to the output side.

[0360] The equation of state can be expressed as shown in Equation 13 below.

[0361] [Mathematical Formula 13]

[0362]

[0363] Here, And, silver It is the current ripple applied to am.

[0364] Referring to Fig. 11(b), state 2 is [ , ] and, switch time Turning off at It flows. Capacitor It is charged and the capacitor is an inductor It is discharged using the energy stored in it.

[0365] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time It decreases linearly.

[0366] The equation of state can be expressed as shown in Equation 14 below.

[0367] [Mathematical Formula 14]

[0368]

[0369] Referring to Fig. 11 (c), state 3 is [ , ] and, is time at It is the same as. Power is not transferred from the input side to the output side.

[0370] The equation of state can be expressed as shown in Equation 15 below.

[0371] [Mathematical Formula 15]

[0372]

[0373] Referring to (d) of Fig. 11, state 4 is [ , ] and, switch is time Turning off at It flows. Capacitor Silver is discharged and capacitor is an inductor It is charged using the energy stored in it.

[0374] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time is decreasing linearly and It conducts. Power is transferred from the input side to the output side.

[0375] The equation of state can be expressed as shown in mathematical equation 16 below.

[0376] [Mathematical Formula 16]

[0377]

[0378] Referring to Fig. 11 (e), state 5 is [ , ] and, switch is time Turning off at It flows. Capacitor Silver is discharged and capacitor is an inductor It is charged using the energy stored in it.

[0379] time Because conduction occurs first at the switch It turns on in ZVS state. At this time and It increases linearly.

[0380] The equation of state can be expressed as shown in Equation 17 below.

[0381] [Mathematical Formula 17]

[0382]

[0383] Referring to (f) in Fig. 11, state 6 is [ , ] and, is time at It is the same as. Power is not transferred from the input side to the output side.

[0384] The equation of state can be expressed as shown in mathematical equation 18 below.

[0385] [Mathematical Formula 18]

[0386]

[0387] Referring to (g) in Fig. 11, state 7 is [ , ] and, time Turning off at It flows. Capacitor is discharged and the capacitor silver inductor It is charged using the energy stored in it.

[0388] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time is increasing linearly It conducts power. Power is transferred from the input side to the output side.

[0389] The equation of state can be expressed as shown in Equation 19 below.

[0390] [Mathematical Formula 19]

[0391]

[0392] Referring to (h) in Fig. 11, state 8 is [ , ] and, switch is time Turning off at It flows. Capacitor is charged and capacitor is an inductor It is discharged using the energy stored in it.

[0393] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time It decreases linearly.

[0394] The equation of state can be expressed as shown in mathematical equation 20 below.

[0395] [Mathematical Formula 20]

[0396]

[0397] Referring to (i) in Fig. 11, state 9 is [ , ] and, is time at It is the same as. Power is not transferred from the input side to the output side.

[0398] The equation of state can be expressed as shown in Equation 21 below.

[0399] [Mathematical Formula 21]

[0400]

[0401] Referring to (j) in Fig. 11, state 10 is [ , ] and, switch time Turning off at It flows. Capacitor is discharged and the capacitor silver inductor It is charged using the energy stored in it.

[0402] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time is decreasing linearly and It conducts. Power is transferred from the input side to the output side.

[0403] The equation of state can be expressed as shown in Equation 22 below.

[0404] [Mathematical Formula 22]

[0405]

[0406] Referring to (k) in Fig. 11, state 11 is [ , ] and, switch time Turning off at It flows. Capacitor Silver is discharged and capacitor is an inductor It is charged using the energy stored in it.

[0407] is time Because conduction occurs first at the switch It turns on in ZVS state. At this time and It increases linearly.

[0408] The equation of state can be expressed as shown in Equation 23 below.

[0409] [Mathematical Formula 23]

[0410]

[0411] Referring to (l) in Fig. 11, state 12 is [ , ] and, is time at It is the same as. Power is not transferred from the input side to the output side.

[0412] The equation of state can be expressed as shown in Equation 24 below.

[0413] [Mathematical Formula 24]

[0414]

[0416] FIG. 12 is a diagram showing the voltage gain in DCM and CCM operation of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0417] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0418] Referring to Fig. 12, the voltage gain in the CCM operation of a Phase Shift Full Bridge (PSFB) converter is Assuming that is very short, during CCM operation It can be calculated by applying the voltage-second balance law to it.

[0419] In CCM Since the waveform is identical in odd and even switching periods even when split complementary phase shift modulation is applied, the voltage gain calculation in CCM operation can be simplified by analyzing only the odd switching period. This can be expressed as shown in Equation 25 below.

[0420] [Mathematical Formula 25]

[0421]

[0422] By rearranging Equation 25, the voltage gain in CCM can be expressed as Equation 26 below.

[0423] [Mathematical Formula 26]

[0424]

[0425] Referring to Fig. 12, silver It shows the voltage gain in CCM according to.

[0426] In the DCM operation of the PSFB converter, the voltage gain is calculated similarly to the voltage gain in the CCM operation of the PSFB converter. In DCM Since the waveform is identical for odd and even switching periods even when split complementary phase shift modulation is applied, only the odd switching period The voltage gain calculation in DCM operation can be simplified by applying and analyzing the voltage-second balance law. This can be expressed as Equation 27 below.

[0427] [Mathematical Formula 27]

[0428]

[0429] By rearranging Equation 27, the voltage gain in DCM can be expressed as Equation 28 below.

[0430] [Mathematical Formula 28]

[0431]

[0432] The output current is By utilizing the fact that it is equivalent to twice the average value, it can be expressed as in mathematical formula 29 below.

[0433] [Mathematical Formula 29]

[0434]

[0435] If mathematical equation 28 is substituted into mathematical equation 29, it can be expressed as the quadratic equation 30 below.

[0436] [Mathematical Formula 30]

[0437]

[0438] Solving Equation 30, the falling phase in DCM can be expressed as Equation 31 below.

[0439] [Mathematical Formula 31]

[0440]

[0441] The total voltage gain in DCM can be expressed as Equation 32 below by substituting Equation 31 into Equation 27.

[0442] [Mathematical Formula 32]

[0443]

[0444] Referring to Fig. 12, silver It shows the voltage gain in DCM according to.

[0446] FIG. 13 is a diagram showing the dead time required for the leading leg switch and the lagging leg switch of a phase-shifting full-bridge converter according to one embodiment of the present invention.

[0447] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0448] Referring to Fig. 13, the condition is α is 400V, and The voltage is 12V.

[0449] Referring to Fig. 13, the horizontal axis is Power and the vertical axis is minimum deadtime.

[0450] Referring to Fig. 13, the true leg with the existing modulation and the ground leg with the existing modulation are shown.

[0451] Referring to FIG. 13, the dead time required for ZVS of a switch located in the leading leg is different from the dead time required for ZVS of a switch located in the lagging leg. Conventional switching methods apply different dead times, but the method of the present invention naturally enables ZVS by applying different dead times.

[0452] Referring to Fig. 13, the required dead time in the DCM area is relatively long, and the dead time required for the leading leg switch and the lagging leg switch is different. That is, in DCM operation, different dead times must be applied specifically to the leading leg switch and the lagging leg switch.

[0453] The roles of the leading leg and the lagging leg change with every switching cycle in split complementary modulation. Since the lagging leg switch operates more slowly, an extra dead time is applied before the lagging leg switch turns on.

[0454] Therefore, the dead time sequence applied to the primary switch under light load appears differently in odd switching cycles and even switching cycles.

[0455] Referring to Fig. 13, dead time is required to completely discharge the parasitic capacitance of the switch located in the leading leg in CCM operation.

[0456] The dead time required for the phase lead leg switch in CCM operation can be expressed by the following mathematical formula 33.

[0457] [Mathematical Formula 33]

[0458]

[0459] Here, am.

[0460] The dead time required for the phase lead leg switch in CCM operation can be expressed as the following Equation 34 by rearranging Equation 33.

[0461] [Mathematical Formula 34]

[0462]

[0463] The dead time required for the ground leg switch in CCM operation can be expressed by the following mathematical formula 35.

[0464] [Mathematical Formula 35]

[0465]

[0466] Here, am.

[0467] The dead time required for the ground leg switch in CCM operation can be expressed as the following Equation 36 by rearranging Equation 35.

[0468] [Mathematical Formula 36]

[0469]

[0470] The dead time required for the phase lead leg switch in DCM operation can be expressed by the following mathematical formula 37.

[0471] [Mathematical Formula 37]

[0472]

[0473] Here, am.

[0474] The dead time required for the phase lead leg switch in DCM operation can be expressed as the following Equation 38 by rearranging Equation 37.

[0475] [Mathematical Formula 38]

[0476]

[0477] The dead time required for the ground leg switch in DCM operation can be expressed by the following mathematical formula 39.

[0478] [Mathematical Formula 39]

[0479]

[0480] Here, am.

[0481] The dead time required for the ground leg switch in DCM operation can be expressed as the following Equation 40 by rearranging Equation 39.

[0482] [Mathematical Formula 40]

[0483]

[0485] FIG. 14 is a diagram showing the turn-off switching loss occurring at the primary side switch of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0486] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0487] Referring to FIG. 14, the turn-off switching loss that occurs when applying the conventional method and the divided complementary modulation method of the present invention to the leading leg and the lagging leg is shown.

[0488] Referring to FIG. 14, the results when a conventional method is applied to the leading leg, the results when a conventional method is applied to the lag leg, and the results when the divided complementary modulation method of the present invention is applied to the leading leg and the lag leg are shown.

[0489] Referring to FIG. 14, FIG. 14 (a) and FIG. 14 (b) have power [W] on the horizontal axis and switching loss [pu] on the vertical axis, while FIG. 14 (c) has phase shift value on the horizontal axis. and the vertical axis is the switching loss [pu].

[0490] Referring to FIG. 14, the conventional switching method has a problem in that switching loss occurs significantly in the switch located in the leading leg, but the method of the present invention can be seen to have the same switching loss in all switches located on the primary side.

[0491] The split complementary modulation method of the present invention alternately operates each leg as a leading leg and a lagging leg during every switching cycle to balance the loss distribution between the primary side switches.

[0492] Total switching loss of the switch It can be expressed by the following mathematical formula 41.

[0493] [Mathematical Formula 41]

[0494]

[0495] Here, Is It is the turn-on loss of the nth switch, and Is It is the turn-off loss of the nth switch, and am.

[0496] Since the secondary switch operates for synchronous rectification, switching losses occurring on the secondary side can be ignored.

[0497] Since the converter of the present invention can achieve ZVS at the moment of turn-on It can be considered as 0.

[0498] It can be expressed by the following mathematical formula 42.

[0499] [Mathematical Formula 42]

[0500]

[0501] Here, Is Energy consumed during the turn-off period of the nth switch, Is Voltage at the turn-off moment of the nth switch, Is Current at the turn-off moment of the nth switch, Is This is the time it takes for the current of the nth switch to decrease.

[0502] In the divided complementary modulation scheme of the present invention It is the same during two consecutive switching cycles. is constant and It is the same as.

[0503] however It varies depending on the odd switching period and even switching period in CCM (Continuous Conduction Mode) and DCM (Discontinuous Conduction Mode), respectively.

[0504] The turn-off loss in CCM can be expressed by the following mathematical formula 43.

[0505] [Mathematical Formula 43]

[0506]

[0507] Here, It can be expressed by the following mathematical formula 44, and It can be expressed by the following mathematical formula 45.

[0508] [Mathematical Formula 44]

[0509]

[0510] [Mathematical Formula 45]

[0511]

[0512] The turn-off loss in DCM can be expressed by the following mathematical equation 46.

[0513] [Mathematical Formula 46]

[0514]

[0515] Here, It can be expressed by the following mathematical formula 47, and It can be expressed by the following mathematical formula 48.

[0516] [Mathematical Formula 47]

[0517]

[0518] [Mathematical Formula 48]

[0519]

[0520] Referring to Fig. 14, per unit Is is, is the maximum switching loss at maximum output.

[0521] Referring to Fig. 14, in a conventional phase shift method, the current flowing through the leading leg and the current flowing through the lagging leg are different.

[0522] Differences in turn-off current stress increase switching losses occurring at the moment of turn-off in the ground leg switch.

[0523] In CCM (Continuous Conduction Mode), the current applied to the leading leg switch at the moment of turn-off as shown in Equation 44 is slightly higher than the current applied to the lagging leg switch as shown in Equation 45.

[0524] In DCM (Discontinuous Conduction Mode), the current applied to the leading leg switch at the moment of turn-off as in Equation 47 is higher than the current applied to the lagging leg switch as in Equation 48.

[0525] In other words, the imbalance of switching losses becomes more severe in DCM than in CCM.

[0526] However, in the split complementary modulation method of the present invention, since the roles of the leading leg switch and the lagging leg switch are exchanged in the PSFB converter every switching cycle, the switching loss between the primary side switches is balanced regardless of the output power and duty cycle.

[0527] Referring to FIG. 14 (a), the fixed Using the value per unit according to power It represents.

[0528] Referring to Fig. 14 (b), Considering the DC bias characteristics of the actual per unit according to power when using values It represents. The power is increased up to 2.5kW to show the effect of DC bias characteristics.

[0529] For example, The inductance value was theoretically designed to be 3 μH, but in reality Due to the DC bias characteristics of, the higher DC bias current As it passes through The inductance value of decreases.

[0530] The inductance value decreases to 1.8 μH when a current of 210 A flows through the output inductor at 2.5 kW. The small inductance is It can increase current ripple and make the turn-off current applied to the switches of the leading leg and the lagging leg more unbalanced.

[0531] A higher turn-off current can increase the difference in turn-off current between the switches of the leading leg and the lagging leg, and make the gap between the switching losses of the leading leg and the lagging leg larger.

[0532] In other words, current ripple increases, and unbalanced turn-off currents occur in the switches of the leading leg and the lagging leg. The imbalance in turn-off currents causes a difference in switching losses, which can reduce system efficiency.

[0533] The method of the present invention can increase the utilization of switches used in the PSFB converter, thereby reducing the development cost of the PSFB converter.

[0534] Referring to (c) of FIG. 14, per unit according to It represents.

[0535] Referring to Fig. 14, conduction losses are calculated as losses occurring during the period when the active element is conducting.

[0536] Total conduction loss It can be expressed as shown in mathematical formula 49 below.

[0537] [Mathematical Formula 49]

[0538]

[0539] Here, Is nth MOSFET switch ( Conductivity loss occurring when ) is in the turned-on state, Is Through the nth switch RMS current flowing during, Is It is the drain-source on-state resistance of the nth switch.

[0540] Here, in CCM and DCM of The rms current during this period can be expressed by the following mathematical formulas 50 to 55.

[0541] [Mathematical Formula 50]

[0542]

[0543] [Mathematical Formula 51]

[0544]

[0545] [Mathematical Formula 52]

[0546]

[0547] [Mathematical Formula 53]

[0548]

[0549] [Mathematical Formula 54]

[0550]

[0551] [Mathematical Formula 55]

[0552]

[0553] Here, mathematical formula 52 is from The integration interval up to class during Represents the integral of

[0554] Despite applying a divided complementary modulation scheme, the present invention has two consecutive switching periods During this time, the rms current of the switch is maintained at the same level as the rms current during a single switching cycle in the conventional switching modulation scheme.

[0556] FIG. 15 is a diagram showing an experimental apparatus and a power stack of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0557] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0558] Referring to FIG. 15, this is a 1kW converter prototype for verifying the feasibility of switching modulation of a PSFB converter.

[0559] Input voltage Set from 200V to 400V, and the reference output voltage It is 12V, output power Set it to 1.0kW.

[0560] The present invention relates to a dead time in the switch of the ground leg to improve light load efficiency. and additional dead time Apply.

[0561] Circuit parameters and detailed part numbers are shown in Tables 1 and 2 below.

[0562] parameters sign value Input power voltage 200~400V Reference output voltage 12V Output power 1.0kW switching frequency 100kHz Transformer winding cost 14:1:1 Self-inductance 200μH Primary side leakage inductance 1.3μH Output inductance 3μH Output capacitance 200μF Dead Time 100ns Additional Dead Time 100ns

[0563] Components sign Part number Primary side switch , , , UJ4C075044K4S secondary side switch , IRFP4310ZPBF Transformer core PQ4040

[0565] FIG. 16 is a diagram showing the CCM operation experimental waveform of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0566] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0567] Referring to Fig. 16, is 400V and This shows the experimental waveform when split complementary modulation is applied under the condition of 1 kW.

[0568] The divided complementary switching signal is , , and is, and in CCM operation , It is generated by a combination of AND gates and OR gates.

[0569] Referring to FIG. 16 (a), the switching signal , and and primary side voltage It represents.

[0570] Referring to FIG. 16 (a), the generated switching signal Is It is separated by.

[0571] The primary side voltage is the same as the conventional modulation method, but the current flowing through the primary side switch is different.

[0572] Referring to Fig. 16 (b), , , drain-source voltage of switch 1 , current flowing through switch 1 It represents.

[0573] Referring to FIG. 16(b), split complementary modulation changes the switching order so that the circulating current at the end of the odd switching cycle Makes it flow through.

[0574] It turns on in the ZVS state.

[0575] generated is of Fig. 5 It matches the theoretical waveform.

[0576] Referring to (c) of Fig. 16, , , drain-source voltage of switch 3 , current flowing through switch 3 It represents.

[0577] Referring to Fig. 16(c), the circulating current first in an even switching cycle It flows through.

[0578] It turns on in the ZVS state.

[0579] Referring to FIG. 16 (d), the output inductor current , secondary side switch and drain-source voltage and It represents.

[0580] Referring to Fig. 16 (d), the secondary switching is the same as the conventional modulation method even though split complementary modulation is applied to the PSFB converter.

[0581] is of Fig. 5 and It can be obtained by adding.

[0583] FIG. 17 is a diagram showing the DCM operation experimental waveform of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0584] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0585] Referring to Fig. 17, is 400V and This shows the experimental waveform when split complementary modulation is applied under the condition of 70W.

[0586] Referring to FIG. 17(a), the switching signal , and and primary side voltage It represents.

[0587] Referring to Fig. 17(a), the primary side switching of the split complementary modulation in DCM operation is similar to CCM operation.

[0588] To implement ZVS, the switch acting as the ground leg must apply extra dead-time to both the odd switching cycle and the even switching cycle, as shown in Fig. 7.

[0589] Referring to Figures 17 (b) and (c), ZVS can be implemented after applying additional dead time to the ground leg switch.

[0590] Referring to Fig. 17(b), , , drain-source voltage of switch 1 , current flowing through switch 1 It represents.

[0591] Referring to (c) of Fig. 17, , , drain-source voltage of switch 3 , current flowing through switch 3 It represents.

[0592] Referring to FIG. 17 (d), the output inductor current , secondary side switch and drain-source voltage and It represents.

[0593] Referring to (d) of Fig. 17, the secondary side switching of the split complementary modulation is similar to the CCM operation.

[0595] FIG. 18 is a diagram showing the measurement efficiency curve of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0596] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0597] Referring to Fig. 18, the measured efficiency curve of a phase-shifted full-bridge converter with divided complementary modulation applied according to output power change is shown.

[0598] Referring to Fig. 18, It shows the curves when V is 200V, 300V, and 400V.

[0599] The maximum power conversion efficiency is The efficiency is 96.2% when V is 200V, and the efficiency under full load conditions is 96.0%.

[0601] FIG. 19 is a diagram showing a switch row of a phase-shifted full-bridge converter according to one embodiment of the present invention.

[0602] Here, the secondary side of the phase-shifted full-bridge converter is a current distribution circuit.

[0603] Referring to Fig. 19, is 400V, and Figure 1 shows the thermal distribution image according to the switching mode and modulation method of the PSFB converter under 12V conditions.

[0604] Referring to FIG. 19, it can be seen that the switching method of the present invention maintains the temperature between primary switches at nearly the same level compared to the conventional method.

[0605] Figures 19 (a) and (d) are CCM operations, and It is 1kW, is 100kHz.

[0606] Figure 19 (a) applies a conventional method, and Figure 19 (d) applies the divided complementary modulation method of the present invention.

[0607] Referring to Fig. 19 (a), the leading leg is 77.6°C and the lagging leg is 84.8°C.

[0608] That is, the temperature difference between the primary side switches of the leading leg and the lagging leg is 7.2°C.

[0609] Referring to Fig. 19 (d), the split complementary leg 2 is 79.1°C and the split complementary leg 1 is 80.2°C.

[0610] That is, the temperature difference between the primary side switches of Split complementary leg 2 and Split complementary leg 1 is reduced to 1.1°C compared to (a) of Fig. 19.

[0611] In other words, when the PSFB converter uses a split complementary modulation scheme, the loss distribution between primary switches is balanced, which can simplify thermal management tasks and improve the reliability of the PSFB converter.

[0612] Figures 19 (b) and (e) are DCM operations, and It is 70W, is 100kHz.

[0613] Figure 19 (b) applies a conventional method, and Figure 19 (e) applies the divided complementary modulation method of the present invention.

[0614] Referring to Fig. 19(b), the true leg is 35.8°C and the ground leg is 38.5°C.

[0615] That is, the temperature difference between the primary side switches of the leading leg and the lagging leg is 2.7°C.

[0616] Referring to Fig. 19(e), the divided complementary leg 2 is 36.3°C and the divided complementary leg 1 is 36.7°C.

[0617] That is, the temperature difference between the primary side switches of the split complementary leg 2 and the split complementary leg 1 is reduced to 0.4°C compared to (b) of Fig. 19.

[0618] In other words, the present invention maintains a uniform heat distribution even under light loads.

[0619] Recently, high-frequency operation is required to increase the power density of power conversion circuits. When a conventional modulation scheme is applied to a PSFB converter under light load conditions, the peak of the magnetizing current decreases as the switching frequency increases. This can cause the ZVS operation of the primary side switch to fail, and the temperature difference between the primary side switches of the leading leg and the lagging leg increases significantly.

[0620] Figures 19 (c) and (f) are DCM operations, and It is 70W, It is 200kHz.

[0621] Figure 19 (c) applies a conventional method, and Figure 19 (f) applies the divided complementary modulation method of the present invention.

[0622] Referring to Fig. 19 (c), the true leg is 52.7°C and the ground leg is 64.8°C.

[0623] In other words, the temperature difference between the primary switches of the leading leg and the lagging leg is 12.1°C. This temperature difference increases further when the switching frequency exceeds 200 kHz and can only be resolved by introducing a water-cooling method. However, this solution increases the size of the converter system and reduces reliability.

[0624] Referring to Fig. 19 (f), the split complementary leg 2 is 57.5°C and the split complementary leg 1 is 58.1°C.

[0625] That is, the temperature difference between the primary side switches of the split complementary leg 2 and the split complementary leg 1 is reduced to 0.6°C compared to (c) of Fig. 19.

[0626] In other words, the present invention can simplify thermal management issues even under high-frequency operation and light-load conditions.

[0628] The apparatus and method according to the embodiments of the present invention described above may be implemented as computer-readable code on a computer-readable medium. The computer-readable recording medium may be, for example, a removable recording medium (CD, DVD, Blu-ray disc, USB storage device, removable hard disk) or a fixed recording medium (ROM, RAM, computer-equipped hard disk). The computer program recorded on the computer-readable recording medium may be transmitted to another computing device via a network such as the Internet and installed on the other computing device, thereby being used on the other computing device.

[0629] Although it has been described above that all components constituting an embodiment of the present invention are combined or operate as a single unit, the present invention is not necessarily limited to such an embodiment. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate.

[0630] Although operations are depicted in a specific order in the drawings, it should not be understood that the operations must necessarily be executed in the specific order depicted or in a sequential order, or that all depicted operations must be executed to obtain the desired result. In certain situations, multitasking and parallel processing may be advantageous. Furthermore, the separation of various configurations in the embodiments described above should not be understood as necessarily required, and it should be understood that the described program components and systems can generally be integrated together into a single software product or packaged into multiple software products.

[0631] The present invention has been described above with reference to its embodiments. Those skilled in the art will understand that the present invention may be embodied in modified forms without departing from the essential characteristics of the invention. Therefore, the disclosed embodiments should be considered in an illustrative rather than a restrictive sense. The scope of the invention is defined by the claims, not by the foregoing description, and all variations within the scope of the claims should be interpreted as being included in the invention. Explanation of the symbols

[0633] 110: Full bridge section 120: Transformer section 130: Rectifier 140: Signal generation unit 150: Split complementary modulation section 210: Data Analysis Department 220: Modulation signal generation unit 230: Signal operating unit 410: Resonant full bridge section 420: Resonant transformer section 430: Resonant rectifier 530: Diode rectifier section 630: Voltage distribution rectifier section

Claims

Claim 1 A thermal dissipation switching control device for a phase-shifted full-bridge converter, comprising: a full-bridge unit that converts an input DC voltage into an AC signal; a transformer unit that transmits the AC signal to the secondary side of a transformer and steps up or steps down the voltage; a rectifier unit that converts the AC signal into a DC signal, rectifies it to remove ripple, and generates an output voltage; a signal generation unit that calculates an error between the output voltage and a reference output voltage, generates a control signal to correct the error, and generates a PWM signal by comparing the control signal with a Ramp signal; and a divided complementary modulation unit that includes a dead time in the PWM signal and generates a gate signal to control a full-bridge switch. Claim 2 A thermal dissipation switching control device of a phase-shifted full-bridge converter comprising: a data analysis unit that collects data and analyzes the load state of a switch using the data to calculate a dead time in the split complementary modulation unit; a modulation signal generation unit that uses a logic gate to generate a gate signal by inserting a 0.5 duty cycle pulse and generates a switching signal by applying the dead time; and a signal operation unit that transmits the switching signal to a switch to control its operation. Claim 3 In paragraph 2, the data analysis unit applies only dead time if the load state of the switch is CCM and applies additional dead time if the load state of the switch is DCM, a thermal dissipation switching control device of a phase-shifted full-bridge converter. Claim 4 A thermal dissipation switching control device of a phase-shifted full-bridge converter, wherein the modulation signal generation unit further includes switching the roles of the leading leg and the lagging leg according to an odd switching period or an even switching period. Claim 5 In paragraph 2, the modulation signal generating unit in divided complementary modulation A gate driving signal for the nth primary side switch is generated by applying OR logic to the first pulse and the second pulse, and the first pulse is Generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse, and the The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch Generated by applying an AND gate to the gate driving signal for the nth primary side switch, and the second pulse is Generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse, and the The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch A thermal dissipation switching control device for a phase-shifted full-bridge converter generated by applying an OR gate to a gate driving signal for the nth primary side switch. Claim 6 In claim 1, the above AC signal is a thermal dissipation switching control device of a phase-shifted full-bridge converter, which is a resonant high-frequency AC signal. Claim 7 In claim 1, the rectifier section is a diode rectifier section, and the thermal dissipation switching control device of a phase-shifted full-bridge converter. Claim 8 In claim 1, the rectifier section is a thermal dissipation switching control device of a phase-shifted full-bridge converter that is a voltage-doubling rectifier section. Claim 9 A thermal dissipation switching control method for a phase-shifted full-bridge converter comprising: a step of converting an input DC voltage into an AC signal; a step of transmitting the AC signal to the secondary side of a transformer and stepping up or stepping down the voltage; a step of converting the AC signal into a DC signal, rectifying it to remove ripple, and generating an output voltage; a step of calculating an error between the output voltage and a reference output voltage; a step of generating a control signal to correct the error and generating a PWM signal by comparing the control signal with a Ramp signal; and a step of controlling a full-bridge switch by including a dead time in the PWM signal and generating a gate signal. Claim 10 In claim 9, the step of controlling a full-bridge switch by including a dead time in the PWM signal and generating a gate signal comprises: a step of collecting data and analyzing the load state of the switch with the data to calculate the dead time; a step of generating the gate signal by using a logic gate and inserting a 0.5 duty cycle pulse and generating a switching signal by applying the dead time; and a step of transmitting the switching signal to the switch to control the operation. Claim 11 In claim 10, the step of collecting the above data and analyzing the load state of the switch with the above data to calculate the above dead time is a thermal dissipation switching control method for a phase-shifted full-bridge converter in which only the dead time is applied if the load state of the switch is CCM and additional dead time is applied if the load state of the switch is DCM. Claim 12 A thermal dissipation switching control method for a phase-shifted full-bridge converter according to claim 10, wherein the step of generating the gate signal by using the logic gate and inserting a 0.5 duty cycle pulse and generating the switching signal by applying the dead time further comprises switching the roles of the leading leg and the lagging leg according to an odd switching period or an even switching period. Claim 13 In claim 10, the step of using the logic gate to generate the gate signal by inserting a 0.5 duty cycle pulse and applying the dead time to generate the switching signal is in divided complementary modulation. A gate driving signal for the nth primary side switch is generated by applying OR logic to the first pulse and the second pulse, and the first pulse is Generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse, and the The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch Generated by applying an AND gate to the gate driving signal for the nth primary side switch, and the second pulse is Generated by applying AND logic to the gate driving signal and the 0.5 duty cycle pulse, and the The gate driving signal is in the basic modulation In the gate drive signal and basic modulation for the i-th primary side switch A thermal dissipation switching control method for a phase-shifted full-bridge converter generated by applying an OR gate to a gate driving signal for the nth primary side switch.

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