Semiconductor package

Abstract

One embodiment of the present invention provides a semiconductor package comprising: a substrate including a plurality of lands and conductive traces connected to at least one side of each of the plurality of lands; a solder resist layer covering at least a portion of the plurality of lands and the conductive traces; a passive element including a plurality of electrodes disposed on the solder resist layer and electrically connected to the plurality of lands; and solder members connecting the plurality of electrodes and the plurality of lands, respectively, wherein each of the plurality of lands includes a connection edge to which the conductive traces are connected and a non-connection edge other than the connection edge, wherein the connection edge is in contact with the solder resist layer and the non-connection edge is spaced apart from the solder resist layer.

Description

Technology Field

[0001] The present invention relates to a semiconductor package. Background Technology

[0003] To improve the Power Integrity (PI) characteristics of a semiconductor package, a semiconductor chip and a passive component are mounted together on a package substrate. To improve the connection reliability of the passive component, a Non-Solder Mask Defined (NSMD) type land may be used. In this case, solder material may flow along a conductive trace exposed on one side of the NSMD land, which can cause defects such as misalignment or lifting of the component. The problem to be solved

[0005] One of the problems that the present invention aims to solve is to provide a semiconductor package with improved reliability. means of solving the problem

[0007] As a means of solving the above-mentioned problem, an exemplary embodiment of the present invention provides a semiconductor package comprising: a substrate including a plurality of lands and conductive traces connected to at least one side of each of the plurality of lands; a solder resist layer covering at least a portion of the plurality of lands and the conductive traces; a passive element including a plurality of electrodes disposed on the solder resist layer and electrically connected to the plurality of lands; and solder members connecting the plurality of electrodes and the plurality of lands, respectively, wherein each of the plurality of lands includes a connection edge to which the conductive traces are connected and a non-connection edge other than the connection edge, wherein the connection edge is in contact with the solder resist layer and the non-connection edge is spaced apart from the solder resist layer.

[0008] An exemplary embodiment of the present invention provides a semiconductor package comprising: a chip structure; a passive component disposed around the chip structure; a substrate comprising bonding pads to which the chip structure is connected, a plurality of lands to which the passive component is connected, and wiring electrically connected to the bonding pads and the plurality of lands; a solder resist layer disposed on the substrate and having a plurality of openings that expose at least a portion of each of the plurality of lands; and a sealant covering the chip structure and the passive component, wherein each of the plurality of lands comprises non-connecting edges located inside a corresponding opening among the plurality of openings, and at least one connecting edge located outside the opening, and the plurality of lands are connected to the wiring at the at least one connecting edge.

[0009] An exemplary embodiment of the present invention comprises: a substrate comprising first and second lands and first and second conductive traces disposed between the first and second lands; a solder resist layer comprising first and second openings covering the first and second conductive traces and exposing the first and second lands, respectively; and a passive element disposed on the solder resist layer. A semiconductor package is provided that includes first and second solder members disposed in the first and second openings, respectively, and electrically connecting the passive element and the first and second lands, wherein the first land includes a first connection edge located outside the first opening and a first non-connection edge located inside the first opening, and the second land includes a second connection edge located outside the second opening and a second non-connection edge located inside the second opening, and one end of the first conductive trace is connected to the first connection edge and one end of the second conductive trace is connected to the second connection edge.

[0010] An exemplary embodiment of the present invention provides a method for manufacturing a semiconductor package comprising: forming a substrate including at least one pair of lands, wherein each of the at least one pair of lands includes a connection edge connected to wiring and a non-connection edge other than the connection edge; forming a solder resist layer covering the at least one pair of lands; forming a plurality of openings that penetrate the solder resist layer and expose at least a portion of each of the at least one pair of lands, wherein the connection edge is located outside a corresponding opening among the plurality of openings and the non-connection edge is located inside the corresponding opening; and attaching a passive element on the at least one pair of lands via a solder member, wherein the solder member contacts the solder resist layer in the direction of the connection edge and is spaced apart from the solder resist layer in the direction of the non-connection edge. Effects of the invention

[0012] According to embodiments of the present invention, by introducing a mounting pad with improved bonding strength of a solder member without exposure of a conductive trace, a semiconductor package with improved reliability can be provided.

[0013] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0015] FIG. 1a is a cross-sectional view of a semiconductor package according to an exemplary embodiment, and FIG. 1b is a partial enlarged view of region 'A' of FIG. 1a. FIGS. 2a and 2b are plan views illustrating the coupling relationship between a land and a passive element of an exemplary embodiment. FIGS. 3a and 3b are plan views illustrating the coupling relationship between a land and a passive element of an exemplary variation. FIGS. 4a and 4b are plan views illustrating the coupling relationship between a land and a passive element of an exemplary variation. FIGS. 5a and 5b are plan views illustrating the coupling relationship between a land and a passive element of an exemplary variation. FIG. 6 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 7 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 8 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. FIG. 9 is a cross-sectional view of a semiconductor package according to an exemplary embodiment. Specific details for implementing the invention

[0016] Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings. Unless otherwise specifically stated, terms such as 'upper,' 'upper surface,' 'lower,' 'lower surface,' and 'side surface' in this specification are based on the drawings and may actually vary depending on the direction in which the components are arranged.

[0017] Additionally, ordinal numbers such as "first," "second," "third," etc., may be used as labels for specific elements, steps, directions, etc., to distinguish various elements, steps, directions, etc. from one another. Terms not described in the specification using "first," "second," etc., may still be referred to as "first" or "second" in the claims. Furthermore, terms referenced by a specific ordinal number (e.g., "first" in a specific claim) may be described elsewhere by a different ordinal number (e.g., "second" in the specification or another claim).

[0019] FIG. 1a is a cross-sectional view of a semiconductor package (100A) according to an exemplary embodiment, and FIG. 1b is a partial enlarged view of region 'A' of FIG. 1a.

[0020] Referring to FIGS. 1a and 1b, a semiconductor package (100A) of an exemplary embodiment may include a substrate (110), a chip structure (120), and a passive component (130). According to an embodiment, the semiconductor package (100A) may further include a sealing material (145) and / or a connecting bump (115). According to an exemplary embodiment, at least one passive component (130) may be surface-mounted on the substrate (110) to improve the signal integrity (SI) and / or power integrity (PI) characteristics of the semiconductor package (100A). Additionally, the solder resist layer (140) exposes the non-connected edge (10a) of the lands (10) to which the passive element (130) is connected, thereby securing the joint strength of the solder member (135), while the conductive trace (112T) covers the connected edge (10b) of the lands (10) to which it extends, thereby preventing the solder member (135) from spreading or changing in volume during the reflow process and improving the connection reliability of the passive element (130).

[0022] The substrate (110) is a support substrate on which a chip structure (120) is mounted, and may be a package substrate for rewiring the connection pads (120P) of the chip structure (120). The package substrate may include a printed circuit board (PCB), a ceramic substrate, a glass substrate, a tape wiring board, etc. The substrate (110) may include an insulating layer (111) and wiring (112).

[0023] The insulating layer (111) may include an insulating resin. The insulating resin may include a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a resin in which an inorganic filler or / and glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) is impregnated into these resins, for example, a photosensitive resin such as prepreg, ABF (Ajinomoto Build-up Film), FR-4 (Flame Retardant), BT (Bismaleimide Triazine), or PID (Photo-Imageable Dielectric).

[0024] The insulating layer (111) may include a plurality of insulating layers (111) stacked in a vertical direction (Z-axis direction). Among the plurality of insulating layers (111), the uppermost insulating layer (111) may provide the upper surface of the substrate (110), and the lowermost insulating layer (111) may provide the lower surface of the substrate (110). Depending on the process, the boundary between the plurality of insulating layers (111) may be indistinct. According to the embodiment, a number of insulating layers (111) may be formed that is fewer or more than that shown in the drawing. According to the embodiment, the core layer located in the middle among the plurality of insulating layers (111) may be thicker than the insulating layers (111) stacked above and below it. The core layer may be formed using, for example, a copper clad laminate (CCL), an unclad copper clad laminate (Unclad CCL), a glass substrate, or a ceramic substrate.

[0025] Wiring (112) can provide an electrical connection path within the insulating layer (111). Wiring (112) is formed using a plating process, a deposition process, etc., and may include, for example, a metal including copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. Wiring (112) may include, for example, a ground pattern, a power pattern, and a signal pattern. The signal pattern may provide a path for transmitting / receiving various signals, such as data signals, excluding the ground pattern, power pattern, etc. Wiring (112) may include a conductive trace (112T) and a via (112V).

[0026] The conductive traces (112T) may be metal patterns placed on the insulating layer (111). The conductive traces (112T) may be electrically connected to each other through vias (112V). The number of layers of the conductive traces (112T) may be determined according to the number of layers of the insulating layer (111) and may include more or fewer layers than shown in the drawing.

[0027] The via (112V) can penetrate the insulating layer (111) and be electrically connected to a conductive trace (112T). The via (112V) may have the form of a filled via in which a metallic material is filled inside the via hole, or a conformal via in which a metallic material is formed along the inner wall of the via hole. The via (112V) may be integrated with the redistribution layer (112), but embodiments of the present invention are not limited thereto.

[0028] The substrate (110) may further include a plurality of lands (10), a plurality of bonding pads (20), and a plurality of bump pads (30) that are electrically connected to the wiring (112). The plurality of lands (10) and the plurality of bonding pads (20) may be disposed on the upper surface of the substrate (110). The plurality of bump pads (30) may be disposed on the lower surface of the substrate (110). The plurality of lands (10) may be arranged at a pitch greater than the pitch of the plurality of bonding pads (20). The plurality of lands (10), the plurality of bonding pads (20), and the plurality of bump pads (30) may be formed with different sizes and pitches depending on the object to be mounted. The plurality of lands (10), the plurality of bonding pads (20), and the plurality of bump pads (30) are formed integrally with a corresponding conductive trace (112T) and may include the same metal as the conductive trace (112T).

[0029] A plurality of lands (10) may be pads for surface mounting of a passive component (130). A plurality of lands (10) may be electrically connected to an electrode (130P) of the passive component (130). Each of the plurality of lands (10) may be connected to an uppermost conductive trace (112T) on at least one side. A plurality of bonding pads (20) may be pads for flip-chip bonding of a chip structure (120). According to an embodiment, a plurality of bonding pads (20) may be pads for wire bonding of a chip structure (120). A plurality of bump pads (30) may be pads for connecting connection bumps (115). The connection bumps (115) may be solder balls made of, for example, tin (Sn) or an alloy containing tin (Sn).

[0030] A solder resist layer (140) may be disposed on the upper surface of a substrate (110). The solder resist layer (140) may include a plurality of openings (OP) that expose a plurality of lands (10) and a recess area (RC) that exposes a plurality of bonding pads (20). According to an embodiment, the solder resist layer (140) may open a plurality of bonding pads (20). The solder resist layer (140) may contain an insulating material and may be formed using, for example, prepreg, ABF, FR-4, BT, or photo solder resist (PSR). A lower solder resist layer (140B) may be disposed on the lower surface of the substrate (110) and may include openings that expose bump pads (30).

[0031] According to an exemplary embodiment, a plurality of openings (OP) may partially expose a plurality of corresponding lands (10). The plurality of openings (OP) of the solder resist layer (140) may be defined by an NSMD (Non-Solder Mask Defined) type inner wall and an SMD (Solder Mask Defined) type inner wall. By providing the solder resist layer (140) in an NSMD type at the non-connection edge (10a) of the plurality of lands (10), the bonding strength of the solder member (135) and the connection reliability of the passive component (130) can be improved. Additionally, by providing the solder resist layer (140) in an SMD type at the connection edge (10b) of the plurality of lands (10), the conductive trace (112T) is not exposed to the openings (OP), and the volume change of the solder member (135) can be prevented.

[0032] In an exemplary embodiment, each of the plurality of lands (10) may include a non-connecting edge (10a) located inside the corresponding opening (OP) among the plurality of openings (OP), and at least one connecting edge (10b) located outside the opening (OP). Each of the plurality of lands (10) may be connected to the wiring (112) of the substrate (110), i.e., the uppermost conductive trace (112T), at at least one connecting edge (10b). The non-connecting edge (10a) may be understood as an edge providing the perimeter of the plurality of lands (10) in addition to the connecting edge (10b). The non-connecting edge (10a) is located inside the opening (OP) and may be spaced apart from the solder resist layer (140). The connecting edge (10b) is located outside the opening (OP) and may be in contact with the solder resist layer (140).

[0033] In an exemplary embodiment, vias (112V) connected to the uppermost conductive trace (112T) are positioned between corresponding lands (10) to minimize the loop length of the passive element (130), thereby reducing inductance and further improving PI characteristics. For example, a plurality of lands (10) may include a first land (11) and a second land (12) each connected to the electrode (130P) of the passive element (130), and the conductive trace (112T) may include a first conductive trace (112T1) connected to the connection edge (10b) of the first land (11) and a second conductive trace (112T2) connected to the connection edge (10b) of the second land (12). The non-connecting edge (10a) of the first land (11) may be located inside the first opening (OP1), and the connecting edge (10b) of the first land (11) may be located outside the first opening (OP1). The non-connecting edge (10a) of the second land (12) may be located inside the second opening (OP2), and the connecting edge (10b) of the second land (12) may be located outside the second opening (OP2). The first land (11) and the second land (12) are arranged so that the connecting edges (10b) face each other, and the first conductive trace (112T1) and the second conductive trace (112T2) may extend between the facing first land (11) or second land (12). The first via (112V1) connected to the first conductive trace (112T1) and the second via (112V2) connected to the second conductive trace (112T2) may be located between the first land (11) and the second land (12).

[0034] A chip structure (120) is mounted on a substrate (110) and may include connection pads (120P) that are electrically connected to bonding pads (20). The connection pads (120P) may include at least one metal or an alloy composed of two or more metals selected from copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), and zinc (Zn). The connection pads (120P) may be electrically connected to the bonding pads (20) through bump structures (125). The bump structures (125) may include filler bumps (125a) and solder balls (125b). The filler bump (125a) may comprise at least one metal or an alloy composed of two or more metals selected from copper (Cu), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), platinum (Pt), tin (Sn), lead (Pb), titanium (Ti), chromium (Cr), palladium (Pd), indium (In), and zinc (Zn). The solder ball (125b) may be made of tin (Sn) or an alloy containing tin (Sn), for example, an alloy containing at least two of tin (Sn), lead (Pb), silver (Ag), copper (Cu), and bismuth (Bi). According to an embodiment, the bump structure (125) may comprise only one of the filler bump (125a) and the solder ball (125b). In some embodiments, the connection pads (120P) may be connected to the bonding pads (20) via a bonding wire (an embodiment of FIG. 7).

[0035] The chip structure (120) may include a semiconductor wafer and an integrated circuit (IC) made of a semiconductor element such as silicon or germanium, or a compound semiconductor such as SiC (silicon carbide), GaAs (gallium arsenide), InAs (indium arsenide), and InP (indium phosphide). The chip structure (120) may be a bare semiconductor chip without separate bumps or wiring layers formed thereon, but is not limited thereto, and may be a packaged type semiconductor chip.

[0036] The chip structure (120) may include a logic chip such as a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), an application processor (AP), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an application-specific IC (ASIC), a memory chip including a volatile memory such as a dynamic RAM (DRAM) or static RAM (SRAM), and a non-volatile memory such as a phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or flash memory.

[0037] The sealing material (145) can cover the chip structure (120) and the passive element (130). The sealing material (145) may include insulating materials such as prepreg, ABF, FR-4, BT, and EMC (Epoxy Molding Compound), such as thermosetting resins like epoxy resin, thermoplastic resins like polyimide, or resins impregnated with inorganic fillers such as these resins. A capillary underfill (CUF) or a molted underfill (MUF) may be formed on the underside of the chip structure (120) and the passive element (130).

[0038] A passive element (130) may be placed around a chip structure (120). The passive element (130) may be placed on a solder resist layer (140) and may include a plurality of electrodes (130P) electrically connected to a plurality of lands (10). According to an embodiment, the passive element (130) is supported by a portion of the solder resist layer (140) covering the conductive trace (112T), i.e., the solder resist layer (140) between the openings (OP), thereby preventing the passive element (130) from shifting. The passive element (130) may include, for example, a capacitor, an inductor, beads, etc. The plurality of electrodes (130P) may be powered through two or more corresponding lands (10). For example, the first land (11) and the second land (12) may have two or more different voltages, and at least one voltage may be a ground voltage. A plurality of electrodes (130P) may be connected to the corresponding land (10) through solder members (135). The solder members (135) may each be placed within a plurality of openings (OP). The solder members (135) may include tin (Sn), lead (Pb), silver (Ag), copper (Cu), gold (Au), or an alloy thereof.

[0039] In an exemplary embodiment, a solder resist layer (140) covering the connection edge (10b) can minimize spreading and volume change of the solder members (135). The solder member (135) may be in contact with at least one inner wall of an opening (OP) adjacent to the connection edge (10b). The solder member (135) may be in direct contact with the solder resist layer (140) adjacent to the connection edge (10b) of the land (10). The solder member (135) may be in contact with the solder resist layer (140) in the direction of the connection edge (10b) of the corresponding plurality of lands (10) and may be spaced apart from the solder resist layer (140) in the direction of the non-connection edge (10a) of the corresponding plurality of lands (10).

[0040] Hereinafter, with reference to FIGS. 2a and 2b, the land (10) and passive element (130) of an exemplary embodiment will be described in more detail.

[0042] FIGS. 2a and 2b are plan views illustrating the combined relationship between the land (10) and the passive element (130) of an exemplary embodiment.

[0043] Referring to FIGS. 2a and 2b, in an exemplary embodiment, at least one pair of lands (10) connected to one passive element (130) are arranged so that their connection edges (10b) face each other, and a conductive trace (112T) and a via (112V) may be arranged between the pair of lands (10).

[0044] At least one pair of lands (10) may include a first land (11) and a second land (12) spaced apart from each other. A conductive trace (112T) and a via (112V) may include a first conductive trace (112T1) and a first via (112V1) connected to the first land (11), and a second conductive trace (112T2) and a second via (112V2) connected to the second land (12).

[0045] The solder resist layer (140) may cover the entire first and second conductive traces (112T1, 112T2) between a pair of lands (10). The solder resist layer (140) may include first and second openings (OP1, OP2) that expose the first and second lands (11, 12), respectively. The first opening (OP1) may include an NSMD-type inner wall (Wa) corresponding to the first non-connecting edges (11a) and an SMD-type inner wall (Wb) corresponding to the first connecting edge (11b). The second opening (OP2) may include an NSMD-type inner wall (Wa) corresponding to the second non-connecting edges (12a) and an SMD-type inner wall (Wb) corresponding to the second connecting edge (12b).

[0046] The first land (11) may include a first connecting edge (11b) located on the outside of the first opening (OP1) and a first non-connecting edge (11a) located on the inside of the first opening (OP1). The second land (12) may include a second connecting edge (12b) located on the outside of the second opening (OP2) and a second non-connecting edge (12a) located on the inside of the second opening (OP2). The first land (11) and the second land (12) may be arranged so that the first connecting edge (11b) and the second connecting edge (12b) face each other.

[0047] One end of the first conductive trace (112T1) is connected to the first connection edge (11b), and the other end of the first conductive trace (112T1) can be connected to the first via (112V1). One end of the second conductive trace (112T2) is connected to the second connection edge (12b), and the other end of the second conductive trace (112T2) can be connected to the second via (112V2). The first conductive trace (112T1) extends from the first connection edge (11b) in a first direction (e.g., +X direction), and the second conductive trace (112T2) extends from the second connection edge (12b) in a second direction (e.g., -X direction) opposite to the first direction.

[0048] The passive element (130) may include at least one pair of electrodes (130P) connected to the first land (11) and the second land (12), respectively. The electrodes (130P) of the passive element (130) may each be connected to the first land (11) and the second land (12) through a solder member (135). The solder member (135) may be spaced apart from the NSMD type inner wall (Wa) and may come into contact with the SMD type inner wall (Wb).

[0049] In this embodiment, the first and second vias (112V1, 112V2) may be located between the first and second lands (11, 12). The diameter of the first via (112V1) or the second via (112V2) (about 100 μm or less) may be smaller than the gap between the first land (11) and the second land (12). Thus, the loop length of the passive element (130) can be minimized and the PI characteristics can be further improved.

[0050] Additionally, according to the present embodiment, in a plane, the first non-contact edge (11a) of the first land (11) and the second non-contact edge (12a) of the second land (12) may be symmetric with respect to the centerline between the first land (11) and the second land (12). That is, since the first land (11) and the second land (12) have substantially the same planar shape and area, the contact area and volume of the solder members (135) can be formed substantially the same.

[0052] FIGS. 3a and 3b are plan views illustrating the combined relationship between the land (10) and the passive element (130) of an exemplary variation.

[0053] Referring to FIGS. 3a and 3b, in an exemplary variation, at least one pair of lands (10) connected to one passive element (130) may be arranged such that the connection edges (10b) face in the same direction. Hereinafter, descriptions of each component that overlap with those described with reference to FIGS. 2a and 2b have been omitted.

[0054] The first land (11) and the second land (12) may be arranged so that the first connection edge (11b) and the second connection edge (12b) face each other in the same direction (e.g., X direction). One end of the first conductive trace (112T1) may be connected to the first connection edge (11b), and the other end of the first conductive trace (112T1) may be connected to the first via (112V1). One end of the second conductive trace (112T2) may be connected to the second connection edge (12b), and the other end of the second conductive trace (112T2) may be connected to the second via (112V2). The first conductive trace (112T1) extends from the first connection edge (11b) in a first direction (e.g., +X direction), and the second conductive trace (112T2) may extend from the second connection edge (12b) in the same first direction (e.g., +X direction) as the first conductive trace (112T1).

[0056] FIGS. 4a and 4b are plan views illustrating the combined relationship between the land (10) and the passive element (130) of an exemplary variation.

[0057] Referring to FIGS. 4a and 4b, in an exemplary variation, at least one pair of lands (10) connected to one passive element (130) may be arranged such that the connecting edges (10b) do not face each other and face in different directions. Hereinafter, descriptions of each component that overlap with those described with reference to FIGS. 2a and 2b have been omitted.

[0058] The first land (11) may be positioned so that the first connection edge (11b) faces the first direction (e.g., X direction). The second land (12) may be positioned so that the second connection edge (12b) faces the second direction (e.g., Y direction) that intersects the first direction. One end of the first conductive trace (112T1) may be connected to the first connection edge (11b), and the other end of the first conductive trace (112T1) may be connected to the first via (112V1). One end of the second conductive trace (112T2) may be connected to the second connection edge (12b), and the other end of the second conductive trace (112T2) may be connected to the second via (112V2). A first conductive trace (112T1) extends from a first connection edge (11b) in a first direction (e.g., X direction), and a second conductive trace (112T2) may extend from a second connection edge (12b) in a second direction (e.g., Y direction) that intersects the first direction.

[0060] FIGS. 5a and 5b are plan views illustrating the combined relationship between the land (10) and the passive element (130) of an exemplary variation.

[0061] Referring to FIGS. 5a and 5b, in an exemplary variation, at least one pair of lands (10) connected to one passive element (130) may have different numbers of connection edges (10b). At least one land (10) may have two or more connection edges (10b). Hereinafter, descriptions of each component that overlap with those described with reference to FIGS. 2a and 2b have been omitted.

[0062] The first land (11) may have one first connection edge (11b) facing the first direction (e.g., X direction). The second land (12) may have two or more second connection edges (12b) facing the second direction (e.g., Y direction) that intersects or is parallel to the first direction. The first land (11) may be connected to the first conductive trace (112T1) at one first connection edge (11b). The second land (12) may be connected to the second conductive trace (112T2) at two second connection edges (12b). Both of the two second connection edges (12b) may be in contact with the solder resist layer (140). The solder member (135) may be in contact with both of the two SMD-type inner walls (Wb) within the second opening (OP2).

[0064] FIG. 6 is a cross-sectional view of a semiconductor package (100B) according to an exemplary embodiment.

[0065] Referring to FIG. 6, the semiconductor package (100B) of the exemplary embodiment may have the same or similar features as described with reference to FIG. 1a to 5b, except that a passive element (130) is mounted on the lower surface of the substrate (110).

[0066] A passive component (130) can be connected to a plurality of lands (10) disposed on the lower surface of a substrate (110). The lower solder resist layer (140B) may include a plurality of openings (OP) that expose each of the plurality of lands (10). The plurality of lands (10) can be connected to the lowest conductive trace (112T) of the wiring (112).

[0067] A plurality of openings (OP) of the lower solder resist layer (140B) can be defined by NSMD-type inner walls and SMD-type inner walls. By providing the lower solder resist layer (140B) in an NSMD-type at the non-connecting edge ('10a' in FIG. 1b) of a plurality of lands (10), the bonding strength of the solder member (135) can be improved and the connection reliability of the passive component (130) can be improved. Additionally, by providing the lower solder resist layer (140B) in an SMD-type at the connecting edge ('10b' in FIG. 1b) of a plurality of lands (10), the conductive trace (112T) is not exposed to the openings (OP), and the volume change of the solder member (135) can be prevented.

[0069] FIG. 7 is a cross-sectional view of a semiconductor package (100C) according to an exemplary embodiment.

[0070] Referring to FIG. 7, the semiconductor package (100C) of the exemplary embodiment may have the same or similar features as described with reference to FIG. 1a through 6, except that the chip structure (120) includes a plurality of wire-bonded semiconductor chips (121).

[0071] A chip structure (120) may include a plurality of semiconductor chips (121) stacked on a substrate (110). The plurality of semiconductor chips (121) may be attached to the substrate (110) and other vertically adjacent semiconductor chips (121) by an adhesive film (DF). The adhesive film (DF) may include an inorganic adhesive or a polymer adhesive. The connection pads (121P) of the plurality of semiconductor chips (121) may be electrically connected to the bonding pads (20) via a bonding wire (BW). The plurality of semiconductor chips (121) may be electrically connected to each other via the bonding wire (BW). The plurality of semiconductor chips (121) may be offset in at least one direction so that each connection pad (121P) is exposed upward, but the stacking form of the plurality of semiconductor chips (121) is not limited to that shown in the drawing.

[0072] A plurality of semiconductor chips (121) may include non-volatile memory semiconductor devices such as Flash Memory, PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), and RRAM (Resistive Random Access Memory), and volatile memory devices such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory). The Flash Memory may be, for example, V-NAND Flash Memory.

[0074] FIG. 8 is a cross-sectional view of a semiconductor package (100D) according to an exemplary embodiment.

[0075] Referring to FIG. 8, the semiconductor package (100D) of the exemplary embodiment may have the same or similar features as described with reference to FIG. 1a through 7, except for the shape of the substrate (110). The substrate (110) may be a coreless type redistribution substrate. The substrate (110) may include an insulating layer (111) made of a photosensitive resin such as PID. The vias (112V) may have a shape with sides tapered upward or downward. Conductive traces (112T) are formed on each corresponding insulating layer (111), and depending on the process, the boundaries between the insulating layers (111) may not be clearly distinguished.

[0077] FIG. 9 is a cross-sectional view of a semiconductor package (100E) according to an exemplary embodiment.

[0078] Referring to FIG. 9, the semiconductor package (100E) of the exemplary embodiment may have the same or similar features as described with reference to FIG. 1a through 8, except that the chip structure (120) is in the form of a package. The chip structure (120) may include a first electronic component (121), a second electronic component (122), and an interconnection substrate (123). The interconnection substrate (123) may be an interposer substrate that electrically connects the first electronic component (121) and the second electronic component (122). The interconnection substrate (123) may be connected to the bonding pad (30) of the substrate (110) through a bump structure (125). A mold layer (MD) may cover at least a portion of each of the first electronic component (121) and the second electronic component (122) on the interconnection substrate (123). The outer surface of the mold layer (MD) may be coplanar with the outer surface of the interconnect substrate (123). The mold layer (MD) may include an insulating material such as EMC. According to an embodiment, a capillary underfill may be formed on the lower part of the chip structure (120) to surround the bump structures (125).

[0079] The first electronic component (121) and the second electronic component (122) may include different types of semiconductor chips. For example, the first electronic component (121) may include logic chips such as a central processor (CPU), a graphics processor (GPU), a field programmable gate array (FPGA), a digital signal processor, an encryption processor, a microprocessor, a microcontroller, an analog-to-digital converter, an ASIC, etc., and the second electronic component (122) may include memory chips such as DRAM, SRAM, PRAM, ReRAM, FeRAM, MRAM, and flash memory. According to an embodiment, the second electronic component (122) may be provided as a high-performance memory device such as HBM (High bandwidth memory), HMC (Hybrid memory cube), etc.

[0080] The second electronic component (122) may include a plurality of semiconductor chips (SC1, SC2, SC3, SC4, SC5). The plurality of semiconductor chips (SC1, SC2, SC3, SC4, SC5) may be provided in a number greater or less than that shown in the drawing. The plurality of semiconductor chips (SC1, SC2, SC3, SC4, SC5) may be stacked in a vertical direction (Z direction) by a thermal compression bonding method or a hybrid bonding method. The plurality of semiconductor chips (SC1, SC2, SC3, SC4, SC5) may be interconnected through through silicon vias. The plurality of semiconductor chips (SC1, SC2, SC3, SC4, SC5) may include a buffer chip (e.g., SC1) and a plurality of memory chips (e.g., SC2, SC3, SC4, SC5). At least a portion of each of the plurality of semiconductor chips (SC1, SC2, SC3, SC4, SC5) may be sealed by EMC, etc.

[0082] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0084] 100A: Semiconductor Package 110: Substrate 112: Wiring 112T: Conductive trace 112V:via 120: Chip structure 130: Passive component 135: Solder component 145: Suture 10: Lands 20: Bonding pads 30: Bump pads

Claims

Claim 1 A substrate comprising a plurality of lands and conductive traces connected to at least one side of each of the plurality of lands; a solder resist layer covering at least a portion of the plurality of lands and the conductive traces; a passive component comprising a plurality of electrodes disposed on the solder resist layer and electrically connected to the plurality of lands; and solder members connecting the plurality of electrodes and the plurality of lands, respectively, wherein each of the plurality of lands comprises a connection edge to which the conductive traces are connected and a non-connection edge other than the connection edge, wherein the connection edge is in contact with the solder resist layer and the non-connection edge is spaced apart from the solder resist layer. Claim 2 A semiconductor package according to claim 1, wherein the solder members contact the solder resist layer in the direction of the connection edge of the corresponding plurality of lands, and the solder members are spaced apart from the solder resist layer in the direction of the non-connection edge of the corresponding plurality of lands. Claim 3 In claim 1, the plurality of electrodes includes a first electrode and a second electrode, the plurality of lands include a first land connected to the first electrode and a second land connected to the second electrode, the conductive traces include a first conductive trace connected to a first connection edge of the first land and a second conductive trace connected to a second connection edge of the second land, and the first land and the second land are arranged such that the first connection edge and the second connection edge face each other in a semiconductor package. Claim 4 In claim 3, the substrate further comprises a first via connected to the first conductive trace and a second via connected to the second conductive trace, and the first via and the second via are disposed between the first land and the second land in a semiconductor package. Claim 5 In claim 3, the semiconductor package in which, on a plane, the first non-contact edge of the first land and the second non-contact edge of the second land are symmetric with respect to the centerline between the first land and the second land. Claim 6 A semiconductor package according to claim 1, wherein at least one of the plurality of lands includes two or more connection edges, each of the two or more connection edges contacts the solder resist layer, and the solder members contact the solder resist layer in the direction of the two or more connection edges of the corresponding plurality of lands. Claim 7 A semiconductor package comprising: a chip structure; a passive component disposed around the chip structure; a substrate comprising bonding pads to which the chip structure is connected, a plurality of lands to which the passive component is connected, and wiring electrically connected to the bonding pads and the plurality of lands; a solder resist layer disposed on the substrate and having a plurality of openings that expose at least a portion of each of the plurality of lands; and a sealant covering the chip structure and the passive component, wherein each of the plurality of lands comprises non-connecting edges located inside a corresponding opening among the plurality of openings, and at least one connecting edge located outside the opening, and the plurality of lands are connected to the wiring at the at least one connecting edge. Claim 8 In claim 7, the semiconductor package further comprises a solder member disposed within each of the plurality of openings and electrically connecting each of the plurality of lands to the passive element, wherein the solder member contacts at least one inner wall of a corresponding opening among the plurality of openings, and the at least one inner wall is adjacent to the at least one connection edge of each of the plurality of lands. Claim 9 A substrate comprising first and second lands, and first and second conductive traces disposed between the first and second lands; a solder resist layer comprising first and second openings covering the first and second conductive traces and exposing the first and second lands, respectively; and a passive element disposed on the solder resist layer; A semiconductor package comprising first and second solder members disposed in the first and second openings, respectively, and electrically connecting the passive element and the first and second lands, wherein the first land includes a first connection edge located outside the first opening and a first non-connection edge located inside the first opening, and the second land includes a second connection edge located outside the second opening and a second non-connection edge located inside the second opening, and one end of the first conductive trace is connected to the first connection edge and one end of the second conductive trace is connected to the second connection edge. Claim 10 In claim 9, the substrate further comprises a first via connected to the other end of the first conductive trace and a second via connected to the other end of the second conductive trace, wherein the first and second vias are located between the first and second lands in a semiconductor package.

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