Image sensor

Abstract

An image sensor according to one embodiment of the present invention comprises: a substrate including pixel regions each including a photoelectric conversion region; a floating diffusion region disposed on one surface of the substrate at each of the pixel regions and storing a charge transferred from the photoelectric conversion region; circuit elements transmitting a photoelectric signal according to the charge of the floating diffusion region; and a device isolation region defining the floating diffusion region and the circuit elements on the one surface of the substrate; wherein at least one of the circuit elements comprises a gate structure disposed on the one surface of the substrate; and source / drain regions disposed on both sides of the gate structure, and at least one of the source / drain regions is disposed on the device isolation region and includes a conductive layer comprising a material different from the substrate and in contact with the substrate below the gate structure.

Description

Technology Field

[0001] The present invention relates to an image sensor. Background Technology

[0003] An image sensor is a semiconductor-based sensor that receives light and generates an electrical signal, and may include a pixel array having multiple pixels and a logic circuit for driving the pixel array and generating an image. Each pixel may include a photodiode and a pixel circuit that converts the charge generated by the photodiode into an electrical signal. As the number of pixels included in the image sensor increases and the size of each pixel decreases, various methods are being proposed to effectively form the components, contact plugs, and wirings that are placed in each pixel to provide the pixel circuit. The problem to be solved

[0005] One of the objectives of the technical concept of the present invention is to provide an image sensor in which the source / drain regions of a driving transistor are stacked on a separate structure to maximize the gate electrode area of ​​the driving transistor, which is a source follower.

[0006] The invention provides an image sensor that minimizes noise by providing a conductive layer forming separate source / drain regions on a separated structure. means of solving the problem

[0008] An image sensor according to one embodiment of the present invention comprises: a substrate including pixel regions each including a photoelectric conversion region; a floating diffusion region disposed on one surface of the substrate at each of the pixel regions and storing a charge transferred from the photoelectric conversion region; circuit elements transmitting a photoelectric signal according to the charge of the floating diffusion region; and a device isolation region defining the floating diffusion region and the circuit elements on the one surface of the substrate; wherein at least one of the circuit elements comprises a gate structure disposed on the one surface of the substrate; and source / drain regions disposed on both sides of the gate structure, and at least one of the source / drain regions is disposed on the device isolation region and includes a conductive layer comprising a material different from the substrate and in contact with the substrate below the gate structure.

[0010] Meanwhile, an image sensor according to an exemplary embodiment of the present invention comprises: a substrate including pixel regions each including a photoelectric conversion region; a trench isolation region defining the pixel regions within the substrate; a floating diffusion region storing a charge transferred from the photoelectric conversion region on one side of the substrate; a driving transistor including a gate structure disposed adjacent to the trench isolation region and source / drain regions disposed on both sides of the gate structure, which amplifies the charge of the floating diffusion region and transmits a signal; and a device isolation region disposed on the trench isolation region on one side of the substrate and adjacent to the gate structure of the driving transistor; wherein at least one of the source / drain regions of the driving transistor is disposed on the adjacent device isolation region and overlaps in a vertical direction with the trench isolation region and comprises a semiconductor conductive layer having a material different from that of the substrate.

[0011] An image sensor according to an exemplary embodiment of the present invention comprises a plurality of pixel regions arranged along a direction parallel to one surface of a substrate, wherein each of the plurality of pixel regions comprises: a pixel array having at least one photodiode inside the substrate, a color filter disposed on the other surface opposite to the one surface of the substrate, and at least one element disposed on the one surface; and a logic circuit for acquiring a pixel signal from the plurality of pixel regions; wherein the pixel array comprises: a floating diffusion region disposed on each of the plurality of pixel regions on the one surface of the substrate and storing a charge transferred from the photodiode; circuit elements that transmit a photoelectric signal according to the charge in the floating diffusion region; and a device isolation region defining the floating diffusion region and the circuit elements on the one surface of the substrate; and wherein at least one of the circuit elements comprises a gate structure disposed on the one surface of the substrate. and includes source / drain regions disposed on both sides of the gate structure, wherein at least one of the source / drain regions is disposed on the device isolation region and is in contact with the substrate below the gate structure and includes a conductive layer comprising a material different from that of the substrate.

[0013] Meanwhile, a method for manufacturing an image sensor according to an exemplary embodiment of the present invention comprises: a step of forming a trench isolation layer defining pixel regions within a substrate and a device isolation region on one surface of the substrate on the trench isolation layer; a step of etching at least a portion of the device isolation region on the one surface of the substrate to form a first opening; a step of forming a conductive layer by embedding a conductive material in the first opening; and a step of forming a driving transistor having a gate structure on the one surface of the substrate as a source / drain region in the conductive layer.

[0014] The step of forming the conductive layer may involve embedding the conductive material in the first opening so as to protrude inward from the upper surface of the device isolation region.

[0015] The method may further include a step of flattening the conductive material so that the upper surface of the conductive layer forms a co-plane with the one surface of the substrate.

[0016] The depth of the above conductive layer may be smaller than the depth of the above device isolation region.

[0017] After forming the gate structure, the method may further include the step of doping a first conductivity type impurity onto the gate spacer of the gate structure and the conductive layer.

[0018] After doping with the first conductive type impurity, the method may further include a step of activating the impurity by annealing.

[0019] The step of forming the conductive layer above may involve laminating polysilicon with the conductive material.

[0020] The method for manufacturing the image sensor described above may further include the step of forming a contact plug connected to the conductive layer.

[0021] The upper surface of the conductive layer can be formed to be located at a higher level than the one surface of the substrate.

[0022] The above conductive layer can be formed to be shared in the source / drain regions of at least two adjacent driving transistors. Effects of the invention

[0024] According to one embodiment of the present invention, the source / drain regions of a driving transistor are formed separately on a separate structure to maximize the gate electrode area of ​​the driving transistor, which is a source follower buffer amplifier, thereby securing the gate electrode area and minimizing noise.

[0025] Unnecessary capacitance can be minimized by providing a conductive layer forming separate source / drain regions in a buried form after partially removing the separation structure.

[0026] The number of contact plugs can be minimized by forming a conductive layer on a separated structure in various layouts to share source / drain regions.

[0027] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0029] FIG. 1 is a simplified block diagram of an image sensor according to an exemplary embodiment of the present invention. FIG. 2 is a simplified circuit diagram showing a pixel circuit according to an exemplary embodiment of the present invention. Figure 3 is a simplified diagram illustrating the arrangement of pixels of the image sensor of Figure 2. Figure 4 is a cross-sectional view showing the image sensor of Figure 3. Figure 5 is an enlarged view of a part of Figure 4. FIGS. 6 to 11 are enlarged views of an image sensor according to an exemplary embodiment of the present invention. FIG. 12 is a simplified circuit diagram showing a pixel circuit according to an exemplary embodiment of the present invention. FIGS. 13 and FIGS. 14 are layout diagrams of an image sensor according to an exemplary embodiment of the present invention. FIG. 15 is a cross-sectional view of an image sensor according to an exemplary embodiment of the present invention. FIGS. 16a to 16g are cross-sectional views illustrating a method for manufacturing the image sensor of FIG. 4. Specific details for implementing the invention

[0030] Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings.

[0031] FIG. 1 is a simplified block diagram of an image sensor according to an exemplary embodiment of the present invention.

[0032] Referring to FIG. 1, the image sensor (1) may include a pixel array (10) and a logic circuit (20), etc.

[0033] A pixel array (10) may include a plurality of pixels (PX) arranged in an array form along a plurality of rows and a plurality of columns. Each of the plurality of pixels (PX) may include at least one photoelectric conversion element that generates a charge in response to light, and a pixel circuit that generates a pixel signal corresponding to the charge generated by the photoelectric conversion element. The photoelectric conversion element may include a photodiode formed of a semiconductor material, and / or an organic photodiode formed of an organic material.

[0034] For example, the pixel circuit may include a floating diffusion transistor, a transfer transistor, a reset transistor, a driving transistor, and a selection transistor. Depending on the embodiments, the configuration of the pixels (PX) may vary. For example, each of the pixels (PX) may include an organic photodiode containing an organic material, or may be implemented as a digital pixel. If the pixels (PX) are implemented as digital pixels, each of the pixels (PX) may include an analog-to-digital converter for outputting a digital pixel signal.

[0035] The logic circuit (20) may include circuits for controlling the pixel array (10). For example, the logic circuit (20) may include a row driver (21), a readout circuit (22), a column driver (23), control logic (24), etc. The row driver (21) can drive the pixel array (10) in units of row lines. For example, the row driver (21) can generate a transmission control signal that controls a transmission transistor of the pixel circuit, a reset control signal that controls a reset transistor, a selection control signal that controls a selection transistor, etc., and input them to the pixel array (10) in units of row lines.

[0036] The readout circuit (22) may include a Correlated Double Sampler (CDS), an Analog-to-Digital Converter (ADC), etc. Correlated double samplers may be connected to pixels (PX) and column lines. Correlated double samplers may read pixel signals through column lines from pixels (PX) connected to a low line selected by a low line selection signal of the low driver (21). The analog-to-digital converter may convert the pixel signal detected by the correlated double sampler into a digital pixel signal and transmit it to the column driver (23).

[0037] The column driver (23) may include a latch or buffer circuit capable of temporarily storing a digital pixel signal and an amplification circuit, etc., and may process a digital pixel signal received from a readout circuit (22). The row driver (21), the readout circuit (22), and the column driver (23) may be controlled by control logic (24). The control logic (24) may include a timing controller, etc., for controlling the operation timing of the row driver (21), the readout circuit (22), and the column driver (23).

[0038] Among the pixels (PX), pixels (PX) that are positioned at the same location in the horizontal direction may share the same column line. For example, pixels (PX) that are positioned at the same location in the vertical direction may be simultaneously selected by the row driver (21) and may output pixel signals through the column lines. In one embodiment, the readout circuit (22) may simultaneously acquire pixel signals from the pixels (PX) selected by the row driver (21) through the column lines. The pixel signal may include a reset voltage and a pixel voltage, and the pixel voltage may be a voltage in which the charge generated in response to light at each of the pixels (PX) is reflected in the reset voltage.

[0040] FIG. 2 is a simplified circuit diagram showing a pixel circuit according to an exemplary embodiment of the present invention, and FIG. 3 is a simplified diagram showing the arrangement of pixels of the image sensor of FIG. 2.

[0042] Referring to FIG. 2, each of the plurality of pixels (PX in FIG. 1) may include a photoelectric conversion element and a pixel circuit, and the pixel circuit may include a transfer transistor (TX), a reset transistor (RX), a select transistor (SX), and a driving transistor (DX), etc. Additionally, the pixel circuit may further include a floating diffusion region (FD) in which charge generated by the photoelectric conversion element is accumulated. Hereinafter, the photoelectric conversion element (PD) will be described by referring to it as a photodiode, which is an example of a photoelectric conversion element.

[0043] The photodiodes (PD1-PD4) can generate and accumulate charge in response to externally incident light. Depending on the embodiments, the photodiodes (PD1-PD4) may be replaced with a phototransistor, photogate, pinned photodiode, etc.

[0044] The transfer transistors (TX1-TX4) can be turned on or turned off by a transfer signal input to the transfer gates (TG1-TG4). The transfer transistors (TX1-TX4) can transfer the charge generated in the photodiodes (PD1-PD4) to the floating diffusion region (FD). The floating diffusion region (FD) can store the charge generated in the photodiodes (PD1-PD4). Depending on the amount of charge accumulated in the floating diffusion region (FD), the voltage output by the driving transistors (TX1-TX4) may vary.

[0045] A reset transistor (RX) can reset the voltage of a floating diffusion region (FD) by removing the charge accumulated in the floating diffusion region (FD). The drain electrode of the reset transistor (RX) is connected to the floating diffusion region (FD), and the source electrode can be connected to a power supply voltage (VDD). When the reset transistor (RX) is turned on, the power supply voltage (VDD) connected to the source electrode of the reset transistor (RX) is applied to the floating diffusion region (FD), and the charge accumulated in the floating diffusion region (FD) can be removed by the reset transistor (RX).

[0046] The driving transistors (DX1, DX2) can operate as source follower buffer amplifiers. The driving transistors (DX1, DX2) can amplify the voltage change in the floating diffusion region (FD) and output it to the column lines (COL).

[0047] The select transistor (SX) can select pixels (PX) to be read row by row among a plurality of pixels (PX). When the select transistor (SX) is turned on, the voltage of the driving transistor (DX) can be output to the column lines (COL). For example, when the select transistor (SX) is turned on, a reset voltage or a pixel voltage can be output through the column lines (COL).

[0048] The reset transistor (RX) is controlled by a reset control signal (RG), and the select transistor (SX) can be controlled by a select control signal (SEL). The first to fourth transmission transistors (TX1-TX4) can be controlled by a first or second bias voltage, which is a transmission signal (TS1-TS4).

[0049] Each of the pixels (PX) may further include a ground region (GND) capable of receiving a ground voltage input. Accordingly, each of the pixels (PX) may include a ground region (GND), a photodiode (PD1-PD4), a transfer transistor (TX1-TX4), a reset transistor (RX), a select transistor (SX), and a driving transistor (DX1, DX2), and each component may be divided and arranged into a plurality of components connected in parallel. For example, the first to fourth photodiodes (PD1-PD4) may be connected to the first to fourth transfer transistors (TX1-TX4) and may be driven by the first and second driving transistors (DX1, DX2).

[0050] Each pixel (PX) can be structured into a single pixel region (PA), and the single pixel region (PA) can include four sub-pixel regions (PA1-PA4) as shown in FIG. 3. The four sub-pixel regions (PA1-PA4) can be arranged in a 2x2 configuration. The first sub-pixel region (PA1) may include a first photodiode (PD1), at least a portion of a floating diffusion region (FD), and a first transfer transistor (TX1) having a first transfer gate (TG1). In the first pixel region (PA1), the first photodiode (PD1) can be connected to a common floating diffusion region (FD) through the first transfer transistor (TX1). Likewise, the second to fourth photodiodes (PD2-PD4) of the second to fourth subpixel regions (PA2-PA4) can be connected to a common floating diffusion region (FD) through second to fourth transmission transistors (TX2-TX4) each comprising second to fourth transmission gates (TG2-TG4).

[0052] In four adjacent subpixel regions (PA1-PA4), the floating diffusion region (FD) is a single structure connected to one another and can also be defined as a common diffusion region (FD). The common diffusion region (FD) can be understood as a structure extending from the center (n1) of the four subpixel regions (PA1-PA4) to each of the four subpixel regions (PA1-PA4). For example, as shown in FIG. 3, it may include four bar-type regions extending through the center (n1) region of the four subpixel regions (PA1-PA4) to each of the four subpixel regions (PA1-PA4), and may include an extension region at each end.

[0053] Four adjacent subpixel regions (PA1-PA4) may share a pixel circuit, and the shared pixel circuit may include a reset transistor (RX), first and second driving transistors (DX1, DX2), and a select transistor (SX).

[0054] For example, each of the four subpixel regions (PA1-PA4) may include one additional transistor in addition to the transmission transistors (TX1, TX2). Of the four transistors included in the four subpixel regions (PA1-PA4), two may be connected in parallel to provide first and second driving transistors (DX1, DX2), one of the remaining two transistors may be provided as a select transistor (SX), and the other may be configured to provide a reset transistor (RX).

[0055] The pixel circuit described above with reference to FIG. 2 is merely one embodiment and is not necessarily limited to this form. For example, one of the four transistors may be assigned as a driving transistor (DX), one as a selection transistor (SX), and another as a reset transistor (RX). Additionally, the remaining one may be assigned as a dual conversion gain transistor (DCX) connected in series with the reset transistor (RX) to implement an image sensor (1) capable of controlling the conversion gain of the pixel. Alternatively, the pixel circuit may vary depending on the number of transistors included in each of the pixels (PX).

[0057] In FIG. 3, the image sensor (1) is a top view on a substrate (101) in an area corresponding to one pixel (PX) of a pixel array (10), and FIG. 4 is a cross-sectional view showing a cross-section of one of the pixels of FIG. 3. FIG. 4 is a cross-sectional view along the cutting line I-I' of FIG. 3, and FIG. 5 is an enlarged view of area 'A' of FIG. 4.

[0058] The image sensor (1) may include a first structure (L1) corresponding to a pixel array (10) and a second structure (L2) corresponding to a logic circuit (20) bonded thereto.

[0059] Pixel regions (PA) corresponding to a pixel (PX) in a pixel array (10) include 2x2 sub-pixel regions (PA1-PA4). The pixel regions (PA) or sub-pixel regions (PA1-PA4) include all of the photodiodes (PD1-PD4), active regions (123), and ground regions (GND) contained within the substrate (101). The pixel region (PA) can be defined as an area where the elements for operating as a pixel (PX) of FIG. 2 are placed, and the sub-pixel regions (PA1-PA4) can be defined as areas partitioned by a trench separator (103) within the pixel region (PA).

[0060] Accordingly, a trench separator (103) is disposed between sub-pixel regions (PA1-PA4) and between pixel regions (PA). The trench separator (103) is arranged in a grid shape within the substrate (101) and may include a first trench separator (103c) defining each pixel region (PA) and a second trench separator (103a, 103b) defining the sub-pixel regions (PA1-PA4).

[0062] The first trench separator (103c) may be positioned to extend in the X and Y directions to define each pixel area (PA) when viewed from the top surface, thereby partitioning a rectangular, specifically a rectangular or square space inside. The second trench separator (103a, 103b) may be a bar-type structure protruding from the inside of the first trench separator (103c) toward the center (n1) so as to partition each sub-pixel area (PA1-PA4) when viewed from the top surface. As an example, the second trench separator (103a, 103b) may include a second-1 trench separator (103a) extending in the X direction and a second-2 trench separator (103b) extending in the Y direction.

[0063] The second-1 trench separator (103a) and the second-2 trench separator (103b) may have a structure in which one end is cut to expose a center (n1) within a pixel area (PA). A common floating diffusion area (FD) can be positioned from the center (n1) where the second-1 trench separator (103a) and the second-2 trench separator (103b) are separated.

[0064] The trench separator (103) is a vertical structure extending from one side (S1) to the other side (S2) of the substrate (101), and can divide each pixel area (PA) or sub-pixel area (PA1-PA4) across the substrate (101) in a vertical direction.

[0065] The first to fourth sub-pixel regions (PA1-PA4) may have substantially the same area, and circuit elements may be arranged symmetrically with respect to the center (n1) of the pixel region (PA).

[0066] Each of the first to fourth subpixel regions (PA1-PA4) may include a transistor among the circuit elements, at least one transmission gate (TG1-TG4), and a portion of a common floating diffusion region (FD). A ground region (not shown) may be disposed in at least a portion of each subpixel region (PA1-PA4).

[0067] The common floating diffusion region (FD) within the first to fourth subpixel regions (PA1-PA4) is a region doped with a first conductivity type impurity, and may be a region where charge generated in the photodiodes (PD1-PD4) accumulates. For example, the first conductivity type impurity may be an N-type impurity. The first conductivity type impurity may be As or P, and for example, 1x10 16 ~ 1x10 18 / cm 3 It can be doped at a concentration of

[0068] A common floating diffusion region (FD) is electrically connected to at least one contact plug (157), and the common floating diffusion region (FD) may be adjacent to each of the first to fourth transmission gates (TG1-TG4). The first to fourth transmission gates (TG1-TG4) may be adjacent to the first to fourth photodiodes (PD1-PD4) formed inside the trench separator (103) in a first direction (Z direction, vertical direction).

[0069] When a first bias voltage is input to the first to fourth transmission gates (TG1-TG4), the charge generated in the first to fourth photodiodes (PD1-PD4) may not be able to move to the common floating diffusion region (FD). When the voltage of the first to fourth transmission gates (TG1-TG4) is increased to a second bias voltage higher than the first bias voltage, the charge generated in the first to fourth photodiodes (PD1-PD4) may move to the common floating diffusion region (FD). For example, the first bias voltage may be a negative voltage, and the second bias voltage may be a positive voltage. The absolute value of the first bias voltage may be smaller than the absolute value of the second bias voltage.

[0070] In the exemplary embodiment illustrated in FIG. 3, a first transmission gate (TG1) of a first transmission transistor (TX1) connected to a first photodiode (PD1) may be disposed in a first subpixel area (PA1), and a second transmission gate (TG2) of a second transmission transistor (TX2) connected to a second photodiode (PD2) may be disposed in a second subpixel area (PA2). A third transmission gate (TG3) of a third transmission transistor (TX1) connected to a third photodiode (PD3) may be disposed in a third subpixel area (PA3), and a fourth transmission gate (TG4) of a fourth transmission transistor (TX4) connected to a fourth photodiode (PD4) may be disposed in a fourth subpixel area (PA4).

[0071] In the first to fourth sub-pixel regions (PA1-PA4), one of the transistors among the circuit elements, such as a reset transistor (RX), a select transistor (SX), and a driving transistor (DX1, DX2), may be disposed respectively. For example, the first and second driving transistors (DX1, DX2) may be disposed respectively in the first sub-pixel region (PA1) and the fourth sub-pixel region (PA4), and the reset transistor (RX) may be disposed in the second sub-pixel region (PA2) and the select transistor (SX) may be disposed respectively in the third sub-pixel region (PA3).

[0072] Each of the transistors, which are circuit elements, may include a gate structure (GS) and active regions (123) disposed on both sides of the gate structure (GS). The area of ​​each active region (123) may be smaller than the area of ​​the common floating diffusion region (FD). This may be because the area of ​​the common floating diffusion region (FD), where the charge generated in each photodiode (PD1-PD4) accumulates, must be relatively larger.

[0073] The first structure (L1) may further include a device isolation region (105) for separating active regions (123) and a common floating diffusion region (FD) from one side (S1) of the substrate (101).

[0074] Among the transistors that are circuit elements, the driving transistors (DX1, DX2) may have a gate structure (GS) that is larger than the gate structure (GS) of other transistors, for example, the reset transistor (RX) or the select transistor (SX). Here, "large" does not mean height, but rather area, or the area occupied by the gate electrode (125) on the substrate (101).

[0075] The driving transistors (DX1, DX2) are source follower buffer amplifiers, and the noise of the output signal can be reduced as the size of the gate structure (GS) increases. To this end, the area of ​​the gate structure (GS) of the driving transistors (DX1, DX2) can be designed to be larger than that of the gate structure (GS) of other transistors, which can lead to an increase in channel length.

[0076] To this end, the source region and / or drain region (S / D) of the driving transistors (DX1, DX2) can be implemented with a semiconductor conductive layer (150) of a material different from the substrate (101).

[0077] The source region and / or drain region (S / D) includes a conductive layer (150), and the conductive layer (150) may be positioned to overlap at least a portion of the second-1 and / or second-2 trench separator (103a, 103b) in the Z direction on the second-1 and / or second-2 trench separator (103a, 103b). Thus, the active region (123) of the driving transistor (DX1, DX2) is not positioned within the first and fourth sub-pixel regions (PA1-PA4), thereby increasing the area available for use as a gate structure (GS).

[0078] Meanwhile, the subpixel regions (PA1-PA4) may further include an active region for a ground region. The ground region is separated from the common floating diffusion region (FD) and transistors and may not come into contact with the transmission gates (TG1-TG4). Additionally, the ground region may be doped with an impurity of a second conductivity type different from the common floating diffusion region (FD) and the active regions (123).

[0079] Contact plugs (157) may be disposed in the first to fourth transmission gates (TG1-TG4), the common floating diffusion region (FD), the gate structures (GS), the active regions (123), and the ground region.

[0080] Referring to FIGS. 4 and 5 for a detailed description, the substrate (101) may be a semiconductor substrate. For example, the substrate (101) may be a substrate (101) formed of a semiconductor material, for example, a single-crystal silicon substrate. The substrate (101) may include a side (S1) on which gate structures (GS) of circuit elements are arranged and active regions (123), a common floating diffusion region (FD), and an element isolation region (105) are formed, and a side (S2) opposite thereto.

[0081] Photodiodes (PD1-PD4) may be formed in each of the substrates (101) within the four subpixel regions (PA1-PA4). The photodiodes (PD1-PD4) may contain a first conductivity type impurity, and, for example, may contain an N-type impurity. They may be adjacent to each transmission gate (TG1-TG4) in the Z direction perpendicular to one surface (S1) of the substrate (101).

[0082] Meanwhile, an optical unit (170) may be disposed on the other side (S2) of the substrate (101) adjacent to the photodiode (PD1-PD4) in the Z direction and vertical direction. The optical unit (170) may include a color filter (171), a grid structure (173), a flattening layer (175), and a micro lens (177). The color filter (171) is separated from the color filter of an adjacent pixel by the grid structure (173) and can transmit light of a predetermined wavelength band. The micro lens (177) can refract light incident on the pixel (PX) and concentrate it onto the photodiode (PD1-PD4). The photodiode (PD1-PD4) can generate an electric charge in response to the light passing through the optical unit (170).

[0083] Accordingly, optical parts (170) and circuit elements can be arranged on both sides of the photodiodes (PD1-PD4) in the Z direction.

[0084] First and second trench separation films (103a, 103b, 103c) that separate photodiodes (PD1-PD4) within the substrate (101) and partition subpixel regions (PA1-PA4) may be arranged within the substrate (101) in a grid shape and extending from the grid shape toward the center (n1) of each pixel region (PA). The trench separation film (103) may include a conductive material, for example, a semiconductor material, in a central region, and may include a semiconductor material containing impurities of a second conductivity type different from the first conductivity type.

[0085] A liner may be disposed surrounding the conductive material, and a trench insulating layer (104) may be disposed between the liner and the substrate (101). Thus, the conductive material within the trench separator (103) can be electrically insulated from the substrate (101). When the conductive material is included within the trench separator (103), the charge collection ability of the photodiodes (PD1-PD4) can be improved when a black current flows. A substrate insulating region may be further included between the photodiodes (PD1-PD4) and the trench insulating layer (104), but is not limited thereto.

[0086] A device isolation region (105) (STI) defining active regions (123) and a common floating diffusion region (FD) of circuit elements can be disposed on one side (S1) of the substrate (101) into the substrate (101).

[0087] The device isolation region (105) can be formed by removing the entire surface (S1) of the substrate (101), excluding the area where the active region (123) of the circuit devices is placed and the area where the common floating diffusion region (FD) is placed, to a first depth (h1) and then stacking an insulating material.

[0088] The device isolation region (105) may also be positioned on the trench isolation film (103). As shown in FIG. 4, the device isolation region (105) may be aligned in the Z direction on the trench isolation film (103) to form a separation structure (IS) that partitions each pixel region (PA), and the separation structure (IS) may also partition sub-pixel regions (PA1-PA4). The device isolation region (105) on the trench isolation film (103) may be positioned to have a width greater than the width of the trench isolation film (103) and may have a lower width (W1) greater than the upper width of the trench isolation film (103).

[0089] The upper surface of the device isolation region (105) may substantially coplanar with one surface (S1) of the substrate (101), but is not limited thereto, and may also coplanar with the upper surface of the gate insulating layer (128).

[0090] The device isolation region (105) may have a width that decreases from the upper surface to the lower surface, and accordingly may have inclined sides. The device isolation region (105) may include a liner that surrounds the sides and the lower surface, and an insulating material may be disposed on the liner to fill the trench of the device isolation region (105). The insulating material may be a material such as a silicon oxide film, a silicon oxynitride film, or a silicon oxycarbon film. At this time, in a separation structure (IS) in which the device isolation region (105) and the trench separator (103) extend in the Z direction, the liner may not be disposed on the bottom surface of the device isolation region (105) that contacts the upper surface of the trench separator (103). When the device isolation region (105) is formed along the trench separator (103), it may include a grid shape.

[0091] A common floating diffusion region (FD) can be formed to contain a first conductivity type impurity from one side (S1) of the substrate (101) to a predetermined depth. As previously described, the common floating diffusion region (FD) may include bar-type regions extending from the center (n1) of a pixel region (PA) to four sub-pixel regions (PA1-PA4), and may be arranged to include an extension region in which one end of the bar-type region is disposed within each sub-pixel region (PA1-PA4).

[0092] The expansion region can have various shapes, for example, circular, elliptical, or polygonal. The transmission gates (TG1-TG4) of the transmission transistor (TX) can be placed in close proximity to a part of the expansion region.

[0093] Each of the transmission gates (TG1-TG4) may include at least one separate sub-transmission gate, and as an example, may include two sub-transmission gates as shown in FIG. 3. Each sub-transmission gate may have the same structure, but is not limited thereto. Each sub-transmission gate may be placed adjacent to a common floating diffusion region (FD) and may be connected in parallel with each other. The sub-transmission gate may include the same material as the gate electrode (125) of the circuit elements and may be formed of a conductive material such as polysilicon, metal, or metal silicide, and the first bias voltage and the second bias voltage described above may be applied to the transmission gates (TG1-TG4). The transmission transistors (TX) may have a gate insulating layer (128) and a gate spacer (126), etc. The gate insulating layer (128) may be placed between the transmission gates (TG1-TG4) and the substrate (101).

[0094] The transmission gate (TG1-TG4) includes a first electrode layer and a second electrode layer, and the first electrode layer and the second electrode layer may have different shapes. For example, the second electrode layer may be positioned between the first electrode layer and the photodiode (PD1-PD4) in the Z direction and may have a width that narrows as it approaches the photodiode (PD1-PD4). The second electrode layer may be positioned below one surface (S1) of the substrate (101) and embedded within the substrate (101), and the first electrode layer may have a region positioned above one surface (S1) of the substrate (101).

[0095] The gate insulating layer (128) may be formed along the interface between the transmission gate (TG1-TG4) and the substrate (101). The first electrode layer and the second electrode layer may be offset from each other in the horizontal direction and positioned at different locations. Thus, at least a portion of the lower surface of the first electrode layer may not be in direct contact with the upper surface of the second electrode layer, and at least a portion of the gate insulating layer (128) may be positioned between the device isolation region (105) and the first electrode layer in the Z direction.

[0097] The transistors, which are circuit elements, may include active regions (123) as a gate structure (GS) and source / drain region (S / D). The gate structure (GS) may include a gate electrode (125), a gate insulating layer (128), and a gate spacer (126). The gate electrode (125) is positioned on one side (S1) of the substrate (101) and is positioned above the one side (S1), and may have a height corresponding to the first electrode layer of the transmission gate (TG1-TG4), but is not limited thereto. As shown in FIG. 3, the gate electrode (125) may have a shape that is positioned at the corner within each sub-pixel region (PX1-PX4) and is bent in the X and Y directions. That is, it may have a shape that extends in the Y direction, is bent at the corner, and extends in the X direction. At this time, the gate electrode (125) may be positioned so as to be close to the separation structure (IS) on one side (S1) of the substrate (101), and if one end is positioned so as to be close to the second-1 trench separator (103a), the other end may be positioned so as to be close to the second-2 trench separator (103b). The area of ​​the gate electrode (125) of the driving transistor (DX1, DX2) may be larger than the area of ​​the gate electrode (125) of other transistors. Specifically, the extension length in each direction of the gate electrode (125) of the driving transistor (DX1, DX2) may be larger than the extension length in each direction of the gate electrode (125) of other transistors. However, the height of the gate electrode (125) of the driving transistor (DX1, DX2) may be substantially the same as the height of the gate electrode (125) of other transistors.

[0098] The gate electrode (125) of the circuit element may include a semiconductor material, for example, silicon, germanium, or a combination thereof. The gate electrode (125) may include an n-type or p-type doped layer, but may also include an undoped layer.

[0099] A gate insulating layer (128) can be disposed between the gate electrode (125) of a circuit element and the substrate (101), and a gate spacer (126) can be formed of silicon nitride or the like and can be formed on the side of the gate electrode (125).

[0100] In particular, in the driving transistors (DX1, DX2), the gate spacer (126) can be positioned between the gate electrode (125) and the device isolation region (105) when viewed in a planar view, and one side (S1) of the substrate (101) between the gate electrode (125) and the device isolation region (105) may not be exposed or may be exposed with a very small area. In particular, it may be significantly smaller than the area of ​​the active region (123) for the source / drain region (S / D) of other transistors.

[0101] The transistors of other circuit elements, excluding the driving transistors (DX1, DX2), may have active regions (123) disposed on both sides of the gate structure (GS). The active regions (123) may be formed by injecting a first conductivity type impurity to a predetermined depth on one side (S1) of the substrate (101).

[0102] An active region (123) may form a source / drain region (S / D) on one side (S1) of the substrate (101) around the gate structure (GS) of transistors of other circuit elements excluding the driving transistors (DX1, DX2), for example, the reset transistor (RX) and / or the select transistor (SX).

[0103] The circuit element placed in the driving transistor (DX1, DX2), that is, the first and fourth subpixel regions (PA1, PA4), includes a large gate structure (GS), and a conductive layer (150) that forms a source region and a drain region (S / D) adjacent to both sides of the gate structure (GS) may be placed.

[0104] The source / drain region (S / D) of the driving transistor (DX1, DX2) may include a conductive layer (150) and a conductive region (151).

[0105] The conductive layer (150) of the source / drain region (S / D) of the driving transistor (DX1, DX2) overlaps vertically with the trench separator (103) and is placed on the separation structure (IS), and may include a material different from that of the substrate (101).

[0106] The conductive layer (150) may occupy most of the area of ​​the source / drain region (S / D) and may be disposed on the device isolation region (105). Displaced on the device isolation region (105) includes an upper surface disposed at the same level as one side (S1) of the substrate (101) and a lower surface protruding from the upper surface into the device isolation region (105) and in contact with the upper surface of the device isolation region (105), and the vertical distance between the upper surface and the lower surface may have a second depth (h2) that is smaller than the first depth (h1) of the device isolation region (105). The second depth (h2) may be smaller than or equal to the depth of the common floating diffusion region (FD).

[0107] Accordingly, the upper surface of the conductive layer (150) may be co-planar with one surface (S1) of the substrate (101), but is not limited thereto, and may be located at a higher level than the upper surface of the device isolation region (105). The upper width (W2) of the conductive layer (150) may be larger than the lower width (W1) of the device isolation region (105) and may have a slanted side that is continuous with the side of the device isolation region (105). Therefore, when the conductive layer (150) protrudes into the device isolation region (105), it can be understood that the device isolation region (105) is removed by the width and the conductive layer (150) is formed.

[0108] When viewed in a planar view, the conductive layer (150) may have a rectangular shape, and the length of the side facing the gate electrode (125) may be greater than the width of the gate electrode (125).

[0109] The conductive layer (150) includes a conductive material, and as an example, may include a semiconductor material, and may include polysilicon, etc. as a semiconductor material containing impurities of a first conductivity type. Preferably, it may include N-type impurities and may include impurities such as As, P, etc. At this time, the conductive layer (150) may include impurities identical to the impurities of other active regions (123), but is not limited thereto, and may include at least impurities of the same conductivity type as the impurities of other active regions (123).

[0110] A conductive region (151) can be disposed within one side (S1) of the substrate (101) extending from the conductive layer (150).

[0111] The conductive region (151) includes the substrate (101) region below the gate spacer (126) and, when viewed in a planar view, can be defined as the substrate (101) region between the gate electrode (125) and the conductive layer (150).

[0112] One side of the conductive region (151) may be in contact with the conductive layer (150), and the other side may be in contact with the channel region of the driving transistors (DX1, DX2). One side (Sb) of the conductive region (151) may have a continuous slope, and the other side (Sa) may have a discontinuous slope, and may include a curved surface having an inflection point. That is, the shapes of both sides of the conductive region (151) may be different from each other.

[0113] The conductive region (151) can be formed by injecting a first conductive impurity from one side (S1) of the substrate (101) to a predetermined depth, and may have a curved surface on the other side (Sa) depending on the diffusion of the first conductive impurity. That is, the first conductive impurity is doped in the presence of the gate spacer (126), so that the doping depth may vary inversely proportional to the thickness of the gate spacer (126). The length (d1) of the conductive region (151) may be equal to or greater than the width of the lower surface of the gate spacer (126), and in the case where it is equal, one side (S1) of the substrate (101) may not be exposed between the conductive layer (150) and the opposite conductive layer (150).

[0114] The conductive layer (150) and the conductive region (151) are co-planar with one surface (S1) of the substrate (101), and the maximum length of the thickness of the conductive region (151) may be substantially the same as the second depth (h2) of the conductive layer (150), but is not limited thereto.

[0115] The first conductive impurity included in the conductive region (151) and the conductive layer (150) may be the same, and the concentration may also be the same. A driving transistor (TX1) may have a structure in which, when viewed in a planar view, the conductive region (151) is disposed on both sides of the gate electrode (125), and the conductive layer (150) is disposed outside the conductive region (151).

[0116] Accordingly, the distance between the conductive regions (151) may be equal to the length (W3) of the gate electrode (125) and may be smaller than the distance between the conductive layers (150). That is, source / drain regions (S / D) on both sides of the gate electrode (125) each include a conductive region (151) and a conductive layer (150), and can function as a transistor by having a channel region between the two conductive regions (151) on one side (S1) of the substrate (101) below the gate electrode (125).

[0117] When the conductive layer (150) contains a semiconductor material, the conductive layer (150) may have a single crystal structure (151a) from the boundary between the conductive layer (150) and the conductive region (151). That is, crystallization may proceed from the single crystal structure of the silicon substrate (101) to partially have a single crystal structure (150a), and a polycrystalline structure may be formed at the center of the conductive layer (150). Therefore, contact resistance can be minimized by having a crystal structure similar to that of the substrate (101) in the contact region between the conductive region (151) and the conductive layer (150).

[0118] In this way, the source / drain region (S / D) is not formed by doping on one side (S1) of the substrate (101) but is placed on the device isolation region (105), thereby securing the area of ​​the subpixel region (PA1, PA4) that can be utilized as a driving transistor (DX1, DX2).

[0119] In addition, when driving transistors (DX1, DX2) are included in the first sub-pixel region and the fourth sub-pixel region (PA1, PA4), the two driving transistors (DX1, DX2) connected in parallel in FIG. 2 may share a conductive layer (150) placed on one end, that is, on the second-1 trench separator (103a), and a source / drain region (S / D) may be placed thereon, and within each sub-pixel region (PA1, PA4), only the conductive region (151) is placed under each gate spacer (126), thereby maximizing the area of ​​the gate electrode (125) within the pixel region (PA).

[0120] In addition, by placing one contact plug (155) on the conductive layer (150) shared according to the connection relationship of the two transistors (DX1, DX2), the number of contact plugs (155) can also be significantly reduced.

[0121] In one driving transistor (DX1, DX2), the area of ​​the source region and the drain region (S / D) may be the same, but is not limited thereto, and the width of the conductive region (151) of the two regions, that is, the width (d1) of the lower part of the gate spacer (126), may be the same, but the conductive layer (150) of the two regions may be different depending on the width of the separation structure (IS).

[0123] In FIG. 3, only the driving transistors (DX1, DX2) are shown having a source / drain region (S / D) that includes a conductive layer (150) and a conductive region (151), but according to the embodiment, other circuit elements such as transistors may also have a source region or drain region (S / D) that includes a conductive layer (150).

[0125] For example, in the case of a reset transistor (RX) connected to a driving transistor (DX1, DX2) according to the connection of circuit elements, it may include a conductive layer (150) to be shared with the driving transistor (DX1, DX2) and may include a conductive region (151) below the gate electrode (125) of the reset transistor (RX).

[0126] Meanwhile, in the case where the source / drain region (S / D) is not shared with an adjacent transistor, the conductive layer (153) may include a non-shared conductive layer (153) having a structure in which a conductive region (151) is disposed on one side of the conductive layer (153) and a device isolation region (105) is continuous on the other side without a conductive region (151).

[0127] In the case of the non-covalent conductive layer (153), the source region or drain region (S / D) of the transistor placed on the other side may be formed by doping a first conductive type impurity onto one side (S1) of the substrate (101), and the conductive region (151) may be spaced apart from the non-covalent conductive layer (153) with the device isolation region (105) in between. Accordingly, two transistors close to the non-covalent conductive layer (153) may be physically separated and electrically insulated.

[0129] A substrate insulating layer (165) and an upper insulating layer (166) are disposed over the conductive layer (150) and the gate structure (GS), and an interlayer insulating layer (160) may be disposed thereon.

[0130] For electrical connection with the integrated floating diffusion region (FD), source / drain region (S / D), and gate electrodes (125), contact plugs (155, 157) can be positioned to be connected to the upper surface of the integrated floating diffusion region (FD), source / drain region (S / D), and gate electrodes (125) by penetrating the substrate insulating layer (165), the upper insulating layer (166), and the interlayer insulating layer (160). In particular, in the case of the source / drain region (S / D) having a conductive layer (150), the contact plug (155) is positioned on the conductive layer (150) rather than the conductive region (151), as previously described.

[0131] Therefore, the contact plug (155) can be physically separated from the conductive area (151), but can be understood as being electrically indirectly connected through the conductive layer (150).

[0132] Contact plugs (155, 157) may be formed such that diffusion barriers (155a, 157a) are disposed on the side and bottom surfaces, and a metallic material is embedded on the diffusion barriers (155a, 157a).

[0133] The diffusion barrier (155a, 157a) may be TiN, TaN, etc., and the contact plugs (155, 157) may include a conductive material such as W, Al, Cu, etc.

[0134] Therefore, since the source / drain region (S / D) is not formed on one side (S1) of the substrate (101), the substrate (101) and the contact plug (155, 157) are not directly connected, so damage to the semiconductor substrate (101) can be minimized when the contact plug (155, 157) is formed, and the number of contact plugs (155, 157) can also be minimized.

[0136] A substrate insulating layer (165) may be formed conformally on one side (S1) of a substrate (101). The substrate insulating layer (165) may conformally cover the lower gate structure (TG, GS) and the substrate (101) on the gate structure (TG, GS). The substrate insulating layer (165) may include silicon oxide or a low dielectric material.

[0137] The substrate insulating layer (165) can be disposed conformally over the spacers (126) of the gate structures (TG, GS) of each circuit element, for example, the transmission gate (TG), reset gate electrode, select gate electrode, and driving gate electrodes (125), and the exposed substrate (101).

[0138] An upper insulating layer (166) may be disposed on a substrate insulating layer (165). The upper insulating layer (166) may comprise a material different from that of the substrate insulating layer (165) and may conformally cover the substrate insulating layer (165) on the circuit elements and the exposed substrate (101) so as to have a thickness greater than that of the substrate insulating layer (165). The upper insulating layer (166) may comprise silicon nitride, silicon nitrate, or a low dielectric material. Since the upper insulating layer (166) is formed of a material different from that of the substrate insulating layer (165), the upper insulating layer (166) may function as an etch stop layer during the process.

[0139] The substrate insulating layer (165) and the upper insulating layer (166) each have a function and can protect the lower circuit element and the semiconductor substrate (101) by including different materials. The total thickness of the substrate insulating layer (165) and the upper insulating layer (166) can be 30 to 50 nm, and preferably 30 to 40 nm. In addition, the upper insulating layer (166) may have the largest thickness within the above thickness.

[0140] An interlayer insulating layer (160) may be provided on a substrate (101). The interlayer insulating layer (160) may cover the gate electrodes (125) of a transmission gate (TG), a select transistor (SX), a reset transistor (RX), and a driving transistor (DX1, DX2) on an upper insulating layer (166), and the exposed substrate (101) between them. The interlayer insulating layer (160) may include at least one single film or a multilayer structure of silicon oxide (SiO), silicon nitride (SiN), silicon nitride (SiON), and a porous low dielectric film.

[0141] At least one intermetallic insulating layer (163) may be provided on the interlayer insulating layer (160). The intermetallic insulating layer (163) may include a single film or multiple film structure among at least one silicon oxide film (SiO), silicon nitride film (SiN), silicon nitride film (SiON), and porous insulating film. Between the intermetallic insulating layers (163), upper wiring (158) and contact vias may be disposed. The contact vias may include a metal such as tungsten (W), aluminum (Al), or copper (Cu), and preferably tungsten may be applied.

[0142] The contact vias have a columnar shape and may have inclined sides that decrease in width toward the substrate (101).

[0143] The first structure (L1) may include the first bonding structure (166, 169).

[0144] The first bonding structure (166, 169) includes a first bonding insulating layer (166) and first bonding pads (169), and can perform hybrid bonding with the second bonding structure of the second structure (L2).

[0145] The second structure (L2) may include a logic substrate (401), a second wiring structure (430) connected to the second circuit elements (420), a second bonding structure (440) on the second wiring structure (430), and a logic insulating layer (443) covering the second circuit elements (420) and the second wiring structure (430) on the logic substrate (401). The second bonding structure (466, 469) may be connected to the second wiring structure (430) on the second wiring structure (430). The second bonding structure (466, 469) may include a metallic material such as copper (Cu). The second bonding structure (466, 469) may include a bonding pad (469) which is physically bonded to the first bonding pads (169) and may provide an electrical connection path. The second bonding insulating layer (466) can be bonded to the first bonding insulating layer (166) to provide a hybrid bond. The logic insulating layer (440) can cover the second circuit elements (420) and the third wiring structure (430).

[0147] Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 11. FIGS. 6 to 11 are enlarged views of the pixel area of ​​an image sensor according to an exemplary embodiment of the present invention, and are enlarged views of the “A” area of ​​FIG. 5.

[0148] Referring to FIG. 6, the image sensor (1a) of an exemplary embodiment of the present invention may be identical to the image sensor (1) of FIG. 5, except for the shape of the source / drain region (S / D) of the driving transistors (DX1, DX2).

[0149] Specifically, the source / drain region (S / D) of the driving transistors (DX1, DX2) can be implemented with only the conductive layer (150) without the conductive region (151).

[0150] The conductive layer (150) may be a structure that protrudes into the device isolation region (105) adjacent to the gate structure (GS) within the isolation structure (IS), specifically, and fills the device isolation region (105), and whose upper surface forms a co-plane with one surface (S1) of the substrate (101).

[0151] The conductive layer (150) has a lower surface in contact with the device isolation region (105), and at least a portion of its side surface may be in contact with the substrate (101). In particular, it may be positioned to be in contact with the channel region of the driving transistors (DX1, DX2).

[0152] A gate spacer (126) of a gate structure (GS) can be placed on the upper surface of the conductive layer (150), and the lower surface of the gate spacer (126) can be in direct contact with the upper surface of the conductive layer (150).

[0153] Accordingly, the gate spacer (126) and the conductive layer (150) can overlap by a second distance (d2) in the Z direction.

[0154] The shape and material of the conductive layer (150) may be the same as those in FIGS. 3 to 5.

[0156] Referring to FIG. 7, the image sensor (1b) of an exemplary embodiment of the present invention may be identical to the image sensor (1) of FIG. 5, except for the shape of the source / drain region (S / D) of the driving transistors (DX1, DX2). Specifically, the source / drain region (S / D) of the driving transistors (DX1, DX2) can be implemented with only the conductive layer (150) without the conductive region (151).

[0157] The conductive layer (150) may be a structure that protrudes into the device isolation region (105) adjacent to the gate structure (GS) within the isolation structure (IS), specifically and is embedded within the device isolation region (105), and whose upper surface forms a co-plane with one surface (S1) of the substrate (101). A gate spacer (126) may be disposed on the conductive layer (150), and a part of the gate electrode (125) may also be disposed on the conductive layer (150).

[0158] For example, the gate structure (GS) and the conductive layer (150) may overlap by a third distance (d3) in the vertical direction, and the gate electrode (125) and the conductive layer (150) may overlap by a fourth distance (d4).

[0159] At this time, the fourth distance (d4) may be smaller than half of the third distance (d3), but is not limited thereto. Even in this case, since the side of the conductive layer (150) has a continuous slope with the side of the device isolation region (105), the conductive layer (150) can be understood to exist only within the device isolation region (105).

[0160] That is, the overlap between the conductive layer (150) and the gate electrode (125) can be achieved by extending the gate electrode (125) horizontally to cover the device isolation region (105).

[0161] The shape and material of the conductive layer (150) may be the same as those in FIGS. 3 to 5.

[0163] Referring to FIG. 8, the image sensor (1c) of an exemplary embodiment of the present invention may be identical to the image sensor (1) of FIG. 5, except for the shape of the source / drain region (S / D) of the driving transistors (DX1, DX2).

[0164] Specifically, the source / drain region (S / D) of the driving transistors (DX1, DX2) may have an upper surface where the conductive layer (150) is at a higher level than one side (S1) of the substrate (101).

[0165] The conductive layer (150) may be a structure having a first partial depth (h2) that protrudes into the device isolation region (105) adjacent to the gate structure (GS) within the isolation structure (IS), specifically having a first partial depth (h2) that is embedded within the device isolation region (105), and a second partial depth (h3) that protrudes upward from one side (S1) of the substrate (101).

[0166] The depth of the first part (h2) may be greater than the depth of the second part (h3), but is not limited thereto. Accordingly, the depth of the conductive layer (150) may be greater than the conductive layer (150) of FIG. 5.

[0167] The upper region having a second partial depth (h3) of the conductive layer (150) may be in contact with the side of the gate spacer (126), and the lower region having a first partial depth (h2) may be in contact with the side of the conductive region (151), and the sides of the upper region and the lower region may have a continuous slope, but are not limited thereto.

[0168] At this time, the second portion depth (h3) of the upper region of the conductive layer (150) may be greater than the thickness of the gate insulating layer (128) and smaller than the thickness of the gate electrode (125). The level of the upper surface of the conductive layer (150) may be located lower than the level of the upper surface of the gate electrode (125).

[0169] The material of the conductive layer (150) may be the same as that in FIGS. 3 to 5.

[0171] Referring to FIG. 9, the image sensor (1d) of an exemplary embodiment of the present invention may be identical to the image sensor (1) of FIG. 5, except for the shape of the source / drain region (S / D) of the driving transistors (DX1, DX2).

[0172] Specifically, the source / drain region (S / D) of the driving transistors (DX1, DX2) may have an upper width (W3) of the conductive layer (150) that is smaller than the upper width (W2) of the device isolation region (105). In the driving transistors (DX1, DX2) having a conductive layer (150) that fills the device isolation region (105), the conductive layer (150) of the source / drain region (S / D) is not shared with the source / drain region (S / D) of the adjacent driving transistors (DX1, DX2).

[0173] When the upper surface of the device isolation region (105) where the conductive layer (150) is disposed has a second width (W2), the conductive layer (150) may have a fourth width (W4) from one side in contact with the conductive region (151) of the corresponding driving transistors (DX1, DX2), and the fourth width (W4) may be smaller than the second width (W2). Thus, the upper surface of the device isolation region (105) may be disposed in succession, forming a co-plane with the upper surface of the conductive layer (150).

[0174] The material of the conductive layer (150) may be the same as that in FIGS. 3 to 5.

[0176] Referring to FIG. 10, the image sensor (1e) of an exemplary embodiment of the present invention may be identical to the image sensor (1) of FIG. 5, except for the shape of the source / drain region (S / D) of the driving transistors (DX1, DX2).

[0177] Specifically, the source / drain region (S / D) of the driving transistors (DX1, DX2) may have a width of the conductive layer (150) greater than the width of the device isolation region (105). The conductive layer (150) is positioned over the device isolation region (105) and does not fill the device isolation region (105). Thus, the lower surface of the conductive layer (150) contacts the upper surface of the device isolation region (105), and the upper surface may be located at a higher level than one surface (S1) of the substrate (101).

[0178] At this time, the conductive layer (150) can cover the entire width of the device isolation region (105) and extend toward the gate electrode (125) of the driving transistors (DX1, DX2). Thus, at least a portion of the conductive layer (150) can overlap vertically with the conductive region (151).

[0179] The conductive region (151) does not overlap horizontally with the gate electrode (125), and some parts overlap vertically with the gate spacer (126), while the remainder overlaps vertically with the conductive layer (150). At this time, the sides of the conductive layer (150) and the gate spacer (126) may be spaced apart so that a part of the conductive region (151) is exposed between the conductive layer (150) and the gate spacer (126), but is not limited thereto.

[0180] However, in order to maximize the area of ​​the gate electrode (125), the gate electrode (125) may be extended so that the side of the gate spacer (126) and the conductive layer (150) come into contact.

[0181] In this way, the conductive layer (150) can be formed so as to overlap with the device separation region (105) on the device separation region (105) without burying the device separation region (105), and can be arranged in a state where current can be conducted by contacting the conductive region (151) at the interface (Sc) vertically rather than sideways.

[0182] The material of the conductive layer (150) may be the same as that in FIGS. 3 to 5.

[0184] Referring to FIG. 11, the image sensor (1f) of an exemplary embodiment of the present invention may be identical to the image sensor of FIG. 5, except for the shape of the separation structure (IS).

[0185] Specifically, a trench isolation layer may not be placed below the device isolation region (105) that overlaps with the conductive layer (150). This allows a source / drain region (S / D) to be formed by stacking a conductive layer (150) different from the substrate (101) not only on the device isolation region (105) on the trench isolation layer (103) defining each pixel region (PA), but also on the device isolation region (105) within the pixel region (PA).

[0186] The shape and material of the conductive layer (150) may be the same as those in FIGS. 3 to 5.

[0188] Hereinafter, pixel regions in which a pixel circuit different from that of FIG. 2 is implemented are described with reference to FIG. 12 to FIG. 14.

[0189] FIG. 12 is a simplified circuit diagram showing a pixel circuit according to an exemplary embodiment of the present invention, and FIG. 13 and FIG. 14 are layout diagrams of an image sensor according to an exemplary embodiment of the present invention.

[0190] Referring to FIG. 12, a pixel circuit (PX) according to an exemplary embodiment of the present invention may include eight transfer transistors (TX1-TX8) and eight photodiodes (PD1-PD8) respectively connected thereto, and may include a reset transistor (RX), a select transistor (SX), and four driving transistors (DX1-DX4). Additionally, the pixel circuit (PX) may include a floating diffusion region (FD) in which charges generated from the photodiodes (PD1-PD8) are accumulated.

[0191] Floating diffusion regions (FD) may be allocated one per four transfer transistors (TX1-TX4 / TX5-TX8) and may include two floating diffusion regions (FD1, FD2), and the two floating diffusion regions (FD1, FD2) may be connected to each other.

[0192] In this embodiment, four driving transistors (DX1-DX4) are included to amplify the voltage change accumulated in the integrated floating diffusion region (FD) and output it to the column lines (COL). To this end, the four driving transistors (DX1-DX4) can be connected in parallel with each other and each include gate electrodes having the maximum area to minimize noise.

[0193] The reset transistor (RX) is controlled by a reset control signal, and the select transistor (SX) can be controlled by a select control signal. The first to eighth transmission transistors (TX1-TX4 / TX5-TX8) can be controlled by a first or second bias voltage, which is a transmission signal.

[0194] Each pixel (PX) can be structured into a single pixel region (PA), and the single pixel region (PA) may include eight sub-pixel regions (PA1-PA8) as shown in FIG. 13. The eight sub-pixel regions (PA1-PA8) may be arranged in a 4x2 configuration. Among the eight sub-pixel regions (PA1-PA8), the first to fourth sub-pixel regions (PA1-PA4) may be arranged in a 2x2 configuration and may include a first common floating diffusion region (FD1) at the center. Specifically, the first sub-pixel region (PA1) may include a first photodiode (PD1), at least a portion of the common floating diffusion region (FD1), and a first transfer transistor (TX1) having a first transfer gate (TG1). In the first pixel region (PA1), the first photodiode (PD1) may be connected to the common floating diffusion region (FD) through the first transfer transistor (TX1). Likewise, the second to fourth photodiodes (PD2-PD4) of the second to fourth subpixel regions (PA2-PA4) can be connected to the first common floating diffusion region (FD1) through the second to fourth transmission transistors (TX2-TX4), each comprising the second to fourth transmission gates (TG2-TG4).

[0196] Among the eight subpixel regions (PA1-PA8), the fifth to eighth subpixel regions (PA5-PA8) are arranged in a 2x2 configuration and may include a second common floating diffusion region (FD2) at the center. The fifth subpixel region (PA5) may include a fifth photodiode (PD5), at least a portion of the common floating diffusion region (FD), and a fifth transfer transistor (TX5) having a fifth transfer gate (TG5). In the fifth pixel region (PA5), the fifth photodiode (PD5) may be connected to the common floating diffusion region (FD) through the fifth transfer transistor (TX5). Likewise, the 6th to 8th photodiodes (PD6-PD8) of the 6th to 8th subpixel regions (PA6-PA8) can be connected to the 2nd common floating diffusion region (FD2) through 6th to 8th transmission transistors (TX6-TX8) each comprising 6th to 8th transmission gates (TG6-TG8).

[0198] In four adjacent subpixel regions (PA1-PA4, PA5-PA8), a common floating diffusion region (FD1, FD2) can be understood as a single structure connected to one another, extending from the center of the four subpixel regions (PA1-PA4, PA5-PA8) to each of the four subpixel regions (PA1-PA4, PA5-PA8). For example, as shown in FIG. 13, it may include four bar-type regions extending to each of the four subpixel regions (PA1-PA4, PA5-PA8) passing through the center region of the four subpixel regions (PA1-PA4, PA5-PA8), and may include extended regions at each end. The common floating diffusion regions (FD1, FD2) connected to the four subpixel regions (PA1-PA4, PA5-PA8) may be connected to one another through circuit wiring.

[0199] Eight adjacent sub-pixel regions (PA1-PA8) may share a pixel circuit, and the shared pixel circuit may include ground regions (GND), a reset transistor (RX), first to fourth driving transistors (DX1-DX4), and a select transistor (SX).

[0200] For example, each of the eight subpixel regions (PA1-PA8) may include one additional transistor or ground region (GND) in addition to the transmission transistors (TX1-TX8). Among the transistors included in the eight subpixel regions (PA1-PA8), four may be connected in parallel to provide first to fourth driving transistors (DX1-DX4), one may be provided as a select transistor (SX), another as a reset transistor (RX), and the remainder as a ground region (GND).

[0201] The first to fourth driving transistors (DX1-DX4) are connected in parallel with each other and are placed in adjacent sub-pixel regions ((PA3, PA4, PA5, PA6)), and can be arranged symmetrically with respect to the center (n1) of the pixel region (PA).

[0202] For example, the transistors of the third, fourth, fifth, and sixth subpixels (PA3, PA4, PA5, PA6) can function as driving transistors (DX1-DX4). The drain regions of the four driving transistors (DX1-DX4) are densely packed toward the center of the sub-region, and a common conductive layer (156) connecting the drain regions simultaneously can be disposed.

[0203] Specifically, the drain regions of the four driving transistors (DX1-DX4) each include the conductive regions (151) of FIGS. 3 to 5, and a common conductive layer (156) that is in contact with at least a portion of the conductive region (151) may be disposed on the separation structure (IS).

[0204] The common conductive layer (156) may embed at least a portion of the device isolation region (105) as in FIG. 5 and may simultaneously contact four conductive regions (151) from the side, but is not limited thereto, and various structures of the conductive layer (156) of FIG. 6 to FIG. 11 may be applied.

[0205] In this way, the drain regions of four adjacent driving transistors (DX1-DX4) are connected to a common conductive layer (156), so that they can be driven by a single contact plug (155) that contacts the common conductive layer (156).

[0206] Although FIG. 13 illustrates that the conductive layer (156) also performs the function of wiring for connecting each of the drain regions, it can be understood as an expansion of the drain region or placement on the device isolation region (105) of the drain region, which can induce an expansion of the area of ​​the gate electrode (125) of the driving transistors (DX1-DX4). Accordingly, the source regions of the driving transistors (DX1-DX4) may also include a conductive layer (154) connected on the device isolation region (105).

[0208] In FIG. 13, a first conductive layer (154) connecting the source region of a driving transistor (DX1-DX4) and the drain of a selection transistor (SX) and a second conductive layer (158) connecting the ground region of an adjacent pixel region and the ground region of the pixel region may be arranged.

[0209] In addition to the first and second conductive layers (150), additional conductive layers (150) that can function as circuit wiring at the point of connection in the pixel circuit of FIG. 12 may be placed.

[0210] These first and second conductive layers (150) can also be placed on the device isolation region (105) to secure the area of ​​the gate electrode (125) of the circuit element.

[0212] Meanwhile, referring to FIG. 14, the pixel circuit of FIG. 12 has four driving transistors (DX1-DX4) arranged in a folded form and may have a structure that is folded at the corners of the separation structure (IS).

[0213] Each driving transistor (DX1-DX4) extends in the x direction and may include a region that is bent at the corner and extends in the y direction. Each driving transistor (DX1-DX4) may include a drain region (D) at both ends and a source region (S) at the corner.

[0214] A gate structure (GS) may be placed between the drain region (D) and the source region (S) at both ends. Accordingly, the shape of the gate electrode (125) may have a dumbbell shape arranged diagonally as in FIG. 14, but is not limited thereto.

[0215] In this way, the drain regions (D) of one end of the driving transistors (DX1-DX4) are arranged symmetrically with respect to the center (n1) of the pixel region, and a conductive layer (156) connecting them can be arranged.

[0216] A source conductive layer (159) connecting adjacent source regions(s) of driving transistors (DX1-DX4) may be further disposed, and a connecting conductive layer (154) connecting the drain region of the reset transistor (RX) and the drain region of the driving transistors (DX1-DX4) may be further included.

[0217] In this way, if additional conductive layers (154, 159) are arranged, the wiring can be drastically reduced, and the number of contact plugs (155, 157) can also be reduced.

[0219] FIG. 15 shows a cross-section of an image sensor according to an exemplary embodiment of the present invention.

[0220] Referring to FIG. 15, the image sensor (10i) may include a third structure (L3) forming a logic circuit (20), a second structure (L2) positioned below the third structure (L3) and forming a pixel array (10), and a first structure (L1) below it.

[0221] The image sensor (10i) may include a first structure (L1) including a first substrate (101), a second structure (L2) including a second substrate (301), and a third structure (L3) including a third substrate (401). The third structure (L3) may be a logic chip including a logic circuit (20), and the second and first structures (L1, L2) may be image sensor structures including a plurality of pixels (PX). The first structure (L1) may include a driving transistor (DX) and a transmission transistor (TX), and the second structure (L2) may include the remaining transistors excluding the driving transistor (DX) and the transmission transistors (TX).

[0222] The first structure (L1) includes a driving transistor (DX), a transmission gate (TG1-TG4), a common floating diffusion region (FD), and photodiodes (PD1-PD4) among the structures of the first substrate (101) described in FIGS. 1 to 5, and may include a first bonding structure (166, 169) on the upper side. The first structure (L1) may include an optical part (170) on the other side of the first substrate (101), and the description thereof may be the same as in FIG. 4.

[0224] The second structure (L2) may include a second substrate (301) having a lower surface facing the first structure (L1) and an upper surface facing the lower surface, a device isolation film (305) defining an active region (310) within the second substrate (301), circuit elements (320) on the upper surface of the second substrate (301), a wiring region (375) connected to the circuit elements (320), a second lower bonding structure (390, 393) on the lower surface of the second substrate (301), a second upper bonding structure (385) on the upper surface of the second substrate (301), a second lower insulating layer (380) on the lower surface of the second substrate (301), and a second upper insulating layer (370) on the upper surface of the second substrate (301).

[0225] The second circuit elements (320) may have transistors disposed therein, excluding the transmission gates (TG1-TG4). The wiring region (375) may be disposed between the second substrate (301) and the third structure (L3). The wiring region (375) may apply an electrical signal to the second circuit elements (320). The second upper bonding structure (385, 369) may be a structure for bonding with the third structure (L3). The second upper bonding structure (385, 369) may include a metallic material such as copper (Cu), but may otherwise be implemented as a bonding insulating layer.

[0226] The second lower insulating layer (380) may include a bonding insulating layer (393) of a predetermined thickness from the lower surface. The bonding insulating layer (393) may be a layer for dielectric-dielectric bonding with the bonding insulating layer (166) of the first structure (L1).

[0227] The second lower bonding structure (390) may be a structure for bonding with the first structure (L1). The second lower bonding structure (390) may include a third bonding pad (391) on the lower surface of the second substrate (301), a landing structure (397) disposed on the upper surface of the second substrate (301), a third bonding via (395) disposed between the third bonding pad (391) and the landing structure (397), and a side insulating layer (396) between the second substrate (301) and the third bonding via (395). The third bonding pad (391) may include a metallic material such as copper (Cu), and the third bonding via (395) may include a metallic material such as copper (Cu) or tungsten (W). The third bonding pad (391) may include the same metallic material as the third bonding via (395), but is not limited thereto.

[0229] The third structure (L3) may include a third substrate (401), a third wiring structure (430) connected to the third circuit elements (420), a third bonding structure (440) on the third wiring structure (430), and a logic insulating layer (440) covering the third circuit elements (420) and the third wiring structure (430) on the third substrate (401). The third bonding structure (469, 466) may be connected to the third wiring structure (430) on the wiring structure (430). The third bonding structure (469, 466) may include a metallic material such as copper (Cu). The third bonding structure (469, 466) may include a bonding pad (469) to provide an electrical connection path. The logic insulating layer (440) can cover the third circuit elements (420) and the third wiring structure (430) while also covering a portion of the third bonding structure (469, 466).

[0230] In this way, an image sensor chip including a pixel array is separated into two structures (L1, L2), and hybrid bonding is performed between the structures (L1, L2) using a bonding structure (390) to electrically connect them, thereby enabling the implementation of an image sensor (1i) by hybrid bonding of three structures (L1, L2, L3).

[0232] Hereinafter, a method for manufacturing an image sensor of an exemplary embodiment of the present invention is described with reference to FIGS. 16a to 16g. FIGS. 16a to 16g are cross-sectional views for describing a method for manufacturing a pixel array of the image sensor (1) of FIG. 4.

[0234] Referring to FIG. 16a, a substrate (101) can be prepared, and a device isolation region (105) and a trench isolation film (103) can be formed from one side (S1) of the substrate (101).

[0235] Specifically, a photodiode (PD1-PD4) is formed within a substrate (101), and a device isolation region (105) defining an active region (ACT) on one side (S1) of the substrate (101) can be formed by forming a trench and filling the trench. At this time, an oxide film can be formed on the inner wall of the trench, and then a nitride film can be formed as a liner.

[0236] A portion of the device isolation region (105) may be opened to form a deep trench for forming a trench isolation film (103), and the deep trench may be formed in a grid shape to partition each sub-pixel region (PA1-PA4). Additionally, the deep trench may be formed in the X direction and the Y direction to form the second-1 isolation film (103a) and the second-2 isolation film (103b) among the trench isolation films (103).

[0237] That is, after forming a deep trench from the bottom surface of the device isolation region (105), a trench liner (104) can be formed, and a trench isolation film (103), which is a conductive material, can be formed in the center. The conductive material can be polysilicon laminated. Next, a device isolation insulating film can be formed by filling the trench over the device isolation region (105).

[0238] At this time, an insulating material can be over-deposited and then flattened until one side of the substrate is exposed to form a device isolation region (105).

[0240] Referring to FIG. 16b, a portion of the device isolation region (105) in the area where the driving transistors (DX1, DX2) are placed can be removed to form a first opening (OP1) corresponding to the conductive layer (150).

[0241] At this time, the first opening (OP1) can be formed by etching the device isolation region (105) to a second width (W2) and a second depth (d2), and may have different depths depending on the interlayer etching selectivity of the device isolation region (105), but overall it can be formed to have a second depth (d2).

[0243] As shown in Fig. 16c, the first opening (OP1) can be filled by depositing a preliminary conductive material.

[0244] First, cleaning can be performed to remove the natural oxide film. At this time, cleaning can be performed using an HF solution or dry cleaning. After cleaning, the first opening (OP1) can be filled, and a preliminary conductive material can be over-deposited to cover one side (S1) of the substrate.

[0245] The preliminary conductive material (150P) can be formed by depositing polysilicon or by epitaxially growing single-crystal silicon.

[0246] This can be flattened to form a preliminary conductive layer (150P) that fills the first opening (OP1). At this time, the flattening process may be performed by chemical mechanical polishing (CMP) and etch-back, but is not limited thereto. According to such a flattening process, the upper surface of the conductive layer (150P) may have a flat surface with one surface (S1) of the substrate (101).

[0248] Next, as shown in FIG. 16d, a transmission gate (TG1-TG4) and a gate structure (GS) of transistors can be formed. First, an opening is formed to open a region corresponding to the transmission gate (TG1-TG4), and the depth of the opening can be extended vertically into the substrate (101) so as to be close to the photodiode (PD1-PD4).

[0249] A gate insulating layer (128) can be formed on the inner surface of the opening and on one surface (S1) of the substrate (101). The step of forming the gate insulating layer (128) can be performed by removing a surface oxide film by carrying out a cleaning process as a pretreatment, and then depositing a silicon oxide film, etc., as the gate insulating layer (128). At this time, the gate insulating layer (128) can be formed entirely on the remaining area of ​​one surface (S1) of the substrate (101), specifically the area where transistors are formed, excluding the device isolation area (105). A conductive layer (125P) can be formed by filling the opening. At this time, the conductive layer (125P) can be formed by stacking polysilicon, etc., and can be formed to have conductivity by ion implanting after depositing polysilicon, etc. At this time, the conductive layer (125P) can be over-deposited on the entire one surface (S1) of the substrate (101) so that the conductive layer (125P) of other transistors is also formed simultaneously.

[0250] By patterning the conductive layer (125P), the gate electrode layers (125) of the transmission gates (TG1-TG4) and other transistors can be formed simultaneously. At this time, a gate insulating layer (128) may remain at the bottom of each gate electrode layer (125), and a gate spacer (126) may be formed on the side of the gate electrode (125).

[0252] Referring to FIG. 16e, a first conductivity type impurity can be ion-implanted onto a preliminary conductivity layer (150P) and a gate spacer (125).

[0253] For example, impurities such as P and As can be injected as the first conductivity type impurity. At this time, the first conductivity type impurity can also be injected into the floating diffusion region (FD), and the injection concentrations may differ, but are not limited thereto. Additionally, a ground region can also be formed by injecting impurities of different conductivity types.

[0254] Accordingly, conductive regions (151) can be formed below the gate spacer (126), and the source / drain region (S / D) of FIG. 4 can be formed by injecting a first conductive type impurity into the conductive layer (150).

[0256] As shown in Fig. 16f, after forming the substrate insulating layer (165), annealing can be performed to proceed with the activation, i.e., diffusion, of each implanted impurity ion.

[0257] Additionally, after annealing, a nitride film, which is an upper insulating layer (166), can be formed to protect the devices. At this time, the substrate insulating layer (165) and the upper insulating layer (166) can be formed conformally to the shape of each device.

[0259] As shown in FIG. 16g, after forming an interlayer insulating layer (160), contact plugs (155, 157) that penetrate the interlayer insulating layer (160) and contact each element can be formed.

[0260] Contact plugs (155, 157) can be formed by forming via holes, then forming diffusion barriers (155a, 157a), and then depositing and planarizing a metal layer to fill it. The diffusion barriers (155a, 157a) may be TiN, TaN, etc., and the metal layer may include a conductive material such as W, Al, Cu, etc. The via holes can be formed to reach the gate electrode layer (125) and can be formed to open the conductive layer (150).

[0261] Afterwards, upper wiring structures (158) can be formed and bonding structures (166, 169) can be formed, and as shown in FIG. 4, a second structure (L2) can be formed on the upper side and an optical part (170) can be formed on the other side (S2) of the substrate (101) to form the image sensor (1) of FIG. 4.

[0263] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

Claims

Claim 1 An image sensor comprising: a substrate including pixel regions each including a photoelectric conversion region; a floating diffusion region disposed on one side of the substrate at each of the pixel regions and storing a charge transferred from the photoelectric conversion region; circuit elements transmitting a photoelectric signal according to the charge in the floating diffusion region; and a device isolation region defining the floating diffusion region and the circuit elements on the one side of the substrate; wherein at least one of the circuit elements comprises a gate structure disposed on the one side of the substrate; and source / drain regions disposed on both sides of the gate structure, wherein at least one of the source / drain regions is disposed on the device isolation region and includes a conductive layer comprising a material different from the substrate and in contact with the substrate below the gate structure. Claim 2 In claim 1, the conductive layer comprises an image sensor comprising polysilicon containing a first conductive type impurity. Claim 3 The image sensor according to claim 1, wherein the image sensor comprises a trench separator separating the photoelectric conversion region within the substrate, wherein the device isolation region is disposed on the trench separator, and the conductive layer overlaps in a vertical direction with at least a portion of the trench separator. Claim 4 An image sensor according to claim 1, wherein the conductive layer includes an upper surface and a lower surface, the upper surface of the conductive layer forms a co-plane with the one surface of the substrate, and the lower surface of the conductive layer is located at a higher level than the lower surface of the device isolation region. Claim 5 In claim 1, the conductive layer extends downward from the upper surface of the device isolation region to fill the device isolation region, forming an image sensor. Claim 6 In claim 1, the gate structure comprises a gate insulating layer on one surface of the substrate; a gate electrode on the gate insulating layer; and gate spacers on both sides of the gate electrode, and in a planar manner, the conductive layer is spaced apart from the gate electrode and arranged in an image sensor. Claim 7 In claim 6, the source / drain region further comprises a conductive region extending downward from one surface of the substrate between the gate electrode and the conductive layer, in an image sensor. Claim 8 In claim 7, the image sensor in which the conductive region is defined as a region on the substrate doped with the first conductive type impurity. Claim 9 In claim 7, an image sensor in which circuit elements are arranged on both sides of the conductive layer, and the conductive layer contacts the conductive region of each of the circuit elements. Claim 10 In claim 9, the image sensor further comprises a contact plug electrically connected to the circuit elements, and the contact plug contacts the upper surface of the conductive layer. Claim 11 In claim 7, an image sensor comprising at least one of the circuit elements amplifying the charge in the floating diffusion region, the source follower buffer amplifier. Claim 12 In claim 11, the gate structure of the source follower buffer amplifier has a larger area than the gate structure of other circuit elements in the image sensor. Claim 13 In claim 7, the conductive layer includes a side between the upper surface and the lower surface, and the side among the side that contacts the conductive region has a continuous slope with the side of the device isolation region, an image sensor. Claim 14 In claim 1, the image sensor having an upper surface of the conductive layer located at a higher level than one surface of the substrate. Claim 15 In claim 14, the lower surface of the conductive layer forms a co-plane with the one surface of the substrate in the image sensor. Claim 16 An image sensor comprising: a substrate including pixel regions each including a photoelectric conversion region; a trench isolation region defining the pixel regions within the substrate; a floating diffusion region storing a charge transferred from the photoelectric conversion region on one side of the substrate; a driving transistor including a gate structure disposed adjacent to the trench isolation region and source / drain regions disposed on both sides of the gate structure, and amplifying the charge in the floating diffusion region to transmit a signal; and a device isolation region disposed on the trench isolation region on one side of the substrate and adjacent to the gate structure of the driving transistor; wherein at least one of the source / drain regions of the driving transistor is disposed on the adjacent device isolation region and overlaps in a vertical direction with the trench isolation region and comprises a semiconductor conductive layer having a material different from that of the substrate. Claim 17 In claim 16, at least one of the source / drain regions of the driving transistor is doped with a first conductivity type impurity from one surface of the substrate below the gate structure, and the image sensor further comprises a conductive region in contact with the semiconductor conductive layer. Claim 18 In claim 17, the semiconductor conductive layer protrudes inward from the upper surface of the device isolation region and contacts the conductive region from the side of the image sensor. Claim 19 In claim 16, the image sensor comprises, wherein the driving transistors are each disposed within two adjacent pixel regions among the pixel regions, the driving transistors are symmetrically disposed with respect to a trench separator, and the semiconductor conductive layer is shared. Claim 20 A pixel array comprising a plurality of pixel regions arranged along a direction parallel to one surface of a substrate, wherein each of the plurality of pixel regions comprises at least one photodiode inside the substrate, a color filter disposed on the other surface opposite to the one surface of the substrate, and at least one element disposed on the one surface; and a logic circuit for acquiring a pixel signal from the plurality of pixel regions; wherein the pixel array comprises: a floating diffusion region disposed on each of the plurality of pixel regions on the one surface of the substrate and storing a charge transferred from the photodiode; circuit elements that transmit a photoelectric signal according to the charge in the floating diffusion region; and a device isolation region defining the floating diffusion region and the circuit elements on the one surface of the substrate; and wherein at least one of the circuit elements is a gate structure disposed on the one surface of the substrate. An image sensor comprising a source / drain region disposed on both sides of the gate structure, wherein at least one of the source / drain region is disposed on the device isolation region and contacts the substrate below the gate structure, and comprises a conductive layer having a material different from that of the substrate.

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