Electronic devicvce and method for controlling tehreof

Abstract

The processor may include a processing core configured to process requests by accessing memory with virtual addresses, a cache memory (SRAM) that stores chunk data and a block table of the requested memory and can access physical addresses, a buffer that transmits information about address translation to process data requests from virtual addresses, and a Data Memory Controller (DMC) that allocates data to the cache memory or transmits stored data to the buffer based on information about address translation from the buffer.

Description

Technology Field

[0001] The present disclosure relates to an invention for a processor, and more specifically, includes an invention for a processor that increases the efficiency of memory space by allocating memory using a block table. Background Technology

[0002] Recently, as the usage frequency of LLM has increased, research on on-chip memory management methods to support it has become active.

[0003] However, conventionally, there was a problem in the attention module of the Transformer architecture where performance deteriorated as the memory requirement increased rapidly as the sequence length increased.

[0004] Accordingly, there is a recent demand to explore ways to increase memory usage efficiency and improve the utilization of on-chip memory. means of solving the problem

[0005] A processor according to one embodiment of the present disclosure may include: a processing core configured to process a request by accessing memory at a virtual address; a cache memory that stores chunk data and a block table of the requested memory; a buffer that transmits information regarding address translation to process a data request from the virtual address; and a Data Memory Controller (DMC) that allocates data to the cache memory or transmits stored data to the buffer based on information regarding address translation received from the buffer.

[0006] The above DMC can allocate a contiguous physical address space in the cache memory using information about the address translation received from the buffer.

[0007] The above DMC can receive information from the buffer regarding the virtual address, a lookup flag containing information on whether the virtual address is required to be converted to the physical address, and an end command containing information on whether the data requested chunk data is the last block.

[0008] The above DMC may store an allocation bitmap containing information on whether the chunk data is stored in the cache memory and the block table containing information on the physical address corresponding to the virtual address.

[0009] The above allocation bitmap is composed of a number of entries obtained by dividing the size of the cache memory by a preset block size, and the entries may include information that can be accessed to the physical address and information on whether data is stored in the cache memory corresponding to the physical address.

[0010] The block table above is composed of entries for the number of virtual addresses, and the entries can store information that can access the virtual address, a physical address corresponding to the virtual address, information about the number of chunk data continuously allocated from the virtual address to the cache memory, and information about the number of times the virtual address is called.

[0011] The above DMC maps and assigns the virtual address to a physical address stored in the cache memory based on the size of the virtual address and the requested data, and when reading data assigned to the cache memory, it can transmit the physical address obtained using the virtual address and the block table to the buffer.

[0012] When data requested for the above virtual address is allocated to a physical address of the above cache memory, the buffer transmits information regarding the size of the above virtual address and the above requested data to the DMC, allocates the data to the above cache memory using the allocation bitmap, and can update the block table based on the data allocated to the above cache memory.

[0013] The above buffer can transmit information regarding the virtual address and the requested data to the above DMC, obtain information regarding the physical address stored in the block table and the number of consecutive blocks based on the virtual address, and transmit the obtained information to the above buffer.

[0014] An electronic device according to one embodiment of the present disclosure includes a processor comprising a memory and a cache memory, a buffer and a Data Management Controlling (DMC), wherein the DMC stores an allocation bitmap and a block table in the cache memory that include information on whether data is allocated in the cache memory, and the block table includes a use count that includes information on a physical address allocated to the virtual address based on virtual address and data size information, the number of consecutively allocated chunk data, and the number of times the chunk data is used, and the buffer can obtain data regarding the translation of the virtual address and the allocation of the memory from a compiler.

[0015] The data obtained from the above compiler includes information regarding a virtual address, the block size to be allocated, and a use count, and the DMC can obtain the virtual address, the block size to be allocated, and the use count from the above buffer.

[0016] A physical address space with a large number of consecutive zeros in the above allocation bitmap can be identified, the block to be allocated in the identified space can be allocated in the cache memory, and the allocation bitmap and the block table can be updated.

[0017] If the block size to be allocated is larger than the physical address space corresponding to the number of consecutive zeros in the allocation bitmap, a block can be allocated to a space of consecutive zeros in the allocation bitmap, and the remaining block among the blocks to be allocated can be stored in the physical address corresponding to the consecutive zeros in the allocation bitmap.

[0018] The above buffer can transmit the virtual address, lookup flag, and AND command to the DMC for a data request to the DMC.

[0019] When the above lookup flag is set to 1, a physical address is obtained based on the virtual address obtained from the block table, and the data stored at the physical address (p_blk) obtained from the block table and the number of chunk data (cont) can be transmitted to the buffer.

[0020] When the above lookup flag is set to 0, data corresponding to the address obtained from the above buffer is transferred to the above buffer, and when the value of the above AND command is 1, the use count value stored in the above block table can be decreased by 1.

[0021] When the value of the AND command is 1, the use count value stored in the block table is decreased by 1, and then it is determined whether the use count value is 0. When it is determined that the use count value is 0, the block with the use count value of 0 can be removed from the cache memory.

[0022] A control method for an electronic device according to one embodiment of the present disclosure may include the steps of mapping and assigning a virtual address to a physical address stored in a cache memory based on a virtual address and the size of the requested data, and, when reading data assigned to the cache memory, transmitting the physical address obtained using the virtual address and the block table to a buffer.

[0023] When assigning the virtual address to a physical address stored in the cache memory, the method may include the steps of: the buffer transmitting information about the size of the virtual address and the requested data to the DMC; assigning the data to the cache memory; and updating the block table based on the data assigned to the cache memory.

[0024] The method may include the steps of: transmitting information regarding the virtual address and the requested data to the buffer to the DMC; obtaining information regarding the number of consecutive blocks and the physical address stored in the block table based on the virtual address; and transmitting the obtained information to the buffer. Brief explanation of the drawing

[0025] FIG. 1 is a drawing for explaining the configuration of a processor according to one embodiment of the present disclosure, and FIGS. 2 to 9 are drawings for explaining an embodiment of allocating data to a cache memory or reading or obtaining data stored in a cache memory according to an embodiment of the present disclosure. FIG. 10 is a flowchart for explaining a method of controlling an electronic device according to one embodiment of the present disclosure, and, FIG. 11 is a drawing for explaining the configuration of an electronic device (100) according to one embodiment of the present disclosure. Specific details for implementing the invention

[0026] The embodiments described herein are subject to various modifications and may have various forms; specific embodiments are illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the scope of specific embodiments and should be understood to include various modifications, equivalents, and / or alternatives of the embodiments of the present disclosure. In relation to the description of the drawings, similar reference numerals may be used for similar components.

[0027] In describing the present disclosure, if it is determined that a detailed description of related known functions or configurations could unnecessarily obscure the essence of the present disclosure, such detailed description is omitted.

[0028] Additionally, the following embodiments may be modified in various other forms, and the scope of the technical concept of the present disclosure is not limited to the following embodiments. Rather, these embodiments are provided to make the present disclosure more faithful and complete and to fully convey the technical concept of the present disclosure to those skilled in the art.

[0029] The terms used in this disclosure are used merely to describe specific embodiments and are not intended to limit the scope of the rights. The singular expression includes the plural expression unless the context clearly indicates otherwise.

[0030] In the present disclosure, expressions such as “have,” “may have,” “include,” or “may include” indicate the presence of such features (e.g., numerical values, functions, actions, or components such as parts) and do not exclude the presence of additional features.

[0031] In the present disclosure, expressions such as “A or B,” “at least one of A or / and B,” or “one or more of A or / and B” may include all possible combinations of items listed together. For example, “A or B,” “at least one of A and B,” or “at least one of A or B” may refer to cases including (1) at least one A, (2) at least one B, or (3) both at least one A and at least one B.

[0032] Expressions such as "first," "second," "first," or "second" used in this disclosure may modify various components regardless of order and / or importance, and are used only to distinguish one component from another and do not limit said components.

[0033] Where it is stated that a certain component (e.g., a first component) is "(operatively or communicatively) coupled with / to" or "connected to" another component (e.g., a second component), it should be understood that the said certain component may be directly connected to the said other component or connected through another component (e.g., a third component).

[0034] On the other hand, when it is stated that a certain component (e.g., a first component) is "directly connected" or "directly coupled" to another component (e.g., a second component), it may be understood that no other component (e.g., a third component) exists between said certain component and said other component.

[0035] As used in this disclosure, the expression “configured to” may be replaced, depending on the context, with, for example, “suitable for,” “having the capacity to,” “designed to,” “adapted to,” “made to,” or “capable of.” The term “configured to” may not necessarily mean only “specifically designed to” in hardware.

[0036] Instead, in some situations, the expression “device configured to do something” may mean that the device is “capable of doing something” together with other devices or components. For example, the phrase “processor configured (or set) to perform A, B, and C” may mean a dedicated processor for performing those operations (e.g., an embedded processor), or a generic-purpose processor (e.g., a CPU or application processor) capable of performing those operations by executing one or more software programs stored in a memory device.

[0037] In the embodiments, a 'module' or 'part' performs at least one function or operation and may be implemented in hardware or software, or a combination of hardware and software. Additionally, a plurality of 'modules' or a plurality of 'parts' may be integrated into at least one module and implemented by at least one processor, except for the 'module' or 'part' that needs to be implemented in specific hardware.

[0038] Meanwhile, the various elements and areas in the drawings are depicted schematically. Accordingly, the technical concept of the present invention is not limited by the relative sizes or spacing depicted in the attached drawings.

[0039] Hereinafter, various embodiments of the present invention will be described in detail using the attached drawings.

[0040] FIG. 1 is a drawing for explaining the configuration of a processor (100) according to one embodiment of the present disclosure. As shown in FIG. 1, the processor (100) may include a cache memory (110), a processing core (120), a buffer (130), and a Data Memory Controller (DMC) (140).

[0041] Meanwhile, the configuration of the processor (100) illustrated in FIG. 1 is merely one embodiment, and it goes without saying that some configurations may be deleted or added depending on the configuration of the processor (100).

[0042] Meanwhile, the system including the cache memory (110), processing core (120), buffer (130), and DMC (140) will be described later with the assumption of a processor for convenience of explanation, but the processor (100) can specifically be an accelerator processor or an on-chip memory management system.

[0043] First, the cache memory (110) is a configuration located between the computer's CPU and main memory (DRAM). The cache memory (110) can be used to temporarily store frequently used data to increase data access speed and optimize system performance. In this case, the cache memory (110) can be implemented using static RAM (SRAM) technology. Static RAM (SRAM) can alleviate bottlenecks between the CPU and DRAM by providing high speed and low latency. The cache memory (110) can minimize the CPU's data request time by storing recently used data or predicted data. The principles of the cache memory (110) may include temporal locality and spatial locality. Temporal locality may refer to the characteristic that recently used data is likely to be used again, and spatial locality may refer to the characteristic that data adjacent to recently used data is also likely to be used.

[0044] In particular, the cache memory (110) stores chunk data of the requested memory and can be accessed via a physical address.

[0045] In this context, chunk data refers to a portion of data divided into fixed-size units. In other words, chunk data can serve as the basic unit that can be stored in SRAM.

[0046] The processing core (120) may include one or more processing units. Specifically, the processing core (120) may be implemented as one of various types of processing units or as a combination of two or more of various types of processing units. When implemented as a combination of two or more processing units, the processing units included in the combination of processing units may operate in conjunction with each other or operate as an integrated unit. For example, the processing unit may be implemented as an NPU (Neural Processing Unit), or as one of an NPU, CPU (Central Processing Unit), GPU (Graphics Processing Unit), APU (Accelerated Processing Unit), MIC (Many Integrated Core), DSP (Digital Signal Processor), hardware accelerator, and machine learning accelerator. Additionally, the processing core (120) may be implemented as a combination of two or more of an NPU, CPU, GPU, APU, MIC, DSP, hardware accelerator, and machine learning accelerator.

[0047] A processing core (120) can control one or any combination of other components of an electronic device and can perform operations or information processing related to communication. One or more processing cores can execute one or more programs or instructions stored in memory. For example, one or more processing cores can perform a method according to one embodiment of the present disclosure by executing one or more instructions stored in memory. One or more processing cores may be implemented as a single core processor including one core, or as one or more multicore processors including multiple cores (e.g., homogeneous multicore or heterogeneous multicore). When one or more processing cores are implemented as multi-processing cores, each of the multiple cores included in the multicore processor may include internal processing core memory such as cache memory or on-chip memory, and a common cache shared by multiple cores may be included in the multicore processor. Additionally, each of the multiple cores included in the multi-core processor (or some of the multiple cores) may independently read and execute program instructions for implementing a method according to one embodiment of the present disclosure, or all (or some of) of the multiple cores may be linked to read and execute program instructions for implementing a method according to one embodiment of the present disclosure.

[0048] In particular, the processing core (120) can transmit information about the virtual address and the size of the data to the DMC (140). Additionally, the processing core (120) can use the DMC (140) to store or read data from the cache memory (110).

[0049] A buffer (130) is an intermediate medium for temporarily storing and processing data. In particular, the buffer (130) can transfer data between an SRAM (cache memory) and a compiler or processing core. Additionally, the buffer (130) can transfer information about address translation to process data requests from virtual addresses.

[0050] [Meanwhile, in the present disclosure, an intermediate medium for temporarily processing data will be described as a buffer (130) for convenience of explanation only. In particular, the buffer (130) may be a buffer control logic that is a memory type faster than SRAM in the form of a register file. In addition, the buffer (130) may be implemented in various forms such as volatile memory (e.g., DRAM (dynamic RAM) or SDRAM (synchronous dynamic RAM), etc.), non-volatile memory (e.g., OTPROM (one time programmable ROM), PROM (programmable ROM), EPROM (erasable and programmable ROM), EEPROM (electrically erasable and programmable ROM), mask ROM, flash ROM, flash memory (e.g., NAND flash or NOR flash, etc.), hard drive, or solid state drive (SSD).

[0051] Meanwhile, the buffer (130) can compensate for speed differences between the CPU and the disk, between the CPU and the network equipment, or between the CPU and the I / O device, and can prevent loss by temporarily storing data when the data consuming side is not ready to process it. Additionally, the operating principle of the buffer (130) can be distinguished into writing and reading. Specifically, a write operation may refer to an operation in which data is written from a producer (processor or device) to the buffer (130). Additionally, a read operation may refer to an operation in which data stored in the buffer (130) is transferred to a consumer (CPU or other device).

[0052] In particular, the buffer (130) can output to the DMC a look-up flag containing information on whether a conversion to a virtual address or a physical address is required, and an end command indicating that it is the last block in the memory chunk included in the data request.

[0053] At this time, the lookup flag may be a signal containing information on whether to refer to a block table to obtain a physical address mapped to a virtual address.

[0054] For example, when the lookup flag is 1, the DMC (140) can transfer data corresponding to the physical address written to p_blk based on the virtual address received from the block table, and the p_blk value and cont value of the block table to the buffer (130).

[0055] In this case, p_blk refers to the space where the physical address stored in the block table is stored, and cont may refer to the space where information regarding the number of times chunk data is stored consecutively is stored.

[0056] On the other hand, when the lookup flag is 0, the DMC (140) can transfer data corresponding to the received address to the buffer (130) without referring to the block table. Each of the above-described operations will be described later with reference to FIG. 5.

[0057] A Data Memory Controller (DMC) (140) can be a core hardware component that manages and optimizes the flow of data between a processing core (120) and memory in a computer system. Specifically, the DMC (140) can be a controller capable of efficiently performing data requests, memory management, or data transfer. The DMC (140) can ensure data integrity by managing the timing and order of data transfers and correcting errors, and can prevent data loss or damage through efficient processing and scheduling of data exchanges. Additionally, it can reduce the load on the CPU and increase system efficiency by enabling direct data transfer between an I / O device and main memory without direct intervention by the CPU.

[0058] In particular, the DMC (140) can perform the function of converting a virtual address obtained from a compiler or a buffer (130) into a physical address. Additionally, the DMC (140) can allocate data to a cache memory or transfer stored data to the buffer (130) based on information regarding address conversion from the buffer (130). Specifically, the DMC (Data Memory Controller) (140) can allocate a contiguous physical address space of the cache memory (or SRAM) (110) for a data request from a virtual address.

[0059] Additionally, the DMC (140) may store an allocation bitmap containing information on whether chunk data is stored in the cache memory (110) and a block table storing information on physical addresses corresponding to virtual addresses.

[0060] At this time, the block table is composed of entries for the number of virtual addresses, and the entries can store information that can be accessed via the virtual address, a physical address (p_blk) corresponding to the virtual address, information (cont) about the number of blocks continuously allocated from the virtual address to the cache memory (110), and information (use_count) about the number of times the virtual address is called. Specifically, the block table can record the physical address allocated to the virtual address based on the virtual address and the requested data size information, and can store use count information indicating the number of chunk data and how many times it is used continuously.

[0061] At this time, the allocation bitmap is composed of a number of entries divided by the size of the memory block of the cache memory (110), and the entries may include information that allows access to a physical address. Additionally, the allocation bitmap may include information regarding whether there is data in the cache memory (110) corresponding to the physical address.

[0062] Additionally, the processing core (120) may be configured to process requests by accessing memory at a virtual address.

[0063] The DMC (140) can map and assign a virtual address to a physical address stored in the cache memory (110) based on the virtual address and the size of the requested data. Additionally, when reading data assigned to the cache memory (110), the physical address obtained using the virtual address and block table can be transferred to the buffer (130).

[0064] At this time, when the DMC (140) assigns a virtual address to a physical address stored in the cache memory (110), the DMC (140) can receive information about the virtual address and the size of the requested data from the buffer (130). Additionally, data can be assigned to the cache memory (110) using an assignment bitmap, and a block table can be updated based on the data assigned to the cache memory (110).

[0065] Specifically, when transmitting physical address data based on virtual address information, the buffer (130) transmits the information to the DMC (140), and the DMC (140) can check the block table. At this time, chunk data, physical address, and the number of consecutive blocks based on the virtual address in the cache memory (110) can be transmitted to the buffer (130).

[0066] Meanwhile, the operation of each of the above-described SRAM (110), processing core (120), buffer (130), and DMC (140) will be described below with reference to FIGS. 2 to 6.

[0067] FIGS. 2 to 4 are drawings for explaining the operation of a DMC (140) storing chunk data in a cache memory (SRAM) based on a data request obtained from a compiler and a buffer, and then updating an allocation bitmap and a block table, according to one embodiment of the present disclosure.

[0068] First, the DMC (140) can receive a data request signal from the buffer (130) (S205). Specifically, the buffer (130) receives information about a virtual address, block size to be allocated, and use count from the compiler, and can transmit the virtual address, block size to be allocated, and use count to the DMC (140), or transmit the virtual address, lookup flag, and end command to the DMC (140) for a data request.

[0069] For example, as disclosed in FIGS. 3 and 4, the DMC (140) can obtain a data request signal of size 8KB from the buffer (130). At this time, the value of the use count included in the data request signal obtained by the DMC (140) can be '2', and the virtual address can be '6'.

[0070] At this time, the DMC can search for the allocated bitmap (S210).

[0071] Specifically, the DMC (140) can identify whether request data can be stored continuously in the SRAM (110) using the allocated bitmap.

[0072] At this time, the DMC (140) can identify whether there is enough continuous space to match the size of the requested data (S215).

[0073] For example, if the size of the requested data is 8KB, the DMC (140) can determine whether it can store 4 data consecutively in the SRAM after dividing the 8KB into 2KB chunks of data.

[0074] Additionally, the DMC (140) can allocate data to some of the spaces of the SRAM (110) identified in the allocation bitmap according to the identification result (S220).

[0075] If the DMC (140) identifies that the requested data can be stored continuously in the SRAM (110), it can store the chunk data continuously in the SRAM (110).

[0076] For example, as illustrated in FIG. 3, the size of the request data acquired by the DMC (140) may be 8KB. In this case, the DMC (140) may identify that 4 blocks are required in the SRAM (110) when storing (or allocating) 8KB of data.

[0077] The DMC (140) can identify whether there are four consecutive zeros among the multiple numbers stored in the allocation bitmap. If the DMC (140) identifies that there are four or more consecutive zeros as shown in the allocation bitmap of FIG. 3, it can identify that there are four consecutive empty spaces in the SRAM (110). The DMC (140) can store the requested data in the SRAM.

[0078] On the other hand, if the DMC (140) identifies that the requested data cannot be stored continuously in the SRAM (110), it can store chunk data discontinuously in the SRAM (110).

[0079] For example, as illustrated in FIG. 4, the requested data may be 8KB. In this case, the DMC (140) can identify that 4 blocks of space in the SRAM (110) are required to store 8KB of data.

[0080] The DMC (140) can identify whether there are four consecutive zeros among the multiple numbers stored in the allocation bitmap. After identifying that there are no four consecutive zeros in the allocation bitmap, the DMC can allocate four chunk data (or block data) discontinuously.

[0081] At this time, DMC (140) can update the allocated bitmap (S230).

[0082] For example, after the DMC (140) stores data in the SRAM (110), it can update the number of the allocated bitmap corresponding to the space stored in the SRAM (110) from '0' to '1'.

[0083] Additionally, DMC (140) can update the block table (S235).

[0084] As illustrated in FIG. 3, when data is stored in the SRAM (110), the physical address can be identified as 6 to 9. Additionally, the DMC (140) can be identified as a case where four chunks of data (or block data) are stored consecutively.

[0085] DMC (140) can update the block table using the identified information.

[0086] Specifically, the DMC (140) can store the physical address (p_blk) of the block table as 6 to 9 and also store information that the chunk data is stored four times consecutively.

[0087] Meanwhile, if DMC (140) obtains information from buffer (130) that the use count is 2, it can update the obtained information in the block table.

[0088] Meanwhile, the above-described FIG. 3 is an embodiment in which chunk data is stored continuously in the SRAM (110). However, this is only one embodiment, and as shown in FIG. 4, an embodiment in which chunk data is stored discontinuously in the SRAM (110) is also possible.

[0089] Specifically, as illustrated in FIG. 4, the DMC (140) can find the physical address space with the most consecutive zeros in the allocation bitmap, allocate the requested block size to the cache memory (110), and update the allocation bitmap and block table.

[0090] In this case, if the requested block size is larger than the physical address space of consecutive zeros, the DMC (140) can first allocate the block to the space of consecutive zeros and then repeat the same operation for the remaining blocks.

[0091] For example, the DMC (140) can identify that blocks 3 to 5 of the allocated bitmap have 3 consecutive zeros, and block 10 has 1 zero.

[0092] At this time, the DMC (140) can allocate chunk data (or blocks) to the SRAM (110) corresponding to 0 in the allocated bitmap.

[0093] After allocating blocks to blocks 3 through 5 and block 10 of the SRAM (110), the DMC (140) can update the block table.

[0094] For example, if three blocks are stored consecutively, the physical address is 3 to 5, and it can be identified as a case where three blocks are stored consecutively.

[0095] At this time, the DMC (140) can store physical addresses (p_blk) in the block table as 3 to 5, and the number of consecutive blocks as 3.

[0096] Additionally, it can be identified that a block is allocated to 10 blocks of the SRAM (110). In this case, the DMC (140) can store 1 in the block table because the physical address (p_blk) is 10 and the number of consecutive blocks is 1.

[0097] At this time, since the use count value obtained from the buffer (130) is '2', it is obvious that the value 2 can be stored in use_cnt (or use_count).

[0098] Meanwhile, an embodiment for allocating data to the cache memory (or SRAM) in response to a data request was described above.

[0099] Hereinafter, operations to search for a physical address by querying a block table or to read data directly will be described with reference to FIGS. 5 to 7.

[0100] FIG. 5 is a flowchart illustrating the operation of reading data stored in SRAM or obtaining a physical address using a lookup flag and a block table according to one embodiment of the present disclosure.

[0101] First, the DMC (140) can obtain a signal requesting data (S510).

[0102] Specifically, the DMC (140) can obtain virtual address, lookup flag information and end command information from the buffer (130).

[0103] At this time, DMC (140) can identify whether the lookup flag is 1 (S520).

[0104] If the DMC (140) identifies that the lookup flag is not 1 (S520-N), it can identify that the lookup flag is 0. Additionally, the DMC (140) can obtain the physical address of the SRAM (110) without using a block table.

[0105] This will be described later with reference to Fig. 6.

[0106] For example, as illustrated in FIG. 6, the DMC (140) can obtain information from the buffer (130) that the virtual address is '4', the lookup flag is '0', and the AND command value is '0'.

[0107] Specifically, if the lookup flag is '0', the DMC (140) contains information that the physical address can be obtained without using the block table, and if the AND command value is '0', it may mean that no additional action (e.g., decrementing the use count value or updating the allocation bitmap) is required because the requested data is not the last block.

[0108] At this time, since the lookup flag of DMC (140) is '0', data stored at the physical address of SRAM (110) can be obtained without using a block table.

[0109] Specifically, DMC (140) can identify that data is stored in physical address block 4 because the virtual address is 4 and the lookup flag is 0.

[0110] At this time, the DMC (140) can obtain data stored at physical address 4. In addition, the DMC (140) can transmit the obtained data to the buffer (130).

[0111] Meanwhile, if the DMC (140) identifies that the lookup flag is 1 (S520-Y), it can obtain the physical address (p_blk) that matches the virtual address, the cont value, and the use count value from the block table (S540). This will be described later with reference to FIG. 7.

[0112] As illustrated in FIG. 7, the DMC (140) can identify that the 'virtual address of the requested data' is 7, the lookup flag value is 1, and the AND command value is 0.

[0113] At this time, DMC (140) can identify that the virtual address of the requested data is 7, and that the block table must be referenced because the lookup flag value is 1. Also, since the AND command value is 0, it can be identified that the requested data is not the last block, so the operation to decrease the use count value by 1 is not performed.

[0114] At this time, since the virtual address of DMC (140) is 8, it can query the block table based on this.

[0115] Specifically, the DMC (140) can identify that the physical address (p_blk) mapped to virtual address 7 is 3. At this time, the DMC (140) can identify that there are 3 consecutive blocks (or chunk data, memory blocks).

[0116] At this time, DMC (140) can acquire data from SRAM (110) and then transfer the acquired data to a buffer (S550).

[0117] For example, the DMC (140) can obtain (or read) 2KB of data from block 3 at physical address stored in the SRAM (110). At this time, the DMC can transfer the data read from block 3 at physical address to a buffer.

[0118] Meanwhile, since the DMC (140) stores three blocks consecutively, it is possible to transfer data read from physical address blocks 4 and 5 to the buffer.

[0119] That is, DMC (140) can transmit information to the buffer (130) that the physical address (p_blk) is 3 and the number of times block data (or chunk data) is stored consecutively in the block (cont) is 3.

[0120] DMC (140) can identify whether the AND command value is 0.

[0121] At this time, if the DMC (140) identifies that the AND command value is 0 (S560-Y), it can process the data using the physical address obtained from the block table.

[0122] On the other hand, if the DMC (140) identifies that the AND command value is not 0 (S560-N), the value of the use count stored in the block table is decreased by 1, and the block data (or chunk data) with a use count value of 0 can be changed to 0 and released from the allocation bitmap (S580).

[0123] Specifically, DMC (140) can identify that the AND command value is 1. At this time, DMC can identify that the requested data is the last block. Therefore, the use count of the chunk data (or block data) can be decreased by 1.

[0124] This will be described later with reference to FIGS. 8 and FIGS. 9.

[0125] As shown in FIG. 8, the DMC (140) can identify that the virtual address is 3, the lookup flag is 1, and the AND command value is 1.

[0126] At this time, the DMC (140) can identify that the physical address mapped to virtual address 3 in the block table is block 3. Also, since the cont value is 3, the number of consecutive blocks can be identified as 3. For example, the DMC (140) can identify that blocks 3, 4, and 5 are stored consecutively.

[0127] Since DMC (140) has an end command value of 1, it can decrease the use count value of blocks 3 through 5 by 1.

[0128] At this time, the DMC (140) can identify that the use count of blocks 3 through 5 is 0 and remove the data of blocks 3 through 5. Additionally, the data of blocks 3 through 5 in the allocation bitmap can be updated from 1 to 0.

[0129] FIG. 9 is a diagram illustrating the operation of deleting data stored in SRAM and updating a bitmap according to one embodiment of the present disclosure.

[0130] DMC (140) can identify blocks in the block table that have a use count value of 0. After identifying blocks with a use count value of 0, DMC (140) can evict those blocks from SRAM. Additionally, it can update the value of the corresponding bitmap to 0.

[0131] Through the above-described operation, the DMC (140) can remove unnecessary data to secure space for storing new data. Afterward, during the Pre-load process, after allocating new data, the bitmap can be set to 1.

[0132] FIG. 10 is a flowchart illustrating a method for controlling an electronic device according to one embodiment of the present disclosure.

[0133] First, the electronic device (100) can map and assign a virtual address to a physical address stored in a cache memory based on the size of the virtual address and the requested data (S1010).

[0134] At this point, the step of allocating a physical address matching a virtual address or obtaining information regarding it has been described above, so a detailed explanation will be omitted.

[0135] When the electronic device (100) reads data allocated in the cache memory, it can transmit the physical address obtained using the virtual address and block table to the buffer (S1020).

[0136] Specifically, when the electronic device (100) acquires data allocated to the cache memory (or SRAM), if the lookup flag is 1, it can transfer the acquired physical address to the buffer using a block table.

[0137] On the other hand, when the lookup flag is 0, the electronic device (100) can transmit the physical address to the buffer without using a block table.

[0138] The various embodiments described with reference to FIGS. 1 to 9 can likewise be applied to the control method of an electronic device described with reference to FIG. 10.

[0139] FIG. 11 is a drawing for explaining the configuration of an electronic device (100) according to one embodiment of the present disclosure.

[0140] The configuration illustrated in FIG. 11 is merely an example of various embodiments, and some components may be omitted or new components may be added. As illustrated in FIG. 11, the electronic device (100) may include a memory (110) and a processor (120). The configuration illustrated in FIG. 11 is merely an example, and it goes without saying that some components may be deleted or added depending on the configuration of the electronic device (100).

[0141] The memory (110) may be implemented as static RAM (SRAM), and the data transfer speed, data access speed, etc., of SRAM may be faster than that of dynamic RAM (DRAM). However, the present disclosure is not limited thereto, and the memory (110) may be implemented in various forms other than SRAM. For example, the memory (110) may be implemented in various forms such as volatile memory (e.g., synchronous dynamic RAM) such as DRAM, SDRAM, etc., non-volatile memory (e.g., one-time programmable ROM, programmable ROM, EPROM, electrically erasable and programmable ROM, EEPROM, mask ROM, flash ROM, flash memory (e.g., NAND flash or NOR flash, etc.), hard drive, or solid state drive (SSD), in addition to SRAM.

[0142] The processor (120) may include one or more processing units. Specifically, the processor (120) may be implemented as one of various types of processing units or as a combination of two or more of various types of processing units. When implemented as a combination of two or more processing units, the processing units included in the combination of processing units may operate in conjunction with each other or operate as an integrated unit. For example, the processing unit may be implemented as an NPU (Neural Processing Unit), or as one of an NPU, CPU (Central Processing Unit), GPU (Graphics Processing Unit), APU (Accelerated Processing Unit), MIC (Many Integrated Core), DSP (Digital Signal Processor), hardware accelerator, and machine learning accelerator. Additionally, the processor (120) may be implemented as a combination of two or more of an NPU, CPU, GPU, APU, MIC, DSP, hardware accelerator, and machine learning accelerator.

[0143] The processor (120) can control one or any combination of other components of the electronic device and can perform operations or data processing related to communication. One or more processors can execute one or more programs or instructions stored in memory. For example, one or more processors can perform a method according to one embodiment of the present disclosure by executing one or more instructions stored in memory.

[0144] One or more processors may be implemented as a single-core processor comprising one core, or as one or more multicore processors comprising multiple cores (e.g., homogeneous multicore or heterogeneous multicore). When one or more processors are implemented as multicore processors, each of the multiple cores included in the multicore processor may include internal processor memory such as cache memory or on-chip memory, and a common cache shared by multiple cores may be included in the multicore processor. Additionally, each of the multiple cores included in the multicore processor (or some of the multiple cores) may independently read and execute program instructions for implementing a method according to one embodiment of the present disclosure, or all (or some) of the multiple cores may be linked together to read and execute program instructions for implementing a method according to one embodiment of the present disclosure.

[0145] In particular, the processor (120) may include a Data Memory Controller (DMC) that allocates data to a cache memory or transfers stored data to a buffer based on information about an address translation received (or obtained) from a buffer.

[0146] Additionally, the processor (120) can have the Data Memory Controller (DMC) allocate a contiguous physical address space in the cache memory using information about address translation obtained from the buffer. The processor (120) can have the DMC receive information from the buffer regarding a virtual address, a lookup flag containing information about whether the virtual address is required to be translated into a physical address, and an AND command containing information about whether it is the last block in the requested chunk of data.

[0147] The processor (120) may store an allocation bitmap containing information about whether chunk data is stored in the cache memory and a block table storing information about physical addresses corresponding to virtual addresses.

[0148] In this case, the allocation bitmap is composed of a number of entries equal to the size of the cache memory divided by a pre-set block size, and the entries may include information regarding which physical addresses can be accessed and information regarding whether data is stored in the cache memory corresponding to the physical address. The block table is composed of a number of entries equal to the number of virtual addresses, and the entries may store information regarding which virtual addresses can be accessed, the physical address corresponding to the virtual address (p_blk), information regarding the number of blocks continuously allocated from the virtual address to the cache memory (cont), and information regarding the number of times the virtual address is called (use_count).

[0149] The processor (120) maps and assigns a virtual address to a physical address stored in a cache memory based on the size of the virtual address and the data requested by the DMC, and when reading data assigned to the cache memory, it can transmit the physical address obtained using the virtual address and block table to a buffer.

[0150] When assigning a virtual address to a physical address stored in the cache memory, the buffer can transmit information about the virtual address and the size of the requested data to the DMC, allocate data to the cache memory using an allocation bitmap, and update the block table based on the data allocated to the cache memory.

[0151] The processor (120) can receive information about the virtual address and the requested data from the buffer, obtain information about the physical address stored in the block table and the number of consecutive chunk data based on the virtual address, and transmit the obtained information to the buffer.

[0152] The various embodiments described with reference to FIGS. 1 to 9 can likewise be applied to the operation of the electronic device described with reference to FIG. 11.

[0153] Additionally, methods according to various embodiments of the present disclosure may be provided by being included in a computer program product. The computer program product may be traded between a seller and a buyer as a product. The computer program product may be distributed in the form of a device-readable storage medium (e.g., compact disc read-only memory (CD-ROM)), or distributed online (e.g., download or upload) through an application store (e.g., Play Store™) or directly between two user (20) devices (e.g., smartphones). In the case of online distribution, at least a portion of the computer program product (e.g., downloadable app) may be temporarily stored or temporarily created in a device-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or a relay server.

[0154] A method according to various embodiments of the present disclosure may be implemented as software comprising instructions stored on a machine-readable storage medium (e.g., a computer). The machine may include a server device or an electronic device according to the disclosed embodiments, which is a device capable of calling instructions stored from the storage medium and operating according to the called instructions.

[0155] Meanwhile, a device-readable storage medium may be provided in the form of a non-transitory readable recording medium. Here, 'non-transitory readable recording medium' simply means that it is a tangible device and does not contain a signal (e.g., electromagnetic waves), and this term does not distinguish between cases where data is stored semi-permanently and cases where it is stored temporarily. For example, a 'non-transitory storage medium' may include a buffer in which data is stored temporarily.

[0156] When the above instruction is executed by a processor, the processor may perform the function corresponding to the instruction directly or by using other components under the control of the processor. The instruction may include code generated or executed by a compiler or an interpreter.

[0157] Although preferred embodiments of the present disclosure have been illustrated and described above, the present disclosure is not limited to the specific embodiments described above. It is understood that various modifications can be made by those skilled in the art without departing from the essence of the present disclosure as claimed in the claims, and such modifications should not be understood individually from the technical spirit or perspective of the present disclosure. Explanation of the symbols

[0158] 100: Processor 110: Cache memory 120: Processing core 130: Buffer 140: DMC (Data Memory Controller)

Claims

Claim 1 A processor comprising: a processing core configured to process a request by accessing memory by a virtual address; a cache memory that stores chunk data and a block table of the requested memory; a buffer that transmits information about address translation to process a data request from the virtual address; and a Data Memory Controller (DMC) that allocates data to the cache memory or transmits stored data to the buffer based on information about address translation received from the buffer. Claim 2 A processor according to claim 1, wherein the DMC allocates a contiguous physical address space in the cache memory using information regarding the address translation received from the buffer. Claim 3 A processor according to claim 1, wherein the DMC receives from the buffer information for the virtual address, a lookup flag including information on whether the virtual address is required to be converted to the physical address, and an AND command including information on whether the data is the last block in the requested chunk data. Claim 4 In claim 3, the processor, wherein the DMC stores an allocation bitmap containing information on whether the chunk data is stored in the cache memory and the block table containing information on the physical address corresponding to the virtual address. Claim 5 A processor according to claim 4, wherein the allocation bitmap is composed of a number of entries obtained by dividing the size of the cache memory by a predetermined block size, and the entries include information that can be accessed to the physical address and information that data is stored in the cache memory corresponding to the physical address. Claim 6 A processor according to claim 4, wherein the block table is composed of entries for the number of virtual addresses, and the entries store information that can access the virtual address, a physical address corresponding to the virtual address, information about the number of blocks continuously allocated from the virtual address to the cache memory, and information about the number of times the virtual address is called. Claim 7 A processor according to claim 1, wherein the DMC maps and assigns the virtual address to a physical address stored in the cache memory based on the virtual address and the size of the requested data, and when reading the data assigned to the cache memory, transmits the physical address obtained using the virtual address and the block table to the buffer. Claim 8 A processor according to claim 7, wherein when data requested for the virtual address is allocated to a physical address of the cache memory, the buffer transmits information about the size of the virtual address and the requested data to the DMC, allocates the data to the cache memory using the allocation bitmap, and updates the block table based on the data allocated to the cache memory. Claim 9 A processor according to claim 7, wherein the DMC receives information regarding the virtual address and the requested data from the buffer, obtains information regarding the number of consecutive chunk data and the physical address stored in the block table based on the virtual address, and transmits the obtained information to the buffer. Claim 10 An electronic device comprising: a memory; and a processor including a cache memory, a buffer, and a Data Management Controlling (DMC); wherein the DMC stores an allocation bitmap and a block table in the cache memory that include information on whether data is allocated in the cache memory, and the block table includes a use count that includes information on a physical address allocated to the virtual address based on virtual address and data size information, the number of consecutively allocated chunk data, and the number of times the chunk data is used, and the buffer obtains data regarding the translation of the virtual address and the allocation of the memory from a compiler. Claim 11 An electronic device according to claim 10, wherein the data obtained from the compiler includes information regarding a virtual address, information on the block size to be allocated, and a use count, and wherein the DMC obtains the virtual address, the block size to be allocated, and the use count from the buffer. Claim 12 An electronic device according to claim 11, which identifies a physical address space with a large number of consecutive zeros in the allocation bitmap, allocates the block to be allocated to the identified space in the cache memory, and updates the allocation bitmap and the block table. Claim 13 An electronic device according to claim 12, wherein, when the block size to be allocated is larger than the physical address space corresponding to the number of consecutive zeros in the allocation bitmap, the block is allocated to a space of consecutive zeros in the allocation bitmap, and the remaining block among the blocks to be allocated is stored in the physical address corresponding to the consecutive zeros in the allocation bitmap. Claim 14 In claim 10, the buffer is an electronic device that transmits the virtual address, lookup flag, and AND command to the DMC for a data request to the DMC. Claim 15 An electronic device according to claim 14, wherein when the lookup flag is set to 1, it obtains a physical address based on a virtual address obtained from the block table, and transmits data stored at the physical address obtained from the block table and the number of chunk data consecutively to the buffer. Claim 16 An electronic device according to claim 15, wherein when the lookup flag is set to 0, data corresponding to an address obtained from the buffer is transferred to the buffer, and when the value of the AND command is 1, the use count value stored in the block table is decreased by 1. Claim 17 An electronic device according to claim 16, wherein when the value of the AND command is 1, the use count value stored in the block table is decreased by 1, and then the use count value is identified as 0, and when the use count value is identified as 0, the block with the use count value of 0 is removed from the cache memory. Claim 18 A control method for an electronic device comprising: a step of mapping and assigning a virtual address to a physical address stored in a cache memory based on a virtual address and the size of the requested data; and a step of transmitting the virtual address and the physical address obtained using the block table to a buffer when reading data assigned to the cache memory. Claim 19 A control method according to claim 18, wherein when the virtual address is assigned to a physical address stored in the cache memory, the buffer transmits information about the size of the virtual address and the requested data to the DMC; assigns the data to the cache memory; and updates the block table based on the data assigned to the cache memory. Claim 20 A control method according to claim 18, comprising: a step of transmitting information about the virtual address and the requested data to the buffer to the DMC; a step of obtaining information about the number of consecutive blocks and the physical address stored in the block table based on the virtual address; and a step of transmitting the obtained information to the buffer.

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