Comparator and solid-state imaging device

Abstract

A comparator and a solid-state imaging element are provided that can achieve a wide dynamic range while simultaneously realizing a smaller area, higher speed, and lower power consumption of the image sensor. The comparator has one lamp signal input unit for inputting a lamp signal, a plurality of pixel signal input units for inputting pixel signals, and a comparator that compares the lamp signal input from the lamp signal input unit with the pixel signal input from any one of the plurality of pixel signal input units and outputs a comparison result.

Description

Technology Field

[0001] The present invention relates to a comparator and a solid-state imaging element. Background Technology

[0002] Recently, the miniaturization and high functionality of camera-equipped devices, such as mobile phones and digital cameras, have been progressing rapidly. For the miniaturization and high functionality of these devices, the reduction of the surface area, increased speed, and reduced power consumption of solid-state image sensors are important.

[0003] In addition, for solid-state imaging devices, a wide dynamic range, which represents the range of brightness that can be reproduced as an image, is also an important factor. As one method to obtain a wide dynamic range, for example, a method of synthesizing multiple frames with different brightness levels is known when the image obtained from a single exposure is considered as one frame. However, in this method, motion blur (blurring of the subject) may occur because the exposure timing of the same pixel in multiple frames is different. Furthermore, there are challenges such as the difficulty of performing signal processing for each frame in real time when generating a video or preview image by synthesizing multiple frames.

[0004] Meanwhile, in a single frame, the development of a technology to realize a wide dynamic range by using pixel signals of two different charge voltage conversion gains (hereinafter also simply referred to as "conversion gains") is also underway (for example, Patent Document 1 and Patent Document 2 below). In Patent Documents 1 and 2, a configuration is disclosed in which a comparison unit for each conversion gain is provided to compare a pixel signal and a ramp signal for two conversion gains, a high conversion gain and a low conversion gain. Prior art literature

[0005] (Patent Document 0001) JP 2022-36068 A1 (Patent Document 0002) US 2018-0302578 A1 The problem to be solved

[0006] In order to obtain a wider dynamic range, it is considered important to increase the ratio of the conversion gains in a pixel configuration having two or more conversion gains. However, in the technology of Patent Document 1, since an Analog-to-Digital (AD) converter is installed for each conversion gain, the frame rate may decrease, and power consumption and circuit area may increase. Furthermore, in the technology of Patent Document 2, an increase in the input capacity and differential area, which occupy a large area in the comparison unit, is unavoidable and may affect the cost. Therefore, when the number of conversion gains is multiple, the number of comparison units also becomes multiple according to the number of conversion gains, so an increase in the circuit area of ​​the solid-state image sensor is unavoidable.

[0007] The present invention was made to solve the above-mentioned problems. Accordingly, the main objective of the present invention is to provide a comparator and a solid-state imaging element capable of realizing a wide dynamic range of a single frame while suppressing an increase in the circuit area of ​​the comparator. means of solving the problem

[0008] The above objective of the present invention is achieved by the following.

[0009] (1) A comparator having an AD converter that converts an analog pixel signal into a digital signal, and a comparator that compares a ramp signal and the pixel signal, the comparator having: one ramp signal input unit that inputs the ramp signal; a plurality of pixel signal input units that each input the pixel signal; and a comparator that compares the ramp signal input from the ramp signal input unit with the pixel signal input from one of the plurality of pixel signal input units and outputs a comparison result.

[0010] (2) A comparator described in (1) having a selection unit for selecting one of the plurality of pixel signal input units.

[0011] (3) A pixel configuration configured to switchably convert a conversion gain corresponding to the ratio at which a charge generated in the pixel is converted into a voltage; and a comparator that inputs a pixel signal corresponding to the conversion gain from the pixel configuration to the pixel signal input unit; a solid-state imaging device having

[0012] (4) The above comparison unit sequentially compares the ramp signal and the pixel signal for each conversion gain, a solid-state imaging element described in any one of (1) to (3).

[0013] (5) The above comparison unit compares the pixel signal of the reset pixel configuration and the ramp signal for each conversion gain, and then compares the pixel signal corresponding to the captured image with the ramp signal, and is a solid-state imaging element described in any one of (1) to (4).

[0014] (6) The pixel signal input selected by the lamp signal input and the selection unit comprises a differential pair, and the differential pair comprises: a first transistor into which the lamp signal is input; a first switch for initializing the first transistor; a second transistor into which the pixel signal is input; and a second switch for initializing the second transistor; and immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor, the solid-state imaging element described in (5).

[0015] (7) The pixel configuration described above is a solid-state imaging element having a plurality of pixels with different sensitivities, as described in any one of (1) to (6).

[0016] (8) The above comparison unit compares the pixel signal from the plurality of pixels and the ramp signal for each pixel sequentially, a solid-state imaging element described in any one of (1) to (7).

[0017] (9 The above comparison unit compares the pixel signal of the reset pixel configuration and the ramp signal for each conversion gain, and then compares the pixel signal corresponding to the captured image with the ramp signal, the solid-state imaging element described in (7) or (8).

[0018] (10) The pixel signal input selected by the lamp signal input and the selection unit comprises a differential pair, and the differential pair comprises: a first transistor into which the lamp signal is input; a first switch for initializing the first transistor; a second transistor into which the pixel signal is input; and a second switch for initializing the second transistor; and immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor, the solid-state imaging element described in (9).

[0019] (11) The pixel configuration and the plurality of pixel signal input units are connected by a single wire. A solid-state imaging element described in any one of (1) to (10).

[0020] (12) The first switch is connected between the gate terminal and the source or drain terminal of the first transistor, and the second switch is connected between the gate terminal and the source or drain terminal of the second transistor.

[0021] A solid-state imaging device described in (6), wherein the first switch is turned on only once immediately after the reset of the pixel configuration, thereby connecting the gate terminal of the first transistor to the source or drain terminal, so that the first transistor is initialized, and for each conversion gain, the second switch corresponding to the conversion gain is turned on, thereby connecting the gate terminal of the second transistor to the source or drain terminal, so that the second transistor is initialized.

[0022] (13) The first switch is connected between the gate terminal and the source or drain terminal of the first transistor, and the second switch is connected between the gate terminal and the source or drain terminal of the second transistor, and the first switch is turned on only once immediately after the reset of the pixel configuration so that the gate terminal and the source or drain terminal of the first transistor are connected, thereby initializing the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on so that the gate terminal and the source or drain terminal of the second transistor are connected, thereby initializing the second transistor, the solid-state imaging device described in (10).

[0023] (14) The above comparison unit has a differential pair that differentially amplifies the ramp signal and the pixel signal, and the differential pair has a first switch that initializes a first transistor into which the ramp signal is input and a second switch that initializes a second transistor into which the pixel signal is input, and immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor, the solid-state imaging element described in (5).

[0024] (15) The above comparison unit has a differential pair that differentially amplifies the ramp signal and the pixel signal, and the differential pair has a first switch that initializes a first transistor into which the ramp signal is input and a second switch that initializes a second transistor into which the pixel signal is input, and immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor, the solid-state imaging element described in (9). Effects of the invention

[0025] In a solid-state imaging device according to the present invention, each comparator includes one ramp signal input unit that inputs a ramp signal and a plurality of pixel signal input units that input pixel signals. Accordingly, when the number of conversion gains in the pixel configuration is multiple, the number of pixel signal input units becomes multiple, but the number of comparators can be maintained at one. Accordingly, according to the comparator of the present invention, even if the number of conversion gains is multiple, the increase in circuit area can be suppressed, and even when the number of conversion gains in the pixel configuration is large, the decrease in the operating speed of the solid-state imaging device and the increase in power consumption can be suppressed. Brief explanation of the drawing

[0026] FIG. 1 is a schematic diagram illustrating the configuration of a solid-state imaging element according to a first embodiment. Figure 2 is a circuit diagram illustrating the pixel circuit shown in Figure 1. Figure 3 is a circuit diagram illustrating the configuration of the comparator shown in Figure 1. FIG. 4 is a flowchart illustrating an overview of the processing sequence in the solid-state imaging element shown in FIG. 1. Figure 5 is a timing chart illustrating an overview of the operation of the solid-state imaging element illustrated in Figure 1. FIG. 6 is a circuit diagram illustrating a pixel circuit of a solid-state imaging element according to a second embodiment. FIG. 7 is a circuit diagram illustrating the configuration of a comparator of a solid-state imaging element according to a second embodiment. FIG. 8 is a timing chart illustrating an overview of the operation of a solid-state imaging element according to a second embodiment. FIG. 9 is a graph illustrating a signal-to-noise ratio (SNR) curve for illuminance of a solid-state imaging element according to a second embodiment. FIG. 10 is a circuit diagram illustrating a pixel circuit of a solid-state imaging element according to a third embodiment. FIG. 11 is a timing chart illustrating an overview of the operation of a solid-state imaging element according to a third embodiment. FIG. 12 is a circuit diagram illustrating a pixel circuit of a solid-state imaging element according to a fourth embodiment. FIG. 13 is a timing chart illustrating an overview of the operation of a solid-state imaging element according to a fourth embodiment. Specific details for implementing the invention

[0027] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. In the drawings below, the same reference numerals indicate the same components, and in the drawings, the size of each component is expressed in a ratio different from that of the embodiments for clarity and convenience of explanation.

[0028] In the following, what is described as "upper" or "above" may include not only what is directly above in contact, but also what is above without contact.

[0029] A component expressed in the singular includes a plural component unless the context clearly implies otherwise. Also, when a specific part is said to "include" or "have" a specific component, this means that, unless specifically stated otherwise, it does not exclude other components but may additionally include other components.

[0030] In addition, the use of the term "above" and similar descriptive terms corresponds to either the singular or the plural.

[0031] Unless the order of the steps constituting the method is explicitly stated or otherwise explained, the steps are executed in the appropriate order. The use of any examples or exemplary terms (e.g., e.g., e.g.) is merely for illustrating the technical concept and, unless limited by the claims, the scope is not limited by such examples or exemplary terms.

[0032] FIG. 1 is a schematic diagram illustrating the configuration of a solid-state imaging element according to a first embodiment. FIG. 2 is also a circuit diagram illustrating a pixel circuit (pixel configuration) illustrated in FIG. 1.

[0033] As illustrated in FIG. 1, the solid-state imaging element (10) has a pixel array (11), a vertical scanning circuit (12), a ramp signal generation unit (13), a plurality of comparators (14), a plurality of counters (15), a plurality of latches (16), a horizontal scanning circuit (17), and a control unit (18). The ramp signal generation unit (13), the plurality of comparators (14), the plurality of counters (15), and the plurality of latches (16) constitute an analog-to-digital converter (AD converter, 20).

[0034] The pixel array section (11) has a plurality of pixel circuits (PX*) arranged in a two-dimensional manner (matrix arrangement) in the row direction and column direction. As illustrated in FIG. 2, in this embodiment, a pixel circuit (PX1) is described as an example of a pixel circuit (PX*). Other examples of pixel circuits (PX*) are described in the second to fourth embodiments.

[0035] Each pixel circuit (PX1) has a photoelectric conversion element (pixel) (PD), a transfer transistor (TT), a reset transistor (RT), a gain selection transistor (GT), an amplifier transistor (AT), and a selection transistor (ST). Each pixel circuit (PX1) converts incident light into a photoelectric element and outputs a pixel signal (VPIX) according to the amount of incident light. The photoelectric conversion element (PD) may be, for example, a photodiode, a phototransistor, etc.

[0036] The gate terminal, drain terminal, and source terminal of the reset transistor (RT) are respectively connected to the RST input terminal, the pixel power supply (VDDP), and the drain terminal of the gain select transistor (GT). A capacitance (CF1) of floating diffusion (FD) is formed between the connection between the source terminal of the reset transistor (RT) and the drain terminal of the gain select transistor (GT) and ground.

[0037] The gate terminal, drain terminal, and source terminal of the gain select transistor (GT) are respectively connected to the CGS1 input terminal, the source terminal of the reset transistor (RT), and the source terminal of the transfer transistor (TT).

[0038] The gate terminal, drain terminal, and source terminal of the transfer transistor (TT) are respectively connected to the TS input terminal, the cathode terminal of the photoelectric conversion element (PD), and the source terminal of the gain selection transistor (GT). A capacitance (CF2) of floating / diffusion (FD) is formed between the connection between the source terminal of the transfer transistor (TT) and the source terminal of the gain selection transistor (GT) and ground.

[0039] The gate terminal, drain terminal, and source terminal of the amplifier transistor (AT) are respectively connected to the source terminal of the transfer transistor (TT), the pixel power supply (VDDP), and the drain terminal of the select transistor (ST).

[0040] The gate terminal, drain terminal, and source terminal of the select transistor (ST) are respectively connected to the SEL input terminal, the source terminal of the amplifier transistor (AT), and the output terminal (POUT) of the pixel circuit (PX1). From the output terminal (POUT), a signal of a voltage level corresponding to the amount of charge accumulated in the floating diffusion (FD) is output.

[0041] As illustrated in FIG. 1, the pixel array unit (11) outputs analog pixel signals (VPIX.1 to VPIX.N) for the pixel circuits (PX1) of a row selected by the vertical scanning circuit (12). The pixel signals (VPIX.1 to VPIX.N) are pixel signals of the pixel circuits (PX1) of the first to the Nth column of the selected row. In this specification, a plurality of pixel circuits (PX1) arranged in a row direction are referred to as pixel rows, and a plurality of pixel circuits (PX1) arranged in a column direction are referred to as pixel columns.

[0042] The pixel circuit (PX1) of the present embodiment can operate with either one of two conversion gains: a high conversion gain and a low conversion gain. The conversion gain corresponds to the ratio at which the charge (electron) generated in the photoelectric conversion element (PD) is converted into voltage. The charge generated in the photoelectric conversion element (PD) is transferred to and accumulated in the floating diffusion (FD), and the charge accumulated in the floating diffusion (FD) is converted into voltage.

[0043] More specifically, in FIG. 2, when the pixel circuit (PX1) has a high conversion gain, the floating diffusion (FD) is configured by the capacitance (CF2). Meanwhile, when the pixel circuit (PX1) has a low conversion gain, the floating diffusion (FD) is configured by the capacitance (CF1 and CF2).

[0044] That is, when the pixel circuit (PX1) has a low conversion gain, the capacity of the floating diffusion (FD) in the pixel circuit (PX1) increases more than when the pixel circuit (PX1) has a high conversion gain. Therefore, when the same amount of charge is accumulated in the floating diffusion (FD), when the pixel circuit (PX1) has a low conversion gain, the potential due to the charge accumulated in the floating diffusion (FD) in the pixel circuit (PX1) decreases more than when the pixel circuit (PX1) has a high conversion gain.

[0045] The first of the seven 2016s, which were the first of the seven 2016s, was the second of the seven 2016s. The first of the 1016s, and the second of the 11, 2016s, was the 1, 2016, and the second of the 11, 201, 101, 201, 201, 201, 201, 101, and 101, 201, 101, and 101, 101, and 101, 101, and 101, 101, and 10162016, 2016, 2016, 2016, 2016, 2016, 2016,

[0046] The solid-state imaging element (10) can select whether to operate each pixel circuit (PX1) in a high conversion gain mode, which operates at a high conversion gain, and in a low conversion gain mode, which operates at a low conversion gain. In the example shown in FIG. 2, the conversion gain mode is selected by the CGS1 control signal. Hereinafter, the high conversion gain mode is also referred to as the "HCG (High Conversion Gain) mode" and the low conversion gain mode as the "LCG (Low Conversion Gain) mode".

[0047] When a plurality of pixel circuits (PX1) of the pixel array unit (11) operate in HCG mode, dark areas are clearly expressed in the generated image. Meanwhile, when a plurality of pixel circuits (PX1) of the pixel array unit (11) operate in LCG mode, dark areas are clearly expressed in the generated image.

[0048] In this embodiment, each pixel circuit (PX1) of a row selected by the vertical scanning circuit (12) can operate continuously in HCG mode and LCG mode during one readout period. In one frame, an image in which dark areas are clearly expressed by high conversion gain and an image in which bright areas are clearly expressed by low conversion gain are merged to create an image with a wide dynamic range.

[0049] The vertical scanning circuit (12) outputs a pulse signal to a signal line (VS.1 to VS.n) corresponding to the selected row in order to select one row among a plurality of pixel rows having the pixel array unit (11). The vertical scanning circuit (12) has a vertical decoder and a vertical driving circuit (both not shown). The vertical decoder decodes the position information of a pixel circuit (PX1) designated by the control unit (18) to designate a vertical readout row, that is, to select one row among a plurality of pixel rows. The vertical driving circuit drives the pixel circuit (PX1) by supplying a pulse signal to the pixel circuit (PX1) of the readout row designated by the vertical decoder.

[0050] The ramp signal generation unit (13) is a DA conversion circuit that supplies a ramp signal (VRAMP) to the AD conversion unit (20). The ramp signal generation unit (13) generates a voltage signal of a ramp wave (hereinafter referred to as "ramp signal") (VRAMP) in which the voltage level decreases monotonically over time, and converts an analog signal from the pixel circuit (PX1) into a digital signal.

[0051] The comparator (14) compares the ramp signal (VRAMP) generated by the ramp signal generation unit (13) with the pixel signal (VPIX) from the pixel array unit (11) and outputs the comparison result. VPIX represents any pixel signal among VPIX.1 to VPIX.N. The comparison result becomes a High level when, for example, the ramp signal (VRAMP) is greater than or equal to the pixel signal (VPIX), and a Low level when the ramp signal (VRAMP) is less than or equal to the pixel signal (VPIX). For example, the comparator (14) is configured to output a High level from the start of measurement of the pixel signal (VPIX) until the pixel signal (VPIX) and the ramp signal (VRAMP) cross each other, and to output a Low level after the pixel signal (VPIX) and the ramp signal (VRAMP) cross each other. Details regarding the configuration and function of the comparator (14) will be described later.

[0052] The counter (15) inputs the output signal of the comparator (14) as an enable signal and counts the enable period using a clock input of a predetermined period. The counter (15) counts the number of clocks input from the start of measurement until the pixel signal (VPIX) and the ramp signal (VRAMP) cross. The count result (count value) of this counter (15) becomes a digital value that digitizes the analog pixel signal (VPIX).

[0053] The counter (15) may be, for example, an up counter or a down counter. If the counter (15) is an up counter, the counter (15) counts up from an initial value of 0 during the period when the enable signal is active (high level). If the counter (15) is a down counter, the counter (15) counts down from an initial value of M during the period when the enable signal is active.

[0054] The latch (16) maintains (latches) the count value of the counter (15) and performs Correlated Double Sampling (CDS) processing. The latch (16) has a plurality (e.g., two) latch circuits and a subtraction circuit. The ADC (20) performs AD conversion twice, in an RST phase corresponding to a reset level pixel signal (VPIX) and a SIG phase corresponding to a signal level pixel signal (VPIX). The reset level corresponds to the output level (DARK level) from the pixel circuit (PX1) immediately after being reset. The output signal from the pixel circuit (PX1) immediately after being reset may contain noise such as fixed pattern noise or reset noise. The signal level corresponds to the output level of the image captured of the subject. The signal level may also contain the above noise. The latch circuit maintains the count value of the counter (15) in the RST phase and the SIG phase. The count value held in the latch (16) is called the “AD conversion value”.

[0055] The latch (16) performs CDS processing by calculating the difference between the count value corresponding to the signal level pixel signal (VPIX) and the count value corresponding to the reset level pixel signal (VPIX). Through CDS processing, the deviation of the pixel signal (VPIX) for each pixel circuit (PX1) is removed. That is, by subtracting the count value of the counter (15) in the RST phase from the count value of the counter (15) in the SIG phase, noise such as fixed pattern noise or reset noise of the pixel value containing the deviation for each pixel circuit (PX1) can be removed. By doing so, the pixel value corresponding to the signal level after noise removal is extracted. The latch (16) outputs the difference to the horizontal transmission line (HTR) in synchronization with the driving signal (HS.1~HS.N) supplied from the horizontal scanning circuit (17).

[0056] Additionally, the subtraction between the count value of the SIG phase and the count value of the RST phase can be performed using an up-down counter. In this case, the counter (15) has an up-down counter, and the latch (16) is omitted. The counter (15) counts down during the RST phase and counts up during the SIG phase. By doing so, the subtraction between the count value of the SIG phase and the count value of the RST phase is performed equivalently within the counter (15), and the count value corresponding to the result of this subtraction is maintained in the counter (15). That is, through two count processing steps of counting down during the RST phase and counting up during the SIG phase, noise such as fixed pattern noise or reset noise of pixel values ​​including deviations for each pixel circuit (PX1) can be removed. By doing so, a pixel value corresponding to the signal level after noise removal is extracted.

[0057] The horizontal scanning circuit (17) outputs a pulse signal to a selection signal line (HS) corresponding to the selected column in order to select one column among a plurality of pixel columns having the pixel array unit (11). HS represents any selection signal line among HS.1 to HS.N. The horizontal scanning circuit (17) has a horizontal decoder and a horizontal driving circuit (both not shown). The horizontal decoder decodes the position information of the pixel circuit (PX1) designated by the control unit (18) to designate a horizontal readout column, that is, to select one column among a plurality of pixel columns. The horizontal driving circuit supplies a pulse signal to the latch (16) of the readout column designated by the horizontal decoder to read out the data held in the latch (16).

[0058] The control unit (18) generates various timing signals and control signals, and based on the generated signals, performs driving control of the vertical scanning circuit (12), ramp signal generation unit (13), horizontal scanning circuit (17), AD conversion unit (20), etc. The timing signals include, for example, a reset signal, and the control signals include, for example, a CGS1 signal, a TS signal, a SEL signal, a PC1 signal, a PC2 signal, an R1 signal, a P1 signal, a P2 signal, etc.

[0059] FIG. 3 is a circuit diagram illustrating the configuration of the comparator (14) shown in FIG. 1. The comparator (14) has a current mirror circuit (140), a ramp signal input section (141), a first pixel signal input section (142), a second pixel signal input section (143), a selection section (145), an output circuit (146), and a bias circuit (147).

[0060] The ramp signal input section (141) has a ramp input terminal, an input capacitor (CR1), a ramp signal initialization switch (SWR1), and a transistor (TR3). One terminal of the input capacitor (CR1) is connected to the ramp input terminal, and the other terminal of the input capacitor (CR1) is connected to the gate terminal of the transistor (TR3). The input capacitor (CR1) prevents the DC component included in the ramp signal (VRAMP) input from the ramp input terminal from being transmitted to the transistor (TR3).

[0061] The first pixel signal input unit (142) has a VPIX_1 input terminal, an input capacitor (CP1), a pixel signal initialization switch (SWP1), and a transistor (TR4). The VPIX_1 input terminal is connected to one terminal of the input capacitor (CP1), and the gate terminal of the transistor (TR4) is connected to the other terminal of the input capacitor (CP1). By the input capacitor (CP1), the DC component included in the pixel signal (VPIX) input from the VPIX_1 input terminal is prevented from being transmitted to the transistor (TR4).

[0062] The second pixel signal input unit (143) has a VPIX_2 input terminal, an input capacitor (CP2), a pixel signal initialization switch (SWP2), and a transistor (TR5). One terminal of the input capacitor (CP2) is connected to the VPIX_2 input terminal, and the other terminal of the input capacitor (CP2) is connected to the gate terminal of the transistor (TR5). By the input capacitor (CP2), the DC component included in the pixel signal (VPIX) input from the VPIX_2 input terminal is prevented from being transmitted to the transistor (TR5).

[0063] In this embodiment, the VPIX_1 input terminal of the first pixel signal input unit (142) and the VPIX_2 input terminal of the second pixel signal input unit (143) are connected by a single wire (CL) to each pixel circuit (PX1) of the pixel column (see FIG. 2 and FIG. 3).

[0064] The selection unit (145) selects one of the pixel signal input units, the first pixel signal input unit (142) and the second pixel signal input unit (143), by turning on one of the current path control switches (SWPC1, SWPC2) according to the current path control signals (PC1, PC2). The current path control signals (PC1, PC2) are controlled by the control unit (18) so that they are mutually exclusive active (see FIG. 5).

[0065] One of the pixel signal input units selected by the selection unit (145) among the lamp signal input unit (141), the first pixel signal input unit (142), and the second pixel signal input unit (143) constitutes a differential pair.

[0066] When SWPC1 is turned on, the transistors ((TR3, the first transistor) and (TR4, the second transistor)) form a differential pair. In this case, the current mirror circuit (140) and the differential pair function as a comparator. Meanwhile, when SWPC2 is turned on, the transistors ((TR3, the first transistor) and (TR5, the second transistor)) form a differential pair. In this case, the current mirror circuit (140) and the differential pair function as a comparator.

[0067] The gate terminals of the transistors (TR1 and TR2) of the current mirror circuit (140) are connected to each other, and the drain terminals of the transistors (TR1 and TR2) are connected to the power line (VDD). Additionally, the source terminal of the transistor (TR1) is connected to the gate terminal of the transistor (TR1), the gate terminal of the transistor (TR2), and the drain terminal of the transistor (TR3). Additionally, the source terminal of the transistor TR2 is connected to one terminal of the current path control switch (SWPC1 and SWPC2) of the selection unit (145) and the gate terminal of the transistor (TR6).

[0068] The drain terminal of the transistor (TR3) is connected to one output terminal of the current mirror circuit (140), and the source terminal of the transistor (TR3) is connected to one drain terminal of the transistor (TR8) in the bias circuit (147).

[0069] The ramp signal initialization switch (SWR1, the first switch) is turned on in response to the ramp auto-zero signal (RampAZ). When the ramp signal initialization switch (SWR1) is turned on, the gate terminal and the drain terminal of the transistor (TR3) are connected, so the transistor (TR3) is initialized. By doing so, the offset of the ramp signal input section (141) can be removed.

[0070] The drain terminal of the transistor (TR4) is connected to the other terminal of the current path control switch (SWPC1) of the selection unit (145), and the source terminal of the transistor (TR4) is connected to the drain terminal of the transistor (TR8) in the bias circuit (147).

[0071] The pixel signal initialization switch (SWP1, the second switch) is turned on in response to pixel auto-zero (PixelAZ). When the ramp signal initialization switch (SWR1) is turned on, the gate terminal and drain terminal of the transistor (TR4) are connected, so the transistor (TR4) is initialized. By doing so, the offset of the first pixel signal input unit (142) can be removed.

[0072] The drain terminal of the transistor (TR5) is connected to the other terminal of the current path control switch (SWPC2) of the selection unit (145), and the source terminal of the transistor (TR5) is connected to the drain terminal of the transistor (TR8) in the bias circuit (147).

[0073] The pixel signal initialization switch (SWP2, the second switch) is turned on in response to pixel auto-zero (PixelAZ). When the pixel signal initialization switch (SWP2) is turned on, the gate terminal and drain terminal of the transistor (TR5) are connected, so the transistor (TR5) is initialized. By doing so, the offset of the second pixel signal input section (143) can be removed.

[0074] The comparison unit compares the ramp signal (VRAMP) input from the ramp signal input unit (141) with the pixel signal input from one of the first pixel signal input units (142) and the second pixel signal input unit (143) selected by the selection unit (145), and outputs the comparison result. In the example illustrated in FIG. 3, the comparison unit outputs a high level when the ramp signal (VRAMP) is greater than or equal to the pixel signal (VPIX), while outputting a low level when the ramp signal (VRAMP) is less than the pixel signal (VPIX).

[0075] The output circuit (146) has transistors (TR6, TR7) and an output terminal (Vout2). The gate terminal of transistor (TR6) is connected to the source terminal of transistor (TR2), and the drain terminal of transistor (TR6) is connected to the power line (VDD). Additionally, the source terminal of transistor (TR6) is connected to the drain terminal of transistor (TR7) and the output terminal (Vout2). The output circuit (146) controls the output current according to a control signal input to the gate terminal of transistor (TR7) and outputs the comparison result by the comparison unit from the output terminal (Vout2).

[0076] The bias circuit (147) has a transistor (TR8) and controls a predetermined bias current to flow to a comparator according to a control signal input to the gate terminal of the transistor (TR8).

[0077] FIG. 4 is a flowchart illustrating an overview of the processing procedure in the solid-state imaging element illustrated in FIG. 1, and FIG. 5 is a timing chart illustrating an overview of the operation of the solid-state imaging element illustrated in FIG. 1.

[0078] As illustrated in FIG. 4, first, the control unit (18) resets the floating diffusion (FD) of each pixel circuit (PX1) (step S101). More specifically, the control unit (18) controls the reset transistor (RT) and the gain select transistor (GT) to turn on. As illustrated in FIG. 5, an RST signal is input to the RST input terminal of the reset transistor (RT) for a predetermined period. By doing so, the pixel power supply (VDDP) is applied to the floating diffusion (FD), and the charge accumulated in the floating diffusion (FD) is reset. Then, the voltage level of the reset state is transmitted to the comparator (14) as a pixel signal (VPIX) (readout of the reset state).

[0079] Additionally, the control unit (18) turns on SWPC1 and turns off SWPC2 in the selection unit (145) by making the PC1 signal high level and the PC2 signal low level. By doing so, the input of the pixel signal (VPIX) from the first pixel signal input unit (142) becomes valid, and the input of the pixel signal (VPIX) from the second pixel signal input unit (143) becomes invalid.

[0080] Furthermore, the control unit (18) initializes the ramp signal input unit (141) by turning on SWR1 by setting the R1 signal to a high level (RampAZ) for a predetermined period before the measurement of the pixel signal (VPIX) begins. Additionally, the control unit (18) initializes the first pixel signal input unit (142) by turning on SWP1 by setting the P1 signal to a high level (PixelAZ) for a predetermined period.

[0081] Next, the control unit (18) converts the pixel signal (VPIX) at the reset level in LCG mode to AD (step S102). The control unit (18) controls the gain select transistor (GT) to maintain the turn-on state. As shown in FIG. 5, the CGS1 signal is maintained at a high level during the "LCG Reset" period for converting the pixel signal (VPIX) at the reset level in LCG mode to AD. By doing so, the pixel circuit (PX1) operates in LCG mode and outputs the pixel signal (VPIX) at the reset level in LCG mode.

[0082] The comparator (14) receives a pixel signal (VPIX) from the pixel circuit (PX1), compares the pixel signal (VPIX) at the reset level in LCG mode with the ramp signal (VRAMP), and outputs the comparison result. The counter (15) counts the period during which the comparison result by the comparator (14) is at a high level. The latch (16) maintains the count value by the counter (15).

[0083] Next, the control unit (18) turns off SWPC1 and turns on SWPC2 in the selection unit (145) by setting the PC1 signal to a low level and the PC2 signal to a high level. By doing so, the input of the pixel signal (VPIX) from the first pixel signal input unit (142) is disabled, and the input of the pixel signal (VPIX) from the second pixel signal input unit (143) is enabled.

[0084] Furthermore, the control unit (18) initializes the second pixel signal input unit (143) by turning on SWP2 by making the P2 signal high level (PixelAZ) for a predetermined period before the ramp signal (VRAMP) and pixel signal (VPIX) are input. Also, regarding SWR1 connected to the ramp signal input unit (141), it is already turned on once before step S102, and since the transistor (TR3) in the ramp signal input unit (141) is initialized, there is no need to turn it on again. That is, as shown in FIG. 5, SWR1 is turned on only once immediately after the pixel circuit (PX1) is reset and the transistor (TR3) is initialized, and in the part enclosed by the dotted line shown in FIG. 5, the control unit (18) does not turn R1 to a high level.

[0085] Next, the control unit (18) converts the reset level pixel signal (VPIX) in HCG mode to AD (step S103). The control unit (18) turns off the gain selection transistor (GT). As shown in FIG. 5, the CGS1 signal is maintained at a low level during the "HCG Reset" period for converting the reset level pixel signal (VPIX) in HCG mode to AD. By doing so, the capacity of the floating diffusion (FD) is reduced so that the pixel circuit (PX1) operates in HCG mode. Consequently, the reset level pixel signal (VPIX) in HCG mode becomes higher than the reset level pixel signal (VPIX) in LCG mode.

[0086] The comparator (14) receives a pixel signal (VPIX) from the pixel circuit (PX1), compares the pixel signal (VPIX) at the reset level in HCG mode with the ramp signal (VRAMP), and outputs the comparison result. The counter (15) counts the period during which the comparison result by the comparator (14) is at a high level. The latch (16) maintains the count value by the counter (15).

[0087] Next, the control unit (18) performs AD conversion on the pixel signal (VPIX) at the signal level in HCG mode (step S104). The control unit (18) keeps the gain selection transistor (GT) off and turns on the transfer transistor (TT). As shown in FIG. 5, the CGS1 signal is maintained at a low level during the "HCG Signal" period for performing AD conversion on the pixel signal (VPIX) at the signal level in HCG mode. Additionally, a TS signal is input to the TS input terminal of the transfer transistor (TT) for a predetermined period.

[0088] Light from the subject is incident on the solid-state image element, and the charge generated in the photoelectric conversion element (PD) is transmitted to the floating diffusion (FD) through the transfer transistor (TT) and accumulated. As a result, the voltage level of the floating diffusion (FD) decreases according to the amount of transmitted charge (electrons). The pixel signal (VPIX) is transmitted to the comparator (14). In addition, FIG. 5 illustrates a case where the range of the voltage level drop of the floating diffusion (FD) is small (DARK case) for the sake of simplicity of illustration.

[0089] The comparator (14) receives a pixel signal (VPIX) from the pixel circuit (PX1), compares the pixel signal (VPIX) at a signal level in HCG mode with a ramp signal (VRAMP), and outputs a comparison result. The counter (15) counts the period during which the comparison result by the comparator (14) is at a high level. The latch (16) maintains the count value by the counter (15).

[0090] Next, the control unit (18) turns on SWPC1 and turns off SWPC2 in the selection unit (145) by making the PC1 signal high level and the PC2 signal low level. By doing so, the input of the pixel signal (VPIX) from the first pixel signal input unit (142) becomes valid, and the input of the pixel signal (VPIX) from the second pixel signal input unit (143) becomes invalid.

[0091] Next, the control unit (18) performs AD conversion on the pixel signal (VPIX) at the signal level in LCG mode (step S105). The control unit (18) turns on the gain selection transistor (GT). As shown in FIG. 5, the CGS1 signal is maintained at a high level during the "LCG Signal" period for performing AD conversion on the pixel signal (VPIX) at the signal level in LCG mode. The charge generated in the photoelectric conversion element (PD) is transferred to the floating diffusion (FD) through the transfer transistor (TT) and accumulated. As a result, the voltage level in the floating diffusion (FD) decreases according to the amount of transferred charge (electrons).

[0092] The comparator (14) receives a pixel signal (VPIX) from the pixel circuit (PX1), compares the pixel signal (VPIX) at a signal level in LCG mode with a ramp signal (VRAMP), and outputs a comparison result. The counter (15) counts the period during which the comparison result by the comparator (14) is at a high level. The latch (16) maintains the count value by the counter (15).

[0093] In this way, in the present embodiment, the pixel circuit (PX1) transmits a pixel signal (VPIX) to the comparator (14) via a single line (CL) serially in time for each conversion gain. The control unit (18) controls the AD conversion unit (20) to convert the pixel signal (VPIX) at the reset level in the pixel circuit (PX1) that has been reset in the order of LCG and HCG modes, and then convert the pixel signal (VPIX) at the signal level corresponding to the captured image in the order of HCG and LCG modes.

[0094] The comparator (14) compares the ramp signal (VRAMP) and the received pixel signal (VPIX) sequentially, that is, in time, serially for each conversion gain during AD conversion by the AD conversion unit (20).

[0095] Next, each latch (16) performs CDS processing using the AD conversion values ​​of the reset level and the signal level for each mode. More specifically, the control unit (18) controls each latch (16) to subtract the count value corresponding to the reset level pixel signal (VPIX) from the count value corresponding to the signal level pixel signal (VPIX) for LCG mode and HCG mode. By doing so, the latch (16) can calculate a pixel value corresponding to the amount of light received by the photoelectric conversion element (PD) in each pixel circuit (PX1) for LCG mode and HCG mode.

[0096] In the first embodiment described above, the comparator (14) and the solid-state imaging element (10) having the comparator (14) exhibit the following effects.

[0097] In the solid-state imaging element (10), each comparator (14) is equipped with one ramp signal input section (141) for inputting a ramp signal and a plurality of pixel signal input sections (142, 143) for inputting pixel signals. Accordingly, when the number of conversion gains in the pixel circuit (PX1) is multiple, the number of pixel signal input sections becomes multiple, but the number of comparators can be maintained as one. Therefore, according to the comparator (14), even if the number of conversion gains is multiple, the increase in circuit area can be suppressed, so even if the number of conversion gains in the pixel circuit (PX1) increases, the decrease in the operating speed of the solid-state imaging element (10) and the increase in power consumption can be suppressed.

[0098] Based on the configuration of the comparator (14) of the present embodiment shown in FIG. 3, the area and power consumption of the comparator (14) are calculated using circuit design software. In addition, a comparison was performed with a comparator having a comparison section for each conversion gain, such as Comparative Example 1 (Japanese Patent Publication No. 2022-36068) and Comparative Example 2 (U.S. Patent Publication No. 2018 / 0302578). As a result of the comparison, it was confirmed that the area of ​​the comparator (14) in the present embodiment is about 30% smaller than the area of ​​the comparator in Comparative Example 1 and Comparative Example 2. In addition, it was confirmed that the power consumption of the comparator (14) in the present embodiment is about half the power consumption of the comparator in Comparative Example 1. However, the operating speed was made to be the same in the present embodiment and the comparative examples.

[0099] In the first embodiment, a case was described in which the pixel circuit (PX1) is configured to select one of two conversion gains (low conversion and high conversion gain) and the comparator (14) has two pixel signal inputs (first and second pixel signal inputs (142, 143)). In the second embodiment, a case was described in which the pixel circuit is configured to select one of three conversion gains (high conversion gain, medium conversion gain, and low conversion gain) and the comparator has three pixel signal inputs. Additionally, to avoid duplication of description, the description of configurations identical to those in the first embodiment is omitted or simplified.

[0100] FIG. 6 is a circuit diagram illustrating a pixel circuit of a solid-state imaging device according to a second embodiment. Each pixel circuit (PX2) has a photoelectric conversion device (PD), a transfer transistor (TT), a reset transistor (RT), a gain selection transistor (GT1, GT2), an amplifier transistor (AT), and a selection transistor (ST). Each pixel circuit (PX2) converts incident light into an electric circuit and outputs an electrical signal according to the amount of incident light. The solid-state imaging device (10) can select whether to operate each pixel circuit (PX2) in one of the following conversion gain modes: a high conversion gain mode in which it operates at a high conversion gain, a medium conversion gain mode in which it operates at a medium conversion gain, and a low conversion gain mode in which it operates at a low conversion gain. In the example illustrated in FIG. 6, the conversion gain mode is selected by the control signals of CGS1 and CGS2, specifically, when CGS1 and CGS2 are at a low level, a high conversion gain mode is selected; when CGS1 is at a high level and CGS2 is at a low level, a medium conversion gain mode is selected; and when CGS1 and CGS2 are at a high level, a low conversion gain mode is selected. Hereinafter, the medium conversion gain mode is also referred to as the "MCG (Middle Conversion Gain) mode."

[0101] The gate terminal, drain terminal, and source terminal of the reset transistor (RT) are respectively connected to the RST input terminal, the pixel power supply (VDDP), and the drain terminal of the gain select transistor (GT2). A floating diffusion capacitance (CF3) is formed between the connection between the source terminal of the reset transistor (RT) and the drain terminal of the gain select transistor (GT2) and ground.

[0102] The gate terminal, drain terminal, and source terminal of the gain select transistor (GT)2 are respectively connected to the CGS2 input terminal, the source terminal of the reset transistor (RT), and the drain terminal of the gain select transistor (GT1).

[0103] The gate terminal, drain terminal, and source terminal of the gain select transistor (GT)1 are respectively connected to the CGS1 input terminal, the source terminal of the gain select transistor (GT2), and the drain terminal of the transfer transistor (TT). A floating diffusion capacitance (CF2) is formed between the connection between the drain terminal of the gain select transistor (GT1) and the source terminal of the gain select transistor (GT2) and ground.

[0104] The gate terminal, drain terminal, and source terminal of the transfer transistor (TT) are respectively connected to the TS input terminal, the cathode terminal of the photoelectric conversion element (PD), and the source terminal of the gain selection transistor (GT)1. A floating diffusion capacitance (CF1) is formed between the connection between the source terminal of the transfer transistor (TT) and the source terminal of the gain selection transistor (GT)1 and ground.

[0105] The gate terminal, drain terminal, and source terminal of the amplifier transistor (AT) are respectively connected to the source terminal of the transfer transistor (TT), the pixel power supply (VDDP), and the drain terminal of the select transistor (ST).

[0106] The gate terminal, drain terminal, and source terminal of the select transistor (ST) are respectively connected to the SEL input terminal, the source terminal of the amplifier transistor, and the output terminal (POUT) of the pixel circuit (PX2).

[0107] FIG. 7 is a circuit diagram illustrating the configuration of a comparator of a solid-state imaging element according to a second embodiment. Each comparator (14) has a current mirror circuit (140), a ramp signal input unit (141), a first pixel signal input unit (142), a second pixel signal input unit (143), a third pixel signal input unit (144), a selection unit (145), an output circuit (146), and a bias circuit (147).

[0108] The configuration of the lamp signal input unit (141), the first pixel signal input unit (142), the second pixel signal input unit (143), the output circuit (146), and the bias circuit (147) is the same as that of the first embodiment, so a detailed description is omitted.

[0109] The third pixel signal input unit (144) has a VPIX_3 input terminal, an input capacitor (CP3), a pixel signal initialization switch (WP3), and a transistor (TR9). One terminal of the input capacitor (CP3) is connected to the VPIX_3 input terminal, and the other terminal of the input capacitor (CP3) is connected to the gate terminal of the transistor (TR9). By the input capacitor (CP3), the DC component included in the pixel signal (VPIX) input from the VPIX_3 input terminal is prevented from being transmitted to the transistor (TR9).

[0110] In this embodiment, the VPIX_1 input terminal of the first pixel signal input unit (142), the VPIX_2 input terminal of the second pixel signal input unit (143), and the VPIX_3 input terminal of the third pixel signal input unit (144) are connected to each pixel circuit (PX2) of the pixel column by a single wire (CL) (see FIG. 6 and FIG. 7).

[0111] The selection unit (145) turns on any one of the current path control switches (SWPC1 to SWPC3) according to the current path control signals (PC1 to PC3). By doing so, one of the pixel signal input units among the first pixel signal input unit (142), the second pixel signal input unit (143), and the third pixel signal input unit (144) is selected. The current path control signals (PC1 to PC3) are controlled by the control unit (18) so that they are mutually exclusive active (see FIG. 8).

[0112] A pixel signal input unit selected by a selection unit (145) among a lamp signal input unit (141), a first pixel signal input unit (142), a second pixel signal input unit (143), and a third pixel signal input unit (144) forms a differential pair.

[0113] When SWPC1 is turned on, the transistors ((TR3, the first transistor) and (TR4, the second transistor)) form a differential pair. In this case, the current mirror circuit (140) and the differential pair function as a comparator. When SWPC2 is turned on, the transistors ((TR3, the first transistor) and (TR5, the second transistor)) form a differential pair. In this case, the current mirror circuit (140) and the differential pair function as a comparator. When SWPC3 is turned on, the transistors ((TR3, the first transistor) and (TR9, the second transistor)) form a differential pair. In this case, the current mirror circuit (140) and the differential pair function as a comparator.

[0114] FIG. 8 is a timing chart illustrating an overview of the operation of the solid-state imaging element illustrated in FIG. 1. In this embodiment, the control unit (18) controls the pixel signal (VPIX) at the reset level to be converted to AD in the order of LCG, MCG, and HCG modes, and then controls the pixel signal (VPIX) at the signal level to be converted to AD in the order of HCG, MCG, and LCG modes.

[0115] Since the AD conversion of the reset level and signal level pixel signal (VPIX) in LCG and HCG modes is the same as in the first embodiment, a detailed description thereof is omitted. Below, an overview of the AD conversion of the reset level and signal level pixel signal (VPIX) in MCG mode is described.

[0116] The control unit (18) performs AD conversion processing on the pixel signal (VPIX) at the reset level in LCG mode, then sets the PC2 signal to a high level and sets the PC1 signal and PC3 signal to a low level. By doing so, SWPC2 is turned on in the selection unit (145), and SWPC1 and SWPC3 are turned off. By doing so, the input of the pixel signal (VPIX) from the second pixel signal input unit (143) becomes valid, and the input of the pixel signal (VPIX) from the first pixel signal input unit (142) and the third pixel signal input unit (144) becomes invalid.

[0117] Furthermore, the control unit (18) initializes the transistor (TR5) in the second pixel signal input unit (143) by turning on SWP2 by keeping the P2 signal at a high level for a predetermined period before the ramp signal (VRAMP) and pixel signal (VPIX) are input. In addition, regarding SWR1 connected to the ramp signal input unit (141), since it has already been turned on once during the AD conversion processing in LCG mode and the transistor (TR3) in the ramp signal input unit (141) has been initialized, there is no need to turn it on again. That is, as shown in FIG. 8, SWR1 is turned on only once and the transistor (TR3) is initialized immediately after the pixel circuit (PX2) is reset, and in the part enclosed by the dashed line shown in FIG. 8, the control unit (18) does not turn R1 to a high level.

[0118] The control unit (18) converts the reset level pixel signal (VPIX) in MCG mode to AD. The control unit (18) maintains the turn-on state of the gain select transistor (GT)1 and controls the gain select transistor (GT2) to turn off. During the "MCG Reset" period for converting the reset level pixel signal (VPIX) in MCG mode to AD, the CGS1 signal is maintained at a high level. By doing so, the pixel circuit (PX1) operates in MCG mode and outputs the reset level pixel signal (VPIX) in MCG mode.

[0119] The comparator (14) receives a pixel signal (VPIX) from the pixel circuit (PX1), compares the pixel signal (VPIX) at a reset level in MCG mode with a ramp signal (VRAMP), and outputs the comparison result. The counter (15) counts the period during which the comparison result by the comparator (14) is at a high level. The latch (16) maintains the count value by the counter (15).

[0120] Next, the control unit (18) performs AD conversion on the pixel signal (VPIX) at the reset level and signal level in HCG mode, and then performs AD conversion on the pixel signal (VPIX) at the signal level in MCG mode. Before AD conversion in MCG mode, the control unit (18) sets the PC2 signal to a high level and sets the PC1 signal and PC3 signal to a low level, thereby turning on SWPC2 in the selection unit (145) and turning off SWPC1 and SWPC3. By doing so, the input of the pixel signal (VPIX) from the first pixel signal input unit (142) and the third pixel signal input unit (144) becomes invalid, and the input of the pixel signal (VPIX) from the second pixel signal input unit (143) becomes valid.

[0121] The control unit (18) turns on the gain selection transistor (GT)1 and keeps the gain selection transistor (GT)2 off. During the "MCG Signal" period for converting the pixel signal (VPIX) of the signal level in MCG mode to AD, the CGS1 signal is maintained at a high level. The charge generated in the photoelectric conversion element (PD) is transferred to the floating diffusion (FD) through the transfer transistor (TT) and accumulated. As a result, the voltage level in the floating diffusion (FD) decreases according to the amount of transferred charge (electrons).

[0122] The comparator (14) receives a pixel signal (VPIX) from the pixel circuit (PX1), compares the pixel signal (VPIX) at a signal level in MCG mode with a ramp signal (VRAMP), and outputs a comparison result. The counter (15) counts the period during which the comparison result by the comparator (14) is at a high level. The latch (16) maintains the count value by the counter (15).

[0123] Subsequently, after the signal level pixel signal (VPIX) in the HCG mode is AD converted, each latch (16) performs CDS processing using the reset level and the signal level AD converted value for each mode. More specifically, the control unit (18) controls each latch (16) to subtract the count value corresponding to the reset level pixel signal (VPIX) from the count value corresponding to the signal level pixel signal (VPIX) for the LCG mode, MCG mode, and HCG mode. By doing so, the latch (16) can calculate a pixel value corresponding to the amount of light received by the photoelectric conversion element (PD) in each pixel circuit (PX2) for the LCG mode, MCG mode, and HCG mode.

[0124] FIG. 9 is a graph illustrating a signal-to-noise ratio (SNR) curve for illuminance of a solid-state imaging element according to a second embodiment. In the figure, the horizontal axis is illuminance [lx] and the vertical axis is the signal-to-noise ratio (SNR).

[0125] For example, a wide dynamic range (DR) can be realized by using three conversion gains: a high conversion gain, a medium conversion gain, and a low conversion gain. On the other hand, if one attempts to secure the above wide dynamic range by using two conversion gains, such as a high conversion gain and a low conversion gain, an SNR dip occurs at intermediate illuminance. That is, by adding a medium conversion gain to the high conversion gain and the low conversion gain, the dynamic range can be extended toward high illuminance.

[0126] Based on the configuration of the comparator (14) of the present embodiment illustrated in FIG. 7, the area and consumption strategy of the comparator (14) were calculated using circuit design software. In addition, a comparison was performed with a comparator having a comparator for each conversion gain, such as Comparative Example 1 (Patent Publication No. 2022-36068) and Comparative Example 2 (U.S. Patent Publication No. 2018 / 0302578). As a result of the comparison, it was confirmed that the area and consumption strategy of the comparator (14) in the present embodiment were reduced compared to the area and consumption strategy of the comparator (14) in the first embodiment. However, the operating speed was kept the same in the present embodiment and the comparative examples.

[0127] In the first embodiment, the case where the pixel circuit (PX1) has one photoelectric conversion element (PD) was described. In the third embodiment, the case where the pixel circuit has two photoelectric conversion elements is described. In addition, to avoid duplication of description, the description of the same configuration as in the first embodiment is omitted or simplified.

[0128] FIG. 10 is a circuit diagram illustrating a pixel circuit of a solid-state imaging element according to a third embodiment. The pixel circuit (PX3) has a photoelectric conversion element (PD1, PD2), a transfer transistor (TT1, TT2), a reset transistor (RT), a gain selection transistor (GT), an amplification transistor (AT), and a selection transistor (ST). In this embodiment, the photoelectric conversion element (PD1), the transfer transistor (TT1), the reset transistor (RT), the gain selection transistor (GT), the amplification transistor (AT), and the selection transistor (ST) of the pixel circuit (PX3) correspond, respectively, to the photoelectric conversion element (PD), the transfer transistor (TT), the reset transistor (RT), the gain selection transistor (GT), the amplification transistor (AT), and the selection transistor (ST) of the pixel circuit (PX1) in the first embodiment.

[0129] That is, in this embodiment, the pixel circuit (PX3) has, in addition to the configuration of the pixel circuit (PX1) in the first embodiment, a photoelectric conversion element (PD2) and a transfer transistor (TT2) (part enclosed by a dotted line in FIG. 10). The gate terminal, drain terminal, and source terminal of the transfer transistor (TT2) are respectively connected to the TS2 input terminal, the cathode terminal of the photoelectric conversion element (PD2), and the source terminal of the gain selection transistor (GT).

[0130] The photoelectric conversion element (PD2) may be a photodiode, phototransistor, etc., with a sensitivity different from that of the photoelectric conversion element (PD1). For example, the photoelectric conversion element (PD2) may be a photoelectric conversion element with lower sensitivity than that of the photoelectric conversion element (PD1). In this case, the pixel circuit (PX3) may be controlled by the control unit (18) so that the charge generated by the photoelectric conversion element (PD2) and transmitted via floating diffusion (FD) is converted into voltage at a low conversion gain. By doing so, the dynamic range can be extended toward the high illumination side. That is, scenes with higher illumination (brighter) can also be reproduced as images.

[0131] Additionally, the pixel circuit (PX3) is generated by a photoelectric conversion element (PD1) that has higher sensitivity than the photoelectric conversion element (PD2), and can be controlled by a control unit (18) so that the charge transmitted to the floating diffusion (FD) is converted into a voltage at a high conversion gain. By doing so, the dynamic range can be extended to the low-illumination side. That is, scenes with lower illumination (darker) can also be reproduced as images.

[0132] In this embodiment, the configuration of the comparator of the solid-state imaging element (10) is the same as the configuration of the comparator (14) of the solid-state imaging element (10) in the first embodiment, so the detailed description thereof is omitted.

[0133] FIG. 11 is a timing chart illustrating an overview of the operation of a solid-state imaging element (10) according to a third embodiment.

[0134] The processing up to the AD conversion of the reset level pixel signal (VPIX) in LCG mode and HCG mode, and the AD conversion of the signal level pixel signal (VPIX) in HCG mode, is the same as the timing chart shown in FIG. 5 in the first embodiment. In HCG mode, the transfer transistor (TT1) is turned on by the TS1 control signal. By this, the charge generated in the photoelectric conversion element (PD1) is transferred to the floating diffusion (FD) through the transfer transistor (TT1) and accumulated. In HCG mode, the charge generated in the photoelectric conversion element PD1 is converted into voltage and output as a pixel signal (VPIX).

[0135] In LCG mode, before the AD conversion of the pixel signal (VPIX) at the signal level, the transfer transistor (TT2) is turned on by the TS2 control signal. As a result, the charge generated in the photoelectric conversion element (PD2) is transferred to the floating diffusion (FD) through the transfer transistor (TT2) and accumulated. In LCG mode, the charge generated in the photoelectric conversion element (PD2) is converted into voltage and output as the pixel signal (VPIX).

[0136] In this embodiment, the pixel circuit (PX3) transmits a pixel signal (VPIX) to the comparator (14) via a single line (CL) in a serial manner over time for the photoelectric conversion elements (PD1, PD2) (multiple pixels). The control unit (18) controls the AD conversion unit (20) to convert the pixel signal (VPIX) at the reset level in the reset pixel circuit (PX1) in the order of LCG and HCG modes, and then convert the pixel signal (VPIX) at the signal level corresponding to the captured image in the order of HCG and LCG modes. When converting by the AD conversion unit (20), the comparator (14) sequentially compares the pixel signal (VPIX) and the ramp signal (VRAMP) from the photoelectric conversion elements (PD1, PD2) (multiple pixels) for each pixel.

[0137] Next, after the pixel signal (VPIX) of the signal level in LCG mode is AD converted, each latch (16) performs CDS processing using the AD converted values ​​of the reset level and the signal level for each mode.

[0138] The control unit (18) controls each latch (16) to subtract the count value corresponding to the reset level pixel signal (VPIX) from the count value corresponding to the signal level pixel signal (VPIX) for the LCG mode and the HCG mode. By doing so, the latch (16) can calculate a pixel value corresponding to the amount of light received by the photoelectric conversion element (PD1) in each pixel circuit (PX3) for the HCG mode, and calculate a pixel value corresponding to the amount of light received by the photoelectric conversion element (PD2) in each pixel circuit (PX3) for the LCG mode.

[0139] Thus, according to the third embodiment, in addition to the effects of the first embodiment, the following effects are exhibited.

[0140] The pixel circuit (PX3) has two photoelectric conversion elements (PD1, PD2) (multiple pixels) with different sensitivities, with a floating diffusion (FD) in common. By configuring the photoelectric conversion elements (PD1, PD2) such that the charge generated by the photoelectric conversion element with lower sensitivity and transmitted to the floating diffusion (FD) is converted into a voltage at a low conversion gain, the dynamic range can be extended toward the high illumination side. Additionally, by configuring the photoelectric conversion elements (PD1, PD2) such that the photoelectric conversion element with higher sensitivity and transmitted to the floating diffusion (FD) is converted into a voltage at a high conversion gain, the dynamic range can be extended toward the low illumination side.

[0141] In the fourth embodiment, as in the second embodiment, a case is described in which one of three conversion gains is selected and the comparator has three pixel signal input sections, and as in the third embodiment, the pixel circuit has two photoelectric conversion elements. Additionally, to avoid duplication of description, the description of configurations identical to those in the first to third embodiments is omitted or simplified.

[0142] FIG. 12 is a circuit diagram illustrating a pixel circuit of a solid-state imaging element according to a fourth embodiment. The pixel circuit (PX4) has a photoelectric conversion element (PD1, PD2), a transfer transistor (TT1, TT2), a reset transistor (RT), a gain selection transistor (GT1, GT2), an amplification transistor (AT), and a selection transistor (ST). In this embodiment, the photoelectric conversion element (PD1), the transfer transistor (TT1), the reset transistor (RT), the gain selection transistor (GT1), the amplification transistor (AT), and the selection transistor (ST) of the pixel circuit (PX4) correspond, respectively, to the photoelectric conversion element (PD), the transfer transistor (TT), the reset transistor (RT), the gain selection transistor (GT), the amplification transistor (AT), and the selection transistor (ST) of the pixel circuit (PX2) in the second embodiment.

[0143] In this embodiment, the pixel circuit (PX4) has, in addition to the configuration of the pixel circuit (PX2) in the second embodiment, a photoelectric conversion element (PD2) and a transfer transistor (TT2) in the third embodiment (part enclosed by a dotted line in FIG. 12). The gate terminal, drain terminal, and source terminal of the transfer transistor (TT2) are respectively connected to the TS2 input terminal, the cathode terminal of the photoelectric conversion element (PD2), and the source terminal of the gain selection transistor (GT1).

[0144] In this embodiment, the configuration of the comparator of the solid-state imaging element (10) is the same as the configuration of the comparator (14) of the solid-state imaging element (10) in the second embodiment, so the detailed description thereof is omitted.

[0145] FIG. 13 is a timing chart illustrating an overview of the operation of a solid-state imaging element (10) according to a fourth embodiment.

[0146] The processing up to the AD conversion of the reset level pixel signal (VPIX) in each of the LCG, MCG, and HCG modes, or the AD conversion of the signal level pixel signal (VPIX) in each of the HCG and MCG modes, is the same as the processing of the timing chart shown in FIG. 8 of the second embodiment. In addition, the processing of the AD conversion of the signal level pixel signal (VPIX) in the LCG mode is the same as the processing of the timing chart shown in FIG. 11 of the third embodiment.

[0147] In the fourth embodiment, in addition to the effects of the second embodiment, the effects of the third embodiment may also be exhibited. That is, the pixel circuit (PX4) is configured to select one of three conversion gains (high conversion gain, medium conversion gain, and low conversion gain), and the comparator (14) has three pixel signal input sections. By adding the medium conversion gain to the high conversion gain and the low conversion gain, the dynamic range can be extended toward the high illumination side. Additionally, the pixel circuit (PX4) has two photoelectric conversion elements (PD1, PD2) (multiple pixels) with different sensitivities, sharing a common floating diffusion (FD). The charge generated by the photoelectric conversion element with low sensitivity among the photoelectric conversion elements (PD1, PD2) is converted into voltage at the low conversion gain, and the charge generated by the photoelectric conversion element with high sensitivity is converted into voltage at the high conversion gain. By this, the dynamic range can be extended to the low-illumination and high-illumination sides.

[0148] As described above, the comparator and solid-state imaging element of the present invention have been explained in the embodiments. However, it goes without saying that the present invention can be appropriately added, modified, and omitted by those skilled in the art within the scope of the technical concept.

[0149] For example, in the second and fourth embodiments described above, the case in which the comparator (14) has three pixel signal inputs was described as an example, but the number of pixel signal inputs in the comparator (14) may be four or more.

[0150] In addition, the third and fourth embodiments described above describe a case in which the pixel circuit (PX3, PX4) has two photoelectric conversion elements (PD1, PD2) with different sensitivities, using floating diffusion (FD) in common. However, the number of photoelectric conversion elements in the pixel circuit is not limited to two, and may be three or more.

[0151] In addition, in the first to fourth embodiments described above, a solid-state imaging element comprising a plurality of pixel circuits having photoelectric conversion elements, such as photodiodes, in the pixels was described as an example. However, the present invention is not limited to such cases and may be applied to an AD converter that converts an analog signal from an optical sensor into an AD by using an optical sensor instead of a pixel circuit. Such optical sensors include, for example, illuminance sensors, contrast sensors, infrared distance sensors, etc.

[0152] In addition, the solid-state imaging element of the present invention can be used in various devices that sense light such as visible light, near-infrared light, infrared light, ultraviolet light, and X-rays. Such devices are not particularly limited, but examples include smartphones, mobile phones, personal computers, office equipment, vehicle-mounted devices, medical devices, entertainment devices, nature observation devices, security devices, etc. For example, the solid-state imaging element of the present invention can be used in visible light cameras such as smartphones, mobile phones, and digital cameras. In addition, the solid-state imaging element of the present invention can also be used in Time of Flight (TOF) or Light Detection and Ranging (LiDAR) in conjunction with a light-emitting device. Explanation of the symbols

[0153] FD: Floating Diffusion PD, PD1, PD2: Photoelectric conversion device PX1~PX4: Video circuits 10 : Solid-state imaging element 11: Pixel array section 12: Vertical Scanning Circuit 13: Lamp signal generator 14 : Comparator 140: Current mirror circuit 141: Lamp signal input section 142: First pixel signal input section 143 : Second pixel signal input section 144: Third pixel signal input section 145 : Selection 146 : Output circuit 147 : Bias circuit 15 : Counter 16 : Latch 17 : Horizontal scanning circuit 18 : Control unit 20 : Analog-to-Digital Converter

Claims

Claim 1 A comparator having: an AD converter that converts an analog pixel signal into a digital signal; a comparator that compares a ramp signal and the pixel signal, wherein the comparator has: one ramp signal input unit that inputs the ramp signal; a plurality of pixel signal input units that each input the pixel signal; and a comparator that compares the ramp signal input from the ramp signal input unit with the pixel signal input from any one of the plurality of pixel signal input units and outputs a comparison result. Claim 2 A comparator according to claim 1, further comprising a selection unit for selecting one of the plurality of pixel signal input units. Claim 3 A solid-state imaging element having: a pixel configuration configured to switchably have a conversion gain corresponding to the ratio at which a charge generated in the pixel is converted into a voltage; and a comparator that inputs a pixel signal from the pixel configuration to a pixel signal input unit corresponding to the conversion gain. Claim 4 In claim 3, the comparison unit sequentially compares the ramp signal and the pixel signal for each conversion gain, a solid-state imaging element. Claim 5 In claim 4, the comparison unit compares the pixel signal of the reset pixel configuration and the ramp signal for each conversion gain, and then compares the pixel signal corresponding to the captured image with the ramp signal, a solid-state imaging element. Claim 6 A solid-state imaging device according to any one of claims 3 to 5, wherein the pixel signal input selected by the ramp signal input unit and the selection unit constitutes a differential pair, and the differential pair comprises: a first transistor into which the ramp signal is input; a first switch for initializing the first transistor; a second transistor into which the pixel signal is input; and a second switch for initializing the second transistor; wherein immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor. Claim 7 In claim 3, the pixel configuration is a solid-state imaging element having a plurality of pixels with different sensitivities. Claim 8 In claim 7, the comparison unit sequentially compares pixel signals from the plurality of pixels and the ramp signals for each pixel, a solid-state imaging element. Claim 9 In claim 8, the comparison unit compares the pixel signal of the reset pixel configuration and the ramp signal for each conversion gain, and then compares the pixel signal corresponding to the captured image with the ramp signal, a solid-state imaging element. Claim 10 A solid-state imaging device according to any one of claims 7 to 9, wherein the pixel signal input selected by the ramp signal input unit and the selection unit constitutes a differential pair, and the differential pair comprises: a first transistor into which the ramp signal is input; a first switch for initializing the first transistor; a second transistor into which the pixel signal is input; and a second switch for initializing the second transistor; wherein immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor. Claim 11 In claim 3, the pixel configuration and the plurality of pixel signal input units are a solid-state imaging element connected by a single wire. Claim 12 A solid-state imaging device according to claim 6, wherein the first switch connects the gate terminal of the first transistor to the source or drain terminal, and the second switch connects the gate terminal of the second transistor to the source or drain terminal, and the first switch is turned on only once immediately after the reset of the pixel configuration so that the gate terminal of the first transistor is connected to the source or drain terminal, thereby initializing the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on so that the gate terminal of the second transistor is connected to the source or drain terminal, thereby initializing the second transistor. Claim 13 A solid-state imaging device according to claim 10, wherein the first switch connects the gate terminal of the first transistor to the source or drain terminal, and the second switch connects the gate terminal of the second transistor to the source or drain terminal, and the first switch is turned on only once immediately after the reset of the pixel configuration so that the gate terminal of the first transistor is connected to the source or drain terminal, thereby initializing the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on so that the gate terminal of the second transistor is connected to the source or drain terminal, thereby initializing the second transistor. Claim 14 A solid-state imaging device according to any one of claims 3 to 5, wherein the comparator has a differential pair that differentially amplifies the ramp signal and the pixel signal, and the differential pair has a first switch that initializes a first transistor into which the ramp signal is input and a second switch that initializes a second transistor into which the pixel signal is input, and immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor. Claim 15 A solid-state imaging device according to any one of claims 7 to 9, wherein the comparator has a differential pair that differentially amplifies the ramp signal and the pixel signal, and the differential pair has a first switch that initializes a first transistor into which the ramp signal is input, and a second switch that initializes a second transistor into which the pixel signal is input, and immediately after the pixel configuration is reset, the first switch is turned on only once to initialize the first transistor, and for each conversion gain, the second switch corresponding to the conversion gain is turned on to initialize the second transistor.

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