Memory system, operating method of memory system

Abstract

The present invention relates to an electronic device, and a memory system according to the present invention may include a cache memory, a main memory, and an Error Correction Code (ECC) engine. The cache memory may store data symbols and parity symbols. The main memory may store data symbols. A controller may generate a first virtual tag symbol containing tag information used to identify the location where a data symbol is stored in the main memory, and may generate a second virtual tag symbol containing tag information where a cache hit of a data symbol in the cache memory is expected based on an access address requested from a host. The ECC engine may perform encoding for the data symbol and the first virtual tag symbol, generate a parity symbol based on the result of the encoding, perform decoding for the second virtual tag symbol, the data symbol and parity symbol read from the cache memory, and check for errors in the data symbol and errors in the second virtual tag symbol based on the result of the decoding.

Description

Technology Field

[0001] The present invention relates to an electronic device, and more specifically, to a memory system and a method for operating a memory system. Background Technology

[0002] A memory system is a device that stores data under the control of a host device, such as a computer or smartphone. A memory system may include a memory device where data is stored and a memory controller that controls the memory device. Memory devices are classified into volatile memory devices and non-volatile memory devices.

[0003] Memory systems must simultaneously satisfy reliability and performance in environments requiring high-speed computation and large-capacity storage. To this end, memory systems may include controllers, cache memory, and main memory. DRAM-based cache memory can reduce data access latency between the system and main memory. Data stored in cache memory can be corrupted by soft errors or electrical noise. To detect and recover errors in such cached data, an ECC (Error Correction Code) engine may be integrated within the controller or memory module. The problem to be solved

[0004] An embodiment of the present invention provides a memory system and a method of operation thereof that can reduce the overhead of tag information stored in a cache memory. means of solving the problem

[0005] A memory system according to an embodiment of the present invention may include a cache memory, a main memory, and an Error Correction Code (ECC) engine. The cache memory may store data symbols and parity symbols. The main memory may store data symbols. A controller may generate a first virtual tag symbol containing tag information used to identify the location where a data symbol is stored in the main memory, and may generate a second virtual tag symbol containing tag information where a cache hit of a data symbol in the cache memory is expected based on an access address requested from a host. The ECC engine may perform encoding for the data symbol and the first virtual tag symbol, generate a parity symbol based on the result of the encoding, perform decoding for the second virtual tag symbol, the data symbol and parity symbol read from the cache memory, and check for errors in the data symbol and errors in the second virtual tag symbol based on the result of the decoding.

[0006] A method of operation of a memory system according to an embodiment of the present invention may include: generating a first virtual tag symbol including tag information used to identify a location in main memory where a data symbol is stored; reading a data symbol and a parity symbol stored in a cache memory based on an access address requested from a host; generating a second virtual tag symbol including tag information where a cache hit of a data symbol in the cache memory is expected based on an access address; performing decoding on the second virtual tag symbol, the data symbol and the parity symbol read from the cache memory; and checking for errors in the data symbol and errors in the second virtual tag symbol based on the result of the decoding. Effects of the invention

[0007] According to the present invention, a memory system and a method of operation thereof are provided that can reduce the overhead of tag information stored in a cache memory. Brief explanation of the drawing

[0008] FIG. 1 is a drawing for explaining the configuration and operation of a memory system according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a cache hit and a cache miss according to an embodiment of the present invention. FIG. 3 is a diagram for explaining the structure of the cache memory of FIG. 1 according to an embodiment of the present invention. FIGS. 4a and FIGS. 4b are drawings for explaining ECC encoding and ECC decoding according to an embodiment of the present invention. FIG. 5 is a diagram for explaining the structure of the cache memory of FIG. 1 according to an embodiment of the present invention. FIGS. 6a and 6b are drawings for explaining ECC encoding and ECC decoding according to an embodiment of the present invention. FIG. 7 is a flowchart for explaining the operation of a memory system according to one embodiment. FIG. 8 is a flowchart for explaining the operation of a memory system according to one embodiment. FIG. 9 is a flowchart for explaining the operation of a memory system according to one embodiment. Specific details for implementing the invention

[0009] Specific structural or functional descriptions regarding embodiments according to the concept of the present invention disclosed in this specification or application are provided merely for the purpose of explaining embodiments according to the concept of the present invention, and embodiments according to the concept of the present invention may be implemented in various forms and should not be interpreted as being limited to the embodiments described in this specification or application.

[0010] FIG. 1 is a drawing for explaining the configuration and operation of a memory system according to an embodiment of the present invention.

[0011] Referring to FIG. 1, the memory system (10) may include a controller (100), a cache memory (200), a main memory (300), and an ECC (Error Correction Code) engine (400).

[0012] The memory system (10) is a device that stores data under the control of a host (20), such as a mobile phone, smartphone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system.

[0013] The memory system (10) can be manufactured as any one of various types of memory systems depending on the communication method with the host (20). For example, the memory system (10) can be configured as any one of various types of memory systems such as an SSD, MMC, eMMC, RS-MMC, micro-MMC type multimedia card, SD, mini-SD, micro-SD type secure digital card, USB (universal serial bus) memory system, UFS (universal flash storage) device, PCI (peripheral component interconnection) card type memory system, PCI-E (PCI express) card type memory system, CF (compact flash) card, smart media card, memory stick, etc.

[0014] The memory system (10) can be manufactured in any one of various types of package forms. For example, the memory system (10) can be manufactured in any one of various types of package forms such as POP (package on package), SIP (system in package), SOC (system on chip), MCP (multi-chip package), COB (chip on board), WFP (wafer-level fabricated package), WSP (wafer-level stack package), etc.

[0015] The cache memory (200) is located between the CPU or controller (100) and the main memory (300) and can perform the role of storing frequently referenced data and minimizing data access latency. The cache memory (200) is generally organized in units of 'cache lines,' and each line can store 'tag' information to identify data and the corresponding memory block. When an access request for a specific address is received, the controller (100) can compare the cache lines using the tag of the address and determine a cache hit or a cache miss based on whether they match. If a cache miss occurs, the controller (100) can read data from the main memory (300), update the corresponding cache line, and store new tag information. The new tag information can be generated based on the upper bits of the access address received from the host (20).

[0016] The DRAM-based cache memory (200) utilizes its large capacity and high speed characteristics to operate as a temporary storage space faster than the main memory (300) and can also provide ECC protection.

[0017] The main memory (300) can store data. The main memory (300) operates in response to the control of the controller (100). The main memory (300) may include a plurality of memory blocks. A memory block may include a plurality of memory cells that store data.

[0018] In the embodiment, the cache memory (200) and main memory (300) may include Random Access Memory (RAM) and Non-Volatile Memory (NVM), DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), RDRAM (Rambus Dynamic Random Access Memory), NAND flash memory, resistive random access memory (RRAM), phase-change memory (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM), etc.

[0019] The main memory (300) may be configured to receive a command and an address from the controller (100) and to access an area of ​​storage selected by the address. That is, the main memory (300) may perform an operation instructed by the command on the area selected by the address. For example, the main memory (300) may perform a write operation (program operation), a read operation, and an erase operation. During the program operation, the main memory (300) will program data in the area selected by the address. During the read operation, the main memory (300) will read the data stored in the area selected by the address. During the erase operation, the main memory (300) will erase the data stored in the area selected by the address.

[0020] The controller (100) controls the overall operation of the memory system (10).

[0021] In an embodiment, the controller (100) receives data and a logical address requested for access from the host (20), and can convert the logical address into a physical address representing the address of a memory cell to be stored in the main memory (300).

[0022] The controller (100) can control the main memory (300) to perform program operations, read operations, or erase operations, etc., according to a request from the host (20). When performing a program operation, the controller (100) can provide a write command, a physical address, and data to the main memory (300). When performing a read operation, the controller (100) can provide a read command and a physical address to the main memory (300). When performing an erase operation, the controller (100) can provide an erase command and a physical address to the main memory (300).

[0023] The ECC engine (400) may include an encoder (410) and a decoder (420) as dedicated circuit blocks responsible for detecting and correcting errors in data. The encoder (410) may operate before data is stored in memory, and the decoder (420) may operate when reading data from memory. In one embodiment, the ECC engine (400) may use an ECC technique based on Reed-Solomon (RS) code.

[0024] The encoder (410) can generate parity bits by applying a predetermined error correction code algorithm to the original data transmitted from the host (20) or the controller (100). The encoder (410) can generate a codeword by adding parity bits to the original data. The data stored in memory in the form of a codeword along with the generated parity bits can be verified in the same way when read later.

[0025] The decoder (420) can receive a codeword read from the cache memory (200) or main memory (300) as input and perform a decoding process that analyzes the stored parity bits and data bits together.

[0026] The host (20) can communicate with the memory system (10) using at least one of various communication methods such as CXL (Compute Express Link), USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed ​​Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM).

[0027] In an embodiment, the cache memory (200) can store data symbols and parity symbols. The main memory (300) can store data symbols. The cache memory (200) includes random access memory, and the main memory (300) may include non-volatile memory.

[0028] In an embodiment, the controller (100) may generate a first virtual tag symbol used when the ECC engine (400) encodes and a second virtual tag symbol used when decoding. The first virtual tag symbol may include tag information used to identify the location where a data symbol is stored in the main memory (300). The second virtual tag symbol may include tag information where a cache hit of the data symbol in the cache memory (200) is expected. The second virtual tag symbol may be generated based on an access address requested from the host (20) to the controller (100).

[0029] The controller (100) can read data symbols and parity symbols from the cache memory (200) based on the access address before decoding. After encoding, the controller (100) can discard the first virtual tag symbol without storing it in the cache memory (200).

[0030] The controller (100) may determine that it is a cache hit if no error in the data symbol and no error in the second virtual tag symbol are detected in the result of decoding, and may provide the data symbol to the host (20). The controller (100) may determine that it is a cache hit if no error in the data symbol is detected in the result of decoding and no error in the second virtual tag symbol is detected, and may provide the data symbol corrected by the ECC engine (400) to the host (20).

[0031] The controller (100) may determine that there is a cache miss if an error in the second virtual tag symbol is detected in the result of decoding. If the controller (100) determines that there is a cache miss, it may read the data symbol stored in the main memory (300) based on the access address and provide the data symbol read from the main memory (300) to the host (20). The controller (100) may update the cache memory (200) based on the data symbol read from the main memory (300).

[0032] The ECC engine (400) can perform encoding for data symbols and a first virtual tag symbol. The ECC engine (400) can generate a parity symbol based on the result of the encoding. The ECC engine (400) can perform decoding for a second virtual tag symbol, a data symbol read from the cache memory (200), and a parity symbol. The ECC engine (400) can check for errors in the data symbol and errors in the second virtual tag symbol based on the result of the decoding. At this time, the ECC engine (400) can perform encoding and decoding using a reed-solomon code.

[0033] If an error in the data symbol and an error in the second virtual tag symbol are detected in the result of the decoding, the ECC engine (400) can re-draw the decoding for all possible values ​​that the second virtual tag symbol may have.

[0034] The encoder (410) performs encoding based on the data symbol and the first virtual tag symbol, and can generate a parity symbol based on the result of the encoding. The decoder (420) performs decoding based on the second virtual tag symbol, the data symbol read from the cache memory (200), and the parity symbol, and can correct errors in the data symbol and errors in the second virtual tag symbol based on the result of the decoding.

[0035] FIG. 2 is a diagram illustrating a cache hit and a cache miss according to an embodiment of the present invention.

[0036] Referring to FIG. 2, a memory address may include a tag, an index, and an offset. The memory address may be the address of the data that the host has requested to access. The index is used to select a specific cache line within the cache memory, and the number of bits may be determined according to the number of lines in the cache. The offset specifies the location of the data to be actually accessed within the selected cache line, and its size may be determined according to the byte size of the cache line.

[0037] A cache entry is information stored in a cache line and may include a tag, a valid bit, and data. If the value of the valid bit is 1, the data is valid, and if the value of the valid bit is 0, the data may be invalid. If the value of the valid bit is Null, there may be no data stored in the cache line.

[0038] The process for determining cache hits and cache misses is as follows.

[0039] A cache line corresponding to an index extracted from a memory address is located, and after checking the valid bit, the tag of the memory address can be compared with the tag of the cache entry stored in the cache line. If the value of the valid bit is 1 and the two tags match, it can be determined as a cache hit. At this time, the exact data location within the cache line is referenced through the offset, and the data of the selected cache entry can be returned.

[0040] If the value of the valid bit is 0 or Null, or if the tags are different, it may be determined to be a cache miss. In this case, data is retrieved from main memory, the cache entry stored in the cache line is updated, and a new tag and valid bit can be stored. Through this process, the cache memory can increase the possibility of reusing recently accessed data.

[0041] FIG. 3 is a diagram for explaining the structure of the cache memory of FIG. 1 according to an embodiment of the present invention.

[0042] Referring to FIG. 3, the memory module (2000a) may represent an example of the structure of the cache memory described with reference to FIG. 1.

[0043] The memory module (2000a) may include a plurality of memory chips. Among the plurality of memory chips, the data chip may be a memory chip that stores a data symbol described with reference to FIGS. 4a and 4b. Among the plurality of memory chips, the parity chip may be a memory chip that stores a parity symbol described with reference to FIGS. 4a and 4b. Among the plurality of memory chips, the tag chip may be a memory chip that stores a tag symbol described with reference to FIGS. 4a and 4b.

[0044] FIGS. 4a and FIGS. 4b are drawings for explaining ECC encoding and ECC decoding according to an embodiment of the present invention.

[0045] In the embodiment, ECC encoding and ECC decoding can be performed based on the RS (Reed-Solomon) code. The RS code may be a symbol-based block code widely used to correct multi-bit errors. The RS code groups data bits into fixed-size symbol units (e.g., 8 bits) and can detect / correct errors occurring across multiple symbols on a symbol-by-symbol basis. For example, the RS code adds 2t additional symbols (parity symbols) to correct up to t symbol errors in a codeword, and these parities can be generated by polynomial operations on a Galois field. In a memory system, the symbol-by-symbol error correction characteristics of the RS code can be utilized to prepare for multi-bit errors, such as burst errors or chip-level failures.

[0046] In particular, in server memory protection technology known as Chipkill, data recovery can be achieved even in the event of a single-chip failure by configuring ECC by treating the bits provided by a single DRAM chip as a single RS symbol. In summary, RS codes can be a powerful ECC method that effectively detects and corrects even chip-level multi-bit errors that may occur in memory systems by applying polynomial-based parity to symbolized data blocks.

[0047] The ECC encoding and ECC decoding performed in FIGS. 4a and 4b can be performed based on the (10,8) RS code. The (10,8) RS code consists of 8 data symbols and 2 parity symbols, allowing for 1 symbol error correction. The number of data symbols input to the RS code and the number of parity symbols output are not limited to this embodiment.

[0048] The process described in Fig. 4a can be performed when storing data in the cache memory.

[0049] For example, in FIG. 4a, eight data symbols (DS1 to DS8) are input, and ECC encoding based on the (10,8) RS code can be performed. As a result of the encoding, eight data symbols (DS1 to DS8) and two parity symbols (PS1, P2) can be output. The tag symbol (TS) may include tag information in the cache memory corresponding to the eight data symbols (DS1 to DS8). The eight data symbols (DS1 to DS8) may be stored in the data chip within the memory module (2000a), the two parity symbols (PS1, P2) may be stored in the parity chip, and the one tag symbol (TS) may be stored in the tag chip.

[0050] The process described in Fig. 4b can be performed when reading data from the cache memory.

[0051] For example, in FIG. 4b, eight data symbols (DS1 to DS8) stored in the data chip, two parity symbols (PS1, P2) stored in the parity chip, and one tag symbol (TS) stored in the tag chip can be read.

[0052] Eight read data symbols (DS1–DS8) and two parity symbols (PS1, P2) are input, and ECC decoding based on the (10,8) RS code can be performed. As a result of the decoding, it can be checked whether an error has occurred in the eight data symbols (DS1–DS8). In this case, if an error has occurred in one of the eight data symbols (DS1–DS8), the error can be corrected. The read tag symbol (TS) can be used to determine a cache hit or a cache miss based on the access address requested by the host.

[0053] FIG. 5 is a diagram for explaining the structure of the cache memory of FIG. 1 according to an embodiment of the present invention.

[0054] Referring to FIG. 5, the memory module (2000b) may represent an example of the structure of the cache memory described with reference to FIG. 1.

[0055] The memory module (2000b) may include a plurality of memory chips. Among the plurality of memory chips, the data chip may be a memory chip that stores a data symbol described with reference to FIGS. 6a and FIGS. 6b. Among the plurality of memory chips, the parity chip may be a memory chip that stores a parity symbol described with reference to FIGS. 6a and FIGS. 6b.

[0056] The memory module (2000b) may not include a separate tag chip for storing tag symbols compared to the memory module (2000a) described with reference to FIG. 3.

[0057] FIGS. 6a and 6b are drawings for explaining ECC encoding and ECC decoding according to an embodiment of the present invention.

[0058] In the embodiment, virtual symbol-based error correction may be performed. Virtual symbol-based error correction is a concept that enhances data integrity by utilizing logical symbols that are included in ECC codewords but are not physically stored. Specifically, in a memory system, additional information such as address tags of a cache or memory block is treated as an ECC symbol, so that the information can be protected by ECC without additional storage space.

[0059] During ECC decoding, iterative decoding is performed on all possible values ​​of virtual tag symbols to determine the most reliable data combination. This structure has the advantage of extending correction coverage without increasing additional physical parity bits, and effectively preventing abnormal behavior caused by errors or tag mismatches that occur during cache access.

[0060] For example, when calculating ECC for a single data block (cache line), a portion of the block's address (tag) can be used as an additional input in the form of a hash, and a parity check bit can be generated based on this. In this way, the ECC parity reflects not only the data content but also the address information of the data, allowing an integrity code for the data-address combination to be formed. When reading the data block from memory, the memory controller can calculate the tag hash from the current access address in the same manner and perform ECC verification together with the read data.

[0061] If there is an error in the data bit, the ECC decoder will detect it and correct it or emit an error signal; conversely, even if the data is not corrupted but an error occurs in the address tag and data with an incorrect address is returned, it can be recognized as an error during ECC verification because a discrepancy with the originally calculated parity occurs.

[0062] By utilizing tag-based virtual symbols in this way, it is possible to detect address line errors or incorrect data correspondences in memory or cache systems that are difficult to detect with standard ECC.

[0063] In the (10,8) RS code described with reference to FIGS. 4a and 4b, it consists of 8 data symbols and 2 parity symbols, allowing for 1 symbol error correction.

[0064] In the (11, 8) RS code described with reference to FIGS. 6a and 6b, tag information related to memory addresses is defined as a 'virtual tag symbol' and can be added to the existing RS encoding process. For example, by performing (11, 8) RS encoding that generates two parity symbols using eight data symbols and one virtual tag symbol as input, richer context information can be included within the ECC protection range while maintaining the same correction capability as before. Additionally, since no separate space is required to store tag information within the memory module (4000b), manufacturing and storage costs can be improved.

[0065] The process described in Fig. 6a can be performed when storing data in cache memory.

[0066] For example, in FIG. 6a, eight data symbols (DS1 to DS8) and a first virtual tag symbol (TS1) are input, and ECC encoding based on the (11,8) RS code can be performed. The first virtual tag symbol (TS1) may include tag information in the cache memory corresponding to the eight data symbols (DS1 to DS8).

[0067] As a result of encoding, eight data symbols (DS1 to DS8) and two parity symbols (PS1', P2') can be output. The eight data symbols (DS1 to DS8) can be stored in the data chip within the memory module (2000a), and the two parity symbols (PS1', P2') can be stored in the parity chip. However, the first virtual tag symbol (TS1) may be discarded without being stored in the memory module (2000b).

[0068] The process described in Fig. 6b can be performed when reading data from the cache memory.

[0069] For example, in FIG. 6b, eight data symbols (DS1 to DS8) stored in the data chip and two parity symbols (PS1', P2') stored in the parity chip can be read. Based on the access address requested from the host, the controller (100) can generate a second virtual tag symbol (TS2) containing tag information where a cache hit of the eight data symbols (DS1 to DS8) in the cache memory is expected.

[0070] Eight data symbols (DS1~DS8) read from the memory module (2000b), two parity symbols (PS1, P2), and a second virtual tag symbol (TS2) received from the controller (100) are input, and ECC decoding based on the (11,8) RS code can be performed. As a result of the decoding, it can be checked whether an error has occurred in the eight data symbols (DS1~DS8) and the second virtual tag symbol (TS2).

[0071] If no error occurs in the eight data symbols (DS1 to DS8) and the second virtual tag symbol (TS2), the first virtual tag symbol (TS1) and the second virtual tag symbol (TS2) match, so it can be determined as a cache hit. In this case, the eight read data symbols (DS1 to DS8) can be provided directly to the host.

[0072] Even if an error occurs in one of the eight data symbols (DS1 to DS8), the error can be corrected, and since no error occurs in the second virtual tag symbol (TS2), the first virtual tag symbol (TS1) and the second virtual tag symbol (TS2) match, so it can be determined as a cache hit. In this case, the one data symbol with the error corrected and the remaining seven data symbols that were read normally can be provided to the host.

[0073] If an error occurs in one of the eight data symbols (DS1 to DS8) and the second virtual tag symbol (TS2), the first virtual tag symbol (TS1) and the second virtual tag symbol (TS2) are inconsistent, so it can be determined as a cache miss. In this case, the eight data symbols (DS1 to DS8) read from main memory can be provided to the host.

[0074] FIG. 7 is a flowchart for explaining the operation of a memory system according to one embodiment.

[0075] Referring to FIG. 7, in step S701, the memory system can generate a first virtual tag symbol containing tag information used to identify the location where a data symbol is stored in main memory.

[0076] In step S703, the memory system can perform encoding for the data symbol and the first virtual tag symbol.

[0077] In step S705, the memory system can generate parity symbols based on the result of the encoding.

[0078] In step S707, the memory system can store data symbols and parity symbols in the cache memory.

[0079] In step S709, the memory system may discard the first virtual tag symbol without storing it in the cache memory.

[0080] FIG. 8 is a flowchart for explaining the operation of a memory system according to one embodiment.

[0081] Referring to FIG. 8, in step S801, the memory system can read data symbols and parity symbols from the cache memory based on the host's access address.

[0082] In step S803, the memory system may generate a second virtual tag symbol based on the host's access address. The second virtual tag symbol may include tag information where a cache hit of a data symbol within the cache memory is expected.

[0083] In step S805, the memory system can perform decoding for the data symbol, parity symbol, and second virtual tag symbol.

[0084] In step S807, the memory system can determine whether an error has occurred in the data symbol and the second virtual tag symbol based on the decoding result. If an error occurs, proceed to step S813; if no error occurs, proceed to step S809.

[0085] At step S809, the memory system may determine that there is a cache hit. A cache hit may mean that a data symbol corresponding to the access address requested by the host exists within the cache memory.

[0086] In step S811, the memory system may provide the host with the data symbol read from the cache memory in step S801, the error-corrected data symbol in step S815, or the data symbol read from the main memory in step S821 in response to the host's request.

[0087] At step S813, the memory system can determine whether the type of error that occurred is a correctable error (CE) or an uncorrectable error (UE). If the error type is a correctable error, the system proceeds to step S815; if it is an uncorrectable error, it proceeds to step S901. An uncorrectable error may refer to an error that exceeds the error correction capability of the memory system.

[0088] In step S815, the memory system can correct an error in a data symbol or an error in a second virtual tag symbol.

[0089] In step S817, the memory system can determine the location of the error that occurred in step S807. If the result of the determination is that the error occurred in the Data Symbol (DS), the system proceeds to step S809, and if the error occurred in the second virtual Tag Symbol (TS), the system proceeds to step S819.

[0090] At step S819, the memory system may determine that there is a cache miss. A cache miss may mean that there is no data symbol in the cache memory corresponding to the access address requested by the host.

[0091] In step S821, the memory system can read a data symbol from main memory based on the access address and update the cache memory based on the read data symbol.

[0092] FIG. 9 is a flowchart for explaining the operation of a memory system according to one embodiment.

[0093] Referring to FIG. 9, in step S901, the memory system can repeat the decoding by considering all possible values ​​that the second virtual tag symbol may have.

[0094] In step S903, the memory system can determine, based on the result of decoding, whether the error type is a correctable error (CE) or an uncorrectable error (UE).

[0095] For example, when the error correction capability of the memory system is capable of correcting an error for only one symbol, in step S813, if an error occurs in both the data symbol and the second virtual tag symbol, it may be determined to be an uncorrectable error. Subsequently, in step S901, the error of the second virtual tag symbol may be corrected as a result of re-performing decoding for all possible cases of the second virtual tag symbol. In this case, since it can be viewed as a case where an error ultimately occurred in only one data symbol, it may be determined to be a correctable error.

[0096] As another example, in step S813, if an error occurs in two data symbols, it may be determined to be an uncorrectable error. This is because the error in two data symbols cannot be corrected by the decoding performed in step S901, so it may be determined to be an uncorrectable error.

[0097] If the error type is a correctable error, proceed to step S903; if it is an uncorrectable error, proceed to step S905. An uncorrectable error may refer to an error that exceeds the error correction capability of the memory system.

[0098] In step S905, the memory system can perform error correction non-processing.

[0099] In step S907, the memory system can correct errors in the second virtual tag symbol and data symbol. Then, it can proceed to step S819. Explanation of the symbols

[0100] 10: Memory System 20: Host 100: Controller 200: Cache memory 300: Main memory 400: ECC engine 410: Encoder 420: Decoder

Claims

Claim 1 A memory system comprising: a cache memory for storing data symbols and parity symbols; a main memory for storing data symbols; a controller for generating a first virtual tag symbol including tag information used to identify the location where the data symbols are stored in the main memory, and generating a second virtual tag symbol including tag information where a cache hit of the data symbols in the cache memory is expected based on an access address requested from a host; and an ECC (Error Correction Code) engine for performing encoding on the data symbols and the first virtual tag symbol, generating the parity symbol based on the result of the encoding, performing decoding on the second virtual tag symbol, the data symbols and the parity symbols read from the cache memory, and checking for errors in the data symbols and errors in the second virtual tag symbol based on the result of the decoding. Claim 2 In claim 1, the controller is a memory system that reads the data symbol and the parity symbol from the cache memory based on the access address prior to the decoding. Claim 3 In claim 1, the controller is a memory system that, after the encoding, discards the first virtual tag symbol without storing it in the cache memory. Claim 4 A memory system according to claim 1, wherein the controller determines a cache hit if no error of the data symbol and no error of the second virtual tag symbol are detected in the result of the decoding, and provides the data symbol to the host. Claim 5 A memory system according to claim 1, wherein the controller determines a cache hit if, in the result of the decoding, an error in the data symbol is detected and an error in the second virtual tag symbol is not detected, controls the ECC engine to correct the error in the data symbol, and provides the data symbol corrected by the ECC engine to the host. Claim 6 A memory system according to claim 1, wherein the controller determines a cache miss when an error of the second virtual tag symbol is detected in the result of the decoding, reads the data symbol stored in the main memory based on the access address, and provides the data symbol read from the main memory to the host. Claim 7 In claim 6, the controller is a memory system that updates the cache memory based on data symbols read from the main memory. Claim 8 In claim 1, the ECC engine is a memory system that performs the encoding and decoding using a Reed-Solomon code. Claim 9 In claim 1, the memory system wherein the ECC engine re-performs the decoding for all possible values ​​of the second virtual tag symbol when an error of the data symbol and an error of the second virtual tag symbol are detected in the result of the decoding. Claim 10 A memory system according to claim 1, wherein the ECC engine comprises: an encoder that performs the encoding based on the data symbol and the first virtual tag symbol and generates the parity symbol based on the result of the encoding; and a decoder that performs the decoding based on the second virtual tag symbol, the data symbol read from the cache memory and the parity symbol, and corrects errors in the data symbol and errors in the second virtual tag symbol based on the result of the decoding. Claim 11 A memory system according to claim 1, wherein the cache memory includes Random Access Memory and the main memory includes Non-Volatile Memory. Claim 12 A method of operating a memory system comprising: generating a first virtual tag symbol including tag information used to identify the location where a data symbol is stored in main memory; reading the data symbol and parity symbol stored in a cache memory based on an access address requested from a host; generating a second virtual tag symbol including tag information where a cache hit of the data symbol in the cache memory is expected based on the access address; performing decoding on the second virtual tag symbol, the data symbol read from the cache memory, and the parity symbol; and checking for errors in the data symbol and errors in the second virtual tag symbol based on the result of the decoding. Claim 13 A method of operation of a memory system according to claim 12, further comprising: a step of performing encoding for the data symbol and the first virtual tag symbol; a step of generating the parity symbol based on the result of the encoding; a step of storing the data symbol and the parity symbol in the cache memory; and a step of discarding the first virtual tag symbol without storing it in the cache memory. Claim 14 A method of operation of a memory system according to claim 12, further comprising: a step of determining a cache hit if, in the step of checking the error, an error of the data symbol and an error of the second virtual tag symbol are not detected; and a step of providing the data symbol read from the cache memory to the host. Claim 15 A method of operation of a memory system according to claim 12, further comprising: a step of determining a cache hit if, in the step of checking the error, an error in the data symbol is detected and an error in the second virtual tag symbol is not detected; a step of correcting the error in the data symbol; and a step of providing the corrected data symbol to the host. Claim 16 A method of operation of a memory system according to claim 12, further comprising: a step of determining a cache miss if an error of the second virtual tag symbol is detected in the step of checking the error; a step of reading the data symbol stored in the main memory based on the access address; and a step of providing the data symbol read from the main memory to the host. Claim 17 A method of operation of a memory system, further comprising the step of updating the cache memory based on data symbols read from the main memory in claim 16. Claim 18 A method of operation of a memory system according to claim 12, further comprising the step of re-performing the decoding for all possible values ​​that the second virtual tag symbol may have when an error of the data symbol and an error of the second virtual tag symbol are detected in the step of checking the error. Claim 19 In claim 13, the above encoding and above decoding are a method of operation of a memory system performed using a Reed-Solomon code. Claim 20 A method of operation of a memory system according to claim 12, wherein the cache memory includes Random Access Memory and the main memory includes Non-Volatile Memory.

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