Diode structures of stacked transistors and mehtods of manufacturing the same

The three-dimensional transistor structure with shared contacts between source/drain regions of opposite conductivity types addresses parasitic capacitance issues, enhancing electrical reliability and stability in integrated circuit devices by integrating diode structures like SMS or PIN diodes.

KR1020260138972APending Publication Date: 2026-09-21SAMSUNG ELECTRONICS CO LTD
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Patent Information

Application Number
KR1020250132944
Authority / Receiving Office
KR · KR
Patent Type
Applications
Current Assignee / Owner
Priority Date
2025-08-12
Filing Date
2025-09-16
Publication Date
2026-09-21

AI Technical Summary

Technical Problem

The challenge in integrated circuit devices is to reduce parasitic capacitance without significantly reducing the channel width, particularly in three-dimensional transistor structures like Gate-All-Around (GAA) devices, where stacked transistors are used to increase density and improve performance.

Method used

A three-dimensional transistor structure is designed with a shared contact connecting source/drain regions of opposite conductivity types, allowing for the integration of diode structures such as semiconductor-metal-semiconductor (SMS) diodes, PIN diodes, or bipolar junction transistors, which enhances electrical reliability and stability.

Benefits of technology

The structure improves electrical reliability and stability by reducing parasitic capacitance while maintaining channel width, facilitating the integration of diode structures without additional manufacturing steps.

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Abstract

The technical concept of the present invention provides a three-dimensional transistor structure and a method for manufacturing the same, comprising: a first stacked transistor structure including a first lower source / drain region and a first upper source / drain region stacked with an insulating layer between the first lower source / drain region and the first upper source / drain region, wherein the first lower source / drain region has a first conductivity type and the first upper source / drain region has a second conductivity type opposite to the first conductivity type; a first contact connected to the first upper source / drain region; a second contact connected to the first lower source / drain region; and a shared contact connecting the first upper source / drain region and the first lower source / drain region.
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