Semiconductor package and method for forming the same

Abstract

A semiconductor package and a method for forming the same are provided. The method comprises: providing a substrate; providing a semiconductor die stack including a first semiconductor die; mounting the semiconductor die stack on an upper surface of the substrate; forming a first barrier wall on an upper surface of the substrate, wherein the first barrier wall covers a side surface of the first semiconductor die and protrudes from the upper surface of the first semiconductor die; dispensing a first fluid material on an upper surface of the first semiconductor die, wherein the first barrier wall prevents the first fluid material from flowing across it; and curing the first fluid material to form a back metallized (BSM) layer.

Description

Technology Field

[0001] This application generally relates to semiconductor technology, and more specifically, to a semiconductor package and a method for forming the same. Background Technology

[0002] As consumers increasingly pack more functionality into a single device and demand that electronic devices be smaller, faster, and higher in performance, the semiconductor industry is constantly facing complex integration challenges. To meet consumer demands, more and more electronic components are tightly integrated within a single device or package. However, due to this tight integration, heat generated by one electronic component can be blocked by other components within the same package, leading to unsatisfactory heat dissipation and consequently affecting the performance of the semiconductor package.

[0003] Therefore, a semiconductor package with improved heat dissipation capacity is required.

[0004] The object of the present application is to provide a method for manufacturing a semiconductor package having improved heat dissipation capacity.

[0005] According to an aspect of the present application, a method for forming a semiconductor package is provided. The method may include: providing a substrate; providing a semiconductor die stack comprising a first semiconductor die; mounting the semiconductor die stack on an upper surface of the substrate; forming a first barrier wall on an upper surface of the substrate, wherein the first barrier wall covers a side surface of the first semiconductor die and protrudes from the upper surface of the first semiconductor die; dispensing a first fluid material on an upper surface of the first semiconductor die, wherein the first barrier wall prevents the first fluid material from flowing across it; and curing the first fluid material to form a back side metallization (BSM) layer.

[0006] According to another aspect of the present application, a semiconductor package is provided. The semiconductor package may comprise: a substrate; a semiconductor die stack mounted on an upper surface of the substrate, wherein the semiconductor die stack comprises a first semiconductor die; a first barrier wall formed on an upper surface of the substrate, wherein the first barrier wall covers a side surface of the first semiconductor die and protrudes from an upper surface of the first semiconductor die; and a back metallization (BSM) layer formed on an upper surface of the first semiconductor die, wherein the BSM layer is at least partially surrounded by the first barrier wall.

[0007] It should be understood that the foregoing general description and the following detailed description are both illustrative and illustrative and do not limit the invention. Additionally, the accompanying drawings, incorporated herein and constituting part of this specification, serve to illustrate embodiments of the invention and, together with the description, explain the principles of the invention. Brief explanation of the drawing

[0008] The drawings mentioned herein constitute part of the specification. The features illustrated in the drawings illustrate only some of the embodiments of the application, not all of the embodiments of the application, unless the detailed description expressly indicates otherwise, and readers of the specification should not imply otherwise. FIG. 1a is a cross-sectional view of a semiconductor package having a semiconductor die stack. Figure 1b is a microscopic image illustrating a back side metallization (BSM) layer of a semiconductor package. FIGS. 2a through 2k are cross-sectional or plan views illustrating various steps of a method for forming a semiconductor package according to an embodiment of the present application. FIGS. 3a to 3c are cross-sectional views illustrating various steps of a method for forming a semiconductor package according to another embodiment of the present application. FIGS. 4a to 4c are cross-sectional views illustrating various steps of a method for forming a semiconductor package according to another embodiment of the present application. FIG. 5a is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present application. FIG. 5b illustrates an enlarged view of a portion of the semiconductor package shown in FIG. 5a. The same reference numbers will be used throughout the drawings to refer to identical or similar parts. Specific details for implementing the invention

[0009] The following detailed description of exemplary embodiments of the present application refers to the accompanying drawings, which form part of the description. The drawings illustrate specific exemplary embodiments in which the present application may be practiced. The detailed description including the drawings describes these embodiments in sufficient detail to enable those skilled in the art to practice the present application. Those skilled in the art may further utilize other embodiments of the present application and may make logical, mechanical, and other modifications without departing from the spirit or scope of the present application. Accordingly, readers of the following detailed description should not interpret it in a limiting sense, and only the appended claims define the scope of the embodiments of the present application.

[0010] In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of "or" means "and / or" unless otherwise specified. Furthermore, the use of the term "including" as well as other forms such as "includes" and "included" is not limited. Also, terms such as "element" or "component" include both elements and components comprising one unit and elements and components comprising one or more subunits, unless specifically stated otherwise. Additionally, section headings used in this specification are for organizational purposes only and should not be interpreted as limiting the subject matter described.

[0011] As used herein, spatially relative terms such as "beneath," "below," "above," "over," "on," "upper," "lower," "left," "right," "vertical," "horizontal," "side," and similar terms may be used herein for convenience of explanation to describe the relationship between one element or feature and another element(s) or feature(s), as illustrated in the drawings. Spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device may be oriented differently (rotated 90 degrees or in a different orientation), and spatially relative terms used herein may likewise be interpreted accordingly. When an element is referred to as being "connected" or "combined" with another element, it must be understood that the element may be directly connected or combined with the other element, or that intervening elements may exist.

[0012] FIG. 1a is a cross-sectional view of a semiconductor package (100) having a semiconductor die stack. Specifically, the semiconductor package (100) includes a first semiconductor die (110) mounted on a substrate (130) and a second semiconductor die (120) stacked on top of the first semiconductor die (110). To dissipate heat generated by the semiconductor package (100) during operation, the first semiconductor die (110) is thermally coupled to a heat diffuser (140) through a thermal interface material (TIM) layer (112) and a metal support (160), and the second semiconductor die (120) is also thermally coupled to the heat diffuser (140) through another TIM layer (122), so that heat generated by the first semiconductor die (110) and the second semiconductor die (120) can be transferred to the heat diffuser (140) and additionally to the external environment. However, as illustrated in FIG. 1a, the second semiconductor die (120), which is used as a path for the heat (118) generated by the first semiconductor die (110), may block the dissipation of the heat (118) because the material of the second semiconductor die (120) (e.g., silicon) may not have ideal thermal conductivity. Therefore, the performance of the semiconductor package (100) may be negatively affected due to poor heat dissipation.

[0013] The TIM layer (112) and the TIM layer (122) may be made of a metal material having high thermal conductivity. However, metal TIMs generally require a back metallization (BSM) layer formed on a semiconductor die (e.g., a first semiconductor die (110) or a second semiconductor die (120) mounted on a substrate (130)) to improve bonding performance. To apply a laser assist bonding (LAB) method for flip-chip soldering, dispensing techniques such as inkjet printing are generally used to form a BSM layer on the semiconductor die. However, as illustrated in FIG. 1b, the inventors of the present applicant have discovered that the BSM layer may have a tapering shape in its peripheral regions, which may be caused by the flow properties of the material (e.g., ink composition) used to form the BSM layer. As a result, voids or delamination may occur between the metal TIM layer and the BSM layer and / or between the BSM layer and the semiconductor die, which can reduce the heat dissipation capacity of the semiconductor package. Additionally, the inventors of the present applicant have discovered that the BSM layer may be consumed after soldering with the metal TIM layer, and thus more delamination may be induced between the BSM layer and the semiconductor die.

[0014] To solve at least one of the above problems, a method for forming a semiconductor package is provided. In this method, a semiconductor die stack is provided, comprising a first semiconductor die and a second semiconductor die mounted on the first semiconductor die. After the semiconductor die stack is mounted on the upper surface of a substrate, a first barrier wall is formed on the upper surface of the substrate. The first barrier wall covers the side surface of the first semiconductor die and protrudes from the upper surface of the first semiconductor die. The first barrier wall can prevent a fluid material used to form the BSM layer from flowing across it, so that the BSM layer can have a uniform thickness. Accordingly, the gap or delamination between the BSM layer and the first semiconductor die can be reduced, and the heat dissipation capacity of the semiconductor package can be improved.

[0015] Referring to FIGS. 2a through 2k, various steps of a method for forming a semiconductor package according to an embodiment of the present application are illustrated. Hereinafter, the method will be described in more detail with reference to FIGS. 2a through 2k.

[0016] Referring to FIG. 2a, a semiconductor die stack (201) is provided. The semiconductor die stack (201) may include a first semiconductor die (210) and a second semiconductor die (220).

[0017] The first semiconductor die (210) and / or the second semiconductor die (220) may include any of a logic chip, a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a radio frequency circuit, a wireless baseband system on chip (SoC) processor, a sensor, a memory controller, or a memory device. In certain examples, the first semiconductor die (210) may be a logic chip and the second semiconductor die (220) may be a memory chip. However, the present application is not limited to the above examples. In some other embodiments, there may be more than one semiconductor die bonded vertically on the first semiconductor die. In some embodiments, the first semiconductor die (210) and the second semiconductor die (220) may each have a bottom surface and a top surface. In some embodiments, the lower surface may be an active surface on which a surface manufacturing process can be implemented to form various types of semiconductor devices. The upper surface may serve as a support surface to which other electronic components can be attached. That is, the second semiconductor die (220) is flip-chip laminated on the upper surface of the first semiconductor die (210). In the example illustrated in FIG. 2a, the second semiconductor die (220) covers a central area but exposes a peripheral area of ​​the upper surface of the first semiconductor die (210). However, the present application is not limited to this example. In other embodiments, the second semiconductor die (220) is laminated on other locations on the upper surface of the first semiconductor die (210) but exposes at least a portion of the upper surface of the first semiconductor die (210) for heat dissipation.

[0018] As illustrated in FIG. 2a, the first semiconductor die (210) and the second semiconductor die (220) are bonded together by an interconnect layer (215). For example, the second semiconductor die (220) may be mounted on the upper surface of the first semiconductor die (210) by hybrid bonding. The interconnect layer (215) may include a dielectric material and conductive interconnect structures extending through the dielectric material between the first semiconductor die (210) and the second semiconductor die (220). For example, the conductive interconnect structures may include copper posts and may be electrically coupled with through silicon vias (TSVs) formed in the first semiconductor die (210). However, the present application is not limited to the above examples. In other embodiments, the interconnect layer (215) may include a ball grid array (BGA) or other suitable interconnect structures. Additionally, the first semiconductor die (210) may include a plurality of conductive bumps (212) formed on its lower surface. In the example illustrated in FIG. 2a, the conductive bumps (212) are exemplified as solder bumps, but the present application is not limited thereto. In some other embodiments, the conductive bumps (212) may include conductive fillers or copper balls. The conductive bumps (212) may be used to electrically connect the semiconductor die stack (201) to an external device or substrate.

[0019] Referring to FIG. 2b, a substrate (230) is provided, and a semiconductor die stack (201) is mounted on the upper surface of the substrate (230).

[0020] The substrate (230) may support the semiconductor die stack (201) and further connect the semiconductor die stack (201) to other electronic components. For example, the substrate (230) may be a printed circuit board. However, the substrate (230) is not limited thereto. In other examples, the substrate (230) may be a semiconductor substrate, a laminate interposer, a strip interposer, a lead frame, or other suitable substrates. According to the scope of the present application, the substrate (230) may include any structure on which integrated circuit systems are manufactured on or in the substrate. For example, the substrate (230) may include one or more insulating layers or passivation layers, one or more conductive vias formed through the insulating layers, and one or more conductive layers formed over or between the insulating layers. For example, redistribution structures (RDS) may be formed on a substrate (230), and include a plurality of upper conductive patterns on the upper surface of the substrate (230), a plurality of lower conductive patterns on the lower surface of the substrate (230), and a plurality of conductive vias electrically connecting at least one of the upper conductive patterns to at least one of the lower conductive patterns.

[0021] In some embodiments, the semiconductor die stack (201) may be placed on the substrate (230) using a pick-and-place operation with the conductive bumps (212) of the first semiconductor die (210) oriented toward the substrate (230). The conductive bumps (212) may come into contact with the upper conductive pattern of the RDS within the substrate (230). In some embodiments, a laser-assisted bonding (LAB) process may be performed to mount the semiconductor die stack (201) on the substrate (230) through the conductive bumps (212). However, the present application is not limited to the above embodiments. In some other embodiments, a mass reflow process or a thermocompression bonding process may be performed to mount the semiconductor die stack (201) on the upper surface of the substrate (230). In some embodiments, an underfill encapsulant (232) may be formed between the first semiconductor die (210) and the substrate (230). The underfill encapsulant (232) may comprise a polymer composite material such as epoxy resin, epoxy acrylate, or a polymer with or without a filler. The underfill encapsulant (232) may provide mechanical support to the conductive bumps (212) to help mitigate the risk of cracking or delamination due to differential thermal expansion between the first semiconductor die (210) and the substrate (230).

[0022] Referring to FIG. 2c, a first barrier wall (240) is formed on the upper surface of the substrate (230). The first barrier wall (240) covers the side surface of the first semiconductor die (210) and may protrude from the upper surface of the first semiconductor die (210).

[0023] In some embodiments, a direct dispensing apparatus may be used to dispense a fluid composition comprising a photocurable material and / or a thermosetting material onto the upper surface of the substrate (230) and around the underfill encapsulator (232) and the first semiconductor die (210), after which the fluid composition may be cured to form a first barrier wall (240). Depending on the properties of the fluid composition, the fluid composition may be cured by ultraviolet (UV), infrared (IR), or near-infrared (NIR) radiation, or at a predetermined temperature for a predetermined period.

[0024] For example, an inkjet printing device may be used to form a first barrier wall (240) on a substrate (230). The inkjet printing device may include a dispensing nozzle configured to dispense an ink composition and a light source configured to irradiate a light beam with a predetermined intensity. Specifically, the dispensing nozzle of the inkjet printing device is controlled to generate droplets of an ink composition with a diameter of several to tens of micrometers, which are to be projected toward the substrate (230). By moving the substrate (230) or the dispensing nozzle relative to each other, the droplets may be dispensed onto the upper surface of the substrate (230) at the location where the first barrier wall (240) is to be formed. The light source of the inkjet printing device may be controlled to irradiate a light beam to cure the material within the droplets. A first barrier wall (240) can be formed on the upper surface of the substrate (230) by continuously moving the dispensing nozzle of the substrate (230) or the inkjet printing device, dispensing droplets of the ink composition, and curing the droplets by light irradiation. In another example, an aerosol printing device may be used to form the first barrier wall (240) on the substrate (230). The aerosol printing device may atomize the fluid composition via ultrasonic or pneumatic means to produce droplets with a diameter of one to several micrometers. The droplets may be entrained in a gas stream and delivered to a print head. At the print head, a sheath gas flow may be introduced to focus the droplets into a tightly collimated beam of material. Afterwards, the combined gas streams can be ejected from the print head through a converging nozzle that compresses the aerosol stream into particles or droplets with a small diameter.A jet of droplets can fly out of the print head at high speed and collide with the upper surface of the substrate (230), and the droplets can be continuously dispensed onto the upper surface of the substrate (230) by moving the print head of the aerosol printing device. Afterward, the fluid composition can be cured to form a first barrier wall (240). Since the inkjet printing device and the aerosol printing device can accurately control the position and / or dispensing time of the droplets, the first barrier wall (240) can be formed directly in a desired area having a desired shape without any mask or any photolithography process. It should be understood that the present application is not limited to the above embodiments, and that the first barrier wall (240) can be formed by any other suitable printing device, such as an electrohydrodynamic (EHD) printing device, a nozzle printing device, or a spray coating device.

[0025] In some embodiments, the fluid composition for forming the first barrier wall (240) may include an epoxy compound. The epoxy compound may include various photosensitive resin compositions or various thermosetting resin compositions. In some embodiments, the first barrier wall (240) may include other dielectric / insulating materials having sufficient properties such as hardness, heat resistance, chemical resistance, and / or electrical insulation reliability. In some embodiments, the first barrier wall (240) may include a solder resist, a paste, a UV-curable material, a fluid including a metal precursor, and / or other materials having high viscosity that can be coated by inkjet printing, aerosol printing, EHD printing, nozzle printing, or spray coating techniques.

[0026] FIG. 2d illustrates a plan view of the structure illustrated in FIG. 2c. In some embodiments, as illustrated in FIG. 2d, the first barrier wall (240) may have a width in the range of micrometers to millimeters and may be formed along four edges of the first semiconductor die (210). Thus, the first barrier wall (240) forms a closed ring having rectangular geometric footprints on the upper surface of the substrate (230). The first barrier wall (240) may have a rectangular cross section, a trapezoidal cross section, or other polygonal cross sections. It should be understood that the present application is not limited to the example illustrated in FIG. 2d. In other embodiments, depending on the shape of the first semiconductor die (210), the first barrier wall (240) may form a closed or partially closed ring having square, hexagonal, or any other geometric footprints on the upper surface of the substrate (230).

[0027] In some embodiments, a second barrier wall may be formed on the upper surface of the first semiconductor die (210). The second barrier wall may cover the side surface of the second semiconductor die (220). Thus, in subsequent steps, fluid material dispensed on the upper surface of the first semiconductor die (210) may be restricted between the first barrier wall (240) and the second barrier wall. In some embodiments, the second barrier wall may also protrude from the upper surface of the first semiconductor die (210) to prevent any fluid material dispensed on the upper surface of the second semiconductor die (210) from flowing across it.

[0028] Referring to FIG. 2e, a first fluid material is dispensed onto the upper surface of a first semiconductor die (210), and then the first fluid material is cured to form a back metallized (BSM) layer (252).

[0029] Specifically, the first fluid material may be dispensed onto the upper surface of the first semiconductor die (210) using an inkjet printing device, an aerosol printing device, an EHD printing device, a nozzle printing device, or a spray coating device. As the first barrier wall (240) covers the side surface of the first semiconductor die (210) and protrudes from the upper surface of the first semiconductor die (210), the first barrier wall (240) may prevent the first fluid material from flowing across it. After the first fluid material is cured by UV, IR, or NIR radiation or under a predetermined temperature for a predetermined period, the BSM layer (252) may be formed with a generally uniform thickness. That is, the BSM layer (252) does not have a tapering shape in its surrounding regions and may assist the TIM layer formed in a subsequent process to adhere to the first semiconductor die (210). In some embodiments, the BSM layer (252) may comprise one or more materials selected from the group consisting of silver, copper, gold, or aluminum. However, the BSM layer (252) is not limited to the above materials and may comprise other suitable materials.

[0030] Referring to FIG. 2f, a second fluid material is dispensed onto the BSM layer (252), and then the second fluid material is cured to form a barrier layer (254) on the BSM layer (252).

[0031] Specifically, the second fluid material may be dispensed onto the BSM layer (252) using an inkjet printing device, an aerosol printing device, an EHD printing device, a nozzle printing device, or a spray coating device. The first barrier wall (240) may have a height sufficient to prevent the second fluid material from flowing across it. After the second fluid material is cured by UV, IR, or NIR radiation or under a predetermined temperature for a predetermined period, a barrier layer (254) may be formed on the BSM layer (252). The barrier layer (254) may reduce the consumption of the BSM layer (252) during a subsequent soldering process. In some embodiments, the barrier layer (254) may comprise one or more materials selected from the group consisting of nickel, titanium, silicon oxide, aluminum oxide, graphene, boron nitride, or molybdenum sulfide. However, the barrier layer (254) is not limited to the above materials and may comprise other suitable materials.

[0032] In the above embodiments, the second fluid material is dispensed after the first fluid material has cured. However, the present application is not limited thereto. In other embodiments, the second fluid material may be dispensed onto the first fluid material, and then the first fluid material and the second fluid material are cured simultaneously.

[0033] Referring to FIG. 2g, a first thermal interface material (TIM) layer (256) is placed on a barrier layer (254).

[0034] In some embodiments, the first TIM layer (256) may comprise indium or an indium-silver (InAg) alloy. However, the first TIM layer (256) is not limited to the above materials and may comprise other materials having high thermal conductivity. In some embodiments, the first TIM layer (256) may be pre-formed and attached to the barrier layer (254). That is, the first TIM layer (256) will not be in direct contact with the BSM layer (252). In one example, a first soldering flux layer may be formed on the lower surface of the first TIM layer (256), and a second soldering flux layer may be formed on the upper surface of the first TIM layer (256). Accordingly, the first TIM layer (256) can be attached to the barrier layer (254) through the first soldering flux layer, and other components can be attached to the TIM layer (256) through the second soldering flux layer. The first soldering flux layer and the second soldering flux layer can facilitate the reflow of the first TIM layer (256) in subsequent processes. However, the present application is not limited to the above embodiments, and in some other embodiments, the first TIM layer (256) may be formed on the barrier layer (254) using sputtering, electroplating, electroless plating, or other suitable deposition processes.

[0035] Referring to FIG. 2h, a heat transfer component (262) is placed on the first TIM layer (256).

[0036] In some embodiments, the upper surface of the heat transfer component (262) is substantially coplanar with or coplanar with the upper surface of the second semiconductor die (220) to facilitate the attachment of a heat diffuser in a subsequent process. The heat transfer component (262) can serve as a path to the heat diffuser for the heat generated by the first semiconductor die (210) during operation. In some embodiments, the heat transfer component (262) can completely surround the second semiconductor die (220). In some embodiments, the heat transfer component (262) can partially surround the second semiconductor die (220). In some embodiments, the heat transfer component (262) may include a plurality of sub-blocks, such as four sub-blocks each positioned adjacent to the four lateral sides of the second semiconductor die (220).

[0037] In some embodiments, the heat transfer component (262) may comprise copper, aluminum, nickel-plated copper, nickel-plated aluminum, or other materials having high thermal conductivity. In one example, a first surface finishing layer may be formed on the lower surface of the heat transfer component (262), and a second surface finishing layer may be formed on the upper surface of the heat transfer component (262). The first and second surface finishing layers may prevent oxidation of the heat transfer component (262). In this example, the heat transfer component (262) is attached to the first TIM layer (256) through the first surface finishing layer. Thus, the first surface finishing layer may comprise a material suitable for wetting the first TIM layer (256). In some embodiments, the first and second surface finishing layers may comprise gold. In some embodiments, the first and second surface finishing layers may comprise other materials such as silver or indium.

[0038] In some embodiments, after the heat transfer component (262) is placed on the first TIM layer (256), the first TIM layer (256) is reflowed to solder the first TIM layer (256) and the barrier layer (254) together, and to solder the first TIM layer (256) and the heat transfer component (262) together so that the heat transfer component (262) is firmly attached to the upper surface of the first semiconductor die (210). Specifically, the first TIM layer (256) may be heated above its melting point, thereby allowing the soldering flux between the first TIM layer (256) and the barrier layer (254) to flow into the environment, and the first TIM layer (256) and the barrier layer (254) may react to form an intermetallic compound (IMC). IMC can improve adhesion between the first TIM layer (256) and the barrier layer (254). Similarly, when the first TIM layer (256) is heated above its melting point, the soldering flux between the first TIM layer (256) and the heat transfer component (262) can leak into the environment, and the first TIM layer (256) and the heat transfer component (262) can react to form another IMC, which can improve adhesion between the first TIM layer (256) and the heat transfer component (262).

[0039] Referring to FIG. 2i, the second TIM layer (264) is placed on the second semiconductor die (220), and the third TIM layer (266) is placed on the heat transfer component (262).

[0040] The second TIM layer (264) and the third TIM layer (266) may be pre-formed and attached to the second semiconductor die (220) and the heat transfer component (262), respectively. The second TIM layer (264) and / or the third TIM layer (266) may comprise a material identical or different from the first TIM layer (256), for example, indium or an InAg alloy. In some embodiments, a soldering flux may be formed on the lower and upper surfaces of the second TIM layer (264) and / or the third TIM layer (266) to facilitate subsequent soldering processes. In some other embodiments, the second TIM layer (264) and / or the third TIM layer (266) may be formed on the second semiconductor die (220) and / or the heat transfer component (262) using sputtering, electroplating, electroless plating, or other suitable deposition processes.

[0041] Referring to FIG. 2j, a heat diffuser (270) is provided. The heat diffuser (270) may include a cover (270a) and a first side portion (270b) extending downward from the cover (270a). An adhesive layer (272) may be formed on the upper surface of a substrate (230), and then the first side portion (270b) of the heat diffuser (270) is attached to the upper surface of the substrate (230) through the adhesive layer (272) with the cover (270a) in contact with the second TIM layer (264) and the third TIM layer (266).

[0042] In some embodiments, the adhesive layer (272) may comprise a solder material and is dispensed onto the upper surface of the substrate (230). In some embodiments, the adhesive layer (272) may comprise a conductive or non-conductive film, a UV film, an instant adhesive, a thermosetting adhesive, or any other suitable adhesive material. In some embodiments, the heat diffuser (270) may comprise copper, aluminum, nickel, or other metal materials. However, the heat diffuser (270) is not limited to the above materials and may comprise other materials having high thermal conductivity. To facilitate bonding between the heat diffuser (270) and the second TIM layer (264) and the third TIM layer (266), a surface finishing layer may be formed on the bottom surface of the cover (270a).

[0043] After the first side portion (270b) of the heat diffuser (270) is attached to the upper surface of the substrate (230) through the adhesive layer (272), the second TIM layer (264) and the third TIM layer (266) can be reflowed, so that the cover (270a) of the heat diffuser (270) can be attached to the second semiconductor die (220) and the heat transfer component (262). Consequently, the first semiconductor die (210) is thermally bonded to the cover (270a) of the heat diffuser (270) through the BSM layer (252), the barrier layer (254), the first TIM layer (256), the heat transfer component (262), and the third TIM layer (266); and the second semiconductor die (220) is thermally bonded to the cover (270a) of the heat diffuser (270) through the second TIM layer (264). Therefore, the heat dissipation capacity of the semiconductor package can be improved.

[0044] After that, referring to FIG. 2k, a plurality of conductive bumps (236) can be formed on the lower surface of the substrate (230).

[0045] For example, conductive bumps (236) may be formed on conductive patterns on the lower surface of the substrate (230) to electrically connect with the first semiconductor die (210) and / or the second semiconductor die (220). In the example illustrated in FIG. 2k, the conductive bumps (236) are exemplified as solder bumps, but the present application is not limited thereto. In some other embodiments, the conductive bumps (236) may include conductive fillers or copper balls. When the semiconductor package is mounted on an external device or substrate, such as a printed circuit board (PCB), the conductive bumps (212) may be used to electrically connect the semiconductor package to the external device or substrate.

[0046] In the above example illustrated in FIGS. 2a through 2k, the first TIM layer (256) is reflowed first after the heat transfer component (262) is placed on the first TIM layer (256), and then the second TIM layer (264) and the third TIM layer (266) are reflowed after the first side portion (270b) of the heat diffuser (270) is attached to the upper surface of the substrate (230). However, the present application is not limited thereto. In some other embodiments, the first TIM layer (256), the second TIM layer (264), and the third TIM layer (266) may be reflowed simultaneously, for example, after the first side portion (270b) of the heat diffuser (270) is attached to the upper surface of the substrate (230).

[0047] Referring to FIGS. 3a through 3c, various steps of a method for forming a semiconductor package according to another embodiment of the present application are illustrated.

[0048] Referring to FIG. 3a, a package (302) is provided. The package (302) may include a substrate (330), a first semiconductor die (310) mounted on the upper surface of the substrate (330), and a second semiconductor die (320) mounted on the upper surface of the first semiconductor die (310). A first barrier wall (340) is formed on the upper surface of the substrate (330), and the first barrier wall (340) covers the side surface of the first semiconductor die (310) and protrudes from the upper surface of the first semiconductor die (310). A BSM layer (352) is formed on the upper surface of the first semiconductor die (310) and is at least partially surrounded by the first barrier wall (340). Additionally, a barrier layer (354) is formed on the BSM layer (352), and a first TIM layer (356) is formed on the barrier layer (354). The package (302) shown in FIG. 3a is similar to the structure shown in FIG. 2g and will not be described in detail here.

[0049] Referring to FIG. 3b, a heat diffuser (370) is provided. The heat diffuser (370) may include a cover (370a) and a first side portion (370b) extending downward from the cover (370a). Then, a heat transfer component (362) may be attached to the lower surface of the cover (370a) of the heat diffuser (370). For example, the heat transfer component (362) may be attached to the lower surface of the cover (370a) through a third TIM layer (366). However, the present application is not limited thereto. In some other embodiments, the heat transfer component (362) may be attached to the lower surface of the cover (370a) through other attachment methods such as welding, brazing, soldering, or pressing.

[0050] Then, referring to FIG. 3c, a second TIM layer (364) is placed on the second semiconductor die (320). Then, an adhesive layer (372) may be formed on the upper surface of the substrate (330), and a first side portion (370b) of a heat diffuser (370) is attached to the upper surface of the substrate (330) through the adhesive layer (372) in such a state that the heat transfer component (362) is in contact with the first TIM layer (356) and the cover (370a) is in contact with the second TIM layer (364). Then, the first TIM layer (356) and the second TIM layer (364) are reflowed to attach the heat transfer component (362) to the first semiconductor die (310) and to attach the cover (370a) of the heat diffuser (370) to the second semiconductor die (320). Finally, a plurality of conductive bumps (336) may be formed on the lower surface of the substrate (330).

[0051] Referring to FIGS. 4a through 4c, various steps of a method for forming a semiconductor package according to another embodiment of the present application are illustrated.

[0052] Referring to FIG. 4a, a package (402) is provided. The package (402) may include a substrate (430), a first semiconductor die (410) mounted on the upper surface of the substrate (430), and a second semiconductor die (420) mounted on the upper surface of the first semiconductor die (410). A first barrier wall (440) is formed on the upper surface of the substrate (430), and the first barrier wall (440) covers the side surface of the first semiconductor die (410) and protrudes from the upper surface of the first semiconductor die (410). A BSM layer (452) is formed on the upper surface of the first semiconductor die (410) and is at least partially surrounded by the first barrier wall (440). Additionally, a barrier layer (454) is formed on the BSM layer (452), and a first TIM layer (456) is formed on the barrier layer (454). The package (402) shown in FIG. 4a is similar to the structure shown in FIG. 2g and will not be described in detail here.

[0053] Referring to FIG. 4b, a heat diffuser (470) is provided. The heat diffuser (470) may include a cover (470a) and a first side portion (470b) extending downward from the cover (470a). Unlike the heat diffuser (370) shown in FIG. 3b, the heat diffuser (470) further includes a second side portion (470c) extending downward from the cover (470a). Compared to the first side portion (470b), the second side portion (470c) is closer to the center region of the cover (470a). In some embodiments, the cover (470a), the first side portion (470b), and the second side portion (470c) are formed integrally as a single piece.

[0054] Then, referring to FIG. 4c, a second TIM layer (464) is placed on the second semiconductor die (420). Then, an adhesive layer (472) may be formed on the upper surface of the substrate (430), and the first side portion (470b) of the heat diffuser (470) is attached to the upper surface of the substrate (430) through the adhesive layer (472) in such a state that the second side portion (470c) of the heat diffuser (470) is in contact with the first TIM layer (456) and the cover (470a) is in contact with the second TIM layer (464). After that, the first TIM layer (456) and the second TIM layer (464) are reflowed to attach the second side portion (470c) of the thermal diffuser (470) on the first semiconductor die (410) and to attach the cover (470a) of the thermal diffuser (470) on the second semiconductor die (420). Finally, a plurality of conductive bumps (436) may be formed on the lower surface of the substrate (430).

[0055] According to another aspect of the present application, a semiconductor package is provided. Referring to FIG. 5a and FIG. 5b, FIG. 5a illustrates a cross-sectional view of a semiconductor package (500) according to an embodiment of the present application, and FIG. 5b illustrates an enlarged view of a portion (503) of the semiconductor package (500) shown in FIG. 5a.

[0056] Referring to both FIG. 5a and FIG. 5b, a semiconductor package (500) may comprise, for example, a substrate (530), a first semiconductor die (510) mounted on the upper surface of the substrate (530) by hybrid bonding, and a second semiconductor die (520) mounted on the upper surface of the first semiconductor die (510). A first barrier wall (540) is formed on the upper surface of the substrate (530), and the first barrier wall (540) covers the side surface of the first semiconductor die (510) and protrudes from the upper surface of the first semiconductor die (510). A BSM layer (552) is formed on the upper surface of the first semiconductor die (510) and is at least partially surrounded by the first barrier wall (540). In some embodiments, a barrier layer (554) is formed on the BSM layer (552), and the barrier layer (554) is at least partially surrounded by the first barrier wall (540). The BSM layer (552) may include silver, copper, gold, or aluminum, and the barrier layer (554) may include nickel, titanium, silicon oxide, aluminum oxide, graphene, boron nitride, or molybdenum sulfide.

[0057] In some embodiments, the first TIM layer (556) is attached to the barrier layer (554), the heat transfer component (562) is attached to the first TIM layer (556), and the third TIM layer (566) is attached to the heat transfer component (562). In the example illustrated in FIG. 5b, a first surface finishing layer (581) may be formed on the lower surface of the heat transfer component (562) to improve the interface characteristics between the heat transfer component (562) and the first TIM layer (556), and a second surface finishing layer (582) may be formed on the upper surface of the heat transfer component (562) to improve the interface characteristics between the heat transfer component (562) and the third TIM layer (566).

[0058] In some embodiments, the semiconductor package (500) may further include a heat diffuser (570) having a cover (570a) and a first side portion (570b) extending downward from the cover (570a). The first side portion (570b) of the heat diffuser (570) may be attached to the upper surface of the substrate (530) through an adhesive layer (572). The cover (570a) of the heat diffuser (570) is attached to the second semiconductor die (520) through a second TIM layer (564) and to the heat transfer component (562) through a third TIM layer (566). In the example illustrated in FIG. 5b, a third surface finishing layer (583) may be formed on the lower surface of the cover (570a) of the heat diffuser (570) to improve the interface characteristics between the cover (570a) of the heat diffuser (570) and the third TIM layer (566).

[0059] The semiconductor package (500) may be formed by the method described above with reference to FIGS. 2a through 2k or by the method described above with reference to FIGS. 3a through 3c. Accordingly, more details regarding the semiconductor package (500) may be provided by referring to the disclosures and drawings regarding the methods disclosed above, and will not be described in detail here.

[0060] Although the semiconductor package of the present application is described with reference to FIGS. 5a and 5b, those skilled in the art will understand that modifications and adaptations to the semiconductor package may be made without departing from the scope of the invention. For example, in some other embodiments, a second barrier wall may be formed on the upper surface of the first semiconductor die. The second barrier wall may cover the side surface of the second semiconductor die and protrude from the upper surface of the second semiconductor die. In some other embodiments, the heat diffuser may further include a second side portion extending downward from the cover. Thus, the second side portion of the heat diffuser may be directly attached to the first semiconductor die through the first TIM layer. That is, the heat transfer component may be omitted in these embodiments. For example, the semiconductor package of these embodiments may be formed by the method described above with reference to FIGS. 4a through 4c.

[0061] The discussion in this specification includes numerous exemplary drawings illustrating various parts of a semiconductor package and methods for manufacturing the same. For the sake of clarity of illustration, these drawings do not illustrate all aspects of each exemplary semiconductor package. Any of the exemplary packages and / or methods provided in this specification may share any or all characteristics with any or all other packages and / or methods provided in this specification.

[0062] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes may be made and additional embodiments implemented without departing from the broader scope of the invention as set forth in the following claims. Furthermore, other embodiments will be apparent to those skilled in the art by considering the implementation and description of one or more embodiments of the invention disclosed herein. Accordingly, the examples in this application and this specification are to be regarded merely as illustrative, and the true scope and spirit of the invention are intended to be indicated by the following list of illustrative claims.

Claims

Claim 1 A method for forming a semiconductor package, comprising: providing a substrate; providing a semiconductor die stack including a first semiconductor die; mounting the semiconductor die stack on an upper surface of the substrate; forming a first barrier wall on an upper surface of the substrate, wherein the first barrier wall covers a side surface of the first semiconductor die and protrudes from an upper surface of the first semiconductor die; dispensing a first fluid material on an upper surface of the first semiconductor die, wherein the first barrier wall prevents the first fluid material from flowing across it; and curing the first fluid material to form a back side metallization (BSM) layer. Claim 2 A method according to claim 1, wherein the step of providing the semiconductor die stack comprises: the step of providing the first semiconductor die; and the step of mounting a second semiconductor die on the upper surface of the first semiconductor die by hybrid bonding. Claim 3 In paragraph 2, before dispensing the first fluid material onto the upper surface of the first semiconductor die, the method further comprises the step of forming a second barrier wall onto the upper surface of the first semiconductor die, wherein the second barrier wall covers the side surface of the second semiconductor die. Claim 4 A method according to claim 3, further comprising the step of dispensing a second fluid material onto the BSM layer—wherein the first barrier wall prevents the second fluid material from flowing across it—; and the step of curing the second fluid material to form a barrier layer on the BSM layer. Claim 5 A method according to claim 4, further comprising: forming an adhesive layer on the upper surface of the substrate; providing a heat spreader comprising a cover and a first lateral portion extending downward from the cover; and attaching the first lateral portion of the heat spreader to the upper surface of the substrate through the adhesive layer. Claim 6 A method according to claim 5, further comprising: a step of placing a first thermal interface material (TIM) layer on the barrier layer; a step of placing a heat transfer component on the first TIM layer; a step of reflowing the first TIM layer to attach the heat transfer component to the first semiconductor die; a step of placing a second TIM layer on the second semiconductor die; a step of placing a third TIM layer on the heat transfer component; a step of placing the heat diffuser on the second semiconductor die such that the cover is in contact with the second TIM layer and the third TIM layer; and a step of reflowing the second TIM layer and the third TIM layer to attach the cover of the heat diffuser to the second semiconductor die and the heat transfer component. Claim 7 A method according to claim 5, further comprising: a step of placing a first thermal interface material (TIM) layer on the barrier layer; a step of placing a heat transfer component on the first TIM layer; a step of placing a second TIM layer on the second semiconductor die; a step of placing a third TIM layer on the heat transfer component; a step of placing the heat diffuser on the second semiconductor die such that the cover is in contact with the second TIM layer and the third TIM layer; and a step of reflowing the first TIM layer, the second TIM layer, and the third TIM layer to attach the heat transfer component on the first semiconductor die and attach the cover of the heat diffuser on the second semiconductor die and the heat transfer component. Claim 8 A method according to claim 5, further comprising: a step of placing a first thermal interface material (TIM) layer on the barrier layer; a step of attaching a heat transfer component on the lower surface of the cover of the heat diffuser; a step of placing a second TIM layer on the second semiconductor die; a step of placing the heat diffuser on the second semiconductor die such that the heat transfer component is in contact with the first TIM layer and the cover is in contact with the second TIM layer; and a step of reflowing the first TIM layer and the second TIM layer to attach the heat transfer component on the first semiconductor die and attach the cover of the heat diffuser on the second semiconductor die. Claim 9 A method according to any one of claims 6 to 8, wherein a first surface finishing layer is formed on the lower surface of the heat transfer component and a second surface finishing layer is formed on the upper surface of the heat transfer component. Claim 10 In claim 5, the thermal diffuser further comprises a second side portion extending downward from the cover, and the method further comprises: a step of placing a first thermal interface material (TIM) layer on the barrier layer; a step of placing a second TIM layer on the second semiconductor die; a step of placing the thermal diffuser on the second semiconductor die such that the second side portion contacts the first TIM layer and the cover contacts the second TIM layer; and a step of reflowing the first TIM layer and the second TIM layer to attach the second side portion of the thermal diffuser to the first semiconductor die and attach the cover of the thermal diffuser to the second semiconductor die. Claim 11 A semiconductor package comprising: a substrate; a semiconductor die stack mounted on an upper surface of the substrate, wherein the semiconductor die stack comprises a first semiconductor die; a first barrier wall formed on an upper surface of the substrate, wherein the first barrier wall covers a side surface of the first semiconductor die and protrudes from an upper surface of the first semiconductor die; and a back metallization (BSM) layer formed on an upper surface of the first semiconductor die, wherein the BSM layer is at least partially surrounded by the first barrier wall. Claim 12 A semiconductor package according to claim 11, wherein the semiconductor die stack further comprises a second semiconductor die mounted on the upper surface of the first semiconductor die by hybrid bonding. Claim 13 A semiconductor package according to claim 12, further comprising a second barrier wall formed on the upper surface of the first semiconductor die, wherein the second barrier wall covers the side surface of the second semiconductor die. Claim 14 A semiconductor package according to claim 13, further comprising a barrier layer formed on the BSM layer, wherein the barrier layer is at least partially surrounded by the first barrier wall. Claim 15 A semiconductor package according to claim 14, wherein the BSM layer comprises silver, copper, gold, or aluminum, and the barrier layer comprises nickel, titanium, silicon oxide, aluminum oxide, graphene, boron nitride, or molybdenum sulfide. Claim 16 A semiconductor package according to claim 14, further comprising: an adhesive layer formed on the upper surface of the substrate; and a heat diffuser comprising a cover and a first side portion extending downward from the cover, wherein the first side portion of the heat diffuser is attached to the upper surface of the substrate through the adhesive layer. Claim 17 A semiconductor package according to claim 16, further comprising: a first thermal interface material (TIM) layer attached to the barrier layer; a heat transfer component attached to the first TIM layer; a second TIM layer attached to the second semiconductor die; and a third TIM layer attached to the heat transfer component, wherein the cover of the heat diffuser is attached to the second semiconductor die and the heat transfer component, respectively, through the second TIM layer and the third TIM layer. Claim 18 A semiconductor package according to claim 16, further comprising: a first thermal interface material (TIM) layer attached to the barrier layer; a second TIM layer attached to the second semiconductor die; and a heat transfer component attached to the lower surface of the cover of the heat diffuser, wherein the heat transfer component is also attached to the first semiconductor die through the first TIM layer, and the cover of the heat diffuser is attached to the second semiconductor die through the second TIM layer. Claim 19 A semiconductor package according to claim 17 or 18, wherein a first surface finishing layer is formed on the lower surface of the heat transfer component and a second surface finishing layer is formed on the upper surface of the heat transfer component. Claim 20 In claim 16, the thermal diffuser further comprises a second side portion extending downward from the cover, and the semiconductor package further comprises: a first thermal interface material (TIM) layer attached to the barrier layer; and a second TIM layer attached to the second semiconductor die, wherein the second side portion of the thermal diffuser is attached to the first semiconductor die through the first TIM layer, and the cover of the thermal diffuser is attached to the second semiconductor die through the second TIM layer, the semiconductor package.

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