3D capacitance structure

Abstract

A 3D capacitance structure is provided, comprising a plurality of sub-capacitance stack structures, a plurality of first electrode contacts, and a plurality of second electrode contacts. Each sub-capacitance stack structure comprises a dielectric stack, a lower electrode structure, and an upper electrode structure. The dielectric stack comprises a stack of dielectric layers and etch stop layers. The lower electrode structure comprises a lower electrode plate disposed on a lower dielectric layer and a plurality of lower electrode extensions passing upward from the lower electrode plate through a lower etch stop layer to an intermediate dielectric layer. The upper electrode structure comprises an upper electrode plate disposed on an upper dielectric layer and a plurality of upper electrode extensions extending downward from the upper electrode plate to a lower etch stop layer. The first electrode contacts and the second electrode contacts are respectively connected to the lower and upper electrode plates of two adjacent layers in the sub-capacitance stack structures.

Description

Technology Field

[0001] The present disclosure relates to a capacitance structure, and more specifically, to a 3D capacitance structure. Background Technology

[0002] Due to technical bottlenecks caused by the successive miniaturization of chips, the industry has shifted from improving manufacturing processes to increase the number of transistors on a single silicon wafer area to improving overall performance through complex system-level chip designs at a relatively manageable cost. 'Chiplets' have garnered significant attention for enabling higher transistor density and performance at a relatively lower cost.

[0003] Chiplets are intended to divide the many elements originally contained in a single chip into multiple small units, and to individually enhance, redesign, and remanufacture their functions to form a system chip through advanced packaging technology.

[0004] However, a single capacitor in a chiplet is limited to being manufactured on a silicon substrate, but it cannot be made into a capacitor with too high a capacitance, and therefore the capacitance is limited and cannot be increased.

[0005] The 3D capacitance structure of the present disclosure comprises a substrate, a plurality of sub-capacitance stack structures, a plurality of first electrode contacts, and a plurality of second electrode contacts. The sub-capacitance stack structures are disposed on the substrate. Each sub-capacitance stack structure comprises a dielectric stack, a lower electrode structure, and an upper electrode structure. The dielectric stack comprises a stack of a lower dielectric layer, a lower etching stop layer, an intermediate dielectric layer, an upper etching stop layer, and an upper dielectric layer. The lower electrode structure includes a lower electrode plate disposed on a lower dielectric layer and a plurality of lower electrode extended portions passing upward from the lower electrode plate through a lower etch stop layer to an intermediate dielectric layer. The upper electrode structure includes an upper electrode plate disposed on an upper dielectric layer and a plurality of upper electrode extended portions passing downward from the upper electrode plate through an upper etch stop layer and an intermediate dielectric layer to a lower etch stop layer.First electrode contacts each connect the lower electrode plates of two adjacent layers in the sub-capacitance stack structures. Second electrode contacts each connect the upper electrode plates of two adjacent layers in the sub-capacitance stack structures. In the two adjacent lower electrode extensions and upper electrode extensions, the top end of the lower electrode extension is located above the bottom end of the upper electrode extension. Each of the plurality of first electrode contacts is connected to two adjacent lower electrode plates. Each of the plurality of second electrode contacts is connected to two adjacent upper electrode plates. The intermediate dielectric layer comprises an upper layer and a lower layer, the upper layer of the intermediate dielectric layer contacts the upper etch stop layer, and the lower layer of the intermediate dielectric layer contacts the lower etch stop layer. The upper layer of the intermediate dielectric layer is used as a structural boundary to limit the top stop position of the lower electrode extension. The lower etching stop layer is used as a structural boundary to limit the bottom stop position of the upper electrode extension.

[0006] A method for manufacturing a 3D capacitance structure according to the present disclosure comprises: (a) forming a first lower electrode plate on a substrate; (b) forming a first dielectric stack on the first lower electrode plate, wherein the first dielectric stack comprises a stack of a lower dielectric layer, an etch stop layer, and an upper dielectric layer; (c) forming a plurality of first lower electrode extensions on the first dielectric stack, wherein the first lower electrode extensions pass upward from the first lower electrode plate through the etch stop layer to the upper dielectric layer; (d) forming a second dielectric stack, wherein the structure of the second dielectric stack is identical to that of the first dielectric stack; (e) forming a plurality of first upper electrode extensions on the second dielectric stack, wherein the first upper electrode extensions pass through the etch stop layer of the second dielectric stack and extend to the etch stop layer of the first dielectric stack; and (f) forming a first upper electrode plate on the upper dielectric layer of the second dielectric stack, wherein the first upper electrode plate is connected to the first upper electrode extensions. -, (g) a step of forming a third dielectric stack - the structure of the third dielectric stack is identical to the first dielectric stack -, (h) a step of forming a first contact opening passing through the third dielectric stack, the second dielectric stack, and the first dielectric stack until the first lower electrode plate is exposed, (i) a step of forming a lower electrode plate trench in the upper dielectric layer of the third dielectric stack - the lower electrode plate trench and the first contact opening form a first dual damascene opening -, (j) a step of forming a conductor material in the first dual damascene opening to simultaneously form the first electrode contact and the second lower electrode plate, (k) a fourth dielectric stack,A step of repeating steps (b) through (d) to form a plurality of second lower electrode extensions and a fifth dielectric stack; (l) a step of forming a second contact opening through the fifth dielectric stack, the fourth dielectric stack, and the third dielectric stack until the first upper electrode plate is exposed; (m) a step of forming a plurality of extended portion openings through the fifth dielectric stack and the upper dielectric layer of the fourth dielectric stack until the etching stop layer of the fourth dielectric stack is exposed; (n) a step of forming an upper electrode plate trench in the upper dielectric layer of the fifth dielectric stack—the upper electrode plate trench, the extended portion openings, and the second contact opening form a second dual damascene opening—; (o) a step of forming a conductive material in the second dual damascene opening to simultaneously form a second electrode contact, a plurality of second upper electrode extensions, and a second upper electrode plate; and (p) the steps of (g) and (d) Includes the step of repeating (o) at least once.

[0007] To make the features and advantages of the present disclosure more easily understandable, specific embodiments below are described in detail in conjunction with the drawings. Brief explanation of the drawing

[0008] FIG. 1 is a schematic cross-sectional view of a 3D capacitance structure according to a first embodiment of the present disclosure. FIG. 2 is a schematic cross-sectional view of a 3D capacitance structure along the line (I-I') of FIG. 1. Figure 3 is a schematic cross-sectional view of another 3D capacitance structure along the line (l-l') of Figure 1. FIG. 4 is a schematic cross-sectional view of a 3D capacitance structure according to a second embodiment of the present disclosure. FIGS. 5a to 5s are schematic cross-sectional views of a manufacturing process of a 3D capacitance structure according to a third embodiment of the present disclosure. Specific details for implementing the invention

[0009] FIG. 1 is a schematic cross-sectional view of a 3D capacitance structure (10) according to a first embodiment of the present disclosure. Refer to FIG. 1. The 3D capacitance structure (10) of the present embodiment includes a substrate (100), a plurality of sub-capacitance stack structures (SC), a plurality of first electrode contacts (E1), and a plurality of second electrode contacts (E2). The sub-capacitance stack structures (SC) are disposed on the substrate (100), and each sub-capacitance stack structure (SC) includes a dielectric stack (DS), a lower electrode structure (LE), and an upper electrode structure (UE). The dielectric stack (DS) includes a stack of a lower dielectric layer (102), a lower etch stop layer (104), an intermediate dielectric layer (106), an upper etch stop layer (108), and an upper dielectric layer (110). In an embodiment, the lower dielectric layer (102), the intermediate dielectric layer (106), and the upper dielectric layer (110) comprise a silicon oxide film, and the lower etch stop layer (104) and the upper etch stop layer (108) comprise silicon nitride. However, the present disclosure is not limited thereto. The lower electrode structure (LE) comprises a lower electrode plate (112) disposed on the lower dielectric layer (102) and a plurality of lower electrode extensions (114) passing upward from the lower electrode plate (112) through the lower etch stop layer (104) to the intermediate dielectric layer (106). The upper electrode structure (UE) comprises an upper electrode plate (116) disposed on the upper dielectric layer (110) and a plurality of upper electrode extensions (118) passing downward from the upper electrode plate (116) through the upper etch stop layer (108) and the intermediate dielectric layer (106) to the lower etch stop layer (104). In other words, the 3D capacitance structure (10) has three sub-capacitance stack structures (SC). However, the present disclosure is not limited thereto. In other embodiments, the number of stacks of sub-capacitance stack structures (SC) may be higher.

[0010] In FIG. 1, the extending directions of the lower electrode extension (114) and the upper electrode extension (118) are perpendicular to the surface direction of the substrate (100). The surface directions of the lower electrode plate (112) and the upper electrode plate (116) are perpendicular to the extending directions of the first electrode contact (E1) and the second electrode contact (E2).

[0011] Let us continue to refer to FIG. 1. First electrode contacts (E1) each connect the lower electrode plates (112) of two adjacent layers in the sub-capacitance stack structures (SC), and each first electrode contact (E1) directly contacts the lower electrode plate (112) of the adjacent upper layer and the lower electrode plate (112) of the adjacent lower layer. Second electrode contacts (E2) each connect the upper electrode plates (116) of two adjacent layers in the sub-capacitance stack structures (SC), and each second electrode contact (E2) directly contacts the upper electrode plate (116) of the adjacent upper layer and the upper electrode plate (116) of the adjacent lower layer. Since the heights of the first electrode contact (E1) and the second electrode contact (E2) connecting the upper and lower sub-capacitance stack structures (SC) are fixed in approximately one dielectric stack (DS), the stacked 3D capacitance structure (10) can be formed without other connecting structures. Additionally, the upper etch stop layer (108) and the lower etch stop layer (104) in the dielectric stack (DS) are suitable for controlling the thickness of each layer. For example, the size (e.g., height) of the upper electrode extension (118) can be controlled through the lower etch stop layer (104) so ​​that the most suitable stack can be obtained. Additionally, another etch stop layer (120) can be added as a stop layer between the upper and lower sub-capacitance stack structures (SC) during the process of forming the lower electrode plate (112).

[0012] An interconnection structure may be formed on a substrate (100) to connect the circuits of the 3D capacitance structure (10) to external or other elements. For example, the interconnection structure has an insulating layer (122) covering the 3D capacitance structure (10), a first contact window (C1) connected to a lower electrode plate (112), a second contact window (C2) connected to an upper electrode plate (116), a first metal layer (124) placed on the insulating layer (122) and connected to the first contact window (C1), and a second metal layer (126) placed on the insulating layer (122) and connected to the second contact window (C2). However, the present disclosure is not limited thereto. In another embodiment, the interconnection structure may include a plurality of first contact windows (C1) and a plurality of second contact windows (C2), and the arrangement positions may be changed according to requirements.

[0013] FIG. 2 is a schematic cross-sectional view of a 3D capacitor structure (10) along the line (l-l') of FIG. 1. FIG. 1 shows a cross-section in the xz plane and FIG. 2 shows a cross-section in the yz plane. Therefore, FIG. 2 shows only the dielectric stack (DS), upper electrode plate (116), lower electrode plate (112), and lower electrode extension (114) in the sub-capacitance stack structure (SC), and the dotted line is the location of the upper electrode extension (118). Accordingly, the lower electrode extension (114) and the upper electrode extension (118) of the first embodiment may be staggered strip structures along the x direction. Accordingly, the present disclosure is not limited thereto.

[0014] FIG. 3 is a schematic cross-sectional view of another 3D capacitance structure (10) along the line (l-l') of FIG. 1. FIG. 3 also shows a cross-section in the yz plane and indicates that the lower electrode extension (114) and the upper electrode extension (118) are columnar structures staggered along the x and y directions. Since the area between the lower electrode extension (114) and the upper electrode extension (118) in FIG. 3 is larger than that of the structure in FIG. 2, FIG. 3 must have a larger capacitance than FIG. 2 assuming all other structures are identical.

[0015] FIG. 4 is a schematic cross-sectional view of a 3D capacitance structure (40) according to a second embodiment of the present disclosure, wherein the same reference numbers as those in the first embodiment are used to indicate identical or similar parts and elements, and the details regarding identical or similar parts and elements may refer to the details of the first embodiment, which are not described again below.

[0016] Refer to FIG. 4. The 3D capacitance structure (40) of the second embodiment is basically the same as the 3D capacitance structure (10) of the first embodiment. The difference is that the 3D capacitance structure (40) has a total of eight sub-capacitance stack structures (SC). To ensure that the structure of the first contact window (C1) is stable and does not collapse, the eight sub-capacitance stack structures (SC) may be divided into two groups, such that one first contact window (C1) is provided for every four lower electrode plates (112) and the first metal layer (124) is connected by connecting the first contact windows (C1) in series. The original designs may be maintained because the sizes of the second electrode contact (E2) and the second contact window (C2) between the upper electrode plates (116) are smaller (lower). However, the present disclosure is not limited thereto. In other embodiments, the connection design between the upper electrode plates (116) can be changed from the connection design between the lower electrode plates (112).

[0017] FIGS. 5a and 5s are schematic cross-sectional views of a manufacturing process for a 3D capacitance structure according to a third embodiment of the present disclosure. Refer to FIG. 5a. The manufacturing method of the present embodiment may first form a first lower electrode plate (502) on a substrate (500) using a method such as electroplating (step (a)), and then form a first dielectric stack (DS1) on the first lower electrode plate (502) (step (b)). The first dielectric stack (DS1) includes a stack of a lower dielectric layer (LD), an etch stop layer (SL), and an upper dielectric layer (UD). Then, a plurality of extension openings (504) may be formed in the first dielectric stack (DS1) using a photolithography etching process. Because there is an etching selectivity between the etching stop layer (SL), the upper dielectric layer (UD), and the lower dielectric layer (LD) in the first dielectric stack (DS1), the etching process for forming the extension openings (504) uses different etching gases to etch different materials.

[0018] Then, refer to FIG. 5b. To form a plurality of first lower electrode extensions (506) in the first dielectric stack (DS1), the extension openings (504) are filled with a conductive material (M1) using a method such as electroplating (step (c)). The first lower electrode extensions (506) pass upward from the first lower electrode plate (502) through the etching stop layer (SL) to the upper dielectric layer (UD). In the embodiment, the extension direction of the first lower electrode extensions (506) is perpendicular to the surface direction of the substrate (500).

[0019] Next, refer to FIG. 5c. A planarization process may be performed first using a method such as chemical mechanical polishing (CMP), the first lower electrode extension (506) is maintained, and the second dielectric stack (DS2) is then formed (step (d)). The structure of the second dielectric stack (DS2) is identical to that of the first dielectric stack (DS1). However, the thickness and rubbing of each layer of the second dielectric stack (DS2) may be adjusted according to requirements and are not limited to being exactly the same as that of the first dielectric stack (DS1).

[0020] Next, refer to FIG. 5d. A plurality of extension openings (508) can be formed in the second dielectric stack (DS2) using a photolithography etching process until the etch stop layer (SL) of the first dielectric stack (DS1) is exposed as predetermined formation locations of upper electrode extensions.

[0021] Next, refer to FIG. 5e. An upper electrode plate trench (510) can be formed in the upper dielectric layer (UD) of the second dielectric stack (DS2) using a different photolithography etching process. The upper electrode plate trench (510) and the extension opening (508) form a dual damascene opening.

[0022] Refer to FIG. 5f. A plurality of first upper electrode extensions (512) are formed in the second dielectric stack (DS2) (step (e)), and the upper electrode plate (514) is formed in the upper dielectric layer (UD) of the second dielectric stack (DS2) (step (f)). The upper electrode plate trench (510) and the extension opening (508) are filled with a conductive material (M2) using a method such as electroplating. Since this embodiment adopts a dual damascene process, the connected first upper electrode plate (514) and the first upper electrode extensions (512) can be formed simultaneously. However, the present disclosure is not limited thereto. In another embodiment, the first upper electrode extensions (512) may be formed first, and the first upper electrode plate (514) may be formed next. The first upper electrode extension (512) passes through the etch stop layer (SL) of the second dielectric stack (DS2) to extend to the etch stop layer (SL) of the first dielectric stack (DS1). In other words, the size (e.g., height) of the first upper electrode extension (512) can be precisely controlled through the etch stop layer (SL). In an embodiment, the extension direction of the first upper electrode extensions (512) is perpendicular to the surface direction of the substrate (500). In an embodiment, the first lower electrode extensions (506) and the first upper electrode extensions (512) are staggered strip structures along the x direction (similar to the structure of FIG. 2). In another embodiment, the first lower electrode extensions (506) and the first upper electrode extensions (512) are staggered cylindrical structures along the x and y directions (similar to the structure of FIG. 3).

[0023] Next, refer to FIG. 5g. A flattening process, such as a CMP method, may be performed first, and the first upper electrode extension (512) and the first upper electrode plate (514) are maintained, and then the third dielectric stack (DS3) is formed (step (g)). The structure of the third dielectric stack (DS3) is identical to that of the first dielectric stack (DS1). However, the thickness and material of each layer of the third dielectric stack (DS3) may be adjusted according to requirements and are not limited to being exactly the same as that of the first dielectric stack (DS1).

[0024] Next, refer to FIG. 5h. A first contact opening (EO1) passing through the third dielectric stack (DS3), the second dielectric stack (DS2), and the first dielectric stack (DS1) until the first electrode bottom plate (502) is exposed can be formed using photolithography etching (step (h)).

[0025] Next, refer to FIG. 5i. A lower electrode plate trench (516) is formed in the upper dielectric layer (UD) of the third dielectric stack (DS3), and the lower electrode plate trench (516) and the first contact opening (EO1) form a first dual damascene opening (step (i)). Furthermore, in the step of forming the lower electrode plate trench (516) in this embodiment, the etching stop layer (SL) of the third dielectric stack (DS3) may be used as a stop layer.

[0026] Next, refer to FIG. 5j. To simultaneously form the first electrode contact (E1) and the second lower electrode plate (518), a conductive material may be formed in the lower electrode plate trench (516) and the first contact opening (EO1) (first dual damascene opening) using electroplating (step (j)). In the example, the extension direction of the first electrode contact (E1) is perpendicular to the surface direction of the first lower electrode plate (502).

[0027] Next, refer to FIG. 5k. The steps from forming the first dielectric stack (DS1) to forming the second dielectric stack (DS2) are repeated to form the fourth dielectric stack (DS4), a plurality of second lower electrode extensions (520), and the fifth dielectric stack (DS5) (step (k)).

[0028] Next, refer to FIG. 5l. A second contact opening (EO2) is formed through the fifth dielectric stack (DS5), the fourth dielectric stack (DS4), and the third dielectric stack (DS3) until the first upper electrode plate (514) is exposed (step (l)).

[0029] Next, refer to FIG. 5m. A mask layer (522) may first be formed on the fifth dielectric stack (DS5) to fill the second contact opening (EO2), and the mask layer (522) may be, for example, spin-on-carbon (SOC) or photoresist. Then, a plurality of mask openings (524) may be formed in the mask layer (522) using a photolithography process as predetermined formation locations of upper electrode extensions.

[0030] Next, refer to FIG. 5n. The fifth dielectric stack (DS5) exposed from the mask opening (524) is etched to be removed using the mask layer (522) of FIG. 5m until the etch stop layer (SL) of the fourth dielectric stack (DS4) is exposed to form a plurality of extension openings (526) (step (m)). Then, the mask layer (522) of FIG. 5m is removed.

[0031] Next, refer to Figure o. An upper electrode plate trench (528) can be formed in the upper dielectric layer (UD) of the fifth dielectric stack (DS5) using a photolithography process (step (n)). The upper electrode plate trench (528), extension openings (526), ​​and second contact opening (EO2) form a second dual damascene opening.

[0032] Next, refer to FIG. 5p. To simultaneously form a second electrode contact (E2), a plurality of second upper electrode extensions (530), and a second upper electrode plate (532), a conductive material may be formed in the upper electrode plate trench (528), the extension opening (526), ​​and the second contact opening (EO2) (second dual damascene opening) using electroplating (step (o)). In the embodiment, the extension direction of the second electrode contact (E2) is perpendicular to the surface direction of the first upper electrode plate (514).

[0033] Refer again to Fig. q. The steps of Fig. 5g through Fig. 5p are repeated at least once (step (p)) to form a 3D capacitance structure (50). The present disclosure is not limited thereto. The number of repetitions of the aforementioned steps may be increased according to requirements for forming a 3D capacitance structure with a greater number of stacks.

[0034] Next, refer to FIG. 5r. An interconnection structure may be formed on the substrate (500) to connect the circuits of the 3D capacitance structure (50) to external or other elements. For example, a space reserved for a contact window next to the 3D capacitance structure (50) is defined first, and then an insulating layer (534) covering the entire 3D capacitance structure (50) is comprehensively formed.

[0035] Next, refer to FIG. 5s. A first contact window (C1) connected to a first lower electrode plate (502) and a second contact window (C2) connected to a second upper electrode plate (532) are first formed on an insulating layer (534), and a first metal layer (536) connected to the first contact window (C1) and a second metal layer (538) connected to the second contact window (C2) are then formed on the insulating layer (534). However, the present disclosure is not limited thereto. In other embodiments, the interconnection structure may include a plurality of first contact windows (C1) and a plurality of second contact windows (C2), and their arrangement positions may be changed according to requirements.

[0036] In summary, in the present disclosure, by stacking sub-capacitance stack structures and directly connecting the sub-capacitance stack structures to electrode contacts, close and overlapping 3D capacitance structures can be formed, thereby increasing capacitance and making it difficult for the multilayer structure to collapse. Furthermore, an etch stop layer is disposed in the sub-capacitance stack structure, so that the thickness of each layer can be controlled and thereby the most suitable stack is obtained, that is, an optimal upper limit configuration according to the requirements is obtained.

[0037] Although the present disclosure is disclosed in the above embodiments, these embodiments are not intended to limit the present disclosure. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present disclosure. Accordingly, the scope of protection of the present disclosure will be defined by the appended claims.

Claims

Claim 1 A 3D capacitance structure comprises a substrate and a plurality of sub-capacitance stack structures disposed on the substrate, wherein each of the plurality of sub-capacitance stack structures comprises: a dielectric stack comprising a stack of a lower dielectric layer, a lower etch stop layer, an intermediate dielectric layer, an upper etch stop layer, and an upper dielectric layer; a lower electrode structure comprising a lower electrode plate disposed on the lower dielectric layer and a plurality of lower electrode extensions passing upward from the lower electrode plate through the lower etch stop layer to the intermediate dielectric layer; and an upper electrode structure comprising an upper electrode plate disposed on the upper dielectric layer and a plurality of upper electrode extensions passing downward from the upper electrode plate through the upper etch stop layer and the intermediate dielectric layer to the lower etch stop layer. The 3D capacitance structure further comprises a plurality of first electrode contacts connecting the lower electrode plates of two adjacent layers in the sub-capacitance stack structures, and a plurality of second electrode contacts connecting the upper electrode plates of two adjacent layers in the sub-capacitance stack structures. Including, in two adjacent lower electrode extensions and upper electrode extensions, the top end of the lower electrode extension is positioned above the bottom end of the upper electrode extension, each of the plurality of first electrode contacts is connected to two adjacent lower electrode plates, each of the plurality of second electrode contacts is connected to two adjacent upper electrode plates, and the intermediate dielectric layer has an upper layer and a lower layer, the upper layer of the intermediate dielectric layer is in contact with the upper etching stop layer, the lower layer of the intermediate dielectric layer is in contact with the lower etching stop layer, the upper layer of the intermediate dielectric layer is used as a structural boundary for limiting the top stop position of the lower electrode extension, and the lower etching stop layer isA 3D capacitance structure used as a structural boundary to limit the bottom stop position of the upper electrode extension. Claim 2 In claim 1, the extension directions of the lower electrode extensions and the upper electrode extensions are perpendicular to the surface direction of the substrate, 3D capacitance structure. Claim 3 A 3D capacitance structure according to claim 1, wherein the surface directions of the lower electrode plate and the upper electrode plate are perpendicular to the extension directions of the first electrode contacts and the second electrode contacts. Claim 4 In claim 1, the lower electrode extensions and the upper electrode extensions are 3D capacitance structures that are staggered strip structures along the x-direction. Claim 5 A 3D capacitance structure according to claim 1, wherein the lower electrode extensions and the upper electrode extensions are columnar structures staggered along the x and y directions. Claim 6 A 3D capacitance structure according to claim 1, wherein the lower dielectric layer, the intermediate dielectric layer, and the upper dielectric layer comprise a silicon oxide film, and the lower etching stop layer and the upper etching stop layer comprise a silicon nitride film. Claim 7 In claim 1, the lower electrode extensions and the upper electrode extensions are a 3D capacitance structure that is staggered in the x-direction.

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