A carrier comprising a charge trapping layer for a composite substrate

KR1020260139100APending Publication Date: 2026-09-21SOITEC SA
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Patent Information

Application Number
KR1020267020592
Authority / Receiving Office
KR · KR
Patent Type
Applications
Current Assignee / Owner
Priority Date
2024-01-19
Filing Date
2024-11-08
Publication Date
2026-09-21

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Abstract

The present invention relates to a method for manufacturing a carrier (1) for a composite substrate (S), wherein the method comprises the steps of forming a porous surface layer (P) on a first surface (1c) and applying a viscous solution containing a solvent and a filler material precursor to the first surface (1c) of the carrier (1) so that at least a portion of the viscous solution is absorbed into the open pores of the porous surface layer (P). In the fourth step, the carrier (1) is heat-treated to change the viscous solution present in the open pores so that the open pores are filled with the filler material.
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Description

Technology Field

[0001] The present invention relates to a method for manufacturing a carrier having a charge trapping layer, wherein the carrier is intended to accommodate a thin crystalline layer through a layer-transfer technique. A composite substrate formed with such a carrier is applicable to the field of integrated electronic components, particularly radio frequency (RF) components that process signals, the frequency of which may typically be 20 kHz to 300 GHz or higher.

[0002] The thin layer of the composite substrate may be made of a semiconductor material such as silicon, or an insulating material such as a material having piezoelectric and / or ferroelectric properties. In addition to the method of manufacturing the carrier in this way, the present invention also relates to a method of manufacturing a composite substrate having the carrier and having a thin layer transferred thereon. Background Technology

[0003] In the prior art, there are many means of solution aimed at forming a carrier provided with a charge trapping layer (hereinafter more simply "trapping layer"). Such a carrier is intended, for example, to form a base substrate of a silicon-on-insulator type composite substrate. The trapping layer enables limiting electromagnetic coupling occurring between the carrier and an RF component formed on or on a thin layer of the composite substrate.

[0004] The electrical traps in the trapping layer limit the mobility of charge carriers and thus limit interactions with electromagnetic fields generated by high-frequency signals propagating into the bulk of the composite substrate. Thus, while maintaining the quality of useful signals, nonlinear distortion, insertion losses, and possible crosstalk between components are limited.

[0005] Generally, it is desirable to form a trapping layer with a high density of structural defects, such as dislocations, grain boundaries, amorphous regions, interstitial spaces, inclusions, and pores. These structural defects form traps for charges that flow easily through the material, for example, at the locations of incomplete or broken chemical bonds (dangling chemical bonds). Consequently, conduction in the trapping layer is prevented, and as a result, a high resistivity is achieved.

[0006] Literature US2017062284 proposes forming this trapping layer from porous silicon. However, such layers have proven to be chemically and mechanically brittle. They are susceptible to degradation during processing applied to carriers, particularly during the fabrication of composite substrates for transferring thin single-crystal layers.

[0007] These processes can apply mechanical stress to the carrier during thin-layer transfer, for example, by splitting the previously bonded donor substrate. They can also apply chemical stress, for example, during cleaning or wet etching steps of a finishing sequence to finish the composite substrate, which are applied after the thin-layer transfer.

[0008] Literature US2018047614 suggests filling the pores of a porous layer by physical vapor deposition of a filler material or by chemical vapor deposition, for example, using amorphous or polycrystalline silicon. Literature US2022359272 itself suggests forming a mesoporous layer having hollow pores, the inner walls of which are covered mainly with oxide by annealing under an oxidizing atmosphere. The problem to be solved

[0009] One objective of the present invention is to provide an alternative method for forming a charge trapping layer formed from a porous layer, wherein the trapping layer is mechanically and chemically robust. means of solving the problem

[0010] To achieve this objective, the subject of the present invention provides a method for manufacturing a carrier for a composite substrate, the manufacturing method comprising:

[0011] - A first step of porous formation to form a surface porous layer on the first surface (1c) of the carrier;

[0012] - A second step of providing a viscous solution comprising a solvent and a precursor of a filler material;

[0013] - A third step of applying a viscous solution to a first surface of a carrier so that at least a portion of the viscous solution is absorbed into the open pores of the porous surface layer;

[0014] - A fourth step of heat-treating the carrier to modify the viscous solution present within the open pores so that the open pores are filled with the filler material.

[0015] Because at least some of the pores are completely filled with filler material, the trapping layer has good mechanical strength and chemical resistance.

[0016] According to other advantageous and non-limiting features of the present invention, either alone or in any technically feasible combination,

[0017] - The carrier has a resistivity of less than 10 ohm.cm, preferably 1 to 2 ohm.cm;

[0018] - The first step of porosity formation is performed by etching in an acid bath, in particular a bath containing a mixture of nitric acid and hydrofluoric acid;

[0019] - The first step of porosity formation is performed electrochemically or photoelectrochemically;

[0020] - The surface porous layer has a thickness of 100 nm to 20 µm;

[0021] - The third step of application is performed by centrifugation;

[0022] - The filling material is a dielectric and;

[0023] - The filler material is silicon oxide;

[0024] - The precursor of the filler material is a hydrogenated silsesquioxane resin;

[0025] - The method includes a preliminary step of evaporating the solvent prior to the fourth step of heat treatment;

[0026] - The fourth heat treatment step includes exposing the carrier to a temperature between 300°C and 1100°C;

[0027] - A capping layer containing a filling material is also formed on the porous surface layer and in contact with the porous surface layer;

[0028] - In the manufacturing method of the prior claim, the capping layer is removed.

[0029] According to another aspect, the object of the present invention provides a method for manufacturing a composite substrate comprising the steps of providing a carrier manufactured as described above and transferring a thin single crystal layer onto a first surface of the carrier.

[0030] A thin single-crystal layer can be composed of silicon, silicon carbide, or piezoelectric material. Brief explanation of the drawing

[0031] Other features and advantages of the present invention will become apparent from the following detailed description of the invention with reference to the accompanying drawings. FIG. 1 illustrates a carrier according to the present invention. FIG. 2 illustrates a composite substrate utilizing a carrier according to the present invention. FIGS. 3a, 3b, 3c and 3d illustrate a method for manufacturing a carrier according to the present invention. Specific details for implementing the invention

[0032] FIG. 1 illustrates a carrier (1) according to the present invention intended to accommodate a thin crystalline layer via a layer transfer technique to form a composite substrate (S) illustrated in FIG. 2. Very generally, the carrier (1) comprises a trapping layer (1a) formed from a porous layer on a first surface (1c) in which at least some of the pores are completely filled with a filler material. Preferably, most of the pores, for example, more than 50%, more than 60%, or even more than 95%, are filled with a filler material. This material may include or be composed of a dielectric, particularly silicon oxide. Due to its composition, the trapping layer (1a) has a high resistivity, typically a resistivity of more than 10 kohm·cm over its entire thickness, and good mechanical strength and chemical resistance.

[0033] The pores may have any shape, and the porous layer in which at least some of the pores are filled with a filler material may have macroporous properties (pore diameter greater than 50 nm), mesoporous properties (pore diameter between 2 nm and 50 nm), and / or nanoporous properties (pore diameter less than 2 nm). However, preferably, a mesoporous material will be selected. The porosity is typically 40% to 60%, but this does not constitute an essential feature of the invention.

[0034] A person skilled in the art may select the pore properties and porosity according to the properties of the filling material to ensure a good balance between the mechanical properties and electrical properties required for the trapping layer (1a).

[0035] The trapping layer (1a) typically has a thickness of 100 nm to 20 µm, but preferably greater than 1 µm or greater than 10 µm, and the relatively thick trapping layer enables better electromagnetic isolation of the carrier components. The portion (1b) of the carrier (1) itself located under the trapping layer (1a) has a thickness of several hundred microns to ensure the mechanical strength of the assembly.

[0036] As illustrated by the dashed line in the example of FIG. 1, a dielectric layer (2) may be provided on the trapping layer (1a) on the carrier (1) and in contact with the trapping layer, but this dielectric layer (2) is entirely optional. If the dielectric layer (2) is present, it may be composed of or include silicon oxide, silicon nitride and / or silicon oxynitride.

[0037] Typically, in the field of substrates for integrated devices, the carrier (1) may be in the form of a circular wafer, and its diameter may be 100, 150, 200, 300, or even 450 mm.

[0038] Preferably, the starting carrier on which the trapping layer (1a) is formed is made of single-crystal silicon. Advantageously, as disclosed in the remainder of this description, it has a relatively low resistivity of less than 10 ohm·cm, preferably about 1 to 2 ohm·cm, but does not exclude the possibility that this substrate may have a different resistivity. It may be p-type or n-type.

[0039] Referring to FIGS. 3a through 3d, which illustrate a method for manufacturing a carrier according to the present invention to form a trapping layer (1a), a first porous step is applied to a starting carrier for the purpose of forming a porous surface layer (P) on at least one of the faces (1c) (indicated as "first face" in the remainder of this description).

[0040] This step can be performed in a number of ways. According to the first approach, the first step of porosity is performed by etching in an acid bath, specifically a bath containing a mixture of nitric acid and hydrofluoric acid. For a description of the physical phenomenon that induces the formation of a porous surface layer by this chemical treatment, refer to the literature [Starostina et al., "Porous-Silicon formation in HF-HNO3-H2O Etchants", Russian Microelectronics 31, 88-96(2002)].

[0041] This approach tends to form a porous surface layer (P) with a relatively thin thickness of about 1 μm or less. The formation of the porous layer is favored by the relatively low resistivity of the carrier (1), which may allow the carrier (1) to be selected to have a low resistivity of about 10 ohm·cm or less. It can be assumed that the carrier (1) is treated to have a thickness of low resistivity at the surface, and the remainder of the carrier (1b) can then have a resistivity of more freely selected. This may involve introducing a dopant into this surface thickness or forming a doped surface layer by deposition.

[0042] According to another approach, the first step of porosity is performed electrochemically or photoelectrochemically using the anodic dissolution phenomenon in an acidic medium by electrolysis. In practice, a carrier (1) is placed in an electrochemical cell, and a first side (1c) of the carrier is exposed to an electrolyte solution based on hydrofluoric acid (HF).

[0043] This solution may have an HF concentration of more than 30% and may contain additives (e.g., isopropyl alcohol (IPA) or ethanol). The carrier (1) is in contact with the anode, for example, the opposite side of the first surface (1c), and the cathode is positioned toward the first surface (1c) so that current can flow through the electrolyte and the carrier (1).

[0044] Current density flowing within the battery (typically 1 to 50 mA / cm²) 2 ) induces the formation of a porous surface layer on the first surface (1c) of the carrier (1), that is, the surface exposed to the electrolyte. This approach makes it possible to form a relatively thick porous layer (P) of about 10 μm or even about 20 μm by extending the duration of this stage.

[0045] It should be noted that other electrochemical cell configurations capable of forming a porous surface layer (P) also exist. In particular, a "dual cell" configuration is known in which two opposite faces of the starting carriers come into contact with the same electrolyte solution or different solutions (see, for example, US11049724). In this case, one of the faces may be illuminated so that this face generates charge carriers during the electrochemical phase.

[0046] Regardless of how the first step is performed, when the porous step is performed, a porous surface layer (P) is obtained on the first surface (1c) of the carrier (1) as a result of this step. The pores constituting this porous surface layer (P) may be open to some of them and may appear on the first surface (1c) of the carrier (directly or indirectly).

[0047] As mentioned in the preceding part of this specification, it is possible to control the parameters of this step to obtain a given porosity and a given property of the pores (in particular, their average dimensions). The porosity time defines the thickness of the surface porous layer (P) intended to form a trapping layer, all other conditions being equal. Preferably, this thickness will be selected to be between 100 nm and 20 µm, as already specified.

[0048] In the second step of manufacturing the carrier (1), a viscous solution comprising a solvent and a precursor of a filler material is prepared. Since this solution is intended to fill the pores of the porous layer (P), it must have low viscosity to allow it to penetrate and flow into the pores of the layer (P), and in particular, the viscosity of the solution can be controlled by adjusting the ratio of the solvent in the solution.

[0049] In addition to the solvent, the solution contains a precursor of the filler material. "Precursor of the filler material" refers to any material that causes the filler material to be obtained or formed, either directly or after processing, once the solvent is removed from the viscous solution.

[0050] In a preferred embodiment, the filler material is silicon dioxide, and its precursor is hydrogenated silsesquioxane. After heat treatment that induces the removal of at least some of the hydrogen contained therein, the hydrogenated silsesquioxane forms a silicon-rich oxide SiO with the chemical formula [HSiO3 / 2] that is chemically resistant to etching agents such as tetramethylammonium hydroxide (TMAH or TMAOH). n It is an inorganic compound. It can combine with organic solvents, for example, methyl isobutyl ketone (often referred to as MIBK), to form a viscous solution.

[0051] However, the present invention is by no means limited to silicon oxide filler materials and their precursors. By using silicon and nitrogen-based precursors, for example, compounds of the silazane, disilazane, or polysilazane type, filler materials based on silicon nitride, silicon oxynitride, or alloys comprising silicon and carbon may be conceivable.

[0052] The use of these filler material precursor polymers is documented, for example, in US4312970A or US4756977A.

[0053] In the third step of the method for manufacturing a carrier substrate (1), a viscous solution is applied to a first surface (1c) of the carrier (1) to absorb at least a portion of the viscous solution within the open pores of the porous surface layer (P). This application step is intended to uniformly coat the first surface (1c) of the carrier to advantageously enable filling the open pores over the entire area of ​​the first surface (1c). This step, illustrated in FIG. 3b, may be performed particularly by spin coating, dip coating, spray coating, or flow coating.

[0054] The low viscosity of the solution allows it to penetrate into the pores of the surface porous layer (P) and fill the pores. It should be noted that the pores of this layer that are not in direct or indirect communication with the first surface (1c) of the carrier cannot accommodate the viscous solution by flow. However, this does not pose any obvious problem unless these blocked pores are the dominant pores in the surface porous layer.

[0055] When an excess amount of viscous solution is supplied, it tends to come into contact with the porous surface layer (P) to form a capping layer (4). This capping layer may have a thickness of several micrometers and, especially when applied by centrifugation, may be very uniform due to the viscous nature of the solution.

[0056] Optionally, at this stage of the method, a solvent evaporation step may be provided. This evaporation step may be achieved by simply drying the carrier or by raising its temperature in an oven to an intermediate temperature, for example, between 50°C and 300°C.

[0057] Regardless of whether such an evaporation step is applied, a method for manufacturing a carrier (1) according to the present invention provides a fourth step of heat treatment after a third step of applying a viscous solution. This step, illustrated in FIG. 3c, is intended to modify the viscous solution present in the open pores of the porous layer to fill it with a filler material.

[0058] In cases where a preliminary solvent evaporation step is not applied, the solvent is removed from the solution during this heat treatment. This also results in the removal of volatile species present in the precursor of the filler material, and as a result of this heat treatment, the pores are effectively filled with this material.

[0059] For example, if the precursor of the viscous solution is hydrogenated silsesquioxane, heat treatment causes at least some of the hydrogen to be removed from the precursor to fill the pores with silicon-rich, hydrogen-depleted oxides (in this case, forming volatile species).

[0060] This heat treatment is, of course, suitable for the properties of the viscous solution, and more specifically, for the properties of the precursor present in the solution. In the case where the latter is hydrogenated silsesquioxane, the annealing can be from 300°C to 1100°C.

[0061] If a capping layer (4) is present on the carrier, the heat treatment step also causes the viscous material constituting the capping layer to deform. If the capping layer is undesirable for the use of the carrier, this layer may be removed, for example, by a polishing step. Alternatively, if the filler material actually has dielectric properties, the capping layer may be retained and help to form the dielectric layer (3) of the carrier (1).

[0062] Regardless of whether this capping layer (4) is maintained, the manufacturing method according to the present invention may also include the step of forming a dielectric layer (2) on a carrier by a conventional deposition process.

[0063] FIG. 3d illustrates a carrier substrate (1) obtained as a result of this process (without forming a dielectric layer (2) in the illustrated example). The initially formed porous surface layer (P) was transformed into a trapping layer (1a) formed of pores filled with silicon and a filler material.

[0064] As previously mentioned, the carrier substrate (1) is intended to accommodate a thin layer (3) by transfer and thus form a composite substrate (S) illustrated as an example in FIG. 2. The thin layer (3) is essentially generally crystalline and advantageously single-crystalline. The carrier (1) has suitable properties (particularly in terms of surface roughness and deformation) or has been pre-treated (e.g., by polishing) to accommodate such a thin layer (3).

[0065] The composite substrate (S) includes a dielectric layer (2) that is in contact with and inserted between the carrier (1) and the thin layer (3). The thickness of this dielectric layer is selected according to the characteristics of the components to be formed inside and on the surface of the thin layer (3), that is, according to the use of the composite substrate (S). This thickness may be, for example, between 10 nm and 10 μm.

[0066] As is well known in itself, the transfer of a thin layer (3) onto a carrier (1) is usually achieved by bonding a free face of a donor substrate to a first face (1c) of the carrier (1) preferably by molecular bonding. A surface dielectric layer is provided on at least one of these faces, and these layers are formed by bonding a dielectric layer (2) of a composite substrate (S).

[0067] The properties of the donor substrate are selected according to the desired properties of the thin layer (3). Accordingly, the donor substrate may be a substrate formed of a single-crystal semiconductor, for example, silicon, or a substrate formed of a single-crystal piezoelectric material or comprising a surface layer of such a single-crystal piezoelectric material. In this case, it may be lithium tantalate or lithium niobate.

[0068] It is also possible for the donor substrate to have completed or partially completed components, and the transfer aims to place these components on the carrier (1) to utilize radio frequency characteristics.

[0069] Similar to the carrier (1), the donor substrate can take the form of a circular wafer, and its dimensions can correspond to the dimensions of the carrier.

[0070] After this bonding step, the thickness of the donor substrate is reduced to form a thin layer (4). This reduction step can be performed by mechanical or chemical thinning, particularly when the donor substrate contains components that are to be placed on the carrier (1).

[0071] A reduction in the thickness of the donor substrate can preferably be achieved by dividing a weakened plane previously introduced into the donor substrate by, for example, by the injection of a light species such as hydrogen and / or helium. This weakened plane defines a thin layer (3) together with the free surface of the donor substrate.

[0072] After such thinning, or preferably after the splitting step, steps to finish the thin layer (3), such as a polishing step, heat treatment under reduction or an inert atmosphere, sacrificial oxidation, etc., may be applied.

[0073] As a result of these steps, a composite substrate (S) formed of a thin single-crystal layer transferred onto a carrier (1) is obtained.

[0074] Of course, the present invention is not limited to the described embodiments, and variations of the embodiments may be applied without departing from the scope of the invention as defined by the claims.

Claims

Claim 1 A method for manufacturing a carrier (1) for a composite substrate (S), comprising: a first step of porousing to form a porous surface layer (P) on a first surface (1c) of the carrier (1); a second step of providing a viscous solution comprising a solvent and a precursor of a filler material; a third step of applying the viscous solution on the first surface (1c) of the carrier (1) so as to absorb at least a portion of the viscous solution into the open pores of the porous surface layer (P); and a fourth step of heat-treating the carrier (1) to modify the viscous solution present in the open pores so that the open pores are filled with the filler material. Claim 2 A method of manufacturing, wherein the carrier (1) has a resistivity of less than 10 ohm.cm, preferably 1 to 2 ohm.cm. Claim 3 A manufacturing method according to claim 1 or 2, wherein the first step of porosity is performed by etching in an acid bath, particularly a bath containing a mixture of nitric acid and hydrofluoric acid. Claim 4 A manufacturing method according to any one of claims 1 to 3, wherein the first step of porous formation is performed electrochemically or photoelectrochemically. Claim 5 A method of manufacturing, wherein, in any one of claims 1 to 4, the porous surface layer (P) has a thickness of 100 nm to 20 μm. Claim 6 A manufacturing method according to any one of claims 1 to 5, wherein the third step of applying is performed by centrifugation. Claim 7 A manufacturing method according to any one of claims 1 to 6, wherein the filling material is a dielectric. Claim 8 A method of manufacturing, wherein, in any one of claims 1 to 7, the filling material is silicon oxide. Claim 9 A method of manufacturing, wherein in any one of claims 1 to 8, the precursor of the filler material is a hydrogenated silsesquioxane resin. Claim 10 A manufacturing method according to any one of claims 1 to 9, comprising a preliminary step of evaporating the solvent prior to the fourth step of heat treatment. Claim 11 A manufacturing method according to any one of claims 1 to 10, wherein the fourth step of heat treatment comprises the step of exposing the carrier (1) to a temperature between 300°C and 1100°C. Claim 12 A manufacturing method according to any one of claims 1 to 11, wherein a capping layer (4) containing the filling material is also formed on the porous surface layer (P) and in contact with the porous surface layer. Claim 13 A manufacturing method in which the capping layer (4) is removed in paragraph 12. Claim 14 A method for manufacturing a composite substrate (S), comprising the steps of providing a carrier (1) prepared according to any one of claims 1 to 13 and transferring a thin single crystal layer (4) onto the first surface of the carrier. Claim 15 In claim 14, a method for manufacturing a composite substrate (S), wherein the thin single crystal layer (4) is composed of silicon, silicon carbide, or a piezoelectric material.