Stacked integrated circuit devices including logic dies and memory stacks

Abstract

A stacked IC device comprises a first memory stack comprising two or more memory dies coupled to a substrate and a second memory stack comprising two or more memory dies coupled to a substrate. The stacked IC device also comprises a logic die electrically connected to the memory dies of the first memory stack via face-to-face connections to the top die of the first memory stack and electrically connected to the memory dies of the second memory stack via face-to-face connections to the top die of the second memory stack. The stacked IC device further comprises a patch component disposed in an area between the first memory stack and the second memory stack. The patch component comprises conductors that electrically connect the logic die to the substrate.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims the benefit of priority from the jointly owned U.S. Regular Patent Application No. 18 / 428,106, filed January 31, 2024, the contents of which are incorporated herein by reference in their entirety.

[0003] Technology field

[0004] Various features relate to stacked integrated circuit devices including logic dies and memory stacks. Background Technology

[0005] Electrical connections exist at each level of the system hierarchy of an integrated circuit (IC) device. This system hierarchy encompasses interconnections ranging from the lowest system-level active devices to the highest system-level interconnections. For example, interconnection layers can connect different devices on an integrated circuit. As integrated circuits become more complex, more interconnection layers are used to provide electrical connections between devices. Recently, the number of interconnection levels for circuits has increased significantly due to the large number of devices interconnected in modern electronic devices. The increased number of interconnection levels to support this increased number of devices entails more complex manufacturing processes.

[0006] During the design of modern integrated circuit devices, conflicts often exist between various design goals. For example, in some applications, limiting IC package size is desirable, as is improving heat dissipation. However, generally speaking, as IC packages become smaller, the surface area available for heat removal decreases. Consequently, reducing IC package size tends to reduce heat dissipation. Since higher-performance processors tend to generate more heat, similar conflicts can arise between heat dissipation and processing performance. Furthermore, the goal of cost reduction can conflict with almost any other improvement objective. Therefore, providing high-performance IC devices capable of meeting diverse design goals is a challenging task. These challenges are particularly critical for mobile applications, where power constraints, device size, processing performance, heat dissipation, cost, and many other factors interact simultaneously.

[0007] Various features relate to IC devices.

[0008] One example provides a stacked IC device comprising a first memory stack comprising two or more memory dies coupled to a substrate and a second memory stack comprising two or more memory dies coupled to a substrate. The stacked IC device also includes a logic die electrically connected to the memory dies of the first memory stack via face-to-face connections to the top die of the first memory stack and electrically connected to the memory dies of the second memory stack via face-to-face connections to the top die of the second memory stack. The stacked IC device further includes a patch component disposed in an area between the first memory stack and the second memory stack. The patch component includes conductors that electrically connect the logic die to the substrate.

[0009] Another example provides a stacked IC device comprising a first memory stack comprising two or more memory dies coupled to a substrate and a second memory stack comprising two or more memory dies coupled to a substrate. The stacked IC device further comprises a first logic die electrically connected to the memory dies of the first memory stack via face-to-face connections to the top die of the first memory stack and a second logic die electrically connected to the memory dies of the second memory stack via face-to-face connections to the top die of the second memory stack. The stacked IC device further comprises a patch component disposed in an area between the first memory stack and the second memory stack. The patch component comprises first conductors electrically connecting the first logic die to the substrate and second conductors electrically connecting the second logic die to the substrate.

[0010] Another example provides a method for manufacturing a stacked IC device, comprising the step of bonding a plurality of memory stacks to a substrate, wherein each memory stack comprises two or more memory dies. The method also comprises the step of electrically connecting a patch component to the substrate in an area between two or more of the plurality of memory stacks. The method further comprises the step of electrically connecting a logic die to the substrate through the patch component and electrically connecting face-to-face to the top dies of the two or more memory stacks. Brief explanation of the drawing

[0011] Various features, attributes, and advantages may become apparent from the detailed description below when considered together with the drawings, and identical reference numerals in the drawings are identified correspondingly throughout. FIG. 1a illustrates a schematic plan view of an example of an exemplary stacked IC device. FIG. 1b illustrates a schematic front view of an example of an exemplary stacked IC device of FIG. 1a. FIG. 1c illustrates a schematic perspective view of an example of an exemplary stacked IC device of FIG. 1a. FIG. 2 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIG. 3 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIG. 4 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIG. 5 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIG. 6 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIG. 7 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIG. 8 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIG. 9 illustrates a schematic cross-sectional view of another example of the exemplary stacked IC device of FIG. 1a. FIGS. 10a and FIGS. 10b together illustrate an exemplary sequence for manufacturing an example of a patch component. FIGS. 11a and FIGS. 11b together illustrate an exemplary sequence for manufacturing another example of a patch component. FIGS. 12a and FIGS. 12b together illustrate an exemplary sequence for manufacturing another example of a patch component. FIGS. 13a and FIGS. 13b together illustrate an exemplary sequence for manufacturing another example of a patch component. FIGS. 14a and FIGS. 14b together illustrate an exemplary sequence for manufacturing an example of a stacked IC device. FIGS. 15a and FIGS. 15b together illustrate an exemplary sequence for manufacturing an example of a stacked IC device. FIG. 16 illustrates an exemplary sequence for manufacturing another example of a stacked IC device. FIG. 17 illustrates various electronic devices capable of incorporating the die, stacked IC device, electronic circuit, integrated device, package, and / or device package described in this specification. Specific details for implementing the invention

[0012] Specific aspects of the present disclosure describe stacked integrated circuit (IC) devices comprising one or more logic dies and a plurality of memory stacks. The logic die(s) may comprise a single logic die or a plurality of logic dies configured to operate independently or in cooperation with each other. For example, the logic die(s) may comprise chiplets configured to interact with each other to perform various operations. In the disclosed examples, the logic die(s) are electrically connected face-to-face with the top die of each of two or more memory stacks and are electrically connected to a substrate by conductors extending through a region between two of the memory stacks.

[0013] Face-to-face electrical connections between the logic die(s) and the top dies of memory stacks provide short interconnection paths, which improves the data transfer speed of memory access compared to configurations where logic and memory dies are interconnected by less direct routes, such as side-by-side configurations and package-on-package configurations. One problem associated with face-to-face coupling of logic and memory dies is how to route other connections of the logic dies (e.g., power connections and other input / output (I / O) connections). Examples disclosed herein solve this problem by routing many (or all) of these other connections of the logic die(s) through a patch component placed in an area between at least two memory stacks. The patch component includes a body and conductors extending through the body to electrically connect the logic die(s) to a substrate.

[0014] In the context of the present disclosure, the “face” of the die refers to the surface of the die adjacent to the active region of the die. For example, the active region may include various layers and structures defining circuit elements such as transistors, conductors, passive circuit elements (e.g., resistors, inductors, capacitors, etc.), and power transfer networks. In this example, the face of the die corresponds to the side of the die that delineates the active region. In contrast, the “back” of the die refers to the opposite side of the die that delineates the inactive region of the die. For example, the inactive region typically includes an undoped single-crystal semiconductor material, other inactive layers (e.g., passivation layers), or both.

[0015] As used herein, the term “stacked” (as in “stacked dies” and / or “stacked ICs”) refers to arrangements in which one die or device (e.g., a first die) is placed on top of another die or device (e.g., a second die) (including directly or partially on top). “Memory stacked” refers to two or more memory dies (and possibly other dies, such as memory controllers) arranged in a stacked configuration. As used herein, “face-to-face” refers to a stacked die arrangement in which a first die and a second die are stacked such that the normal of the face of the first die is antiparallel to the normal of the face of the second die. In other words, the face of the first die faces the face of the second die, and the back faces of the first and second dies are oriented away from each other.

[0016] Electrically connecting the top die of a memory stack to the logic die in a face-to-face configuration enables the use of short, high-density (e.g., small pitch) interconnects between the memory stack and the logic die. Shorter interconnects generally result in lower resistive losses, leading to improved power efficiency and reduced heat generation. Additionally, shorter interconnects enable faster signal exchange than longer interconnects.

[0017] In some implementations, the patch component includes other features in addition to conductors. For example, the patch component may include traces to form conductive paths between the logic die(s) and other components (e.g., one or more other logic dies). As another example, the patch component may include passive circuit elements such as capacitors, inductors, and / or resistors. The patch component may include a single body through which conductors extend, or the patch component may include a plurality of stacked and interconnected bodies that together define the conductors.

[0018] Compared to conventional approaches, such as parallel configurations or package-on-package configurations, the face-to-face arrangement of logic die(s) and memory stacks disclosed herein enables low-cost manufacturing of IC devices having a small form factor, high-density logic-memory interconnects, high-speed logic-memory communication, improved thermal management, improved power distribution network performance, as well as other advantages. For example, since the thickness of the logic die(s) used in the disclosed embodiments does not result in longer conductive paths, the logic die(s) may have thick inactive regions to facilitate heat transfer, and as a result, thermal management is improved. As another example, face-to-face electrical connections can reduce reliance on horizontal connections and / or redistribution layers, which can reduce manufacturing costs and decrease losses due to shortened end-to-end conductive path lengths.

[0019] In the following description, specific details are provided to provide a sufficient understanding of the various embodiments of the present disclosure. However, it will be understood by those skilled in the art that the embodiments may be practiced without these specific details. For example, circuits may be illustrated in block diagrams to avoid obscuring the embodiments by providing unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be illustrated in detail so as not to obscure the embodiments of the present disclosure.

[0020] Specific aspects of the present disclosure are described below with reference to the drawings. In the description, common features are designated by common reference numbers. As used herein, various terms are used solely for the purpose of describing specific implementations and are not intended to limit implementations. For example, the singular forms “a,” “an,” and “the” are intended to include plural forms as well, unless the context otherwise clearly indicates. Additionally, some features described herein are singular in some implementations and plural in others. For ease of reference in the present specification, such features are generally introduced as “one or more” features, and are referred to in the singular or optional plural (as indicated by “s”) unless aspects related to multiple features are subsequently described.

[0021] In some drawings, multiple instances of a specific type of feature are used. These features are physically and / or logically separate, but the same reference number is used for each, and different cases are distinguished by adding a letter to the reference number. When features are referred to in this specification as a group or a type (e.g., when no specific one of the features is referred to), the reference number is used without a distinguishing letter. However, when a specific feature of one of a number of features of the same type is referred to in this specification, the reference number is used with a distinguishing letter. For example, referring to FIG. 1a, a number of memory stacks are illustrated and associated with reference numbers 104A and 104B. When referring to a specific memory stack among these memory stacks, such as memory stack (104A), the distinguishing letter "A" is used. However, when referring to any conductive pad among these memory stacks or when referring to these memory stacks as a group, the reference number 104 is used without a distinguishing letter.

[0022] As used herein, the terms “comprise,” “comprises,” and “comprising” may be used interchangeably with “include,” “includes,” or “including.” As used herein, “exemplary” indicates an example, implementation, and / or mode, and should not be interpreted as limiting or indicating a preference or preferred implementation. As used herein, ordinal terms used to modify elements such as structures, components, behaviors, etc. (e.g., “first,” “second,” “third,” etc.) do not themselves indicate any priority or order of the element relative to other elements, but rather merely distinguish the element from other elements having the same name (except for the use of ordinal terms). As used in this specification, the term “set” refers to one or more of a specific element, and the term “plural” refers to a multiple of a specific element (e.g., two or more).

[0023] Advancements in manufacturing technology and the demand for lower-cost and more capable electronic devices have resulted in increased complexity of ICs. Often, more complex ICs feature more complex interconnection schemes to enable interaction between the ICs in a device. The number of interconnection levels in circuitry has increased significantly in current state-of-the-art applications, such as ICs for mobile application devices, due to the large number of interconnected devices.

[0024] These interconnects include back-end-of-line (BEOL) interconnect layers, which may refer to conductive interconnect layers for electrically coupling to front-end-of-line (FEOL) active devices of the IC. Various BEOL interconnect layers are formed at corresponding BEOL interconnect levels, and lower BEOL interconnect levels generally use thinner metal layers compared to upper BEOL interconnect levels. The BEOL interconnect layers can be electrically coupled to middle-of-line (MOL) interconnect layers, which are interconnected to the FEOL active devices of the IC.

[0025] State-of-the-art applications often require IC devices with small form factors, low costs, tight power budgets, and high electrical performance. IC package designs have evolved to meet these conflicting goals for specific applications, such as multimedia-enabled mobile devices. For example, fan-out (FO) wafer-level packaging (WLP) or FO-WLP process technology is an advanced form of packaging technology useful for mobile applications. These chip-first FO-WLP process technology solutions provide flexibility for fan-in and fan-out connections from the die to the package balls. Additionally, these solutions also provide a reduction in the height of first-level interconnections between the IC package die and the package balls. However, these IC packages are susceptible to power and signal routing issues when multiple dies are arranged within a small form factor.

[0026] Stacked die techniques and chiplet architectures are becoming more common as significant power performance area (PPA) yield improvements are demonstrated in stacked die and chiplet architecture production lines. Forming IC devices using stacked dies, chiplets, or both can offer various advantages compared to providing identical functional circuits on a single monolithic chip. For example, each chiplet is smaller than a single monolithic die containing all identical functional circuit blocks. Since yield losses and the costs associated with lost yield in IC manufacturing tend to increase with increasing die size, using smaller dies can reduce yield losses in the IC manufacturing process (i.e., increase yield). Another advantage is that chiplets can be manufactured at different locations and / or by different manufacturers, and in some cases, using different manufacturing technologies (e.g., different manufacturing technology nodes). For example, one die of a chiplet-based integrated device may include components having a first minimum size (e.g., interconnects, transistors, etc.), and another die of a chiplet-based integrated device may include components having a second minimum size (e.g., interconnects, transistors, etc.), and the second minimum size is larger than the first minimum size.

[0027] In contrast, all circuits of a monolithic die are manufactured using the same manufacturing technologies and equipment. Consequently, when manufacturing a monolithic die, the entire die may be subject to the strictest manufacturing constraints of the most complex components. However, when using chiplets, different chiplets can be manufactured using different manufacturing technologies (e.g., different manufacturing technology nodes), and only the chiplets containing the most complex components or chiplets themselves are subject to the strictest manufacturing constraints. In this arrangement, chiplets manufactured using less expensive / more expensive or higher-yield manufacturing technologies can be integrated with chiplets manufactured using more expensive / more expensive or lower-yield manufacturing technologies to form an IC (e.g., a stacked IC device), resulting in overall savings. Furthermore, in some cases, the design of the chiplets may change as technology improves. New chiplet designs can be used alongside older chiplet designs to form IC devices, which improves manufacturing flexibility and reduces design costs.

[0028] As used herein, the term “layer” includes a film and should not be interpreted as indicating a vertical or horizontal thickness unless otherwise noted. As used herein, the term “chiplet” may refer to an integrated circuit block, a functional circuit block, or other similar circuit blocks specifically designed to operate with one or more other chiplets to form a larger and more complex chiplet architecture. As used herein, the term “die” may include a chiplet or a monolithic IC. For example, a logic die may be configured to operate independently of other logic dies (e.g., as a monolithic IC). Alternatively, a logic die may include a first set of functional logic blocks configured to operate with the functional logic blocks of one or more other logic dies (e.g., in a chiplet architecture).

[0029] A three-dimensional (3D) integrated circuit (3D IC) comprises a set of stacked and interconnected dies. Generally, a 3D IC architecture can achieve higher performance, increased functionality, lower power consumption, and / or a smaller footprint compared to the same circuitry provided by a monolithic die or a two-dimensional (2D) IC structure.

[0030] Exemplary stacked IC device

[0031] FIGS. 1a, FIGS. 1b, and FIGS. 1c illustrate a schematic plan view, front view, and perspective view, respectively, of an exemplary stacked IC device (100). The stacked IC device (100) comprises a memory stack (104A), a memory stack (104B), a logic die (110), a patch component (130), and a substrate (102). As described in more detail below, the logic die (110) is electrically connected face-to-face to the top die of each of the memory stacks (104) and is electrically connected to the substrate (102) by conductors (106) extending through the patch component (130) (illustrated by dashed lines to indicate that the conductors (106) are not visible in the illustrated front view).

[0032] The logic die (110) includes an active circuit section (e.g., a plurality of interconnected transistors) arranged to form various functional blocks. Examples of functional blocks that may be included in the logic die (110) may include, but are not limited to, arithmetic blocks, logic blocks, flow control blocks, and combinations thereof. In some embodiments, the logic die (110) also includes interconnected transistors to form local memory units, such as registers or caches, for temporarily storing data during operations.

[0033] The active circuit portion of the logic die (110) is formed in an active region bounded by the face (112) of the logic die (110) shown in FIG. 1b. The face (112) of the logic die (110) is opposite to the back face (114) of the logic die (110). For example, in FIG. 1b, the logic die (110) is illustrated in a face-down orientation in which the face (112) faces the substrate (102) and the back face (114) is oriented away from the substrate (102).

[0034] Each memory stack (104) includes a plurality of memory dies. In some embodiments, each of the memory stacks (104) also includes a memory controller associated with the memory dies of the memory stack (104). The memory dies include active circuits (e.g., a plurality of interconnected transistors) arranged to form blocks of memory cells. For example, the memory dies may include dynamic random access memory (DRAM) dies (e.g., double data transfer rate (DDR) memory dies), high bandwidth memory (HBM) dies, etc. In this context, "high bandwidth memory" includes arrangements of dies and similar arrangements that conform to the high bandwidth memory (HBM) DRAM standard published by the JEDEC Solid State Technology Association. The memory dies may also include other circuits such as read / write circuits, address decoders, etc.

[0035] The top die of each memory stack (104) includes an active circuit formed in an active region bounded by the face (116) of the top die. In some examples, the bottom of each memory stack (104) is bounded by the back face (118) of the bottom die of the memory stack (104). In these examples, each die of the memory stack (104) is oriented in a face-up orientation. In this context, "face-up" means that the face of the die is oriented away from the substrate (102) and the back face of the die is oriented toward the substrate (102). In some examples, the dies of the memory stack (104) include through-silicon vias (TSVs) to provide electrical connections between the top die of the memory stack (104), the bottom die of the memory stack (104), and the dies between the top die and the bottom die of the memory stack (104).

[0036] A logic die (110) is stacked on memory stacks (104) and electrically connected face-to-face to the top die of each memory stack (104). For example, in FIGS. 1a through 1c, interconnects (108A) electrically connect the logic die (110) to the top die of the memory stack (104A), and interconnects (108B) electrically connect the logic die (110) to the top die of the memory stack (104B). The interconnects (108) may include conductive pillars (e.g., copper (Cu) pillars), solder bumps, pillar bumps (e.g., pillars including attached solder caps), or other types of die-to-die electrical interconnects.

[0037] The substrate (102) comprises a plurality of metal layers separated by dielectric layers. In this example, the metal layers are patterned to define metal lines and are optionally interconnected by conductive vias to define conductive paths between on-package contacts on the top (120) of the substrate (102) and off-package contacts (124) on the bottom (122) of the substrate (102). In certain examples, the substrate (102) comprises redistribution layers built on other components of the stacked IC device (100). In other examples, the substrate (102) comprises an array of pre-formed layers attached to other components of the stacked IC device (100).

[0038] The patch component (130) comprises a body in which conductors (106) are embedded. The body of the patch component (130) may comprise a semiconductor (e.g., silicon) material or a polymer or a polymer-based material (e.g., a mold compound, one or more prepreg layers, or other composite materials containing a filler within a polymer matrix). In these embodiments, the patch component (130) may be bonded to a substrate (102) such that the upper surface of the patch component (130) is substantially coplanar with the face (116) of the top dies of the memory stacks (104). In some embodiments, the patch component (130) may include other circuits in addition to the conductors (106), such as active circuits (e.g., transistors) and passive circuits (e.g., conductive traces, capacitors, inductors, resistors, etc.).

[0039] The height of the conductors (106) is related to the distance between the face (112) of the logic die (110) and the top (120) of the substrate (102). Since the logic die (110) is coupled face-to-face with each top die of the memory stacks (104), the distance between the face (112) of the logic die (110) and the top (120) of the substrate (102) is related to the height of the memory stacks (104). In some embodiments, the patch component (130) may include a stacking arrangement to provide sufficient height to the patch component (130) to interconnect the logic die (110) and the substrate (102).

[0040] In some embodiments, the stacked IC device (100) includes one or more redistribution layers (RDLs). For example, the RDL(s) may be coupled to a logic die (110), in which case interconnects (108), conductors (106), or both are electrically connected to the circuit portion of the logic die (110) through the RDL(s).

[0041] Although the stacked IC device (100) is illustrated in FIGS. 1a through 1c as comprising a single logic die (110) and two memory stacks (104), the stacked IC device (100) may comprise more than one logic die (110), two or more memory stacks (104), or both. In an exemplary embodiment in which the stacked IC device (100) comprises two or more logic dies (110), the logic dies (110) may be electrically connected to each other through conductive paths through a substrate (102), conductive paths through a patch component (130), an interposer or RDL between the logic dies (110) and the patch component (130), or a combination thereof. In some embodiments in which the stacked IC device (100) comprises two or more memory stacks (104), a single logic die (110) may be electrically connected to all memory stacks (104).

[0042] In some embodiments, the stacked IC device (100) may include devices, dies, or components in addition to those illustrated in FIGS. 1a through 1c. For example, the stacked IC device (100) may correspond to or be included in an integrated device comprising communication circuits (e.g., one or more wireless transceivers, one or more modems, etc.), sensors (e.g., global positioning system sensors, inertial sensors, image sensors, etc.), special purpose or general purpose processors (e.g., central processing units (CPUs), graphics processing units (GPUs), artificial intelligence processing units, various auxiliary processors and accelerators, etc.).

[0043] FIGS. 2 through 7 illustrate schematic cross-sectional views of exemplary stacked IC devices. The stacked IC devices of FIGS. 2 through 7 are examples of the stacked IC devices (100) of FIGS. 1a through 1c, each comprising a single logic die (110). For example, the stacked IC devices of FIGS. 2 through 7 each include a memory stack (104A), a memory stack (104B), a logic die (110), a patch component (130), and a substrate (102) as described with reference to FIGS. 1a through 1c. Unless otherwise specifically indicated, each of the stacked IC devices of FIGS. 2 through 7 may include any of the features, functions, and / or alternative configurations described with reference to FIGS. 1a through 1c.

[0044] In FIGS. 2 through 7, each of the memory stacks (104) is illustrated as comprising five dies. For example, memory stack (104A) comprises a top die (210A), a memory die (212A), a memory die (214A), a memory die (216A), and a bottom die (218A). Additionally, memory stack (104B) comprises a top die (210B), a memory die (212B), a memory die (214B), a memory die (216B), and a bottom die (218B). In a particular embodiment, at least one die of each memory stack (104) comprises a memory control circuit (e.g., a memory controller), and the remaining dies of the memory stack (104) comprise a memory circuit (e.g., memory dies). For example, in FIGS. 2 through 7, the top die (210) of each memory stack (104) corresponds to or includes a memory controller, and the remaining dies of the memory stack (104) (e.g., memory die (212), memory die (214), memory die (216), and bottom die (218)) are memory dies. In other examples, the memory controller circuitry is integrated within the logic die (110), and each die of each memory stack (104) (including the top die (210)) is a memory die. Each die of the memory stacks (104) is interconnected by conductors (220) (e.g., TSVs) extending through each die. For example, the dies of memory stack (104A) are interconnected by conductors (220A), and the dies of memory stack (104B) are interconnected by conductors (220B).

[0045] In the stacked IC device (200) of FIG. 2, the side (112) of the logic die (110) is directly electrically connected to the side (116) of the top die (210) of each memory stack (104) by interconnections (108). For example, in this example, there are no RDLs or interposers between the side (112) of the logic die (110) and the side (116) of the top die (210) of each memory stack (104). The direct connection between the logic die (110) and the memory stacks (104) can make the signal paths between the logic die (110) and the memory stacks (104) shorter than configurations that include less direct connections, such as connections through RDLs or interposers.

[0046] Additionally, in FIG. 2, the back surface (118) of each bottom die (218) of the memory stacks (104) is bonded to the top surface (120) of the substrate (102) by an adhesive layer (222). For example, the back surface (118A) of the bottom die (218A) is bonded to the top surface (120) of the substrate (102) by an adhesive layer (222A), and the back surface (118B) of the bottom die (218B) is bonded to the top surface (120) of the substrate (102) by an adhesive layer (222B).

[0047] In the stacked IC device (300) of FIG. 3, the back surface (118) of each bottom die (218) of the memory stacks (104) is bonded to the top surface (120) of the substrate (102) by an adhesive layer (222) similar to the arrangement illustrated in FIG. 2. However, in FIG. 3, the side (112) of the logic die (110) is electrically connected to the side (116) of the top die (210) of each memory stack (104) through interconnects (108) and RDLs (302). In this example, the RDLs (302) provide longer signal paths between the logic die (110) and the memory stacks (104) than in the example illustrated in FIG. 2. However, the RDLs (302) facilitate the remapping of contacts of the logic die (110) and / or memory stacks (104), which can facilitate the use of memory stacks (104) with various logic dies (110) (e.g., for different product lines) and accommodate other design or circuit layout constraints. For example, in some cases, it may be difficult to place all memory input / output (I / O) contacts of the logic die (110) in the area directly above the memory stacks (104). In this example, the RDLs (302) can be used to remap the memory I / O contacts of the logic die (110) to facilitate connections to the memory stacks (104).

[0048] In the stacked IC device (400) of FIG. 4, the side (112) of the logic die (110) is directly electrically connected to the side (116) of the top die (210) of each memory stack (104) by interconnections (108) similar to the arrangement illustrated in FIG. 2 (e.g., RDLs are not present between the side (112) of the logic die (110) and the side (116) of the top die (210) of each memory stack (104). However, in FIG. 4, the RDLs (420) are positioned between the bottom dies (218) of each memory stack (104) and the substrate (102), and between the bottom of the patch component (130) and the substrate (102). The RDLs (420) are electrically connected to the substrate (102) through interconnections (422). The RDLs (420) facilitate the remapping of contacts on the top portion (120) of the substrate (102) and contacts of the patch component (130). In some embodiments, the RDLs (420) can function as a package substrate for a stacked IC device (400).

[0049] In the stacked IC device (500) of FIG. 5, the surface (112) of the logic die (110) is electrically connected to the surface (116) of the top die (210) of each memory stack (104) through interconnects (108) and RDLs (302), and the RDLs (420) are positioned between each bottom die (218) of the memory stacks (104) and the substrate (102) and between the bottom of the patch component (130) and the substrate (102). The RDLs (420) facilitate the remapping of contacts on the top (120) of the substrate (102) and contacts of the patch component (130), and the RDLs (302) facilitate the remapping of contacts of the logic die (110) and / or memory stacks (104).

[0050] In FIG. 6, the patch component (130) includes a circuit section (602). The circuit section (602) may include, for example, active components (e.g., transistors) and / or passive components (e.g., inductors, conductors, resistors, etc.). In one example, the circuit section (602) may include capacitors electrically connected to the power distribution network of the logic die (110) to improve the performance of the power distribution network.

[0051] In FIG. 7, the patch component (130) is formed of a plurality of stacked and electrically interconnected layers (702) that together define the conductors (106). In the example illustrated in FIG. 7, the patch component (130) is illustrated as having five layers, including layer (702A), layer (702B), layer (702C), layer (702D), and layer (702E). In other examples, the patch component (130) includes more than five layers (702) or fewer than five layers (702). For example, the number of layers (702) of the patch component (130) may vary depending on the number of dies of the memory stacks (104). For example, the number of layers (702) of the patch component (130) may be equal to the number of dies of the memory stacks (104). Alternatively, the number of layers (702) of the patch component (130) may differ from the number of dies of the memory stacks (104). For example, the number of dies of the memory stacks (104) may be a multiple of the number of layers (702) of the patch component (130).

[0052] FIGS. 8 and FIGS. 9 illustrate schematic cross-sectional views of other examples of exemplary stacked IC devices (800, 900). In a particular embodiment, the stacked IC devices (800, 900) represent examples of the stacked IC device (100) of FIGS. 1a through 1c comprising at least two logic dies (110). Unless otherwise specifically indicated, the stacked IC device (800, 900) may include any of the features, functions, and / or alternative configurations described with reference to FIGS. 1a through 1c.

[0053] In each of FIGS. 8 and FIGS. 9, the logic die (110A) is electrically connected face-to-face to the top die (210A) of the memory stack (104A), and the logic die (110B) is electrically connected face-to-face to the top die (210B) of the memory stack (104B). Each of the logic dies (110) is electrically connected to the substrate (102) through the conductors (106) of the patch component (130). In some embodiments, each of the logic dies (110) is also connected face-to-face to the top dies of one or more additional memory stacks (104).

[0054] In each of FIGS. 8 and FIGS. 9, one or more conductive paths electrically connect the logic die (110A) and the logic die (110B) to each other. For example, in FIGS. 8, the conductive path (802) extends through one of the conductors of the RDLs (302), through one or more of the conductors (106), through another or more of the conductors (106), and through another or more of the conductors of the RDLs (302). Thus, in FIGS. 8, a portion of the conductive path (802) between the logic dies (110) extends through the conductors (106). In FIGS. 9, the conductive path (902) extends through one of the conductors of the RDLs (302). In some embodiments, the aspects of FIGS. 8 and FIGS. 9 may be combined. For example, a stacked IC device may include a conductive path (802) and a conductive path (902).

[0055] Although FIGS. 2 through 7 each illustrate memory stacks (104) comprising five dies, memory stacks (104) of a stacked IC device according to the embodiments described herein may comprise more than five dies or fewer than five dies. For example, a memory stack (104) may comprise two memory dies, in which case a memory control circuit may be integrated within one or both of the memory dies, or separated from the memory dies, such as being integrated within a logic die (110) or another component of the stacked IC device. As another example, a memory stack (104) may comprise two memory dies and a memory controller. As another example, a memory stack (104) may comprise four, eight, sixteen, thirty-two, or some other number of memory dies.

[0056] Additionally, although each of the stacked IC devices of FIGS. 1 through 9 illustrates memory stacks (104), logic dies (110), patch components (130), and substrates (102), the stacked IC device according to the embodiments described herein may include additional components. For example, the stacked IC device may include one or more dies comprising a communication circuit (e.g., a wired or wireless communication circuit).

[0057] Exemplary sequences for manufacturing patch components

[0058] FIGS. 10a through 13b illustrate schematic cross-sectional views of stages during the formation of various types of patch components. For example, FIGS. 10a and 10b together illustrate an exemplary sequence for manufacturing a multilayer patch component including a semiconductor-based body, FIGS. 11a and 11b together illustrate an exemplary sequence for manufacturing a multilayer patch component including a polymer-based body, FIGS. 12a and 12b together illustrate an exemplary sequence for manufacturing a patch component including a core layer, and FIGS. 13a and 13b together illustrate an exemplary sequence for manufacturing a patch component without a core layer. Any sequence of figures 10a to 13b may be used to provide a patch component (130) for one or more of the memory stacked IC devices (100, 200, 300, 400, 500, 600, 700, 800, or 900) of figures 1a to 9 (e.g., during manufacturing thereof).

[0059] In each of the sequences of FIGS. 10a through 13b, two or more stages may be combined to simplify and / or clarify the sequence for providing or manufacturing a patch component. In some examples, the order of the processes may be changed or modified. In some examples, one or more of the processes may be replaced or substituted without departing from the scope of the present disclosure.

[0060] In the sequence for manufacturing the multilayer patch component of FIG. 10a and FIG. 10b, stage 1 of FIG. 10a illustrates a state after forming openings (1004) within a semiconductor layer (1002). For example, the semiconductor layer (1002) may comprise a semiconductor wafer, and the operations described with reference to FIG. 10a and FIG. 10b may include wafer-level operations. The openings (1004) may be formed using one or more etching operations induced by a patterned resist layer. Alternatively, in some embodiments, the openings (1004) may be formed using one or more drilling operations (e.g., laser drilling or mechanical drilling).

[0061] Stage 2 illustrates a state after forming a layer of conductive material (1006). The conductive material (1006) (e.g., copper) is formed to fill the openings (1004) or to plate the sidewalls of the openings (1004). The layer of conductive material (1006) may be formed using one or more deposition operations, such as chemical vapor deposition, physical vapor deposition, electroplating, or a combination thereof. In Stage 2, the conductive material layer (1006) is illustrated as comprising a layer on the surface of the semiconductor layer (1002); however, forming a material layer on the surface of the semiconductor layer (1002) is optional and may be omitted depending on the specific process operations used to form the conductive material layer (1006).

[0062] Stage 3 illustrates a state after further processing the conductive material layer (1006) to electrically insulate the vias (1008) from each other and after forming solder bumps (1010) on the vias (1008). Processing the conductive material layer (1006) to electrically insulate the vias (1008) is optional. For example, if the processing operations used to form the conductive material layer (1006) are controlled to avoid forming a material layer on the surface of the semiconductor layer (1002) illustrated in Stage 2, the operations to electrically insulate the vias (1008) may be omitted.

[0063] In embodiments where portions of the conductive material layer (1006) are removed to electrically insulate the vias (1008) from each other, portions of the conductive material layer (1006) may be removed using one or more material removal processes suitable for the conductive material, such as one or more etching operations, one or more grinding operations, one or more polishing operations, etc. For example, in some embodiments, one or more grinding operations are performed to remove portions of the conductive material layer (1006) so that the ends of the vias (1008) are substantially coplanar with the upper surface of the semiconductor layer (1002).

[0064] In the example illustrated in Stage 3, the ends of the vias (1008) extend over the upper surface of the semiconductor layer (1002), which is optional. In implementations where the ends of the vias (1008) are coplanar with the upper surface of the semiconductor layer (1002), the upper surface of the semiconductor layer (1002) may be etched back to provide a desired standoff height for the ends of the vias (1008). Alternatively, one or more additional deposition operations may be performed to form contacts that are electrically connected to the vias (1008) and extend over the upper surface of the semiconductor layer (1002).

[0065] Solder bumps (1010) are optional examples of contacts that may be formed on vias (1008). In some embodiments, solder bumps (1010) are omitted or replaced with other types of contacts, such as conductive pads. In embodiments including solder bumps (1010), solder bumps (1010) may be formed using one or more deposition operations to deposit solder on the ends of vias (1008) (or on contacts electrically connected to vias (1008). For example, a patterned resist layer may be formed on the surface of the semiconductor layer (1002) and may be used to induce the formation (e.g., deposition) of solder bumps (1010) on vias (1008). In some implementations, a barrier layer (e.g., a nickel layer) may be formed on the ends of the vias (1008) prior to the solder bumps (1010).

[0066] Stage 4 illustrates the state after flipping the semiconductor layer (1002) and bonding the semiconductor layer (1002) to a carrier (1014) using a bond layer (1012). For example, in the case of a wafer-level process, the semiconductor layer (1002) may include a semiconductor wafer, and the carrier (1014) may include a carrier wafer. In other examples, the semiconductor layer (1002) may include a size smaller than the entire wafer, such as a panel or a strip, and the carrier (1014) is sized based on the form factor of the semiconductor layer (1002).

[0067] Stage 5 of FIG. 10b illustrates the state after the formation of conductive pads (1016). For example, the formation of conductive pads (1016) may include performing one or more grinding operations to remove a portion of the semiconductor layer (1002) to expose the ends of the vias (1008). Subsequently, one or more deposition operations induced by a patterned resist layer may be performed to form conductive pads (1016) on the ends of the vias (1008). The conductive pads (1016) are optional examples of contacts that may be formed on the vias (1008). In some embodiments, the conductive pads (1016) are omitted or replaced with other types of contacts, such as solder bumps.

[0068] Stage 6 illustrates a state after removing the bond layer (1012) and the carrier (1014) and after separating a plurality of patch component layers (1020) from the semiconductor layer (1002). In some embodiments, one or both sides of the patch component layers (1020) include exposed ends of vias (1008). In other embodiments, one or both sides of the patch component layers (1020) include contacts on the ends of the vias (1008), and the contacts include solder bumps (e.g., solder bumps (1010)), conductive pads (e.g., conductive pads (1016)), or similar structures. One or more stripping processes may be used to remove the bond layer (1012) and the carrier (1014), and one or more cutting operations may be used to separate the patch component layers (1020) from each other.

[0069] Stage 7 illustrates a state after two or more patch component layers (1020) are stacked to form a patch component (1030). For example, the contacts of two or more patch component layers (1020) can be joined together using reflow operations to form continuous conductive paths (1024) through the patch component (1030). The continuous conductive paths (1024) correspond to examples of conductors (106) of FIGS. 1a through 9. Optionally, two or more patch component layers (1020) of the patch component (1030) may be at least partially embedded within a mold compound (1022).

[0070] The formation of the patch components (1030) is completed in step 7 of FIG. 10b. In FIG. 10b, the patch component (1030) is illustrated as having two patch component layers (1020); however, in other embodiments, the patch component (1030) may include more than two patch component layers (1020). The patch component (1030) includes a plurality of vias (1008) (e.g., through-silicon vias) that extend through the semiconductor layers (1002) and are interconnected in a stacked arrangement. The exposed ends of each via stack are prepared to form electrical connections with a substrate or logic die. For example, in FIG. 10b, one end of each via stack includes a solder bump (1010A), and the other end of each via stack includes a conductive pad (1016B).

[0071] In some embodiments, one or more of the semiconductor layers (1002) may include circuit parts, such as active circuit components (e.g., transistors), passive circuit components (e.g., capacitors, inductors, resistors), and conductors (e.g., traces) formed before stage 1 of FIG. 10a or between two stages of FIG. 10a and FIG. 10b (e.g., between stage 2 and stage 3). In these embodiments, the patch component (1030) may include the circuit part (602) of FIG. 6, the conductive path(s) (802) of FIG. 8, or both.

[0072] In the sequence for manufacturing the multilayer patch component of FIG. 11a and FIG. 11b, stage 1 of FIG. 11a illustrates a state after forming conductive posts (1108) (e.g., copper posts) on a bond layer (1102) formed on a carrier (1104) (e.g., a carrier wafer). For example, the conductive posts (1108) may be formed using one or more deposition operations, such as electroplating induced by a patterned resist layer (1106). Openings of the patterned resist layer (1106) define the locations and diameters of the conductive posts (1108).

[0073] Stage 2 illustrates a state after removing the patterned resist layer (1106) and forming a polymer layer (1110) on the bond layer (1102) (and on or above the conductive posts (1108). The polymer layer (1110) may comprise a resin, which may optionally comprise fillers. For example, the polymer layer (1110) may comprise a resin used in the formation of mold compounds or RDLs. The polymer layer (1110) may be applied to the bond layer (1102) using one or more deposition operations (e.g., spraying, printing, dispensing). The polymer layer (1110) may subsequently be cured or hardened by exposure to light, heat, chemical agents, or a combination thereof.

[0074] Stage 3 illustrates a post-processing state for exposing the ends (1112) of the conductive posts (1108). For example, one or more grinding operations, one or more polishing operations, or both may be performed to remove a portion of the polymer layer (1110) (and optionally a portion of the conductive posts (1108)) and expose the ends (1112) of the conductive posts (1108).

[0075] Stage 4 of FIG. 11b illustrates the state after forming contacts (1114) on conductive posts (1108) and removing the bond layer (1102) and carrier (1104) to expose the second ends (1116) of the conductive posts (1108). For example, the contacts (1114) may be formed using one or more deposition operations (as induced by a patterned resist layer). The formation of the contacts (1114) is optional and may be omitted in some embodiments. In FIG. 11b, the contacts (1114) are illustrated as conductive pads (e.g., copper pads); however, in other embodiments, the contacts (1114) may include solder bumps in addition to or instead of the conductive pads.

[0076] In some embodiments, after removing the bond layer (1102) and the carrier (1104), additional operations may be performed to prepare the second ends (1116) of the conductive posts (1108) for further processing. For example, the additional operations may include one or more flattening operations (e.g., grinding and / or polishing), one or more cleaning operations, etc.

[0077] Stage 5 illustrates the state after forming contacts (1118) on the second ends (1116) of the conductive posts (1108) and after individualizing a plurality of patch components (1120). In the example illustrated in FIG. 11b, each patch component (1120) comprises a plurality of conductive posts (1108) extending through a polymer layer (1110), and each conductive post (1108) comprises contacts (1114, 1118) at each end. As previously described with respect to the contacts (1114), the contacts (1118) may comprise conductive pads or solder bumps.

[0078] Stage 6 illustrates a state after two patch components (1120) are stacked to form a patch component (1130). For example, the contacts (1114, 1118) of the two patch components (1120) can be joined together (e.g., using reflow operations to form continuous conductive paths (1124) through the patch component (1130). The continuous conductive paths (1124) correspond to examples of conductors (106) in FIGS. 1a through 9. Optionally, the two patch components (1120) of the patch component (1130) can be at least partially embedded within a mold compound (1122).

[0079] The formation of the patch components (1130) is completed in step 6 of FIG. 11b. In FIG. 11b, the patch component (1130) is illustrated as having two electrically connected patch components (1120) corresponding to layers of the patch component (1130); however, in other embodiments, the patch component (1130) may include more than two electrically connected patch components (1120). The patch component (1130) includes a plurality of conductive posts (1108) that extend through polymer layers (1110) and are interconnected in a stacked arrangement. The exposed ends of each stack of conductive posts (1108) are prepared to form electrical connections with a substrate or logic die. For example, in FIG. 11b, one end of each stack of conductive posts (1108) includes a contact (1118A), and the other end of each stack of conductive posts (1108) includes a contact (1114B).

[0080] In some embodiments, one or more of the polymer layers (1110) may include circuit parts such as active circuit components (e.g., transistors), passive circuit components (e.g., capacitors, inductors, resistors), and conductors (e.g., traces) that are formed prior to stage 1 of FIG. 10a (e.g., between the bond layer (1102) and the conductive posts (1108)) or while one of the contacts (1114 or 1118) is being formed (e.g., in stage 4 or 5). In these embodiments, the patch component (1030) may include the circuit part (602) of FIG. 6, the conductive path(s) (802) of FIG. 8, or both.

[0081] In the sequence for manufacturing the patch component of FIG. 12a and FIG. 12b, stage 1 of FIG. 12a illustrates a state after forming or obtaining a workpiece comprising a core layer (1202) having metal layers (1204, 1206) on each side. The core layer (1202) may comprise a fiber-reinforced polymer. The metal layers (1204, 1206) may be bonded to the core layer (1202) using one or more lamination operations. In some embodiments, the thickness of the core layer (1202) is selected based on the target height of the patch component being formed. In some embodiments, the core layer (1202) includes an embedded circuit, such as one or more embedded dies, one or more embedded capacitors, etc. In these embodiments, the embedded circuit corresponds to the circuit (602) of FIG. 6.

[0082] Stage 2 illustrates the state after forming openings (1208) through the metal layers (1204, 1206) and the core layer (1202). In FIG. 12a, two openings (1208), including opening (1208A) and opening (1208B), are shown merely for illustrative purposes; however, in other embodiments, more than two openings (1208) are formed in Stage 2. For example, the openings (1208) are formed at positions corresponding to desired locations of the conductors of the patch component being formed (e.g., conductors (106) of any of FIG. 1a through 9). The openings (1208) may be formed using one or more material removal operations, such as mechanical drilling, laser drilling, etching, etc.

[0083] Stage 3 illustrates the state after forming metal layers (1210) within the openings (1208). For example, metal layers (1210A) are formed on the sidewalls of the opening (1208A), and metal layers (1210B) are formed on the sidewalls of the opening (1208B). The metal layers (1210) may be formed using one or more deposition operations, such as electroplating, physical vapor deposition, chemical vapor deposition, etc.

[0084] Stage 4 illustrates the state after forming patterned resist layers (1212, 1214) on the metal layers (1204, 1206). The patterned resist layers (1212, 1214) define areas for forming contacts around each of the openings (1208). In some embodiments, the patterned resist layers (1212, 1214) may also define areas for forming contacts not around the openings, such as contacts for the conductive paths (802) of FIG. 8 or contacts electrically connected to the circuit portion (602) of FIG. 6. Patterned resist layers (1212, 1214) can be formed by applying a dry film resist layer to each of the metal layers (1204, 1206), and then exposing and developing the dry film resist layers to form the patterned resist layers (1212, 1214).

[0085] Stage 5 of FIG. 12b illustrates the state after forming conductive vias (1216) within the openings (1208) of FIG. 12a. Each conductive via (1216) includes a contact (1218) on one side and a contact (1220) on the other side. For example, a conductive via (1216A) includes a contact (1218A) on the top side (in the orientation illustrated in FIG. 12b) and a contact (1220A) on the bottom side. Likewise, a conductive via (1216B) includes a contact (1218B) on the top side and a contact (1220B) on the bottom side. In some embodiments, the conductive vias (1216) and the contacts (1218, 1220) include two or more electrically connected metal layers. The conductive vias (1216) and contacts (1218, 1220) can be formed using one or more deposition operations such as electroplating, physical vapor deposition, chemical vapor deposition, etc., as induced by the patterned resist layers (1212, 1214).

[0086] Stage 6 illustrates the state after the removal of the patterned resist layers (1212, 1214). The patterned resist layers (1212, 1214) may be removed using one or more ashing operations, one or more stripping operations, other cleaning operations, or a combination thereof. After removing the patterned resist layer (1212), portions (1222) of the metal layer (1204) may remain between the contacts (1218). Additionally, or alternatively, after removing the patterned resist layer (1214), portions (1224) of the metal layer (1206) may remain between the contacts (1220).

[0087] Stage 7 illustrates a state after removing at least some of the portions (1222) of the metal layers (1204) and at least some of the portions (1224) of the metal layers (1206). For example, all portions (1222) between the contacts (1218) and all portions (1224) between the contacts (1220) may be removed to electrically insulate the conductive vias (1216) from each other. The portions (1222, 1224) may be removed by a flash etching process. Alternatively, the portions (1222) between the contacts (1218), the portions (1224) between the contacts (1220), or both may be optionally removed. For example, portions (1222) of the metal layer (1204) between two contacts (1220) may be maintained to define portions of the conductive paths (802) of FIG. 8.

[0088] In some embodiments, step 7 also follows the separation of the patch component (1230) from one or more other patch components formed simultaneously with the patch component (1230). For example, the operations described with reference to steps 1 through FIG. 6 may be used to form two or more patch components simultaneously, in which case step 7 follows the separation of the patch component (1230) from one or more other patch components using operations such as cutting, sawing, scribing, and snapping.

[0089] The formation of the patch components (1230) is completed in stage 7 of FIG. 12b. In FIG. 12b, the patch component (1230) is illustrated as including a core layer (1202); however, in other embodiments, two or more patch components (1230) may be stacked and interconnected to form a patch component (130) of any of FIG. 1a through 9. The patch component (1230) includes a plurality of conductive vias (1216) extending through the core layers (1202) and contacts (1218, 1220) on the ends of the conductive vias (1216).

[0090] In the sequence for manufacturing the patch component of FIG. 13a and FIG. 13b, stage 1 of FIG. 13a illustrates a state after forming or obtaining a workpiece comprising a core layer (1302) having release layers (1304, 1306) on each side. The core layer (1302) may comprise a fiber-reinforced polymer. The release layers (1304, 1306) may be bonded to the core layer (1302) using one or more lamination operations.

[0091] Stage 2 illustrates a state after forming a patterned resist layer (1308) on a release layer (1304) and forming a patterned resist layer (1312) on a release layer (1306). For example, dry film lamination techniques may be used to apply a dry film resist layer to each side of the workpiece of Stage 1, and the dry film resist layers may be exposed and developed to form the patterned resist layers (1308, 1312).

[0092] The patterned resist layer (1308) defines openings (1310) corresponding to the locations of contacts of the first patch component formed by the sequence of FIGS. 13a and 13b. In some cases, the patterned resist layer (1308) may also define openings (1310) corresponding to electrical interconnections (e.g., traces) between two or more contacts of the patch component. Similarly, the patterned resist layer (1312) defines openings (1314) corresponding to the locations of contacts of the second patch component formed by the sequence of FIGS. 13a and 13b and optionally the locations of electrical interconnections. In FIGS. 13a and 13b, the first and second patch components formed are illustrated as mirror images of each other with respect to a reflective surface along the centerline of the core layer (1302); however, in some embodiments, the first and second patch components are not of the mirror image type. For example, the patterned resist layer (1308) may have a number and / or arrangement of openings (1310) different from the number and / or arrangement of openings (1314) of the patterned resist layer (1312).

[0093] Stage 3 illustrates the state after the formation of metal layers (1316, 1318) and the removal of patterned resist layers (1308, 1312). For example, the metal layers (1316, 1318) may be formed using one or more deposition operations, such as electroplating, physical vapor deposition, chemical vapor deposition, etc., as induced by the patterned resist layers (1308, 1312). After the deposition of the metal layers (1316, 1318), the patterned resist layers (1308, 1312) may be removed using one or more ashing operations, one or more stripping operations, other cleaning operations, or a combination thereof.

[0094] Stage 4 illustrates a state after forming dielectric layers (1320, 1322) on exposed portions of metal layers (1316, 1318) and release layers (1304, 1306). For example, the dielectric layers (1320, 1322) may be applied using one or more dry film lamination operations.

[0095] Stage 5 of FIG. 13b illustrates the state after forming openings (1324) in the dielectric layer (1320) and openings (1326) in the dielectric layer (1322). The openings (1324) expose portions of the metal layer (1316), and the openings (1326) expose portions of the metal layer (1318). The openings (1324, 1326) may be formed using one or more optional material removal processes, such as mechanical drilling, laser drilling, or etching.

[0096] Stage 6 illustrates the state after the formation of metal layers (1328, 1334). The metal layer (1328) includes conductive vias (1330) within the openings (1324) and contacts (1332) on the surface of the dielectric layer (1320). The conductive vias (1330) are electrically connected to the conductive features of the metal layer (1316). Similarly, the metal layer (1334) includes conductive vias (1336) within the openings (1326) and contacts (1338) on the surface of the dielectric layer (1322). The conductive vias (1330) are electrically connected to the conductive features of the metal layer (1318). In some embodiments, the metal layer (1328), the metal layer (1334), or both include other features such as traces defining parts of the conductive paths (802) of FIG. 8.

[0097] The metal layers (1328, 1334) can be formed using one or more deposition operations, such as electroplating, physical vapor deposition, chemical vapor deposition, etc., as induced by the patterned resist layers. For example, the formation of the metal layers (1328, 1334) can be performed in the same manner as the formation of the metal layers (1316, 1318), as described with reference to stages 2 and 3 of FIG. 13a.

[0098] Stage 7 illustrates the state after the formation of dielectric layers (1340, 1348) and metal layers (1342, 1350). The dielectric layers (1340, 1348) and metal layers (1342, 1350) may be formed by repeating the operations described with reference to Stages 4 through 6. The metal layer (1342) includes conductive vias (1344) extending through the dielectric layer (1340) and contacts (1346) on the surface of the dielectric layer (1340). The conductive vias (1344) are electrically connected to the conductive features of the metal layer (1328). Similarly, the metal layer (1350) includes conductive vias (1352) extending through the dielectric layer (1348) and contacts (1354) on the surface of the dielectric layer (1348), the conductive vias (1352) being electrically connected to the conductive features of the metal layer (1334).

[0099] Stage 8 illustrates a state after forming additional dielectric layers (1356, 1360) and additional metal layers (1358, 1362) by repeating the operations described with reference to Stages 4 through 6. Although Stage 8 illustrates one additional dielectric layer and one additional metal layer on each side of the workpiece (e.g., a dielectric layer (1356) and a metal layer (1358) on the top side (in the orientation illustrated in FIG. 13b), and a dielectric layer (1360) and a metal layer (1362) on the bottom side), more than one additional dielectric layer and more than one additional metal layer may be formed on one or both sides of the workpiece in Stage 8. The number of additional dielectric layers and metal layers depends on the target thickness of the patch component (1370) and the height of each layer.

[0100] Step 8 also follows separating the patch components (1370) from the dislocation layers (1304, 1306), and in some embodiments, separates the patch components (1370) from other patch components formed simultaneously with the patch components (1370). For example, the operations described in relation to steps 1 through 8 may be used to form two or more patch components simultaneously on each side of the core layer (1302), in which case Step 8 follows separating the patch components (1370A) from one or more other patch components formed on the top of the core layer (1302) (e.g., using operations such as cutting, sawing, scribing, and snapping) and separating the patch components (1370B) from one or more other patch components formed on the bottom of the core layer (1302) (e.g., using operations such as cutting, sawing, scribing, and snapping).

[0101] The formation of the patch components (1370) is completed in stage 8 of FIG. 13b. In FIG. 13b, the patch components (1370) are illustrated as including via stacks (1364) extending through multiple layers of dielectric material. The via stacks (1364) may correspond to the conductors (106) of the patch components (130) of any of FIG. 1a through 9.

[0102] Exemplary sequences for manufacturing stacked IC devices

[0103] FIGS. 14a through 15b illustrate schematic cross-sectional views of stages during the formation of stacked IC devices. For example, FIGS. 14a and 14b together illustrate an exemplary first sequence for manufacturing a stacked IC device, and FIGS. 15a and 15b together illustrate an exemplary second sequence for manufacturing a stacked IC device. Using any one of the sequences of FIGS. 14a through 15b, one or more of the memory stacked IC devices (100, 200, 300, 400, 500, 600, 700, 800, or 900) of FIGS. 1a through 9 can be provided (e.g., during their manufacture).

[0104] In each of the sequences of FIGS. 14a through 15b, two or more stages may be combined to simplify and / or clarify the sequence for providing or manufacturing a stacked IC device. In some examples, the order of the processes may be changed or modified. In some examples, one or more of the processes may be replaced or substituted without departing from the scope of the present disclosure.

[0105] In the first sequence for manufacturing the stacked IC device of FIG. 14a and FIG. 14b, stage 1 of FIG. 14a illustrates a state after the logic die (1404) is coupled to the carrier (1402). The logic die (1404) is positioned in a face-up direction so that the back side of the logic die (1404) is coupled to the carrier (1402) and the contacts (1408) on the face (1406) of the logic die (1404) are moved away from the carrier (1402). The logic die (1404) may be attached to the carrier (1402) using an adhesive layer.

[0106] Although FIGS. 14a and 14b illustrate a single logic die (1404), the operations described herein may be performed on more than one logic die (1404) at a time. For example, the carrier (1402) may be a carrier wafer such as that used in reconfigured wafer-level operations. In this example, a plurality (e.g., tens or hundreds) of logic dies (1404) may be coupled to the carrier (1402) in stage 1, each logic die being for its own stacked IC device formed by the sequence of FIGS. 14a and 14b. In some embodiments, the sequence of FIGS. 14a and 14b may be used to form one or more stacked IC devices comprising two or more logic dies each (e.g., one of the stacked IC devices (800 or 900) of FIGS. 8 and 9). In these embodiments, two or more logic dies (1404) of each stacked IC device formed by the sequence of FIG. 14a and FIG. 14b are coupled to a carrier (1402) in stage 1.

[0107] Stage 2 illustrates the state after applying a mold compound (1410) to at least partially encapsulate the logic die (1404) and after forming RDLs (1412). The RDLs (1412) are optional and are omitted in some embodiments. If present, the RDLs (1412) remap the contacts (1408) of the logic die (1404) to contacts (1414) located at positions more convenient for interconnection with contacts such as memory stacks, patch components, etc. The mold compound (1410) can be formed by applying a resin (e.g., epoxy) to a carrier (1402) and subsequently curing it by exposing it to light, heat, and / or a chemical curing agent. The RDLs (1412) can be constructed using patterned metal layers separated by dielectric layers and optionally interconnected by conductive vias.

[0108] Stage 3 illustrates a state after two or more memory stacks (1420) and one or more patch components (1416) are electrically connected to a logic die (1404). In the example illustrated in FIG. 14a, the memory stacks (1420) include a memory stack (1420A) and a memory stack (1420B), and a patch component (1416) is placed between the memory stack (1420A) and the memory stack (1420B). The side (1422) of each die of the memory stacks (1420) is oriented to face the side (1406) of the logic die (1404). For example, the side (1422A) of the die of the memory stack (1420A) faces the side (1406) of the logic die, and the side (1422B) of the die of the memory stack (1420B) faces the side (1406) of the logic die.

[0109] Each of the memory stacks (1420) corresponds to one of the memory stacks (104) of any of FIGS. 1a through 9. The patch component (1416) includes or corresponds to any of the patch components (130) of FIGS. 1a through 9, the patch component (1030) of FIG. 10b, the patch component (1130) of FIG. 11b, the patch component (1230) of FIG. 12b, or the patch component (1370) of FIG. 13b. The patch component (1416) includes conductors (1418) corresponding to the conductors (106) of FIGS. 1a through 9.

[0110] Stage 4 of FIG. 14b illustrates a state after applying a mold compound (1424) and forming RDLs (1426) to at least partially encapsulate the patch component (1416) and memory stacks (1420). The formation of the mold compound (1424) and RDLs (1426) is optional and is omitted in some embodiments. If present, the RDLs (1426) remap the contacts of the conductors (1418) of the patch component (1416) to contacts (1428) (e.g., solder bumps) located at positions more convenient for interconnection with the contacts of the substrate. The mold compound (1424) and RDLs (1426) may be formed using operations similar to those described in relation to Stage 2 of FIG. 14a.

[0111] Stage 5 of FIG. 14b illustrates a state after separating the stacked IC device (1430) from the carrier (1402) and separating the stacked IC device (1430) from other stacked IC devices formed simultaneously. For example, when forming the stacked IC device (1430) using reconfigured wafer-level operations, a plurality of additional stacked IC devices may be formed simultaneously with the stacked IC device (1430) and on the same carrier (1402). In this example, the stacked IC devices may be separated from each other using individualization operations such as cutting, sawing, and / or scribing and snapping.

[0112] In some embodiments, the formation of the stacked IC device (1430) is completed in stage 5. For example, in some of these embodiments, the RDLs (1426) function as the substrate of the stacked IC device (1430). Alternatively, the RDLs (1426) may be coupled to another substrate, such as the substrate (102) of any of FIGS. 4 through 9, via contacts (1428). In other embodiments, the RDLs (1426) are omitted, in which case the stacked IC device (1430) of stage 5 is coupled to the substrate. For example, the back surface of the bottom die of each memory stack (1420) (e.g., the back surface (1432A) of the memory stacks (1420A) and the back surface (1432B) of the memory stack (1420B)) can be bonded to a substrate (e.g., using one of the adhesive layers (222) described with reference to FIG. 2), and the contacts of the conductors (1418) of the patch component (1416) can be electrically connected to the contacts of the substrate.

[0113] In the second sequence for manufacturing the stacked IC device of FIG. 15a and FIG. 15b, stage 1 of FIG. 15a illustrates a state after two or more memory stacks (1504) and one or more patch components (1512) are bonded to a carrier (1502). For example, the memory stacks (1504) and patch component(s) (1512) may be bonded to the carrier (1502) using an adhesive layer.

[0114] Memory stacks (1504) are positioned in a face-up orientation with respect to a carrier (1502) such that the back surface (1506) of the bottom die of each memory stack (1504) is coupled to the carrier (1502), and contacts (1510) on the face (1508) of the top die of each memory stack (1504) are moved away from the carrier (1502). For example, the back surface (1506A) of the bottom die of a memory stack (1504A) is coupled to the carrier (1502), and contacts (1510A) on the face (1508A) of the top die of a memory stack (1504A) are moved away from the carrier (1502). Additionally, the back surface (1506B) of the bottom die of the memory stack (1504B) is coupled to the carrier (1502), and the contacts (1510B) on the surface (1508B) of the top die of the memory stack (1504B) are moved away from the carrier (1502).

[0115] Although FIGS. 15a and 15b illustrate two memory stacks (1504) and one patch component (1512), the operations described herein may be performed simultaneously for more than two memory stacks (1504) and / or more than one patch component (1512). For example, the carrier (1502) may be a carrier wafer such as that used in reconfigured wafer-level operations. In this example, a plurality (e.g., tens or hundreds) of stacked IC devices may be formed simultaneously, and each of these stacked IC devices may include at least two memory stacks (1504) and at least one patch component (1512).

[0116] Each of the memory stacks (1504) corresponds to one of the memory stacks (104) of any of FIGS. 1a through 9. The patch component (1512) includes or corresponds to any of the patch components (130) of FIGS. 1a through 9, the patch component (1030) of FIG. 10b, the patch component (1130) of FIG. 11b, the patch component (1230) of FIG. 12b, or the patch component (1370) of FIG. 13b. The patch component (1512) includes conductors (1514) corresponding to the conductors (106) of FIGS. 1a through 9.

[0117] Stage 2 illustrates a state after applying a mold compound (1516) to at least partially encapsulate the memory stacks (1504) and patch components (1512) and after forming RDLs (1518). The formation of the mold compound (1516) and RDLs (1518) is optional and is omitted in some embodiments. If present, the RDLs (1518) remap the contacts of the conductors (1514) of the patch components (1512), the contacts (1510) of the memory stacks (1504), or both to locations more convenient for interconnection with the contacts of one or more logic dies. The mold compound (1516) may be formed by applying a resin (e.g., epoxy) to a carrier (1502) and subsequently curing it by exposing it to light, heat, and / or a chemical curing agent. RDLs (1518) can be constructed using patterned metal layers separated by dielectric layers and selectively interconnected by conductive vias.

[0118] Stage 3 illustrates a state after one or more logic dies (e.g., an exemplary logic die (1520)) are electrically connected to memory stacks (1504) and patch components (1512) in a face-to-face arrangement. For example, the side (1522) of the logic die (1520) is oriented toward the memory stacks (1504) and patch components (1512), and the back side (1526) of the logic die (1520) is oriented away from the memory stacks (1504) and patch components (1512). Contacts (1524) on the side (1522) of the logic die (1520) are electrically connected to the contacts of the RDLs (1518) through interconnections (1528), if the RDLs (1518) are present. Alternatively, if the RDLs (1518) are omitted, the contacts (1524) on the surface (1522) of the logic die (1520) are directly electrically connected to the contacts (1510) of the memory stacks (1504) and the contacts of the conductors (1514) through the interconnects (1528).

[0119] Stage 4 of FIG. 15b illustrates the state after applying a mold compound (1530) to at least partially encapsulate the logic die (1520). The formation of the mold compound (1530) is optional and may be omitted in some embodiments.

[0120] Stage 5 illustrates the state after separating the stacked IC device (1550) from the carrier (1502) and separating the stacked IC device (1550) from other stacked IC devices formed simultaneously. For example, when forming the stacked IC device (1550) using reconfigured wafer-level operations, a plurality of additional stacked IC devices may be formed simultaneously with the stacked IC device (1550) and on the same carrier (1502). In this example, the stacked IC devices may be separated from each other using individualization operations such as cutting, sawing, and / or scribing and snapping.

[0121] The state exemplified in Stage 5 also follows the attachment of memory stacks (1504) and patch components (1512) to layers (1532). Layers (1532) may comprise layers built directly on a surface exposed by the removal of the carrier (1502) (e.g., layers (1532) may comprise RDLs), or layers (1532) may be pre-formed and attached to a surface exposed by the removal of the carrier (1502) (e.g., layers (1532) may comprise a pre-formed substrate). In either case, layers (1532) comprise two or more metal layers that are patterned to form conductive features (e.g., traces), separated from one another by dielectric layers, and interconnected by vias to form conductive paths between metal layers. Layers (1532) remap the contacts of the conductors (1514) to the contacts (1534).

[0122] Exemplary flowchart of a method for manufacturing stacked IC devices

[0123] In some implementations, manufacturing a stacked IC device involves several processes. FIG. 16 illustrates an exemplary flowchart of a method (1600) for providing or manufacturing a stacked IC device. In some implementations, the method (1600) of FIG. 16 may be used to provide or manufacture any of the stacked IC devices of FIG. 1a through 9, FIG. 14b, and FIG. 15b. Note that the method (1600) may combine one or more processes to simplify and / or clarify the method (1600) for providing or manufacturing a stacked IC device. In some implementations, the order of the processes may be changed or modified.

[0124] The method (1600) includes the step of bonding a plurality of memory stacks to a substrate in block (1602), wherein each memory stack comprises two or more memory dies. For example, the memory stacks may include or correspond to memory stacks (104) of any of FIGS. 1a through 9 that are attached to the substrate (102) directly or via RDLs (420). As another example, the memory stacks may include or correspond to memory stacks (1420) of FIGS. 14a and FIGS. 14b, which may optionally be connected to RDLs (1426), wherein the RDLs (1426) may correspond to the substrate. Alternatively, the RDLs (1426) may be omitted, and the memory stacks (1420) may be bonded to a pre-formed substrate. As another example, memory stacks may include or correspond to memory stacks (1504) of FIG. 15a and FIG. 15b, which are connected to layers (1532), and layers (1532) correspond to a substrate.

[0125] The method (1600) includes the step of electrically connecting a patch component to a substrate in a region between two or more memory stacks among a plurality of memory stacks in block (1604). For example, the patch component may include or correspond to a patch component (130) of any of FIGS. 1a through 9, which is electrically connected to the substrate (102) directly or through RDLs (420). As another example, the patch component may include or correspond to a patch component (1416) of FIGS. 14a and FIGS. 14b, which may optionally be connected to RDLs (1426), in which case the RDLs (1426) may correspond to the substrate. Alternatively, the RDLs (1426) may be omitted, and the patch component (1416) may be electrically connected to a pre-formed substrate. As another example, the patch component may include or correspond to the patch component (1512) of FIG. 15a and FIG. 15b, which is electrically connected to layers (1532), and the layers (1532) correspond to a substrate.

[0126] The method (1600) includes the step of, in block (1606), electrically connecting a logic die to a substrate via a patch component and electrically connecting it face-to-face to the top dies of two or more memory stacks. For example, the logic die may correspond to a logic die(s) (110) of any of FIGS. 1a through 9, which is electrically connected face-to-face to the top die of each memory stack (104) and electrically connected to a substrate (102) via a patch component (130). As another example, the logic die may correspond to a logic die (1404) of FIGS. 14a and FIGS. 14b, which is electrically connected face-to-face to the top die of each memory stack (1420) and electrically connected to RDLs (1426), a pre-formed substrate, or both via a patch component (1416). As another example, the logic die may correspond to the logic die (1520) of FIG. 15a and FIG. 15b, which is electrically connected face-to-face with the top die of each memory stack (1504) and electrically connected to layers (1532) corresponding to the substrate through a patch component (1512).

[0127] In some embodiments, the method (1600) also includes the step of electrically connecting the second logic die to a substrate via a patch component and electrically connecting face-to-face to the top dies of two or more additional memory stacks among a plurality of memory stacks. In these embodiments, the second logic die may be electrically connected to the logic die via redistribution layers, via a patch component (e.g., as described with reference to FIG. 8), or both.

[0128] Exemplary electronic devices

[0129] FIG. 17 illustrates various electronic devices that may include or be integrated with any of the stacked IC devices (100, 200, 300, 400, 500, 600, 700, 800, 900, 1430, or 1550) of FIG. 1a through 9, FIG. 14b, or FIG. 15b. For example, a mobile phone device (1702), a laptop computer device (1704), a fixed-position terminal device (1706), a wearable device (1708), or a vehicle (1710) (e.g., an automobile or aviation device) may include the device (1700). The device (1700) may include any of the stacked IC devices (100, 200, 300, 400, 500, 600, 700, 800, 900, 1430, or 1550) of any of FIGS. 1a through 9, FIG. 14b, or FIG. 15b. The devices (1702, 1704, 1706, 1708) and the vehicle (1710) illustrated in FIG. 17 are merely exemplary.Other electronic devices may also feature a group of devices (e.g., electronic devices) comprising mobile devices, handheld PCS (personal communication systems) units, portable data units, such as personal information terminals, GPS (global positioning system) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units, such as meter reading equipment, communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), IoT (Internet of Things) devices, servers, routers, electronic devices implemented in vehicles (e.g., autonomous vehicles), or any other device for storing or retrieving data or computer commands, or any combination thereof.

[0130] One or more of the components, processes, features, and / or functions illustrated in FIGS. 1a through 17 may be rearranged and / or combined into a single component, process, feature, or function, or implemented in some components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from the present disclosure. It should also be noted that FIGS. 1a through 17 and the corresponding descriptions in the present disclosure are not limited to dies and / or ICs. In some embodiments, FIGS. 1a through 17 and the corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some embodiments, a device may include a die, an integrated device, an integrated passive device (IPD), a die package, an IC device, a device package, an IC package, a wafer, a semiconductor device, a package-on-package (PoP) device, a thermal dissipation device, and / or an interposer.

[0131] It should be noted that the drawings in this disclosure may depict actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, and integrated circuits. In some instances, the drawings may not be scaled. In some instances, for clarity, not all components and / or parts may be depicted. In some instances, the position, location, dimensions, and / or shapes of various parts and / or components in the drawings may be exemplary. In some implementations, various components and / or parts in the drawings may be optional.

[0132] The word “exemplary” is used herein to mean “serving as an example, case, or example.” Any embodiment or aspect described herein as “exemplary” is not necessarily to be interpreted as being advantageous or preferred over other aspects of the disclosure. Likewise, the term “aspects” does not require that all aspects of the disclosure include the discussed features, advantages, or modes of operation. The term “combined” is used herein to refer to a direct or indirect combination (e.g., mechanical combination) between two objects. For example, if object A is in physical contact with object B and object B is in contact with object C, objects A and C may still be considered combined with each other, even if they are not in direct physical contact with each other. Object A combined with object B may be combined with at least a portion of object B. The terms "electrically coupled" or "electrically connected" may mean that two objects are coupled together directly or indirectly so that an electric current (e.g., signal, power, ground) can travel between the two objects. Two electrically coupled objects may or may not have an electric current traveling between them. The use of the terms "first," "second," "third," and "fourth" (and / or more than four) is optional. Any of the described components may be the first component, the second component, the third component, or the fourth component. For example, a component referred to as the second component may be the first component, the second component, the third component, or the fourth component. The terms "encapsulate," "encapsulating," and / or any derivatives mean that an object may partially or completely encapsulate another object. The terms "top" and "bottom" are optional. A component located at the top can be placed on top of a component located at the bottom.The uppermost component may be regarded as the lowermost component, and vice versa. As described in this disclosure, a first component positioned "on" a second component may mean that the first component is positioned above or below the second component, depending on how the lower or uppermost is arbitrarily defined. In other examples, the first component may be positioned on (e.g., above) a first surface of the second component, and a third component may be positioned on (e.g., below) a second surface of the second component, where the second surface is opposite to the first surface. Also, note that in the context of one component positioned on another component as used herein, the term "on" may be used to mean a component that is on and / or within another component (e.g., on the surface of the component or embedded within the component). Accordingly, for example, a first component on a second component may mean (1) that the first component is on the second component but is not in direct contact with the second component, (2) that the first component is on the second component (e.g., on its surface), and / or (3) that the first component is within the second component (e.g., embedded therein). A first component located "within" the second component may be partially located within the second component or entirely located within the second component. A value of about X to XX may mean a value between X and XX, including X and XX. The value(s) between X and XX may be discrete or continuous. The term "about 'value X'" or "approximately value X" as used in this disclosure means within 10% of 'value X'. For example, a value of about 1 or approximately 1 will mean a value within the range of 0.9 to 1.1. "Multiple" components may include all possible components or only some of the possible components.For example, if a device includes 10 components, the use of the term "multiple components" may refer to all 10 components or only some of the 10 components.

[0133] In some implementations, an interconnect is an element or component of a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include an electrically conductive material that can be configured to provide an electrical path to a signal (e.g., a data signal), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or sequences to form interconnects. In some implementations, chemical vapor deposition (CVD) processes, physical vapor deposition (PVD) processes, sputtering processes, spray coating, reflow processes, and / or plating processes may be used to form interconnects.

[0134] Additionally, it should be noted that the various disclosures included in this specification may be described as processes depicted as flowcharts, flow diagrams, structural diagrams, or block diagrams. While flowcharts may describe operations as sequential processes, most operations may be performed in parallel or simultaneously. Furthermore, the order of operations may be rearranged. A process terminates when its operations are completed.

[0135] In the following, additional examples are described to facilitate understanding of the present disclosure.

[0136] According to Example 1, the device comprises: a first memory stack including two or more memory dies coupled to a substrate; a second memory stack including two or more memory dies coupled to a substrate; a logic die electrically connected to the memory dies of the first memory stack through face-to-face connections to the top die of the first memory stack and electrically connected to the memory dies of the second memory stack through face-to-face connections to the top die of the second memory stack; and a patch component disposed in an area between the first memory stack and the second memory stack, wherein the patch component includes conductors that electrically connect the logic die to the substrate.

[0137] Example 2 includes the device of Example 1, and the first memory stack includes a high-bandwidth memory (HBM) stack.

[0138] Example 3 includes the device of Example 1 or Example 2, and the top die of the first memory stack includes a memory controller for two or more memory dies of the first memory stack.

[0139] Example 4 includes a device of any one of Examples 1 to 3, wherein the body of the patch component includes a mold compound, and the conductors include through mold vias extending through the mold compound.

[0140] Example 5 includes a device of any one of Examples 1 to 3, the body of the patch component includes a multilayer structure, and the conductors include stacked and electrically connected conductors extending through the layers of the multilayer structure.

[0141] Example 6 includes a device of any one of Examples 1 to 3, wherein the body of the patch component includes a core layer, and the conductors include vias extending through the core layer.

[0142] Example 7 includes a device of any one of Examples 1 to 3, wherein the body of the patch component includes a semiconductor layer, and one or more of the conductors include through-silicon vias extending through the semiconductor layer.

[0143] Example 8 includes a device of any one of Examples 1 to 7, and the patch component includes active circuit components, passive circuit components, or both.

[0144] Example 9 comprises a device of any one of Examples 1 to 8, and further comprises one or more additional memory stacks including two or more memory dies coupled to a substrate; and a second logic die electrically connected to the memory dies of the one or more additional memory stacks through face-to-face connections to the top die of each of the one or more additional memory stacks, and the conductors of the patch component electrically connect the second logic die to the substrate.

[0145] Example 10 includes the device of Example 9 and further includes redistribution layers that are located between the logic die and the first memory stack, between the logic die and the second memory stack, between the second logic die and one or more additional memory stacks, and electrically connect the logic die to the second logic die.

[0146] Example 11 includes the device of Example 9 or Example 10, and the logic die is electrically connected to a second logic die through a patch component.

[0147] According to Example 12, the device comprises: a first memory stack including two or more memory dies coupled to a substrate; a second memory stack including two or more memory dies coupled to a substrate; a first logic die electrically connected to the memory dies of the first memory stack through face-to-face connections to the top die of the first memory stack; a second logic die electrically connected to the memory dies of the second memory stack through face-to-face connections to the top die of the second memory stack; and a patch component disposed in an area between the first memory stack and the second memory stack, wherein the patch component includes first conductors electrically connecting the first logic die to the substrate and second conductors electrically connecting the second logic die to the substrate.

[0148] Example 13 includes the device of Example 12, the first memory stack includes a first high-bandwidth memory stack, and the second memory stack includes a second high-bandwidth memory stack.

[0149] Example 14 includes the device of Example 12 or Example 13, wherein the top die of the first memory stack includes a first memory controller for two or more memory dies of the first memory stack, and the top die of the second memory stack includes a second memory controller for two or more memory dies of the second memory stack.

[0150] Example 15 includes a device of any one of Examples 12 to 14, and the first logic die and the second logic die are electrically connected to each other through a patch component.

[0151] Example 16 includes a device of any one of Examples 12 to 15, and further includes redistribution layers disposed between a first logic die and a first memory stack and between a second logic die and a second memory stack, and electrically connecting the first logic die to the second logic die.

[0152] According to Example 17, the method comprises the steps of: joining a plurality of memory stacks to a substrate—each memory stack comprising two or more memory dies—; electrically connecting a patch component to the substrate in an area between two or more memory stacks among the plurality of memory stacks; and electrically connecting a logic die to the substrate through the patch component and electrically connecting it face-to-face to the top dies of two or more memory stacks.

[0153] Example 18 includes the method of Example 17 and further includes the step of electrically connecting a second logic die to a substrate through a patch component and electrically connecting face-to-face to the top dies of two or more additional memory stacks among a plurality of memory stacks.

[0154] Example 19 includes the method of Example 17 or Example 18 and further includes the step of electrically connecting a logic die to a second logic die through a patch component.

[0155] Example 20 includes the method of Example 18 or Example 19 and further includes the step of electrically connecting the logic die to a second logic die through redistribution layers.

Claims

Claim 1 A device comprising: a first memory stack including two or more memory dies coupled to a substrate; a second memory stack including two or more memory dies coupled to the substrate; a logic die electrically connected to the memory dies of the first memory stack through face-to-face connections to the top die of the first memory stack and electrically connected to the memory dies of the second memory stack through face-to-face connections to the top die of the second memory stack; and a patch component disposed in an area between the first memory stack and the second memory stack, wherein the patch component comprises conductors electrically connecting the logic die to the substrate. Claim 2 A device according to claim 1, wherein the first memory stack comprises a high bandwidth memory (HBM) stack. Claim 3 A device according to claim 1, wherein the uppermost die of the first memory stack comprises a memory controller for the two or more memory dies of the first memory stack. Claim 4 A device according to claim 1, wherein the main body of the patch component comprises a mold compound, and the conductors comprise through mold vias extending through the mold compound. Claim 5 A device according to claim 1, wherein the main body of the patch component comprises a multilayer structure, and the conductors comprise stacked and electrically connected conductors extending through the layers of the multilayer structure. Claim 6 A device according to claim 1, wherein the main body of the patch component includes a core layer, and the conductors include vias extending through the core layer. Claim 7 A device according to claim 1, wherein the main body of the patch component comprises a semiconductor layer, and one or more of the conductors comprise a silicon through-via extending through the semiconductor layer. Claim 8 A device according to claim 1, wherein the patch component comprises active circuit components, passive circuit components, or both. Claim 9 A device according to claim 1, further comprising: one or more additional memory stacks including two or more memory dies coupled to the substrate; and a second logic die electrically connected to the memory dies of the one or more additional memory stacks through face-to-face connections to each of the top dies of the one or more additional memory stacks, wherein the conductors of the patch component electrically connect the second logic die to the substrate. Claim 10 A device according to claim 9, further comprising redistribution layers located between the logic die and the first memory stack, between the logic die and the second memory stack, and between the second logic die and the one or more additional memory stacks, and electrically connecting the logic die to the second logic die. Claim 11 In claim 9, the device, wherein the logic die is electrically connected to the second logic die through the patch component. Claim 12 A device comprising: a first memory stack including two or more memory dies coupled to a substrate; a second memory stack including two or more memory dies coupled to the substrate; a first logic die electrically connected to the memory dies of the first memory stack through face-to-face connections to the top die of the first memory stack; a second logic die electrically connected to the memory dies of the second memory stack through face-to-face connections to the top die of the second memory stack; and a patch component disposed in an area between the first memory stack and the second memory stack, wherein the patch component comprises first conductors electrically connecting the first logic die to the substrate and second conductors electrically connecting the second logic die to the substrate. Claim 13 A device according to claim 12, wherein the first memory stack comprises a first high-bandwidth memory stack and the second memory stack comprises a second high-bandwidth memory stack. Claim 14 A device according to claim 12, wherein the top die of the first memory stack comprises a first memory controller for the two or more memory dies of the first memory stack, and the top die of the second memory stack comprises a second memory controller for the two or more memory dies of the second memory stack. Claim 15 In claim 12, the device wherein the first logic die and the second logic die are electrically connected to each other through the patch component. Claim 16 A device according to claim 12, further comprising redistribution layers disposed between the first logic die and the first memory stack and between the second logic die and the second memory stack, and electrically connecting the first logic die to the second logic die. Claim 17 A method comprising the steps of: joining a plurality of memory stacks to a substrate, wherein each memory stack comprises two or more memory dies; electrically connecting a patch component to the substrate in an area between two or more memory stacks among the plurality of memory stacks; and electrically connecting a logic die to the substrate through the patch component and electrically connecting it face-to-face to the top dies of the two or more memory stacks. Claim 18 A method according to claim 17, further comprising the step of electrically connecting a second logic die to the substrate through the patch component and electrically connecting face-to-face to the top dies of two or more additional memory stacks among the plurality of memory stacks. Claim 19 A method according to claim 18, further comprising the step of electrically connecting the logic die to the second logic die through the patch component. Claim 20 A method according to claim 18, further comprising the step of electrically connecting the logic die to the second logic die through redistribution layers.

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