Method for predicting the effectiveness of maintenance work in integrated circuit production and related devices

Abstract

A method for predicting the effect of a potential substrate table maintenance operation related to a substrate table of a lithography apparatus is disclosed. The method comprises: acquiring layer-by-layer substrate loading distortion state data related to distortion of a substrate or a group of substrates that occurs by loading a substrate onto the substrate table when exposing one or more layers; acquiring at least one layer-by-layer sensitivity value for each of one or more layers on the substrate, which describes the sensitivity of an error metric induced by the substrate loading distortion to the substrate loading distortion state data; and determining the effect of a potential substrate table maintenance operation on an error metric induced by the substrate loading distortion based on the layer-by-layer substrate loading distortion state data and the at least one layer-by-layer sensitivity value.

Description

Technology Field

[0001] [Cross-reference to related applications]

[0002] This application claims priority to EP application 24151768.9 filed on January 15, 2024, the full text of which is incorporated herein by reference.

[0003] [Technology Field]

[0004] The present invention relates to a method and apparatus usable for manufacturing a device, for example, by lithography technology, and also to a method for manufacturing a device using lithography technology. Background Technology

[0005] A lithography device is a machine that applies a desired pattern onto a substrate, typically onto a target area of ​​the substrate. Lithography devices can be used, for example, in the manufacture of integrated circuits (ICs). In that case, a patterning device, also alternatively referred to as a mask or reticle, can be used to generate a circuit pattern to be formed on individual layers of the IC. This pattern can be transferred onto a target area on a substrate (e.g., a silicon wafer) (e.g., part of a die, a single die, or a number of dies). The transfer of the pattern is typically performed through imaging onto a layer of radiation-sensitive material (resist) provided on the substrate. Generally, a single substrate will contain a network of adjacent target areas that are patterned in succession. These target areas are typically referred to as "fields."

[0006] In the manufacture of complex devices, typically many lithographic patterning steps are performed to form functional features on successive layers of a substrate. Therefore, an important aspect of the performance of a lithography device is the ability to correctly and accurately place the applied pattern relative to features engraved on previous layers (by the same device or a different lithography device). To this end, the substrate is provided with one or more sets of alignment marks. Each mark is a structure whose position can be measured at a later time using a position sensor, typically an optical position sensor. The lithography device includes one or more alignment sensors, and the position of the marks on the substrate can be accurately measured by these alignment sensors. Different types of marks and different types of alignment sensors are known from various manufacturers and different products from the same manufacturer.

[0007] In other applications, a metrology sensor is used to measure exposed structures on a substrate (in the resist, and / or after etching). A scatterometer is a specialized inspection tool that is rapid and non-destructive, in which a radiation beam is directed toward a target on the substrate surface, and the properties of the scattered or reflected beam are measured. Examples of known scatterometers include angle-resolved scatterometers of the type described in US2006033921A1 and US2010201963A1. In addition to measuring feature shapes through reconstruction, diffraction-based overlays can be measured using such devices, as described in published patent application US2006066855A1. Using diffraction-based overlay metrology that utilizes dark-field imaging of diffraction orders enables overlay measurements for smaller targets. Examples of dark-field imaging metrology can be found in international patent applications WO 2009 / 078708 and WO 2009 / 106279, the full text of which is incorporated herein by reference. Further developments regarding the technology are described in published patent publications US20110027704A, US20110043791A, US2011102753A1, US20120044470A, US20120123581A, US20130258310A, US20130271740A, and WO2013178422A1. These targets may be smaller than the illumination spot and may be surrounded by product structures on the wafer. Multiple gratings can be measured in a single image using a composite grating target. The contents of all these applications are also incorporated by reference into this specification.

[0008] It is necessary to perform routine maintenance on the lithography to replace degraded components. In particular, the wafer table (substrate support) requires periodic replacement due to wear on the wafer table burl (protrusion) that actually supports the substrate. Since different layers of the same substrate being exposed before and after maintenance can cause fingerprints of the replaced component or significant overlay errors when compared to the replaced component, it may be necessary to ramp down one or more layers when preparing for maintenance.

[0009] It is desirable to predict the impact of these maintenance tasks on productivity. means of solving the problem

[0010] In a first embodiment, the present invention provides a method for predicting the effect of a potential substrate table maintenance operation associated with a substrate table of a lithography apparatus, the method comprising: obtaining per-layer substrate loading distortion state data associated with distortion of a substrate or group of substrates that occurs by loading a substrate onto the substrate table when exposing one or more layers; obtaining at least one per-layer sensitivity value for each of one or more layers on the substrate, which describes the sensitivity of an error metric induced by substrate loading distortion to the substrate loading distortion state data; and determining the effect of a potential substrate table maintenance operation on an error metric induced by substrate loading distortion based on the per-layer substrate loading distortion state data and the at least one per-layer sensitivity value.

[0011] In addition, a computer program and a lithography device operable to perform the method of the first embodiment are disclosed.

[0012] The above-described aspects and other aspects of the present invention will be understood from the examples described below. Brief explanation of the drawing

[0013] Now, embodiments of the present invention will be described only by way of example with reference to the accompanying drawings. Figure 1 illustrates a lithography apparatus. FIG. 2 schematically illustrates the measurement and exposure processes in the apparatus of FIG. 1. FIG. 3(a) conceptually illustrates the offsetting effect of the wafer table fingerprint overlay on each layer when there is no wafer table replacement, and FIG. 3(b) conceptually illustrates the effect of such wafer table replacement on the performance of the overlay. Figure 4 is a plot of the cumulative lot of wafers produced over time, illustrating the concepts of time A, time B, and time C. FIG. 5 is a flowchart illustrating a method for scheduling and / or determining the effectiveness of maintenance work according to one embodiment. FIG. 6 is a plot of wafer load grid states over time illustrating the concept disclosed in this specification. Specific details for implementing the invention

[0014] Before describing the embodiments of the present invention in detail, it is beneficial to present an exemplary environment in which the embodiments of the present invention may be implemented.

[0015] Figure 1 schematically illustrates a lithography apparatus (LA). The device comprises an illumination system (IL) (illuminator) configured to condition a radiation beam (B) (e.g., UV radiation, or DUV radiation); a patterning device support or support structure (MT) (e.g., mask table) configured to support a patterning device (MA) (e.g., mask) and connected to a first positioner (PM) (the first positioner is configured to accurately position the patterning device according to specific parameters); two substrate tables (WTa and WTb) (e.g., wafer tables), each configured to hold a substrate (W) (e.g., a resist-coated wafer) and connected to a second positioner (PW) (the second positioner is configured to accurately position the substrate according to specific parameters), respectively; and a projection configured to project a pattern imparted to the radiation beam (B) by the patterning device (MA) onto a target portion (C) of the substrate (W) (e.g., including one or more dies). It includes a system (PS) (e.g., a refractive projection lens system). The reference frame (RF) connects various components and serves as a reference for establishing and measuring the positions of the patterning device, the substrate, and the features on it.

[0016] A lighting system may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic, or other types of optical components, or any combination thereof, to direct, shape, or control radiation.

[0017] The patterning device support (MT) holds the patterning device in a manner that depends on the orientation of the patterning device, the design of the lithography device, and other conditions, such as whether the patterning device is maintained in a vacuum environment, for example. The patterning device support may use mechanical, vacuum, electrostatic, or other clamping techniques to hold the patterning device. The patterning device support (MT) may be, for example, a frame or table that can be fixed or movable as needed. The patterning device support can ensure that the patterning device is in a desired position, for example, relative to a projection system.

[0018] The term “patterning device” as used herein should be broadly interpreted to refer to any device that can be used to impart a pattern to the cross-section of a radiation beam in order to create a pattern on a target portion of a substrate. It should be noted that the pattern imparted to the radiation beam may not exactly correspond to a desired pattern within the target portion of the substrate, for example, if the pattern includes phase-shifting features or so-called assist features. Generally, the pattern imparted to the radiation beam will correspond to a specific functional layer within the device created on the target portion, such as an integrated circuit.

[0019] As described herein, the device is transmissive (e.g., using a transmissive patterning device). Alternatively, the device may be configured to be reflective (e.g., using a programmable mirror array of the type previously mentioned or using a reflective mask). Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels. Where the terms "reticle" or "mask" are used herein, they may be considered synonymous with the more general term "patterning device." Additionally, the term "patterning device" may also be interpreted to refer to a device that stores pattern information in digital form for use in controlling such programmable patterning devices.

[0020] As used herein, the term “projection system” should be broadly interpreted to encompass any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic, and electrostatic optical systems, or any combination thereof, to be appropriate for the exposure radiation used, or other factors such as the use of immersion liquid or vacuum. Wherever the term “projection lens” is used herein, it may be considered synonymous with the more general term “projection system.”

[0021] In addition, the lithography apparatus may be of a type in which at least a portion of the substrate can be covered with a liquid having a relatively high refractive index, such as water, to fill the space between the projection system and the substrate. Furthermore, the immersion liquid may also be applied to other spaces within the lithography apparatus, such as between the mask and the projection system. Immersion techniques are well known in the art for increasing the numerical aperture of the projection system.

[0022] When in operation, the illuminator (IL) receives a radiation beam from the radiation source (SO). For example, if the source is an excimer laser, the source and the lithography device may be separate entities. In this case, the source is not considered to form part of the lithography device, and the radiation beam is passed from the source (SO) to the illuminator (IL) with the help of a beam delivery system (BD) including, for example, a suitable directional mirror and / or a beam expander. In other cases, for example, if the source is a mercury lamp, the source may be an integrated part of the lithography device. The source (SO) and the illuminator (IL), together with the beam delivery system (BD), may be referred to as a radiation system as necessary.

[0023] The illuminator (IL) may include, for example, a regulator (AD) for adjusting the angular intensity distribution of the radiation beam, an integrator (IN), and a condenser (CO). The illuminator may be used to condition the radiation beam to have a desired uniformity and intensity distribution across the cross-section of the radiation beam.

[0024] A radiation beam (B) is incident on a patterning device (MA) held on a patterning device support (MT) and is patterned by the patterning device. After traversing the patterning device (e.g., mask) (MA), the radiation beam (B) passes through a projection system (PS), which focuses the beam onto a target portion (C) of a substrate (W). With the help of a second positioner (PW) and a position sensor (IF) (e.g., an interferometer, a linear encoder, a 2-D encoder, or a capacitive sensor), the substrate table (WTa or WTb) can be moved precisely to position different target portions (C), for example, within the path of the radiation beam (B). Similarly, a first positioner (PM) and another position sensor (not clearly shown in FIG. 1) can be used to accurately position a patterning device (e.g., a mask) (MA) in the path of a radiation beam (B), for example, after mechanical retrieval from a mask library or during scanning.

[0025] A patterning device (e.g., a mask) (MA) and a substrate (W) can be aligned using mask alignment marks (M1, M2) and substrate alignment marks (P1, P2). Although the substrate alignment marks as illustrated occupy dedicated target areas, they may also be located within the space between the target areas [known as scribe-lane alignment marks]. Similarly, in situations where more than one die is provided on the patterning device (e.g., a mask) (MA), the mask alignment marks may be located between the dies. Additionally, small alignment marks may be included between device features within the dies; in this case, it is desirable that the markers be as small as possible and not require different imaging or process conditions from adjacent features. An alignment system for detecting alignment markers is further described below.

[0026] The illustrated device can be used in various modes. In scan mode, the patterning device support (MT) (e.g., mask table) and the substrate table (WT) are scanned synchronously while the pattern imparted by the radiation beam is projected onto the target portion (C) [i.e., single dynamic exposure]. The speed and direction of the substrate table (WT) relative to the patterning device support (MT) (e.g., mask table) can be determined by the magnification (reduction) and image inversion characteristics of the projection system (PS). In scan mode, the maximum size of the exposure field limits the width of the target portion (in a direction other than the scanning direction) in single dynamic exposure, while the length of the scanning motion determines the height of the target portion (in the scanning direction). As is well known in the art, other types of lithography devices and modes of operation are possible. For example, a step mode is known. In so-called "maskless" lithography, the programmable patterning device remains stationary while the pattern is changed, and the substrate table (WT) is moved or scanned.

[0027] Combinations and / or variations of the usage modes described above or completely different usage modes may be adopted.

[0028] The lithography device (LA) is a so-called dual-stage type having two substrate tables (WTa, WTb) and two stations—an exposure station (EXP) and a measurement station (MEA), where substrate tables can be exchanged between these stations. While one substrate on one substrate table is being exposed at the exposure station, another substrate can be loaded onto another substrate table at the measurement station, and various preparation steps can be performed. This can significantly increase the throughput of the device. Preparation steps may include mapping the height contour of the substrate using a level sensor (LS) and measuring the positions of alignment markers on the substrate using an alignment sensor (AS). If the position sensor (IF) cannot measure the position of the substrate table while it is at both the exposure station and the measurement station, a second position sensor may be provided to allow the position of the substrate table relative to a reference frame (RF) to be tracked at both stations. Other configurations are known and may be used instead of the illustrated dual-stage configuration. For example, other lithography devices are known that are provided with a substrate table and a measurement table. These are docked together when performing preparatory measurements, and then undocking while the substrate table undergoes exposure.

[0029] FIG. 2 illustrates steps for exposing a target portion (e.g., a die) on a substrate (W) in the dual-stage apparatus of FIG. 1. Steps performed at the measurement station (MEA) are illustrated within the dashed box on the left, while steps performed at the exposure station (EXP) are illustrated on the right. Sometimes, as previously described, one of the substrate tables (WTa, WTb) will be in the exposure station and the other in the measurement station. For the purposes of this description, it is assumed that the substrate (W) has already been loaded into the exposure station. In step 200, a new substrate (W') is loaded into the apparatus by a mechanism not illustrated. These two substrates are processed in parallel to increase the throughput of the lithography apparatus.

[0030] Referring first to the newly loaded substrate (W'), this substrate may be an unprocessed substrate prepared using a new photoresist for the first exposure in the device. However, the described lithography process is generally only one step in a series of exposure and processing steps; therefore, the substrate (W') may have already passed through this device and / or other lithography devices multiple times and may also be scheduled to undergo subsequent processes. Particularly regarding the issue of improving overlay performance, the challenge is to ensure that new patterns are applied to the correct locations on a substrate that has already undergone one or more patterning and processing cycles. These processing steps progressively introduce distortion into the substrate, and such distortion must be measured and corrected to achieve satisfactory overlay performance.

[0031] As mentioned immediately above, the preceding process and / or subsequent patterning steps may be performed on different lithography devices, or even on different types of lithography devices. For example, for some layers that are very demanding in terms of parameters such as resolution and overlay in the device manufacturing process, the process may be performed on a more advanced lithography tool than on other layers that are less demanding. Thus, some layers may be exposed on an immersion-type lithography tool, while others may be exposed on a 'dry' tool. Some layers may be exposed on a tool operating at DUV wavelengths, while others may be exposed using EUV wavelength radiation.

[0032] In step 202, the alignment of the substrate with respect to the substrate table (WTa / WTb) is measured and recorded using substrate marks (P1, etc.) and alignment measurements using an image sensor (not shown). Additionally, several alignment marks across the substrate (W') will be measured using an alignment sensor (AS). These measurements are used to establish a "wafer grid" in one embodiment, which maps the distribution of marks across the substrate very accurately, including any distortion relative to a nominal rectangular grid.

[0033] In step 204, a map of the wafer height (Z) for the XY position is also measured using a level sensor (LS). Conventionally, the height map is used only for the purpose of achieving accurate focusing of the exposed pattern. The height map may be used for other purposes as well.

[0034] When the substrate (W') is loaded, recipe data (206) is received that defines the characteristics of the wafer, the pattern previously created on the wafer, and the pattern to be created thereafter, along with the exposure to be performed. In addition to these recipe data, measurements of the wafer position, wafer grid, and height map created in steps 202 and 204 are added, so that a complete recipe and measurement data set (208) can be transmitted to the exposure station (EXP). The measurements of the alignment data include, for example, the X and Y positions of alignment targets formed in a fixed or nominally fixed relationship with respect to the product pattern, which is the product of the lithography process. These alignment data obtained immediately before exposure are used to create an alignment model, and the alignment model has parameters that fit the model to the data. These parameters and the alignment model will be used during the exposure operation to correct the positions of the patterns applied in the current lithography step. The model used interpolates the position deviation between the measured positions. Conventional alignment models may include four, five, or six parameters that define the translation, rotation, and scaling of an 'ideal' grid with different dimensions. Advanced models are known to use more parameters.

[0035] In step 210, as the wafers (W' and W) are exchanged, the measured substrate (W') becomes the substrate (W) entering the exposure station (EXP). In the exemplary apparatus of FIG. 1, this exchange is performed by exchanging supports (WTa and WTb) within the apparatus, so that the substrates (W, W') are kept accurately clamped and positioned on these supports to preserve the relative alignment between the substrate table and the substrate itself. Thus, when the tables are exchanged, all that is required to use the measurement information (202, 204) for the substrate (W) (formerly W') controlling the exposure step is to determine the relative position between the projection system (PS) and the substrate table (WTb) (formerly WTa). In step 212, reticle alignment is performed using mask alignment marks (M1, M2). In steps 214, 216, and 218, to complete the exposure of multiple patterns, scanning operations and radiation pulses are applied to successive target locations across the substrate (W).

[0036] By using alignment data and height maps acquired from the measurement station when performing the exposure steps, these patterns are accurately aligned to desired locations, and in particular to features previously placed on the same substrate. The exposed substrate (now labeled W”) is unloaded from the device in step 220 to undergo etching or other processes according to the exposed pattern.

[0037] Those skilled in the art will recognize that the foregoing description is a simplified overview of numerous highly detailed steps involved in an example of actual manufacturing practice. For instance, rather than measuring alignment in a single pass, there will often be separate phases of rough and precise measurements using the same or different marks. The rough alignment measurement and / or precise alignment measurement steps may be performed before or after height measurement, or may be interleaved.

[0038] Lithography devices or scanners require regular maintenance tasks, for example, to replace hardware components that degrade over time. As a specific example, a scanner's wafer table degrades and requires periodic replacement. Such hardware replacement and / or maintenance tasks can affect performance.

[0039] The impact on these performance is conceptually illustrated in FIG. 3. Overlay is an important parameter that describes the proper placement of layers relative to the previously exposed (lower) layer. Each wafer table imposes a wafer clamping effect or clamping fingerprint on the substrate clamped to it, which must be compensated for. However, as the wafer table wears down over time, it affects the associated wafer clamping effect (typically becoming larger), which will affect the positioning of exposed structures on the substrate. Accordingly, degradation of the wafer table (and other components) will lead to positional errors, which can be divided into lower-frequency errors or correctable errors (CE) and higher-frequency errors or uncorrectable errors (NCE), correctable errors can be measured and corrected within the scanner (using appropriate metrology tools) through a process correction loop [such as known as advanced process correction or an APC loop, for example], and uncorrectable errors cannot be corrected through APC because the effect of the error cannot be measured using metrology that is sufficiently high speed, cannot be captured by the model used to represent the metrology data, and / or the necessary correction cannot be operated within the scanner.

[0040] In the absence of wafer table replacement, there is essentially no significant change between the exposures of different layers on a single wafer, as the wafer clamping effect changes sufficiently slowly. Since the overlay is a relative measure between two layers, the NCE caused by this effect in each layer is largely canceled out. Referring to FIG. 3(a), the lines for the first layer (L1) and the second layer (L2) represent the high-frequency components of the wafer grid effect of the degraded wafer table. Although this degradation causes relatively large disturbances in the local placement of features in each exposure layer, these disturbances are typically sufficiently similar in each layer and self-cancel out in the overlay (i.e., the positional error is the same in each layer, which means that the misalignment between layers due to this effect is relatively small). Therefore, the overlay NCE in each layer due to this wafer table fingerprint will be small. In contrast, FIG. 3(b) conceptually illustrates a situation where there is a wafer table replacement between the exposures of layers L1 and L2. Although the wafer grid impact caused by wafer table imperfections is reduced overall due to the new table, the influence of the old table remains in the Layer L1 exposure. Consequently, since these effects can no longer be offset, a significantly larger NCE overlay penalty occurs. This can cause jumps that cannot be corrected by APC due to differences in these fingerprints, and these jumps can be large enough to affect yield (uncorrectable errors mean that these wafers cannot be recovered through rework).

[0041] Such overlay penalties resulting from hardware maintenance during wafer processing (i.e., between exposure operations of different layers on the wafer) are often referred to as wafer-in-process (WIP) effects. One strategy to mitigate these WIP effects is to "ramp down" the exposure of multiple layers while preparing for such maintenance work, thereby reducing the number of wafers in progress at the time of operation (wafers with only a portion of the necessary layers exposed). This ramp-down typically involves suspending the exposure of one or more layers for several weeks leading up to the maintenance work, for example, by suspending exposure of each layer sequentially starting from the bottom layer, with intervals ranging from several days to two weeks or weeks between each sequential layer ramp-down. Not all layers may be ramped down. Such ramp-down of layers represents a loss of productivity relative to continuing wafer production at the rate prior to the ramp-down.

[0042] In addition to ramp-down effects, there will be ramp-up effects (i.e., compared to full production speed) accompanying the restart of production after maintenance work. For example, before production of higher layers within a stack can begin, it is necessary to restart production of each ramp-down layer.

[0043] Wafer table reconditioning / replacement will also cause abrupt changes in CE. While APC has the potential to compensate for these sudden changes, for at least the first few lots, the compensation is too slow because there is no (or insufficient) metrological data for the system after maintenance. To address this, the compensation loop or APC loop may be restarted and / or recalibrated, which takes time and thus causes production delays. As an alternative, production may continue without such recalibration, but this typically causes the exposure to fall out of specification. Consequently, many of the first wafers in progress exposed after maintenance will be exposed out of specification and will therefore require rework (removing poorly exposed resist, re-covering, and re-exposing).

[0044] The method for predicting the effect of potential substrate table maintenance work disclosed herein (e.g., predicting CE jumps) may be used to help determine one of these strategies (i.e., restarting / recalibrating the control loop or imposing a rework penalty if it is not done) and / or any alternative strategies (e.g., scheduling small pre-transfer lots for smart calibration so that the calibration can be tuned for known problems).

[0045] This combination of ramp-down and ramp-up times leads to the temporal effect of these ramp-down and ramp-up time intervals relative to when there is no ramp-up or ramp-down, often referred to as C-time. C-time is given in addition to A-time (nominal downtime for actual maintenance work) and B-time [(margin applied to A-time)].

[0046] Figure 4 is a plot of the cumulative number of lots (#lots) over time, representing the velocity for the production time interval (solid line) that includes ramp-down time, maintenance work, and ramp-up time. Time A+B represents the actual maintenance time interval including the margin, during which productivity is zero (machine downtime). The dotted line represents the nominal production velocity where production continues at a constant velocity until maintenance work without ramp-down or ramp-up time, and resumes immediately after the work is completed. Time C is the time difference between the two plots after the ramp-up is completed and production reaches approximately a constant velocity. It can be understood that Time C is typically much larger than Time A+Time B, and is even larger than exemplified in this plot.

[0047] Wafer Load Grid (WLG) is a wafer distortion described typically in terms of overlay distortion, related to the non-equilibrium of the substrate (wafer) during clamping and the finite coefficient of friction between the burles and the substrate. Burles are protrusions on the substrate support (wafer table) on which the substrate is supported. Complete loading of the substrate onto the substrate support means that once the substrate is fully placed on the multiple burles (and clamped thereon), no strain remains within the loaded substrate. Any strain locked within the substrate can deform the substrate in the XY plane and thereby cause overlay error. Local sliding of the substrate may occur when loading the substrate onto the substrate support. Residual deformation within the substrate resulting from this local sliding contributes to the overlay error. The WLG-derived error metric is a metric for quantifying the (correctable) error introduced by such deformation.

[0048] Wafer clamping may include a wafer loading sequence from the e-pin to a substrate holder or wafer table. This process may include the step of transporting the substrate on the e-pin downward to the substrate table, and when the substrate comes into contact with the substrate holder, the substrate is clamped to the substrate holder (e.g., electrostatically or by vacuum depending on the scanner type) so that stress is trapped within the substrate.

[0049] The physical properties of the wafer vary depending on the product and layer. WLG typically causes average wafer deformation, including a donut shape. This average wafer deformation is primarily correctable error (CE), which is partially corrected through alignment correction (e.g., higher-order alignment modeling). Residual CE after alignment correction is handled through process corrections, such as the aforementioned APC control loop. WLG also causes wafer-specific deformation that cannot be corrected by any correction mechanism; that is, this represents uncorrectable error (NCE). As the wafer table condition deteriorates over time, NCE increases until the resulting on-product overlay (OPO) error becomes too large, consequently affecting the yield.

[0050] To prevent yield loss, maintenance work to replace or recondition wafer tables may be performed periodically. As previously explained, replacing a wafer table has a resulting WIP impact because the process calibration will not match the reconditioned wafer table. The process calibration is reset and recalibrated, or the process calibration is automatically recovered. Resetting and recalibrating the process calibration leads to significant C-time (in days or weeks) and involves substantial human effort. Automatically recovering the process calibration causes initial lots to have OPO errors and typically requires rework until the OPO is within specifications.

[0051] The disclosed concept provides a method for predicting the magnitude of a jump in at least one parameter of interest caused by a maintenance operation, based on measurements taken prior to the maintenance operation (e.g., wafer table reconditioning / replacement). This provides information necessary to optimize the timing of the maintenance operation and to plan potential post-maintenance operations.

[0052] The parameter of interest may be an error metric induced by substrate loading distortion dependent on WLG (e.g., a WLG-induced error metric). For example, the WLG-induced error metric may be a CE component (e.g., an overlay) generated by WLG, but other WLG-dependent metrics are also possible.

[0053] In one embodiment, the method can predict two CE jump sizes. The first CE jump is the result of the current layer of the wafer (i.e., the target layer or the last exposed layer) being exposed on a reconditioned / replaced wafer table, but the zero layer of the wafer being exposed on the wafer table prior to maintenance (e.g., the zero layer and the current layer being exposed on substantially different wafer tables, i.e., a worn table and a good table). The second CE jump is the result of both the zero layer and the current layer being exposed again on a common wafer table, e.g., a reconditioned / replaced wafer table, and this jump is determined for the CE value resulting from the first jump. Accordingly, the first jump may be a jump in the first direction (e.g., a jump to a relatively large CE value due to a difference in the wafer table between the zero layer exposure and the current layer exposure), and the second jump may be a jump in the opposite direction (e.g., a jump to a typically very small CE value due to both the zero layer and current layer exposures being performed on a reconditioned and good-condition wafer table, e.g., smaller than the CE value prior to maintenance work). The jump may represent a sudden and relatively large change over a short period of time in the error metric or CE value induced by the measured substrate loading distortion, indicating a sudden change.

[0054] The method disclosed herein may be used to determine the impact of immediate maintenance work. In doing so, a model may be used to predict a WLG-induced error metric based on the WLG state (substrate loading distortion state) of the wafer at the time of exposure of the current layer (e.g., the layer just exposed on the wafer) of each wafer [or a group of wafers such as those held by a cassette or FOUP (Front Open Integrated Pod)] and the associated WLG sensitivity for this current layer, and the WLG state of each wafer (or group of wafers) at the time of exposure of the zero layer and the associated WLG sensitivity for this zero layer. The WLG sensitivity (or substrate loading distortion-induced error metric sensitivity) may describe the layer-by-layer sensitivity of the WLG-induced error metric to the WLG state.

[0055] FIG. 5 is a flowchart illustrating a method for determining the magnitude (e.g., jump) of any change in error metrics induced by substrate loading distortion or error metrics induced by WLG (e.g., overlay effects caused by WLG and, more specifically, correctable overlay effects), and error metrics induced by WLG caused by wafer table maintenance operations or substrate table maintenance operations, particularly wafer table replacement or reconditioning. In particular, the method may include a step of determining two jumps or abrupt changes caused by such substrate table maintenance operations.

[0056] The method can use input data (DATIN) containing the following:

[0057] Measured absolute WLG state data (or substrate loading distortion state data) (500) describing the absolute WLG state of the system (e.g., can be quantified by measuring the overlay difference between reference wafers that are sensitive and insensitive to WLG, respectively, or can be quantified through any other suitable method),

[0058] Layer timing (505), for example, the time / date when each layer (or at least zero layer and target layer or last exposed layer) is exposed per wafer or per group of wafers (for example, per FOUP),

[0059] Product-phase metrology data, or derived data (510) derived from product-phase metrology data. Such product-phase metrology data may include alignment data [e.g., fine wafer alignment measurement (FIWA) data] or correction data derived therefrom (e.g., per-exposure correction data). Alternatively, product-phase metrology data may include product-phase overlay data. Such product-phase metrology data enables monitoring of the product-phase size of a corrected typical WLG shape (before reconditioning, and / or for monitoring before and after reconditioning for sensitivity calibration purposes). Typical WLG shapes are known to include ring or donut shapes, and thus product-phase WLG contributions can be extracted or separated using a suitable WLG shape model (515).

[0060] Accordingly, using product-based metrology data (510) and a typical WLG shape model (515), error metric data (525) derived from WLG on the product [e.g., product-based WLG CE metric data describing the WLG contribution to the metrology data (510), or WLG CE component] can be obtained (520). The WLG contribution on the product can be separated from the product-based metrology data (510) using the WLG shape model (515). Better separation can be achieved by using alignment data or derived correction data, because it is more difficult to distinguish the WLG contribution on the product from other (process) effects compared to using product-based overlay data. The product-based metrology data (510) may be related only to the time range associated with the substrate table maintenance operation, for example, may include only jump data (regarding the first jump and the second jump). To do this, a data range during the time interval in which the maintenance operation was performed is required. However, the calibration step (S3) (described later) can also be performed using pre-maintenance work data. In this case, a more complex layer-to-layer model is applied. The advantage of this is that a prediction can be made before any maintenance work is performed on a specific layer.

[0061] The proposed prediction method (WLG PRED) uses input data (DATIN) to predict CE jumps based on the insight that, for example, there is propagation of WLG shapes within the resist during stack building, i.e., that CE is a layer-to-layer error. This depends not only on WLG degradation when clamping the wafer to expose the current layer, but also on WLG shapes within the resist already present on the wafer due to the exposure of previous layers.

[0062] In step S1, the absolute WLG state metric (500) is used to determine the WLG state metric data (530) for each date (e.g., WLG state drift curve).

[0063] In step S2, the WLG status at the time of exposure for each individual wafer or wafer group (e.g., per FOUP) is determined (535). This needs to be done for the target layer of the prediction (e.g., the current layer or the last exposed layer) and its zero layer (i.e., the first exposed layer), and this yields current layer WLG status data (540) and zero layer WLG status data (545) for each wafer / FOUP and date, respectively.

[0064] Information for both the target layer and the zero layer is used because the typical WLG fingerprint observed on a clamped wafer is the sum of the wafer deformation caused by clamping the wafer for the exposure of the target N-th layer, which depends on the WLG state of the wafer table during the exposure of the N-th layer, and the pattern in the resist on the wafer caused by the wafer deformation during the exposure of the zero layer. The reason for this is that the zero layer will be exposed without alignment correction (since there are no alignment marks to measure), and thus the WLG will be imprinted into the layer.

[0065] In step S3, WLG sensitivity (555) is calibrated for the target layer and the zero layer, respectively (550). The combination of wafer table roughness and wafer backside roughness determines the WLG effect. Since different layers within the stack will have different wafer backside characteristics, the sensitivity due to WLG may vary from layer to layer. In a simpler example, this sensitivity can be estimated from a previously calibrated layer having similar physical wafer (backside) characteristics.

[0066] In step S4, the calibrated sensitivity (555), the WLG status at the zero layer exposure point, and the current WLG status are input into the layer-to-layer model (560). For example, the model (560) may have the following form:

[0067] [Equation 1]

[0068] Here WLG CEcontent is the predicted CE component due to WLG in metrology data or process calibration, and S0, S N are the sensitivities of the zero layer and the target Nth layer, respectively, and WLG(t N ) , WLG(t 0 ) is the exposure time t of the target N-layer N and is the WLG state at exposure time t0 of the zero layer on the same wafer.

[0069] In step S5, the layer-to-layer model (560) can be used to predict (565) the ΔCE jump (570) if the wafer table needs to be replaced / reconditioned at this point. For the prediction of the CE jump after maintenance work, the future after maintenance work WLG(t 0 ) and WLG(t N )...must be predicted. In one example, this prediction assumes that the WLG component is zero for all time points (within the relevant time frame) after the maintenance operation (no WLG effect for a certain period after the maintenance operation). As previously mentioned, two jumps will be predicted. The first jump occurs because the target Nth layer is exposed after the maintenance operation, but the zero layer is still exposed before the maintenance operation. The second jump occurs because the zero layer is also exposed on a good wafer table (since all wafers previously exposed on an old wafer table have now been processed).

[0070] In one embodiment, step S5 involves, for all wafers with a zero layer exposed on an old wafer table, immediately before the maintenance operation WLG CEcontent cast As, and immediately after maintenance work WLG CEcontent cast It may include a step of determining as. Accordingly, the present approach assumes that WLG is 0 immediately after the maintenance work. First jump Δ WLG CEcontentjump1 can be defined as the difference between these values. That is,

[0071] [Equation 2]

[0072] 2nd Jump Δ WLG CEcontentjump2 As all wafers having a zero layer exposed on an old table now also have a target layer exposed thereon, this is applicable at the point when all subsequent wafers having an exposed target layer have their zero layer also exposed on a new table. Δ WLG CEcontentjump2 Is, Immediately after maintenance work defined as WLG CEcontent It is defined as the difference between and 0, that is,

[0073] [Equation 3]

[0074] The second term is assumed to be 0 because, now that both the zero layer and the Nth layer are exposed on a good table, WLG is assumed to be 0 for both layers.

[0075] In the implementation of this concept, t N It can be assumed that = t0, and accordingly, it can be understood that in the determination of each of the first jump and the second jump, for example, each can be made to represent "current" (for example, in the case where both the Nth layer and the zero layer are exposed immediately before the maintenance work for the determination of both jumps).

[0076] In other embodiments, the actual timing of the exposed layers may be used. For example, one embodiment may include using the actual timing of the zero layer exposure date prior to maintenance, instead of assuming that all zero layers of a wafer (WIP) during process were exposed at a single time point t0, for example, immediately before maintenance. This has the advantage of enabling the suppression of first and second jump effects by smarter scheduling of wafer batches so that not all wafer batches have the same ΔCE. Having batch-specific ΔCE predictions makes it possible to schedule batches so that the impact on APC is minimized. An additional advantage is that it provides the possibility to detect and quantify 'local jumps' after maintenance by scheduling wafers / FOUPs with different WLG characteristics (e.g., zero layers exposed before or after maintenance) in a mixed sequence.

[0077] Alternatively or additionally, the proposed method may include the actual timing of the current layer exposure date instead of assuming that the wafer (WIP) during all processes was exposed on a single "current" date. For example, if both the actual timing of the zero layer and the target layer are used, it is possible to predict / identify local jumps (e.g., abrupt changes in WIP metrics across substrate batches) caused by batch scheduling, which are unrelated to wafer table maintenance. This approach may utilize a combined model for the zero layer and the target layer. One application could be, for example, detecting wafers that are more likely to require rework due to poor correction caused by local jumps. Another advantage may involve fine-tuning the second jump prediction by incorporating WLG drift measurements after maintenance (assumed to be zero when predicting the second jump). This can also be used for smarter batch scheduling or to more accurately detect wafers that are more likely to require work.

[0078] Layer sensitivity can be calibrated (e.g., in step S3 above) using substrate loading distortion data (500) corresponding to a time interval including a jump after related maintenance work and error metric data (525) induced by substrate loading. For example, sensitivity can be determined by substituting these data into Equation 2 or Equation 3. Jump Δ WLG CEcontentjump1 or Δ WLG CEcontentjump2 It can be calculated by averaging the wafer groups before and after the jump to obtain the required accuracy. Alternatively, sensitivity can be calibrated using substrate loading distortion data (500) over a time range prior to maintenance operations and error metric data (525) induced by substrate loading. This allows the sensitivity of the active layer and zero layer to be calculated using Equation 1. It may be recognized that the substrate loading distortion data typically has a sigmoid shape over time. In practice, it may be necessary to process any offset (non-WLG) in the data. To this end, it may be helpful to have reference data that includes a time interval without WLG error.

[0079] FIG. 6 is a plot of WLG over time for a wafer or group / FOUP illustrating the aforementioned concept. At time t0, the zero layer is exposed and the shape WLGL0 is applied to the wafer. This shape continues to exist in subsequent layers as indicated by the dashed line, and accordingly, the total WLG for each subsequent layer is the sum of WLGL0 and the additional WLG effect of the subsequent layer(s). At a later time, at time t1, the first layer may be exposed on the zero layer. The additional WLG effect is applied in addition to the zero layer effect WLGL0. This additional WLG effect is mostly a correctable error and can therefore be resolved through alignment and APC correction (CORR1). Note that no correction is required because the WLGL0 component exists in both layers and largely cancels each other out (as described in relation to FIG. 3). At time tN, just before maintenance work is performed at time tMA, an additional (target) layer is exposed to impose an additional WLG effect in addition to the shape WLGL0, which explains the WLG correctable error, and the correction CORRN is determined for this.

[0080] At time t > MA, after the maintenance operation (MA), the Nth layer is exposed on a wafer having a zero layer exposed on an old wafer table on a new / refurbished wafer table (having a WLG of 0). The resulting correction (CORR'N) and the corresponding correctable error are determined based on the zero layer WLG imposed by the old wafer table to minimize overlay. This causes a first jump in the correctable error, the first jump having a magnitude corresponding to the difference in magnitude between the correction (CORRN) and the correction (CORR'N), respectively.

[0081] At a later time t>>MA, when both the zero layer and the target layer are exposed on a good table, a second jump will occur because WLG is now substantially 0 for both layers.

[0082] The above concepts are explained in relation to determining CE jumps. However, it can also be recognized that wafer-to-wafer NCE will cause jumps in NCE after maintenance operations. These NCE jumps can be predicted in a manner similar to CE jumps. Predicting NCE jumps may be relevant, for example, in determining the applicability of a WIP-less maintenance strategy. In the case of NCE jump prediction, the 'bottom layer' (i.e., the layer serving as the reference for alignment), rather than the zero layer, is relevant.

[0083] Various aspects of the present invention are described in the following sections.

[0084] 1. A method for predicting the effect of a potential substrate table maintenance operation related to a substrate table of a lithography apparatus, comprising: a step of obtaining per-layer substrate loading distortion state data related to distortion of a substrate or a group of substrates that occurs by loading a substrate onto the substrate table when exposing one or more layers; a step of obtaining at least one per-layer sensitivity value for each of one or more layers on the substrate, which describes the sensitivity of an error metric induced by substrate loading distortion to the per-layer substrate loading distortion state data; and a step of determining the effect of the potential substrate table maintenance operation on an error metric induced by substrate loading distortion based on the per-layer substrate loading distortion state data and the at least one per-layer sensitivity value.

[0085] 2. A method according to claim 1, wherein the layer-by-layer substrate loading distortion state data includes at least target layer substrate loading distortion state data corresponding to the exposure time of a target layer onto a substrate, and the at least one layer-by-layer sensitivity value includes at least one target layer sensitivity value describing the sensitivity of the target layer substrate loading distortion state data of an error metric induced by substrate loading distortion.

[0086] 3. A method according to claim 2, wherein, in the step of determining the effect of the potential substrate table maintenance operation, the target layer substrate loading distortion state data is assumed to be 0 for the at least one time point following the maintenance operation.

[0087] 4. A method according to claim 2 or 3, wherein the target layer comprises a layer last exposed on each substrate.

[0088] 5. A method comprising, in any one of claims 2 to 4, a step of determining the effect from a first product including at least the product of the target layer substrate loading distortion state data and the at least one target layer sensitivity value.

[0089] 6. A method according to any one of claims 2 to 5, wherein the layer-by-layer substrate loading distortion state data includes at least zero layer substrate loading distortion state data corresponding to the exposure time of a zero layer onto the substrate, wherein the zero layer is the first layer exposed onto the substrate, and the at least one layer-by-layer sensitivity value includes at least one zero layer sensitivity value describing the sensitivity of the error metric induced by substrate loading distortion to the zero layer substrate loading distortion state data.

[0090] 7. A method according to claim 6, wherein, in the step of determining the effect of the potential substrate table maintenance operation, the zero layer substrate loading distortion state data is assumed to be zero for substrates in which the zero layer is exposed when supported by the substrate table following the performance of the maintenance operation.

[0091] 8. A method according to claim 6 or 7, comprising the step of determining the effect from a second product including at least the product of the zero layer substrate loading distortion state data and the at least one zero layer sensitivity value.

[0092] 9. A method in combination of claims 5 and 8, wherein the method comprises the step of determining a layer-by-layer model for at least a target layer and a zero layer, wherein the layer-by-layer model describes an error metric induced by the substrate loading distortion in terms of a combination of a first product and a second product.

[0093] 10. In claim 9, the combination of the first product and the second product comprises the difference between the first product and the second product.

[0094] 11. A method according to claim 9 or 10, comprising the step of using the model to estimate an error metric induced by the substrate loading distortion at at least one point in time prior to the maintenance work and / or following the maintenance work.

[0095] 12. A method according to claim 11, comprising the step of assuming that the substrate loading distortion state is 0 for any layer exposed on the substrate table following the performance of the maintenance work.

[0096] 13. A method according to any one of claims 1 to 12, wherein the effect comprises at least a first jump in the error metric induced by the substrate loading distortion.

[0097] 14. A method according to any one of claims 1 to 13, wherein the effect comprises at least a first jump and a second jump in the error metric induced by the substrate loading distortion.

[0098] 15. A method according to any one of claims 1 to 14, comprising: acquiring substrate loading distortion state data over time related to distortion of a substrate or a group of substrates caused by loading a substrate onto a substrate table; acquiring timing data describing the exposure times of different layers onto the substrate or a group of substrates; and acquiring layer-specific substrate loading distortion state data by correlating the substrate loading distortion state data with the timing data.

[0099] 16. A method according to claim 15, comprising the step of assuming one exposure time for each layer exposure of each layer of a batch of substrates for each of one or more of the layers.

[0100] 17. A method according to claim 15, comprising the step of using actual timing data for each layer exposure across the substrate arrangement for each of one or more of the layers.

[0101] 18. A method according to any one of claims 1 to 17, wherein the effect of a potential substrate table maintenance operation on an error metric induced by substrate loading distortion may include one or more jumps in the error metric induced by substrate loading distortion related to on-product metrology data and / or a correctable error component of a correction derived therefrom.

[0102] 19. A method according to any one of claims 2 to 5, wherein the layer-by-layer substrate loading distortion state data includes at least alignment target layer substrate loading distortion state data corresponding to the exposure time of the aligned-to layer to which the target layer is aligned, and the at least one layer-by-layer sensitivity value includes at least one alignment target layer sensitivity value describing the sensitivity of the alignment target layer substrate loading distortion state data of the error metric induced by substrate loading distortion.

[0103] 20. A method according to claim 19, wherein the effect of a potential substrate table maintenance operation on an error metric induced by substrate loading distortion may include one or more jumps in the error metric induced by substrate loading distortion associated with product metrology data and / or uncorrectable error components of corrections derived therefrom.

[0104] 21. A method according to any one of claims 1 to 18, comprising the step of determining the at least one layer-by-layer sensitivity value from a correctable error component extracted from product metrology data and / or a correction derived therefrom.

[0105] 22. In claim 21, the method wherein the metrology data on the product and / or correction derived therefrom comprises alignment data and / or exposure-specific position correction derived therefrom.

[0106] 23. A method according to claim 21 or 22, wherein the correctable error component is extracted from the product metrology data and / or correction derived therefrom by applying a model having an expected shape for substrate loading distortion on the substrate.

[0107] 24. A method comprising the step of using each assumed value or predicted value for each of the at least one layer-by-layer sensitivity values ​​in any one of claims 1 to 17.

[0108] 25. A method according to any one of claims 1 to 24, comprising the step of scheduling maintenance work based on the determined effect of potential substrate table maintenance work.

[0109] 26. A method comprising the step of determining a post-maintenance strategy based on the determined effect of a potential substrate table maintenance operation in any one of claims 1 to 25.

[0110] 27. In claim 26, the strategy after potential maintenance work may include restarting and / or recalibrating the control loop, not restarting and / or recalibrating the control loop, or any alternative strategy.

[0111] 28. A computer program comprising program instructions operable to perform the method of any one of claims 1 through 27 when executed on a suitable device.

[0112] 29. A non-transient computer program carrier comprising the computer program of claim 28.

[0113] 30. A processing system comprising a processor and a storage device, comprising the computer program of claim 28.

[0114] 31. A lithography device comprising the processing system of claim 30.

[0115] Although specific embodiments of the present invention have been described above, it will be understood that the present invention may be practiced differently from as described.

[0116] Although specific uses of the embodiments of the present invention have been described above in relation to optical lithography, it will be understood that the present invention may be used in other applications, e.g., imprint lithography, and is not limited to optical lithography if permitted by the context. In imprint lithography, the topography in the patterning device defines a pattern created on a substrate. The topography of the patterning device may be pressed against a resist layer supplied to the substrate, and the resist is cured by applying electromagnetic radiation, heat, pressure, or a combination thereof. After the resist is cured, the patterning device is removed from the resist to leave a pattern therein.

[0117] The terms “radiation” and “beam” as used herein encompass all types of electromagnetic radiation, including particle beams such as ion beams or electron beams, as well as ultraviolet (UV) radiation (having wavelengths of, for example, 365, 355, 248, 193, 157, or 126 nm, or similar) and extreme ultraviolet (EUV) radiation (having wavelengths in the range of, for example, 1 to 100 nm).

[0118] Where contextually permissible, the term "lens" may refer to any one or a combination of various types of optical components, including refractive, reflective, magnetic, electromagnetic, and electrostatic optical components. In devices operating in the UV and / or EUV range, reflective components are likely to be used.

[0119] The scope and breadth of the present invention shall not be limited by any of the exemplary embodiments described above, but shall be defined only by the following claims and their equivalents.

Claims

Claim 1 A method for predicting the effect of a potential substrate table maintenance operation related to a substrate table of a lithography apparatus, comprising: acquiring per-layer substrate loading distortion state data related to distortion of a substrate or group of substrates that occurs by loading a substrate onto the substrate table when exposing one or more layers; acquiring at least one per-layer sensitivity value for each of one or more layers on the substrate, which describes the sensitivity of an error metric induced by substrate loading distortion to the substrate loading distortion state data; and determining the effect of the potential substrate table maintenance operation on the error metric induced by substrate loading distortion based on the per-layer substrate loading distortion state data and the at least one per-layer sensitivity value. Claim 2 A method according to claim 1, wherein the layer-by-layer substrate loading distortion state data includes at least a target layer substrate loading distortion state data corresponding to the exposure time of a target layer onto the substrate, and the at least one layer-by-layer sensitivity value includes at least one target layer sensitivity value describing the sensitivity of the error metric induced by the substrate loading distortion to the target layer substrate loading distortion state data. Claim 3 A method according to claim 2, wherein, in the step of determining the effect of the potential substrate table maintenance operation, the target layer substrate loading distortion state data is assumed to be 0 for the at least one time point following the maintenance operation. Claim 4 A method according to claim 2 or 3, wherein the target layer comprises a layer last exposed on each substrate. Claim 5 A method comprising, in any one of claims 2 to 4, a step of determining the effect from a first product including at least the product of the target layer substrate loading distortion state data and the at least one target layer sensitivity value. Claim 6 A method according to any one of claims 2 to 5, wherein the layer-by-layer substrate loading distortion state data includes at least zero layer substrate loading distortion state data corresponding to the exposure time of a zero layer onto the substrate—wherein the zero layer is the first layer exposed onto the substrate—and the at least one layer-by-layer sensitivity value includes at least one zero layer sensitivity value describing the sensitivity of the error metric induced by the substrate loading distortion to the zero layer substrate loading distortion state data. Claim 7 A method according to claim 6, wherein, in the step of determining the effect of the potential substrate table maintenance operation, the zero layer substrate loading distortion state data is assumed to be zero for substrates in which the zero layer is exposed when supported by the substrate table following the performance of the maintenance operation. Claim 8 A method according to claim 6 or 7, comprising the step of determining the effect from a second product including at least the product of the zero layer substrate loading distortion state data and the at least one zero layer sensitivity value. Claim 9 A method in combination of claims 5 and 8, wherein the method comprises the step of determining a layer-by-layer model for at least the target layer and the zero layer, wherein the layer-by-layer model describes an error metric induced by the substrate loading distortion in terms of a combination of the first product and the second product. Claim 10 A method according to any one of claims 1 to 9, wherein the effect comprises at least a first jump and a second jump in the error metric induced by the substrate loading distortion. Claim 11 A method according to any one of claims 1 to 10, comprising: acquiring substrate loading distortion state data over time related to distortion of a substrate or a group of substrates caused by loading a substrate onto a substrate table; acquiring timing data describing the exposure times of different layers onto the substrate or the group of substrates; and acquiring layer-specific substrate loading distortion state data by correlating the substrate loading distortion state data with the timing data. Claim 12 A method according to any one of claims 1 to 11, comprising the step of determining at least one layer-by-layer sensitivity value from a correctable error component extracted from on-product metrology data and / or a correction derived therefrom. Claim 13 A method according to claim 12, wherein the correctable error component is extracted from the product metrology data and / or correction derived therefrom by applying a model having an expected shape for substrate loading distortion on the substrate. Claim 14 A method comprising the step of scheduling a maintenance operation based on the determined effect of the potential substrate table maintenance operation in any one of claims 1 to 13. Claim 15 A method comprising the step of determining a post-maintenance strategy based on the determined effect of the potential substrate table maintenance operation in any one of claims 1 to 14. Claim 16 In claim 15, the strategy after potential maintenance work may include restarting and / or recalibrating the control loop, not restarting and / or recalibrating the control loop, or any alternative strategy. Claim 17 A computer program comprising program instructions operable to perform the method of any one of claims 1 through 16 when executed on a suitable device. Claim 18 A processing system comprising a processor and a storage device, comprising the computer program of claim 17. Claim 19 A lithography apparatus comprising a processing system of claim 18.

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