Semiconductor device and method of forming the e1me

Abstract

A semiconductor device according to the present invention comprises: a bit line extending in a first direction parallel to the upper surface of the substrate on a substrate; a semiconductor pattern extending in a direction perpendicular to the upper surface of the substrate on the bit line; a gate electrode extending in a second direction intersecting the first direction on a side of the semiconductor pattern; a storage node contact on the upper surface of the semiconductor pattern; an upper insulating film covering the side of the storage node contact; and a capping pattern between the upper insulating film and the gate electrode, wherein the upper insulating film is provided on the upper surface of the capping pattern, and the upper surface of the semiconductor pattern and the upper surface of the capping pattern each have a concave profile.

Description

Technology Field

[0001] The present invention relates to semiconductors, and more specifically, to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] Due to characteristics such as miniaturization, multifunctionality, and / or low manufacturing costs, semiconductor devices are gaining prominence as important elements in the electronics industry. Semiconductor devices can be classified into semiconductor memory devices that store logical data, semiconductor logic devices that process logical data, and hybrid semiconductor devices that include both memory and logic elements.

[0003] Recently, with the increasing speed and low power consumption of electronic devices, embedded semiconductor devices are also required to have fast operating speeds and / or low operating voltages. To meet these requirements, semiconductor devices are becoming more highly integrated. Consequently, much research is being conducted to improve the integration density of semiconductor devices. The problem to be solved

[0004] The technical problem that the present invention aims to solve is to provide a semiconductor device with improved productivity and a method for manufacturing the same.

[0005] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. means of solving the problem

[0006] A semiconductor device according to the present invention comprises: a bit line extending in a first direction parallel to the upper surface of the substrate on a substrate; a semiconductor pattern extending in a direction perpendicular to the upper surface of the substrate on the bit line; a gate electrode extending in a second direction intersecting the first direction on a side of the semiconductor pattern; a storage node contact on the upper surface of the semiconductor pattern; an upper insulating film covering the side of the storage node contact; and a capping pattern between the upper insulating film and the gate electrode, wherein the upper insulating film is provided on the upper surface of the capping pattern, and the upper surface of the semiconductor pattern and the upper surface of the capping pattern may each have a concave profile.

[0007] A semiconductor device according to the present invention comprises: a bit line extending in a first direction parallel to the upper surface of the substrate on a substrate; a semiconductor pattern extending in a direction perpendicular to the upper surface of the substrate on the bit line; a gate electrode extending in a second direction intersecting the first direction on a side of the semiconductor pattern; a storage node contact on the upper surface of the semiconductor pattern; an upper insulating film covering the side of the storage node contact; and a capping pattern between the upper insulating film and the gate electrode, wherein the upper insulating film is provided on the upper surface of the capping pattern, the storage node contact includes a first region and a second region between the first region and the semiconductor pattern, the upper surface of the capping pattern may have a concave profile, and the lower surface of the second region of the storage node contact may have a convex profile.

[0008] A semiconductor device according to the present invention comprises: a bit line extending in a first direction parallel to the upper surface of the substrate on a substrate; a semiconductor pattern extending in a direction perpendicular to the upper surface of the substrate on the bit line; a gate electrode extending in a second direction intersecting the first direction on a side of the semiconductor pattern; a back gate electrode extending in the second direction, spaced apart from the gate electrode in the first direction with the semiconductor pattern in between; a storage node contact on the upper surface of the semiconductor pattern; a landing pad on the storage node contact; a data storage pattern on the landing pad; an upper insulating film covering the side of the storage node contact; and a capping pattern between the upper insulating film and the gate electrode, wherein the upper insulating film is provided on the upper surface of the capping pattern, and the upper surface of the semiconductor pattern and the upper surface of the capping pattern may each have a concave profile.

[0009] A method for manufacturing a semiconductor device according to the present invention may include: forming a semiconductor pattern extending in a direction perpendicular to the first substrate on a first substrate; forming a gate insulation pattern and a gate electrode in sequence on the side of the semiconductor pattern; forming a capping pattern on the gate electrode; forming a first recess by removing the upper portion of the semiconductor pattern to expose the side of the gate insulation pattern; forming a second recess by removing a portion of the gate insulation pattern exposed by the first recess; forming a storage node contact within the second recess; forming a third recess by removing a portion of the capping pattern to expose the side of the storage node contact; and forming an upper insulating film within the third recess.

[0010] A method for manufacturing a semiconductor device according to the present invention may further include removing the upper portion of the storage node contact; and forming a landing pad within the area where the upper portion of the storage node contact has been removed.

[0011] After the process of removing the upper portion of the storage node contact, the upper surface of the storage node contact may have a concave profile.

[0012] With respect to the first direction above, the width of the second recess may be larger than the width of the first recess.

[0013] After the process of forming the first recess, the upper surface of the semiconductor pattern may have a concave profile.

[0014] After the process of forming the third recess, the upper surface of the capping pattern may have a concave profile.

[0015] The upper insulating film may include an insulating material different from the capping pattern.

[0016] The upper side of the semiconductor pattern can be exposed by the second recess.

[0017] A first surface of the semiconductor pattern may be exposed by the first recess, and a method for manufacturing a semiconductor device according to the present invention may further include flipping the first substrate and removing the first substrate to expose a second surface of the semiconductor pattern opposite to the first surface of the semiconductor pattern; and forming a bit line on the second surface of the semiconductor pattern.

[0018] The method for manufacturing a semiconductor device according to the present invention may further include forming a back gate electrode spaced apart from the gate electrode with the semiconductor pattern in between. Effects of the invention

[0019] According to the concept of the present invention, a storage node contact can be formed through an intaglio process that fills the area where the upper part of the semiconductor pattern has been removed. Accordingly, the storage node contact can be self-aligned with the semiconductor pattern. As a result, misalignment between the storage node contact and the semiconductor pattern that may occur when forming the storage node contact through a relief process can be prevented. Consequently, manufacturing defects of the semiconductor device can be reduced. Therefore, the productivity of the semiconductor device manufacturing method can be improved.

[0020] In addition, by forming storage node contacts through an intaglio process, mask patterns required when forming storage node contacts through a relief process are not used or can be utilized in formation processes of other configurations. As a result, the productivity of the semiconductor device manufacturing method can be improved.

[0021] According to the concept of the present invention, insulating patterns comprising an oxide-based insulating material interposed between storage node contacts can be replaced by an upper insulating film comprising a nitride-based insulating material. Accordingly, during a cleaning process on the upper surface of a storage node contact for forming a barrier pattern, the cleaning solution can be prevented from penetrating under the upper insulating film. As a result, process defects caused by the cleaning solution can be prevented, and the productivity of the semiconductor device manufacturing method can be improved.

[0022] According to the concept of the present invention, a landing pad can be formed through an intaglio process that fills the area where the upper portion of the storage node contact has been removed. The height of the landing pad may vary depending on the extent to which the storage node contact is removed. Accordingly, adjusting the height of the landing pad may be easier than forming the landing pad through a relief process. Brief explanation of the drawing

[0023] FIG. 1 is a block diagram showing a semiconductor device according to some embodiments of the present invention. FIGS. 2 and FIGS. 3 are perspective views briefly illustrating a semiconductor device according to some embodiments of the present invention. FIG. 4 is a plan view of a semiconductor device according to some embodiments of the present invention. Figure 5 is a cross-sectional view corresponding to line AA' in Figure 4. Figures 6 and 7 are enlarged views corresponding to P1 in Figure 5, respectively. Figure 8 is a cross-sectional view corresponding to line AA' in Figure 4. Figure 9 is an enlarged view corresponding to P2 in Figure 8. FIG. 10 is a plan view of a semiconductor device according to some embodiments of the present invention. FIGS. 11 to 17 are drawings illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. FIG. 18 is a drawing illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. Specific details for implementing the invention

[0024] Hereinafter, in order to explain the present invention more specifically, embodiments according to the present invention will be described in more detail with reference to the accompanying drawings.

[0025] FIG. 1 is a block diagram showing a semiconductor device according to some embodiments of the present invention.

[0026] Referring to FIG. 1, the semiconductor device may include a memory cell array (1), a row decoder (2), a sense amplifier (3), a column decoder (4), and control logic (5).

[0027] A memory cell array (1) may include a plurality of memory cells (MC) arranged in two dimensions or three dimensions. Each of the memory cells (MC) may be connected between a word line (WL) and a bit line (BL) that intersect each other. Each memory cell (MC) may include a selection element (TR) and a data storage element (DS). The selection element (TR) and the data storage element (DS) may be electrically connected to each other. The selection element (TR) may be connected to both the word line (WL) and the bit line (BL). In other words, the selection element (TR) may be provided at the point where the word line (WL) and the bit line (BL) intersect each other.

[0028] The selection element (TR) may include a field-effect transistor. The data storage element (DS) may include a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the gate terminal of the transistor that is the selection element (TR) may be connected to the word line (WL), and the source / drain terminals of the transistor may be connected to the bit line (BL) and the data storage element (DS), respectively.

[0029] The row decoder (2) can decode an externally input address and select one of the word lines (WL) of the memory cell array (1). The address decoded by the row decoder (2) can be provided to a row driver (not shown), and the row driver can provide a predetermined voltage to the selected word line (WL) and the unselected word lines (WL), respectively, in response to the control of the control circuits.

[0030] The sense amplifier (3) can detect and amplify the voltage difference between the selected bit line (BL) and the reference bit line according to the address decoded from the column decoder (4) and output it.

[0031] The column decoder (4) can provide a data transmission path between the sense amplifier (3) and an external component (e.g., a memory controller). The column decoder (4) can decode an externally input address and select one of the bit lines (BL). The control logic (5) can generate a control signal that controls the operation of writing or reading data to the memory cell array (1).

[0032] FIGS. 2 and FIGS. 3 are perspective views briefly illustrating a semiconductor device according to some embodiments of the present invention.

[0033] Referring to FIGS. 2 and 3, the semiconductor device may include a peripheral circuit structure (PS) on a substrate (100) and a cell array structure (CS) connected to the peripheral circuit structure (PS). The substrate (100) may have a plate shape extending along a plane defined by a first direction (D1) and a second direction (D2). The first direction (D1) and the second direction (D2) may each be parallel to the upper surface of the substrate (100) and may intersect each other. A third direction (D3) may be perpendicular to the upper surface of the substrate (100) and may intersect the first direction (D1) and the second direction (D2).

[0034] The peripheral circuit structure (PS) may include core and peripheral circuits formed on the substrate (100). The core and peripheral circuits may include row and column decoders (2, 4), sense amplifiers (3), and control logics (5) described with reference to FIG. 1.

[0035] A cell array structure (CS) may include a memory cell array (1 of FIG. 1) comprising memory cells (MC of FIG. 1) arranged in two or three dimensions. For example, a selection element (TR of FIG. 1) for each of the memory cells (MC of FIG. 1) may include a vertical channel transistor (VCT). The vertical channel transistor may include a channel whose lengthwise direction is a third direction (D3).

[0036] Referring to FIG. 2, a peripheral circuit structure (PS) may be provided on a substrate (100). A cell array structure (CS) may be provided on the peripheral circuit structure (PS). Although not shown in the drawing, the peripheral circuit structure (PS) may be connected to the cell array structure (CS) through a separate contact.

[0037] Referring to FIG. 3, the semiconductor device may have a C2C (chip-to-chip) structure. A peripheral circuit structure (PS) may be provided on a substrate (100). First metal pads (LMP) may be provided on the upper portion of the peripheral circuit structure (PS). The first metal pads (LMP) may be electrically connected to the core and peripheral circuits. The first metal pads (LMP) within the peripheral circuit structure (PS) may be bonded to the second metal pads (UMP) of the cell array structure (CS) described later. Accordingly, the peripheral circuit structure (PS) and the cell array structure (CS) may be bonded.

[0038] A cell array structure (CS) may be provided on a carrier substrate (200). Second metal pads (UMP) may be provided on the lower part of the cell array structure (CS). The second metal pads (UMP) may be electrically connected to a memory cell array (1 in FIG. 1).

[0040] FIG. 4 is a plan view of a semiconductor device according to some embodiments of the present invention. FIG. 5 is a cross-sectional view corresponding to line AA' of FIG. 4. FIG. 6 and FIG. 7 are enlarged views corresponding to P1 of FIG. 5, respectively.

[0041] First, referring to FIGS. 4 and FIGS. 5, FIGS. 4 and FIGS. 5 are a plan view and a cross-sectional view of the configurations within the cell array structure (CS) described with reference to FIGS. 2 and FIGS. 3, respectively.

[0042] A semiconductor device may include a lower insulating layer (LIL). The lower insulating layer (LIL) may include an insulating material. For example, the lower insulating layer (LIL) may be provided below a cell array structure (CS) described with reference to FIG. 2. In this case, the lower insulating layer (LIL) may be adjacent to and in contact with a peripheral circuit structure (PS) described with reference to FIG. 2. Additionally, the peripheral circuit structure (PS) described with reference to FIG. 2 may be interposed between the substrate (100) described with reference to FIG. 2 and the lower insulating layer (LIL). Furthermore, the lower insulating layer (LIL) may include wirings connected to the core and peripheral circuits of the peripheral circuit structure (PS) described with reference to FIG. 2.

[0043] As another example, the cell array structure of the semiconductor device (CS of FIG. 2) may be flipped so that the lower insulating film (LIL) is provided on the upper part of the cell array structure (CS) described with reference to FIG. 3. In this case, the lower insulating film (LIL) may be adjacent to and in contact with the carrier substrate (200) described with reference to FIG. 3. The drawings show a plan view and a cross-sectional view of the cell array structure of the semiconductor device (CS of FIG. 2) in a non-flipped state, and the semiconductor device is described with reference thereto, but is not limited thereto.

[0044] A bit line (BL) may be provided within a lower insulating layer (LIL). The bit line (BL) may extend along a first direction (D1) within the lower insulating layer (LIL). The bit line (BL) may include a conductive material. For example, the bit line (BL) may include at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a metal material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.), a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). The bit line (BL) may be a single film or a composite film. The bit line (BL) may be provided in multiple numbers. The bit lines (BL) may be spaced apart from each other along a second direction (D2).

[0045] A bitline contact (DC) may be provided within the lower insulating layer (LIL). A bitline contact (DC) may be provided on a bitline (BL). The bitline contact (DC) may be interposed between the lower surface (E2) of the semiconductor pattern (SP) described later and the bitline (BL). Accordingly, the bitline (BL) may be connected to the semiconductor pattern (SP) through the bitline contact (DC). The bitline contact (DC) may include a conductive material. For example, the bitline contact (DC) may include doped silicon. Multiple bitline contacts (DC) may be provided. The bitline contacts (DC) may be spaced apart from each other along a first direction (D1) on a single bitline (BL).

[0046] A semiconductor pattern (SP) may be provided on a bit line (BL). For example, the semiconductor pattern (SP) may be provided on the upper surface of a bit line contact (DC). The semiconductor pattern (SP) may extend along a third direction (D3) on the bit line (BL). Multiple semiconductor patterns (SP) may be provided. Semiconductor patterns (SP) may be spaced apart from each other along a first direction (D1) on a single bit line (BL). Semiconductor patterns (SP) may be spaced apart from each other along a second direction (D2).

[0047] The semiconductor pattern (SP) may include a semiconductor material. For example, the semiconductor pattern (SP) may include at least one of silicon (e.g., single-crystal silicon), germanium, and silicon-germanium. For example, the semiconductor pattern (SP) may include an oxide semiconductor. In this case, the oxide semiconductor may include at least one of InGaZnO, InGaSiO, InSnZnO, InZnO, ZnO, ZnSnO, ZnON, ZrZnSnO, SnO, HfInZnO, GaZnSnO, AlZnSnO, YbGaZnO, and InGaO, but is not limited thereto. For example, the semiconductor pattern (SP) may include IGZO (Indium Gallium Zinc Oxide). For example, the semiconductor pattern (SP) may include a two-dimensional semiconductor material. In this case, the two-dimensional semiconductor material may include graphene, carbon nanotubes, or a combination thereof.

[0048] A word line (WL) may be provided on the side of a semiconductor pattern (SP). The word line (WL) may be interposed between semiconductor patterns (SP) adjacent to each other in a first direction (D1). The word line (WL) may be extended along a second direction (D2). Multiple word lines (WL) may be provided. The word lines (WL) may be spaced apart from each other along the first direction (D1). For example, a pair of word lines (WL) adjacent to each other in the first direction (D1) may be interposed between semiconductor patterns (SP) adjacent to each other in the first direction (D1). For example, a pair of word lines (WL) adjacent to each other in the first direction (D1) may be spaced apart from each other with a cutting pattern (CT) described later in between.

[0049] The word line (WL) may include a gate electrode (GE) extending along a second direction (D2) and a third direction (D3), and a gate insulation pattern (GI) between the semiconductor pattern (SP) and the gate electrode (GE). The gate electrode (GE) may include a conductive material. For example, the gate electrode (GE) may include a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the gate insulation pattern (GI) may include at least one of silicon oxide and a high dielectric material. In this specification, a high dielectric material is defined as a material having a dielectric constant higher than the dielectric constant of silicon oxide.

[0050] A first gate capping pattern (GC1) may be provided on the upper surface of a gate electrode (GE). The first gate capping pattern (GC1) may be interposed between the gate electrode (GE) and the upper insulating film (UIL) described later. A portion of the side of the first gate capping pattern (GC1) may be covered by a gate insulating pattern (GI). The first gate capping pattern (GC1) may include an insulating material. For example, the first gate capping pattern (GC1) may include silicon oxide.

[0051] The first gate capping pattern (GC1) may be interposed between gate electrodes (GE) adjacent to each other in the first direction (D1) and may be spaced apart. The first gate capping pattern (GC1) may be extended along the third direction (D3).

[0052] A second gate capping pattern (GC2) may be interposed between the gate electrode (GE) and the lower insulating film (LIL). The second gate capping pattern (GC2) may include an insulating material. For example, the second gate capping pattern (GC2) may include silicon oxide.

[0053] A back gate structure (BGS) may be provided on the side of a semiconductor pattern (SP). The back gate structure (BGS) may be interposed between semiconductor patterns (SP) that are adjacent to each other in a first direction (D1). The back gate structure (BGS) and the word line (WL) may be spaced apart in the first direction (D1) with the semiconductor pattern (SP) in between. The back gate structure (BGS) may extend along a second direction (D2) between semiconductor patterns (SP) that are adjacent to each other in the first direction (D1). Multiple back gate structures (BGS) may be provided. The back gate structures (BGS) may be spaced apart from each other along the first direction (D1).

[0054] By providing a back gate structure (BGS), the threshold voltage of a transistor including a semiconductor pattern (SP) can be controlled by a voltage applied to the back gate structure (BGS). Accordingly, controlling the threshold voltage through the back gate structure (BGS) may be easier than controlling the threshold voltage by injecting impurities into the semiconductor pattern (SP). By controlling the threshold voltage through the back gate structure (BGS), unnecessary turning on of the transistor can be prevented.

[0055] The back gate structure (BGS) may include a back gate electrode (BGE) and a back gate insulating pattern (BGI) covering the side of the back gate electrode (BGE). The back gate electrode (BGE) may be spaced apart from the gate electrode (GE) in a first direction (D1) with a semiconductor pattern (SP) in between. For example, the back gate electrode (BGE) may include a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). For example, the back gate insulating pattern (BGI) may include at least one of silicon oxide and a high dielectric material.

[0056] A first back gate capping pattern (BGC1) may be provided on the upper surface of the back gate electrode (BGE). The first back gate capping pattern (BGC1) may be interposed between the back gate electrode (BGE) and the upper insulating film (UIL) described later.

[0057] A second back gate capping pattern (BGC2) may be interposed between the back gate electrode (BGE) and the lower insulating film (LIL). Each of the first back gate capping pattern (BGC1) and the second back gate capping pattern (BGC2) may include an insulating material. For example, each of the first back gate capping pattern (BGC1) and the second back gate capping pattern (BGC2) may include silicon oxide.

[0058] A storage node contact (BC) may be provided on a semiconductor pattern (SP). The storage node contact (BC) may be provided on an upper surface (E1) of the semiconductor pattern (SP). The storage node contact (BC) may include a conductive material. For example, the storage node contact (BC) may include doped silicon. Multiple storage node contacts (BC) may be provided. The storage node contacts (BC) may be spaced apart from each other in a first direction (D1) and a second direction (D2).

[0059] Due to the process of forming the storage node contact (BC) through the engraving process described below, the shape of the storage node contact (BC) can follow the shape of the semiconductor pattern (SP) from a planar perspective. As illustrated in the drawing, the semiconductor pattern (SP) has a rectangular shape from a planar perspective, but is not limited thereto.

[0060] A landing pad (LP) may be provided on a storage node contact (BC). The landing pad (LP) may be connected to a semiconductor pattern (SP) through the storage node contact (BC). The landing pad (LP) may include a conductive material. For example, the landing pad (LP) may include at least one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.) and a metallic material (e.g., Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.). A plurality of landing pads (LP) may be provided. The landing pads (LP) may be spaced apart from each other in a first direction (D1) and a second direction (D2).

[0061] Storage node contacts (BC) and landing pads (LP) can together form a connection structure (CNS).

[0062] Although not shown in the drawing, a barrier pattern (not shown) may be interposed between the storage node contact (BC) and the landing pad (LP). As an example, the barrier pattern may include at least one of a metal silicide (e.g., a silicide of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.) and a metal nitride (e.g., a nitride of Ti, Mo, W, Cu, Al, Ta, Ru, Ir, Co, etc.).

[0063] An upper insulating layer (UIL) may be provided on each side of the storage node contact (BC) and the landing pad (LP). The upper insulating layer (UIL) may cover each side of the storage node contact (BC) and the landing pad (LP). The upper insulating layer (UIL) may surround each side of the storage node contact (BC) and the landing pad (LP). The upper insulating layer (UIL) may separate multiple storage node contacts (BC) from each other. The upper insulating layer (UIL) may separate multiple landing pads (LP) from each other.

[0064] The upper insulating layer (UIL) may include an insulating material. For example, the upper insulating layer (UIL) may include an insulating material different from the first gate capping pattern (GC1) and the first back gate capping pattern (BGC1), respectively. For example, the upper insulating layer (UIL) may include an insulating material having a higher dielectric constant than the first gate capping pattern (GC1) and the first back gate capping pattern (BGC1), respectively. For example, the upper insulating layer (UIL) may include SiN.

[0065] A data storage pattern (DSP) may be provided on a landing pad (LP). The data storage pattern (DSP) may be connected to a semiconductor pattern (SP) through the landing pad (LP) and a storage node contact (BC). Multiple data storage patterns (DSP) may be provided. The data storage patterns (DSP) may be spaced apart from each other in a first direction (D1) and a second direction (D2). The data storage pattern (DSP) may correspond to a data storage element (DS) described with reference to FIGS. 1 to 3.

[0066] The data storage pattern (DSP) may, for example, be a capacitor comprising a lower electrode, a dielectric film, and an upper electrode. In this case, the semiconductor device according to the present invention may be a dynamic random access memory (DRAM). The data storage pattern (DSP) may, for another example, include a magnetic tunnel junction pattern. In this case, the semiconductor device according to the present invention may be a magnetic random access memory (MRAM). The data storage pattern (DSP) may, for yet another example, include a phase change material or a variable resistance material. In this case, the semiconductor device according to the present invention may be a phase-change random access memory (PRAM) or a resistive random access memory (ReRAM). However, this is merely illustrative and the present invention is not limited thereto, and the data storage pattern (DSP) may include various structures and / or materials capable of storing data.

[0067] Referring to FIG. 6, various features of the configurations described below can be formed by the engraving process of the storage node contact (BC) described later. These features are explained in detail below.

[0068] The upper surface (E1) of the semiconductor pattern (SP) may have a concave profile. Specifically, the upper surface (E1) of the semiconductor pattern (SP) may have a concave profile into the interior of the semiconductor pattern (SP).

[0069] A storage node contact (BC) may include a first region (R1) and a second region (R2) between the first region (R1) and the semiconductor pattern (SP). The first region (R1) and the second region (R2) may be separated at a first level (LV1). The first level (LV1) may be defined at the level of the top surface of the semiconductor pattern (SP). The first region (R1) may be located at a vertical level higher than the first level (LV1), and the second region (R2) may be located at a vertical level lower than the first level (LV1).

[0070] The second region (R2) of the storage node contact (BC) can be inserted into the semiconductor pattern (SP). Accordingly, the upper surface (E1) of the semiconductor pattern (SP) has a concave profile, so that the lower surface (B2b) of the second region (R2) can have a convex profile. The lower surface of the second region (R2) can be located at a vertical level lower than the first level (LV1). For example, the lower surface (B2b) of the second region (R2) can be located at a vertical level lower than the upper surface (GIa) of the gate insulation pattern (GI) and the upper surface (BGIa) of the back gate insulation pattern (BGI).

[0071] A portion of the semiconductor pattern (SP) may be interposed between the second region (R2) of the storage node contact (BC) and the gate insulation pattern (GI), and between the second region (R2) and the back gate insulation pattern (BGI). For example, the gate insulation pattern (GI) and the back gate insulation pattern (BGI) may each be in contact with the lower surface (B1b) of the first region (R1) of the storage node contact (BC).

[0072] At the first level (LV1), with respect to the first direction (D1), the first region (R1) of the storage node contact (BC) may have a first width (W1), and the second region (R2) of the storage node contact (BC) may have a second width (W2). With respect to the first direction (D1), the semiconductor pattern (SP) may have a third width (W3). The first width (W1) may be larger than the second and third widths (W2, W3). For example, the second width (W2) may be substantially the same as the third width (W3).

[0073] The upper insulating film (UIL) may be provided on the upper surface (GCa) of the first gate capping pattern (GC1) and the upper surface of the first back gate capping pattern (BGC1). Each of the upper surface (GCa) of the first gate capping pattern (GC1) and the upper surface of the first back gate capping pattern (BGC1) may have a concave profile. Accordingly, the lower surface (Ub) of the upper insulating film (UIL) may have a convex profile. The upper surface (Ua) of the upper insulating film (UIL) may be co-plane with the upper surface (La) of the landing pad (LP).

[0074] Referring to FIG. 7, unlike the shape of the first region (R1) of the storage node contact (BC) of FIG. 6, the upper surface (B1a) of the first region (R1) of the storage node contact (BC) may have a concave profile. Specifically, the upper surface (B1a) of the first region (R1) may be concave into the first region (R1). Accordingly, the lower surface (Lb) of the landing pad (LP) may have a convex profile.

[0075] Hereinafter, with reference to FIGS. 8 and FIGS. 9, a semiconductor device according to some embodiments of the present invention will be described. For the sake of simplicity, descriptions of content that overlap with the foregoing will be omitted, and the differences from the foregoing content will be described in detail.

[0076] FIG. 8 is a cross-sectional view corresponding to line AA' in FIG. 4. FIG. 9 is an enlarged view corresponding to P2 in FIG. 8.

[0077] Referring to FIGS. 4, 8, and 9, the upper surface (GIa) of the gate insulation pattern (GI) and the upper surface (BGIa) of the back gate insulation pattern (BGI) can each be located at a vertical level lower than the first level (LV1). Accordingly, the lower surface (B1b) of the first region (R1) of the storage node contact (BC) can be located at a vertical level lower than the first level (LV1). Additionally, a portion of the first region (R1) of the storage node contact (BC) can cover the upper side (Ss) of the semiconductor pattern (SP). As a result, the contact area between the storage node contact (BC) and the semiconductor pattern (SP) can be expanded. Thus, the electrical characteristics of the semiconductor device can be improved.

[0078] A portion of the semiconductor pattern (SP) may be interposed between the portion of the first region (R1) of the storage node contact (BC) and the second region (R2) of the storage node contact (BC).

[0079] FIG. 10 is a plan view of a semiconductor device according to some embodiments of the present invention.

[0080] Referring to FIG. 10, due to the formation process of the storage node contact (BC) through the engraving process described later, the shape of the storage node contact (BC) can follow the shape of the semiconductor pattern (SP) in a planar view. As illustrated in the drawing, the semiconductor pattern (SP) can have a semi-elliptical shape in a planar view. Accordingly, the storage node contact (BC) can also have a semi-elliptical shape.

[0081] Due to the formation process of the landing pad (LP) through the engraving process described below, the shape of the landing pad (LP) can follow the shape of the storage node contact (BC) from a planar perspective. As illustrated in the drawing, the landing pad (LP) can have a semi-elliptical shape from a planar perspective.

[0082] Hereinafter, with reference to FIGS. 11 to 18, a method for manufacturing a semiconductor device according to some embodiments of the present invention will be described. For the sake of simplicity, descriptions of content that overlap with the foregoing will be omitted, and the differences from the foregoing content will be explained in detail.

[0083] FIGS. 11 to 17 are drawings illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. More specifically, FIGS. 11, 14, and 16 are cross-sectional views of a semiconductor device according to some embodiments of the present invention. FIGS. 12, 13, 15, and 17 are cross-sectional views corresponding to the line AA' in FIGS. 11, FIGS. 14, and FIGS. 16, respectively.

[0084] Referring to FIGS. 11 and 12, a first substrate (110) may be prepared. A dummy insulating film (120) and a second substrate (not shown) may be formed sequentially on the first substrate (110). For example, the first substrate (110) and the second substrate may include a semiconductor material. The dummy insulating film (120) may include an insulating material.

[0085] Subsequently, a first patterning process can be performed on the dummy insulating film (120) and the second substrate, and accordingly, a first trench can be formed. A first patterning process can be performed on the second substrate, and accordingly, a second trench can be formed. A back gate structure (BGS) and a first back gate capping pattern (BGC1) can be formed within the first trench. A word line (WL) and a first gate capping pattern (GC1) can be formed within the second trench.

[0086] Through the first and second patterning processes, the second substrate can be separated into semiconductor patterns (SP) that are extended in the second direction (D2) and the third direction (D3), respectively, and spaced apart from each other in the first direction (D1). Additionally, a third patterning process can be performed on the semiconductor patterns (SP), and accordingly, the semiconductor patterns (SP) can be separated into semiconductor patterns (SP) that are spaced apart from each other in the second direction (D2).

[0087] Subsequently, a removal process can be performed on the upper surface of each of the semiconductor patterns (SP). Accordingly, first recesses (RS1) can be formed on the upper surface (E1) of each of the semiconductor patterns (SP). The first recesses (RS1) can be vertically superimposed with the semiconductor pattern (SP). By the first recesses (RS1), the side of the gate insulation pattern (GI) and the side of the back gate insulation pattern (BGI) can each be exposed. By the first recesses (RS1), the upper surface (E1) of each of the semiconductor patterns (SP) can be exposed and may have a concave profile.

[0088] Referring to FIGS. 11 and 13, a second recess (RS2) can be formed by removing a portion of each of the gate insulation pattern (GI) and back gate insulation pattern (BGI) exposed by the first recess (RS1). Accordingly, with respect to the first direction (D1), the width (W5) of the second recess (RS2) can be larger than the width (W4) of the first recess (RS1). In other words, the width of the recess can be widened through a removal process on the inner wall of the first recess (RS1). For example, the width (W4) of the first recess (RS1) can be substantially the same as the third width (W3) described with reference to FIG. 6.

[0089] Referring to FIGS. 14 and 15, storage node contacts (BC) may be formed within a second recess (RS2). For example, forming the storage node contacts (BC) may include forming the storage node contacts (BC) through an intaglio process. For example, forming the storage node contacts (BC) may include forming a storage node contact film (not shown) that fills the interior of the second recess (RS2) and covers the upper surface of each of the first gate capping pattern (GC1) and the first back gate capping pattern (BGC1), and removing the upper portion of the storage node contact film to separate it into storage node contacts (BC).

[0090] According to the concept of the present invention, storage node contacts (BC) can be formed through an intaglio process. Specifically, a first recess (RS1) can be formed through a removal process on the upper surface of a semiconductor pattern (SP), and subsequently, a second recess (RS2) can be formed through a removal process on the inner wall of the first recess (RS1). As the second recess (RS2) overlaps with the semiconductor pattern (SP), the storage node contact (BC) filling the second recess (RS2) can be self-aligned with the semiconductor pattern (SP). Accordingly, a misalignment between the storage node contact (BC) and the semiconductor pattern (SP) that may occur when forming the storage node contact (BC) through an embossing process can be prevented. As a result, manufacturing process defects of the semiconductor device can be reduced. Therefore, the productivity of the semiconductor device manufacturing method can be improved.

[0091] Additionally, when forming storage node contacts (BC) through an embossing process, mask patterns may be required to form a storage node contact film covering the front surface of the first substrate (110) and to separate the storage node contact film into storage node contacts (BC) that are spaced apart from each other in a first direction (D1) and a second direction (D2). When forming storage node contacts (BC) through an intaglio process, storage node contacts (BC) can be formed without the mask patterns. Therefore, by not using mask patterns or utilizing mask patterns in a formation process of a different configuration, the productivity of the semiconductor device manufacturing method can be improved.

[0092] In addition, due to the process of forming the second recess (RS2), the width of the recess on the semiconductor pattern (SP) can be widened. Accordingly, the width of the storage node contact (BC) can be wider than when the second recess (RS2) is not formed (in other words, when only the first recess (RS1) is formed). As a result, the contact area between the storage node contact (BC) and the landing pad (LP in FIG. 5) formed thereafter can be increased. Therefore, the electrical characteristics of the semiconductor device can be improved.

[0093] Referring to FIGS. 16 and 17, an upper insulating film (UIL) may be formed between storage node contacts (BC) through an intaglio process. For example, forming the upper insulating film (UIL) may include removing a portion of the first gate capping pattern (GC1), a portion of the first back gate capping pattern (BCG1), and a portion of the back gate insulating pattern (BGI), respectively, interposed between the storage node contacts (BC), to form a third recess (RS3), and filling the upper insulating film (UIL) within the third recess (RS3). Sides of the storage node contacts (BC) may be exposed by the third recess (RS3). The upper surface of each of the first gate capping pattern (GC1) and the first back gate capping pattern (BCG1) may be exposed to the outside by the third recess (RS3). As the upper insulating film (UIL) is formed through an intaglio process, the upper surface of the first gate capping pattern (GC1) (GCa in FIG. 6) and the upper surface of the first back gate capping pattern (BCG1) can each have a concave profile. Accordingly, the lower surface of the upper insulating film (UIL) (Ub in FIG. 6) can have a convex profile.

[0094] Referring to FIGS. 4 and 5, after the process of forming the upper insulating film (UIL) described with reference to FIGS. 16 and 17, landing pads (LP) may be formed on the storage node contacts (BC) through an intaglio process. For example, forming the landing pads (LP) may include removing the upper portion of each storage node contact (BC), forming a landing pad film (not shown) that fills the area where the upper portion of each storage node contact (BC) was removed and covers the upper surface of the upper insulating film (UIL), and removing the upper portion of the landing pad film (not shown) to separate it into landing pads (LP). For example, by removing the upper portion of each storage node contact (BC), the upper surface of each storage node contact (BC) (B1a in FIG. 7) may have a concave profile, as described with reference to FIG. 7. Accordingly, for example, the lower surface (Lb in FIG. 7) of each landing pad (LP) may have a convex profile.

[0095] For example, barrier patterns (not shown) may be formed on the upper surfaces of the storage node contacts (BC) after the process of removing the upper surface of each storage node contact (BC) and before the process of forming the landing pad film. At this time, a cleaning process may be performed on the upper surface of each storage node contact (BC) before the process of forming the barrier patterns. Accordingly, unnecessary oxide formed on the upper surface of each storage node contact (BC) may be removed.

[0096] According to the concept of the present invention, insulating patterns comprising an oxide-based insulating material interposed between storage node contacts (BC) can be replaced by an upper insulating film (UIL) comprising a nitride-based insulating material. Accordingly, during the cleaning process, it is possible to prevent the cleaning solution from penetrating under the upper insulating film (UIL). As a result, process defects caused by the cleaning solution can be prevented, and the productivity of the semiconductor device manufacturing method can be improved.

[0097] According to the concept of the present invention, the landing pad (LP) can be formed through an intaglio process. The height of the landing pad (LP) may vary depending on the extent to which the storage node contact (BC) is removed. Accordingly, adjusting the height of the landing pad (LP) may be easier than forming the landing pad (LP) through a relief process.

[0098] For example, although not shown in the drawing, barrier patterns (not shown) may be formed on storage node contacts (BC) prior to the formation process of landing pads (LP).

[0099] Subsequently, a data storage pattern (DSP) can be formed on the connection structure (CNS).

[0100] Subsequently, the upper and lower sides of the first substrate (110 in FIG. 17) may be inverted. Accordingly, the lower surface of the first substrate (110 in FIG. 17) may be exposed. The first substrate (110 in FIG. 17) and the dummy insulating film (120 in FIG. 17) may be removed. At this time, a portion of the gate electrode (GE) of FIG. 17 may be removed, and the gate electrode (GE) of FIG. 17 may be separated into a pair of gate electrodes (GE) that are spaced apart from each other in a first direction (D1). For example, in this case, a portion of the semiconductor pattern (SP) may be removed. When the upper surface (E1) of the semiconductor pattern (SP) described with reference to FIG. 12 is defined as the first surface, and the lower surface (E2) of the semiconductor pattern (SP) shown in FIG. 12 is defined as the second surface, the second surface of the semiconductor pattern (SP) may be exposed through the removal process. The first side can stand against the second side.

[0101] Second gate capping patterns (GC2) can be formed by replacing part of the gate electrodes (GE), and second back gate capping patterns (BGC2) can be formed by replacing part of the back gate electrodes (BGE).

[0102] A bitline contact (DC) and a bitline (BL) may be formed sequentially on a second surface of a semiconductor pattern (SP). A lower insulating film (LIL) may be formed to cover the bitline contact (DC) and the bitline (BL). The lower insulating film (LIL) may be formed at various times, regardless of whether it is before or after the formation of the bitline contact (DC) and the bitline (BL).

[0103] FIG. 18 is a drawing illustrating a method for manufacturing a semiconductor device according to some embodiments of the present invention. More specifically, FIG. 18 is a cross-sectional view corresponding to line AA' of FIG. 11.

[0104] Referring to FIGS. 11 and FIGS. 18, after the process of the second recess (RS2) described with reference to FIG. 13, unlike as shown in FIG. 13, the inner surface of the second recess (RS2) may be formed to be located at a vertical level lower than the upper surface of the semiconductor pattern (SP). Accordingly, a portion of the upper side (Ss) of the semiconductor pattern (SP) may be exposed by the second recess (RS2). By the second recess (RS2), the upper surface (GIa) of the gate insulation pattern (GI) may be formed to be located at a vertical level lower than the upper surface of the semiconductor pattern (SP). By the second recess (RS2), the upper surface (BGIa) of a portion of the back gate insulation pattern (BGI) may be formed to be located at a vertical level lower than the upper surface of the semiconductor pattern (SP).

[0105] Subsequently, through the semiconductor device manufacturing method described above, the semiconductor device described with reference to FIGS. 4, 8, and 9 can be manufactured.

[0106] The above description of the embodiments of the present invention provides examples for explaining the present invention. Accordingly, the present invention is not limited to the above embodiments, and it is evident that many modifications and changes are possible within the technical scope of the present invention, such as combining the above embodiments by those skilled in the art.

Claims

Claim 1 A semiconductor device comprising: a bit line extending in a first direction parallel to the upper surface of the substrate on a substrate; a semiconductor pattern extending in a direction perpendicular to the upper surface of the substrate on the bit line; a gate electrode extending in a second direction intersecting the first direction on a side of the semiconductor pattern; a storage node contact on the upper surface of the semiconductor pattern; an upper insulating film covering the side of the storage node contact; and a capping pattern between the upper insulating film and the gate electrode, wherein the upper insulating film is provided on the upper surface of the capping pattern, and the upper surface of the semiconductor pattern and the upper surface of the capping pattern each have a concave profile. Claim 2 A semiconductor device according to claim 1, wherein the storage node contact comprises a first region and a second region between the first region and the semiconductor pattern, and the lower surface of the second region of the storage node contact has a convex profile. Claim 3 A semiconductor device according to claim 2, further comprising a gate insulation pattern between the semiconductor pattern and the gate electrode, wherein the lower surface of the second region of the storage node contact is located at a vertical level lower than the upper surface of the gate insulation pattern. Claim 4 In claim 2, the upper surface of the first region of the storage node contact has a concave profile. Claim 5 A semiconductor device according to claim 2, wherein a portion of the first region of the storage node contact covers the upper side of the semiconductor pattern. Claim 6 A semiconductor device according to claim 2, wherein the lower surface of the first region of the storage node contact is located at a vertical level lower than the uppermost surface of the semiconductor pattern. Claim 7 In claim 1, the storage node contact comprises a first region and a second region between the first region and the semiconductor pattern, and the second region of the storage node contact is a semiconductor device inserted into the semiconductor pattern. Claim 8 A semiconductor device according to claim 1, wherein the storage node contact comprises a first region and a second region between the first region and the semiconductor pattern, the first region and the second region of the storage node contact are separated from each other at a first level, and with respect to the first direction, the width of the first region of the storage node contact at the first level is greater than the width of the second region of the storage node contact at the first level. Claim 9 In claim 8, with respect to the first direction, the width at the first level of the second region of the storage node contact is the same as the width of the semiconductor pattern in the semiconductor device. Claim 10 A semiconductor device according to claim 1, wherein the upper insulating film and the capping pattern comprise different insulating materials. Claim 11 A semiconductor device according to claim 1, wherein the lower surface of the upper insulating film has a convex profile. Claim 12 In claim 1, the semiconductor device in which, from a planar perspective, the semiconductor pattern and the storage node contact each have a semi-elliptical shape. Claim 13 A semiconductor device according to claim 1, wherein the semiconductor pattern is a first semiconductor pattern, and a second semiconductor pattern and a third semiconductor pattern are spaced apart from each other in a first direction with the first semiconductor pattern in between; and further comprising a back gate electrode between the first semiconductor pattern and the second semiconductor pattern, wherein the gate electrode comprises a pair of gate electrodes spaced apart from each other in a first direction between the first semiconductor pattern and the third semiconductor pattern. Claim 14 A semiconductor device comprising: a bit line extending in a first direction parallel to the upper surface of the substrate on a substrate; a semiconductor pattern extending in a direction perpendicular to the upper surface of the substrate on the bit line; a gate electrode extending in a second direction intersecting the first direction on a side of the semiconductor pattern; a storage node contact on the upper surface of the semiconductor pattern; an upper insulating film covering the side of the storage node contact; and a capping pattern between the upper insulating film and the gate electrode, wherein the upper insulating film is provided on the upper surface of the capping pattern, the storage node contact includes a first region and a second region between the first region and the semiconductor pattern, the upper surface of the capping pattern has a concave profile, and the lower surface of the second region of the storage node contact has a convex profile. Claim 15 In claim 14, the second region of the storage node contact is a semiconductor device inserted into the semiconductor pattern. Claim 16 In claim 14, the first region and the second region of the storage node contact are separated from each other at a first level, and with respect to the first direction, the width of the second region of the storage node contact at the first level is smaller than the width of the first region of the storage node contact at the first level and is the same as the width of the semiconductor pattern. Claim 17 A semiconductor device according to claim 14, further comprising a gate insulation pattern between the semiconductor pattern and the gate electrode, wherein a portion of the semiconductor pattern is interposed between the second region of the storage node contact and the gate insulation pattern. Claim 18 A semiconductor device according to claim 14, wherein the lowest surface of the second region of the storage node contact is located at a vertical level lower than the upper surface of the semiconductor pattern. Claim 19 A semiconductor device according to claim 14, wherein the upper insulating film and the capping pattern comprise different insulating materials, and the lower surface of the upper insulating film has a convex profile. Claim 20 A method for manufacturing a semiconductor device comprising: forming a semiconductor pattern extending in a direction perpendicular to the first substrate on a first substrate; forming a gate insulation pattern and a gate electrode in turn on the side of the semiconductor pattern; forming a capping pattern on the gate electrode; forming a first recess by removing the upper portion of the semiconductor pattern to expose the side of the gate insulation pattern; forming a second recess by removing a portion of the gate insulation pattern exposed by the first recess; forming a storage node contact within the second recess; forming a third recess by removing a portion of the capping pattern to expose the side of the storage node contact; and forming an upper insulating film within the third recess.

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