Memory device, memory controller and operation method of the memory device

Abstract

A memory device according to an embodiment of the present invention comprises: one or more first pins; a plurality of second pins; a memory interface circuit that obtains control information from one or more control signals received from the one or more first pins, obtains data from a plurality of data signals received from the plurality of second pins, and obtains a command and parity from the control information by interpreting headers included in the control information; a memory cell array that stores the data; an ECC (Error Correction Circuit) decoder circuit that corrects an error in the command using the parity; and a control circuit that controls the memory device based on the error-corrected command in a reset state of a fail flag.

Description

Technology Field

[0001] The present invention relates to a memory device, a memory controller that controls the memory device, and a method of operating the memory device. Background Technology

[0003] A memory device can transmit and receive input / output signals to and from a memory controller through pins predetermined according to a protocol. For example, the memory device can transmit and receive data to and from the memory controller through data input / output pins, and can transmit and receive control signals to and from the memory controller through control signal input / output pins that are different from the data input / output pins. When data and control signals are transmitted and received through different input / output pins, data can be transmitted simultaneously with the transmission of control signals, thereby improving data transmission efficiency.

[0004] However, in order for data transmission efficiency to be further improved amidst the trend of increasing data transmission speeds, it is required that the transmission speed of control signals also increase in tandem with the data transmission speed. The problem to be solved

[0006] The present invention aims to provide a memory device, a memory controller, and a method of operation of the memory device that can reduce the failure rate of a command despite an increase in the transmission speed of a control signal. means of solving the problem

[0008] A memory device according to an embodiment of the present invention comprises: one or more first pins; a plurality of second pins; a memory interface circuit that obtains control information from one or more control signals received from the one or more first pins, obtains data from a plurality of data signals received from the plurality of second pins, and obtains a command and parity from the control information by interpreting headers included in the control information; a memory cell array that stores the data; an ECC (Error Correction Circuit) decoder circuit that corrects an error in the command using the parity; and a control circuit that controls the memory device based on the error-corrected command in a reset state of a fail flag.

[0009] A memory controller according to an embodiment of the present invention comprises: one or more first pins; a plurality of second pins; a processor that generates a command for controlling a memory device; a first ECC (Error Correction Code) circuit that generates a first parity by performing error correction encoding for the command; and a controller interface circuit that provides one or more control signals including the command and the first parity to the memory device through the one or more first pins and inputs and outputs data signals to and from the memory device through the plurality of second pins, wherein the controller interface circuit receives a fail signal indicating a failure of the one or more control signals from the memory device and performs training for the one or more control signals in response to the fail signal.

[0010] A method of operation of a memory device according to an embodiment of the present invention comprises: receiving at least one control signal including a command, an address, and a parity from a controller through at least one control signal line; performing Error Correction Code (ECC) decoding of the command and the address using the parity; setting a fail flag and generating fail information when the error correction of at least one of the command and the address fails; providing a response including the fail information through the at least one control signal line in response to a status read command from the controller and resetting the fail flag; and receiving a training command from the controller and providing a response through the at least one control signal line. Effects of the invention

[0012] According to an embodiment of the present invention, a memory device detects a command, an address, and a parity from a control signal received from a memory controller, and can perform error detection and correction of the command and address using the parity. Accordingly, even if the transmission speed of the control signal received from the memory controller increases, the failure rate of the command can be reduced.

[0013] According to an embodiment of the present invention, a memory device can output fail information of a control signal through a control signal input / output pin in response to a status read command received through the control signal input / output pin. Accordingly, fail information can be provided to a memory controller without design changes that add a separate input / output pin.

[0014] According to an embodiment of the present invention, a memory controller can recover from failures in control signal lines and reduce the failure rate of commands by performing training on control signals in response to failure information received through a control signal input / output pin.

[0015] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be clearly understood by those skilled in the art from the description below. Brief explanation of the drawing

[0017] FIG. 1 is a drawing showing a memory system according to an embodiment of the present invention. Figure 2 is a timing diagram of the control signal and data signal. FIG. 3 is a drawing showing a memory system according to an embodiment of the present invention. FIG. 4 is a drawing showing a memory device according to an embodiment of the present invention. FIG. 5 is a flowchart illustrating the operation of a memory device according to an embodiment of the present invention. FIG. 6 is a timing diagram of a control signal according to an embodiment of the present invention. FIG. 7 is a timing diagram of a control signal and a fail flag signal according to an embodiment of the present invention. FIG. 8 is a flowchart illustrating the operation of a memory device according to an embodiment of the present invention. FIG. 9 is a timing diagram of a control signal and a fail flag signal according to an embodiment of the present invention. FIG. 10 is a diagram showing the interaction between a memory controller and a memory device according to an embodiment of the present invention. Specific details for implementing the invention

[0018] Hereinafter, preferred embodiments of the present invention will be described with reference to the attached drawings.

[0019] FIG. 1 is a drawing showing a memory system according to an embodiment of the present invention.

[0020] Referring to FIG. 1, the memory system (10) may include a memory device group (100) and a memory controller (200). The memory system (10) may support a plurality of channels (CH1-CHm), and the memory device group (100) and the memory controller (200) may be connected through the plurality of channels (CH1-CHm). For example, the memory system (10) may be implemented as a memory system such as a Solid State Drive (SSD).

[0021] A memory device group (100) may include a plurality of memory devices (MD11-MDmn). Each of the plurality of memory devices (MD11-MDmn) may be a flash memory device. However, the present invention is not limited thereto, and each of the plurality of memory devices (MD11-MDmn) may include non-volatile memory such as RRAM (Resistive Random Access Memory), FRAM (Ferroelectric Random Access Memory), PRAM (Phase Change Random Access Memory), TRAM (Thyristor Random Access Memory), MRAM (Magnetic Random Access Memory), or volatile memory such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory).

[0022] Each of the memory devices (MD11-MDmn) may be connected to one of the multiple channels (CH1-CHm) via a corresponding way. For example, memory devices (MD11-MD1n) may be connected to the first channel (CH1) via ways (W11-W1n), and memory devices (MD21-MD2n) may be connected to the second channel (CH2) via ways (W21-W2n). In an exemplary embodiment, each of the memory devices (MD11-MDmn) may be implemented as any memory unit capable of operating according to an individual control signal from the memory controller (200). For example, each of the memory devices (MD11-MDmn) may be implemented as a chip or a die, but the present invention is not limited thereto.

[0023] The memory controller (200) can transmit and receive signals to and from the memory device group (100) through multiple channels (CH1-CHm). For example, the memory controller (200) can transmit control signals (CTRLa-CTRLm) and data signals to the memory device group (100) through the channels (CH1-CHm) and receive data signals (DATAa-DATAm) from the memory device group (100). The control signals may include commands and may further include addresses.

[0024] The memory controller (200) can select one of the memory devices connected to the corresponding channel through each channel and transmit and receive signals with the selected memory device. For example, the memory controller (200) can select a memory device (MD11) among the memory devices (MD11-MD1n) connected to the first channel (CH1). The memory controller (200) can transmit a control signal (CTRLa) and a data signal (DATAa) to the selected memory device (MD11) through the first channel (CH1) and receive data (DATAa) from the selected memory device (MD11).

[0025] The memory controller (200) can transmit and receive signals in parallel with the memory device group (100) through different channels. For example, the memory controller (200) can transmit a control signal (CTRLb) to the memory device group (100) through the second channel (CH2) while transmitting a control signal (CTRLa) to the memory device group (100) through the first channel (CH1). For example, the memory controller (200) can receive a data signal (DATAb) from the memory device group (100) through the second channel (CH2) while receiving a data signal (DATAa) from the memory device group (100) through the first channel (CH1).

[0026] The memory controller (200) can control the overall operation of the memory device group (100). The memory controller (200) can control each of the memory devices (MD11-MDmn) connected to the channels (CH1-CHm) by transmitting a signal to the channels (CH1-CHm). For example, the memory controller (200) can control one of the selected memory devices (MD11-MD1n) by transmitting a control signal (CTRLa) to the first channel (CH1).

[0027] Each of the memory devices (MD11-MDmn) can operate under the control of the memory controller (200). For example, the memory device (MD11) can program data according to a control signal (CTRLa) and a data signal (DATAa) provided through the first channel (CH1). For example, the memory device (MD21) can read data according to a control signal (CTRLb) provided through the second channel (CH2) and transmit the read data to the memory controller (200) as a data signal (DATAb).

[0028] FIG. 1 illustrates a memory device group (100) communicating with a memory controller (200) through m channels, and the memory device group (100) including n non-volatile memory devices corresponding to each channel. However, the number of channels and the number of non-volatile memory devices connected to one channel may vary.

[0029] A channel may include a control signal line for transmitting and receiving control signals and a data signal line for transmitting and receiving data signals. The control signal and the data signal may be transmitted and received in parallel through the control signal line and the data signal line.

[0030] Figure 2 is a timing diagram of the control signal and data signal.

[0031] A memory controller (200) and a memory device (MD: MD11-MDmn) as described with reference to FIG. 1 can transmit and receive one or more control signals (CA[X:0]) through one or more control signal lines and transmit and receive multiple data signals (DQ[Y:0]) through multiple data lines.

[0032] For example, the memory controller (200) and the memory device (MD) can transmit and receive control signals (CA[1:0]) through two control signal lines and transmit and receive data signals (DQ[7:0]) through eight data pins. Hereinafter, an embodiment of the present invention is described with an example in which multiple control signals are transmitted and received between the memory controller (200) and the memory device (MD). However, the present invention does not exclude cases in which a single control signal is transmitted and received through a single control signal line or a single data signal is transmitted and received through a single data line between the memory controller (200) and the memory device (MD).

[0033] The memory device (MD) receives control signals (CA[X:0]) during a first period (T11) and can obtain first control information (CTRL1) from said control signals (CA[X:0]). For example, the first control information (CTRL1) may include a command and an address. Based on the first control information (CTRL1) obtained during a second period (T12), the memory device (MD) can obtain first data (DATA1) from data signals (DQ[Y:0]) or output the first data (DATA1) stored in the memory device (MD) as said data signals (DQ[Y:0]).

[0034] For example, if the above command is a program command, the memory device (MD) can acquire the first data (DATA1) during the second period (T12), and if the above command is a read command, the memory device (MD) can output the first data (DATA1).

[0035] The memory device (MD) receives control signals (CA[X:0]) during the second period (T12) and can obtain second control information (CTRL2) from the control signals (CA[X:0]). That is, the memory device (MD) can obtain second control information (CTRL2) through control signal lines distinct from data signal lines while the first data (DATA1) is input / output simultaneously. Since the input / output paths of the data and control information are different, the memory device (MD) can input / output data while simultaneously obtaining control information, and data input / output efficiency can be improved.

[0036] In order for data input / output efficiency to be further improved, the reception speed of control information may need to be increased to keep pace with the increasing speed of data input / output. The size of the control information may be smaller than the size of the data, and the reception speed of the control information may be slower than the data input / output speed. For example, to prevent malfunction of the memory device (MD), the control information may require a higher level of integrity than the data. Accordingly, the memory controller (200) can provide a sufficient timing margin for sampling the control signals by transmitting control signals having a frequency lower than the frequency of the data signals.

[0037] However, if the period for receiving control signals including the second control information (CTRL2) is longer than the period for inputting and outputting data signals including the first data (DATA1), data signals based on the second control information (CTRL2) may not be input or output until the reception of the control signals is completed, even after the reception of the first data (DATA1) is completed. Therefore, data input / output efficiency may be reduced.

[0038] If the frequency of control signals is increased to improve data input / output efficiency, the timing margin may decrease, and the fail rate of commands or addresses included in the control information may increase. A command or address fail may refer to a state in which a command cannot be executed normally because the received command or address contains an error bit. If the aforementioned fail rate increases, the possibility of malfunction of the memory device (MD) may increase.

[0039] According to an embodiment of the present invention, control information may further include a command and an address, as well as the parity of the command and the address. A memory device may receive control signals (CA[X:0]) including the parity through a control signal line. The memory device may obtain the command, address, and parity from the control signals (CA[X:0]) and reduce the fail rate by detecting and correcting errors in the command and the address using the parity.

[0040] In addition, the memory device can prevent malfunction by setting a fail flag when an error in the control information is not corrected and ignoring the control information. When the fail flag is set, the memory device can output fail information through the control line in response to a status read command received through the control line.

[0041] Hereinafter, a memory system including a memory device according to an embodiment of the present invention is described in detail with reference to FIGS. 3 to 10.

[0042] FIG. 3 is a drawing showing a memory system according to an embodiment of the present invention.

[0043] Referring to FIG. 3, the memory system (20) may include a memory device (300) and a memory controller (400). The memory device (300) may correspond to any one of the memory devices (MD: MD11-MDmn) described with reference to FIG. 1, and the memory controller (400) may correspond to the memory controller (200) described with reference to FIG. 1.

[0044] The memory device (300) may include first to fourth pins (P11-P14), a memory interface circuit (310), an ECC decoder circuit (320), a control logic circuit (330), and a memory cell array (340).

[0045] The memory interface circuit (310) can transmit and receive one or more control signals (CA[X:0]), a control clock signal (CA_CLK), a plurality of data signals (DQ[Y:0]), and a data strobe signal (DQS) through the first to fourth pins (P11-P14).

[0046] Specifically, the memory interface circuit (310) can obtain control information from control signals (CA[X:0]) received through the first pins (P11). The number of the first pins (P11) may be equal to the number of control signals.

[0047] According to an embodiment of the present invention, the control information may include at least a command and parity, and may further include an address. For example, when the control information includes a command, an address, and parity, the parity may include a first parity obtained by performing error correction encoding on the command and a second parity obtained by performing error correction encoding on the address. However, the present invention is not limited thereto, and the parity may be a parity obtained by performing error correction encoding on the command and the address together.

[0048] The memory interface circuit (310) can obtain the control information by sampling the control signals (CA[X:0]) based on the control clock signal (CA_CLK) received through the second pin (P12). The control clock signal (CA_CLK) maintains a static state, such as a high level or a low level, during periods when the control signals (CA[X:0]) are not received, and can toggle between a high level and a low level during periods when the control signals (CA[X:0]) are received.

[0049] Additionally, the memory interface circuit (310) may transmit control signals (CA[X:0]) containing control information, such as a response to a status read command, to the memory controller (400). The memory interface circuit (310) may generate a control clock signal (CA_CLK) and transmit control signals (CA[X:0]) to the memory controller (400) based on the generated control clock signal (CA_CLK).

[0050] The memory interface circuit (310) can obtain data (DATA) from data signals (DQ[Y:0]) received through the third pins (P13) or generate data signals (DQ[Y:0]) containing data (DATA). The number of the third pins (P13) may be equal to the number of data signals (DQ[Y:0]).

[0051] The memory interface circuit (310) can obtain data (DATA) from data signals (DQ[Y:0]) through a data strobe signal (DQS) received from the memory controller (400) via the fourth pin (P14). Additionally, the memory interface circuit (310) can generate a data strobe signal (DQS) and transmit third signals (SIG3) containing data (DATA) to the memory controller (400) based on the generated data strobe signal (DQS).

[0052] In one embodiment, the frequencies of the data signals (DQ[Y:0]) and the data strobe signal (DQS) may be higher than the frequencies of the control signals (CA[X:0]) and the control clock signal (CA_CLK).

[0053] The ECC decoder circuit (320) can perform error detection and correction of control information (CTRL) obtained from the memory interface circuit (310). The ECC decoder circuit (320) can correct errors in the command and address included in the control information (CTRL) by performing error correction decoding using the parity included in the control information (CTRL), and can output the error-corrected command / address (CMD / ADDR).

[0054] According to an embodiment of the present invention, control information (CTRL) received from a memory controller (400) may include parity, and an ECC decoder circuit (320) may use the parity to correct errors in commands and addresses.

[0055] The control logic circuit (330) can control the overall operation of the memory device (300). The control logic circuit (330) can receive a command / address (CMD / ADDR) from the ECC decoder circuit (320). The control logic circuit (330) can generate internal signals to control other components of the memory device (300) according to the received command / address (CMD / ADDR). For example, the control logic circuit (330) can generate various internal signals to program data (DATA) into the memory cell array (340) or to read data (DATA) from the memory cell array (340).

[0056] According to an embodiment of the present invention, if the ECC decoder circuit (320) fails to correct errors in at least some of the commands and addresses, the control logic circuit (330) may set a fail flag. The control logic circuit (330) may ignore commands / addresses (CMD / ADDR) received after the fail flag is set, except for status read commands.

[0057] The control logic circuit (330) can provide fail information to the memory controller (400) in response to a status read command when the fail flag is set, and can reset the fail flag. According to an embodiment of the present invention, the fail information can be transmitted through the first pin (P11).

[0058] The memory cell array (340) can store data (DATA) obtained from the memory interface circuit (310) under the control of the control logic circuit (330). The memory cell array (340) can output the stored data (DATA) to the memory interface circuit (310) under the control of the control logic circuit (330).

[0059] The memory cell array (340) may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells may be non-volatile memory cells or volatile memory cells. Hereinafter, embodiments of the present invention are described with reference to an embodiment in which the memory cells are NAND flash memory cells.

[0060] The memory controller (400) may include first to fourth pins (P21-P24), a host interface circuit (410), a controller interface circuit (420), a processor (430), a buffer memory (440), a data ECC circuit (451), and a control ECC circuit (452).

[0061] The host interface circuit (410) can transmit and receive packets with the host. The packet transmitted from the host to the host interface circuit (410) may include a command or data to be written to the memory device (300). The packet transmitted from the host interface circuit (410) to the host may include a response to the command or data read from the memory device (300).

[0062] The first to fourth pins (P21-P24) may correspond to the first to fourth pins (P11-P14) of the memory device (300). The first pins (P11) and the first pins (P21) may be connected via control signal lines, and the second pin (P12) and the second pin (P22) may be connected via control clock signal lines. The third pins (P13) and the third pins (P23) may be connected via data signal lines, and the fourth pin (P14) and the fourth pin (P24) may be connected via data strobe signal lines.

[0063] The controller interface circuit (420) can transmit and receive control signals (CA[X:0]) and a control clock signal (CA_CLK) to and from the memory device (300) through the first to fourth pins (P21-P24), and transmit and receive data signals (DQ[Y:0]) and a data strobe signal (DQS) to and from the memory device (300).

[0064] Specifically, the controller interface circuit (420) can transmit control signals (CA[X:0]) through the first pins (P21) and transmit a control clock signal (CA_CLK) for sampling the control signals (CA[X:0]) through the second pin (P22). Alternatively, the controller interface circuit (420) can receive control signals (CA[X:0]) through the first pins (P21) and receive a control clock signal (CA_CLK) through the second pin (P22).

[0065] Additionally, the controller interface circuit (420) can transmit data signals (DQ[Y:0]) through the third pins (P23) and transmit a data strobe signal (DQS) for sampling the data signals (DQ[Y:0]) through the fourth pin (P24). Alternatively, the controller interface circuit (420) can receive data signals (DQ[Y:0]) through the third pins (P23) and receive a data strobe signal (DQS) through the fourth pin (P24).

[0066] The processor (430) can control the overall operation of the memory controller (400) by executing firmware such as the Flash Translation Layer (FTL). For example, the processor (430) can perform several functions such as address mapping, wear-leveling, and garbage collection.

[0067] The processor (430) can generate commands and addresses to control the memory device (300). For example, the processor (430) can generate commands such as program commands, read commands, and erase commands, and addresses corresponding to memory regions where said commands are to be executed. Additionally, the processor (430) can generate a status read command to request the status of the memory device (300).

[0068] The buffer memory (440) can store data to be programmed into the memory device (300), data read from the memory device (300), and metadata such as map data. The buffer memory (440) may be provided within the memory controller (400), but may also be placed outside the memory controller (400).

[0069] The data ECC circuit (451) can perform error detection and correction functions for data read from the memory device (300). Specifically, the data ECC circuit (451) can generate parity for program data to be programmed into the memory device (300). The generated parity can be stored in the memory device (300) together with the program data. Furthermore, the data ECC circuit (451) can correct errors in the read data using the parity read from the memory device (300) together with the read data, and output the read data with the errors corrected.

[0070] The control ECC circuit (452) can generate parity for commands and addresses transmitted to the memory device (300). In a first example, the control ECC circuit (452) may generate parity including a first parity for the command and a second parity for the address. In a second example, the control ECC circuit (452) may generate a single parity by performing error correction encoding for the command and the address.

[0071] In one embodiment, different error correction codes may be applied to the data ECC circuit (451) and the control ECC circuit (452). For example, the size of the data may be larger than the size of the command and the size of the address. Accordingly, the error correction code applied to the data ECC circuit (451) may support error correction encoding for codewords of a larger size than the error correction code applied to the control ECC circuit (452).

[0072] In one embodiment, the host interface circuit (410) may include a Host Direct Memory Access (HDMA) (411) that controls data transmission and reception between the host memory and the buffer memory (440). Additionally, the controller interface circuit (420) may include a Flash Direct Memory Access (FDMA) (421) that controls data transmission and reception between the buffer memory (440) and the memory interface circuit (310). The HDMA (411) and FDMA (421) can transmit data without the intervention of the processor (430).

[0073] According to an embodiment of the present invention, the memory controller (400) can protect the command and address from errors and reduce the failure rate of the control signal by transmitting a control signal, in which parity is added to the command and address, to the memory device (300). In response to the trend of increasing the speed of data input / output, the failure rate of the control signal can be reduced even if the transmission speed of the control signal is increased. As a result, data input / output efficiency can be improved.

[0074] Additionally, the memory controller (400) may retransmit a control signal containing a failed command or address in response to fail data from the memory device (300). In one embodiment, the memory controller (400) may lower the frequency of the control signal to increase the timing margin of the control signal and may perform a recovery operation to retrain the control signal line. Thus, the reliability of the memory system (20) can be improved.

[0075] Below, prior to the detailed description of the operation of the memory system according to an embodiment of the present invention, the structure of the memory device is described in more detail with reference to FIG. 4.

[0076] FIG. 4 is a drawing showing a memory device according to an embodiment of the present invention.

[0077] FIG. 4 is an exemplary block diagram illustrating a non-volatile memory device. Referring to FIG. 4, the non-volatile memory (500) may include a control logic circuit (530), a memory cell array (540), a page buffer (550), a voltage generator (560), and a row decoder (570). Although not shown in FIG. 4, the non-volatile memory (500) may further include circuits such as the memory interface circuit (310) and the ECC decoder circuit (320) described with reference to FIG. 3, and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc.

[0078] The control logic circuit (530) can control various operations within the non-volatile memory (500) overall. The control logic circuit (530) can output various internal signals in response to a command (CMD) and / or an address (ADDR) that is received by the memory interface circuit and error-corrected by the ECC decoder circuit. For example, the control logic circuit (530) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0079] The memory cell array (540) may include a plurality of memory blocks (BLK1 to BLKz) (z is a positive integer), and each of the plurality of memory blocks (BLK1 to BLKz) may include a plurality of memory cells. The memory cell array (540) may be connected to a page buffer unit (550) via bit lines (BL) and may be connected to a row decoder (560) via word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0080] In an exemplary embodiment, the memory cell array (540) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the memory cell array (540) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0081] The page buffer (550) may include a plurality of page buffers (PB1-PBn) (where n is an integer greater than or equal to 3), and the plurality of page buffers (PB1-PBn) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer (550) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer (550) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer (550) may apply a bit line voltage corresponding to the data to be programmed with the selected bit line. During a read operation, the page buffer (550) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0082] The voltage generation unit (560) can generate various types of voltages to perform program, read, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generation unit (560) can generate a program voltage, a read voltage, a program verification voltage, an erase voltage, etc. as a word line voltage (VWL).

[0083] The row decoder (570) can select one of a plurality of word lines (WL) and one of a plurality of string select lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (570) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0084] Hereinafter, with reference to FIGS. 5 to 9, the operation of a memory device according to an embodiment of the present invention is specifically described.

[0085] FIG. 5 is a flowchart illustrating the operation of a memory device according to an embodiment of the present invention.

[0086] In step S11, the memory device, for example, the memory interface circuit (310) of FIG. 3, can receive control signals (CA[X:0]) from the memory controller. As described with reference to FIG. 3, the memory device can receive a control clock signal (CA_CLK) along with the control signals (CA[X:0]).

[0087] In step S12, the memory interface circuit (310) can obtain control information including a command (CMD), an address (ADDR), and parity. For example, the memory device can obtain control information including multiple bits by sampling control signals (CA[X:0]) with a control clock signal (CA_CLK).

[0088] Meanwhile, control information may not necessarily include an address. For example, a status read command may not require an address. Therefore, the memory device may obtain control information that includes only a command (CMD) and parity.

[0089] In step S13, the memory device, for example, the ECC decoder circuit (320) of FIG. 3, performs error correction decoding for the command and address and can determine whether to pass the error correction decoding.

[0090] If the error correction decoding is passed (in step S13, "yes"), the memory device, e.g., the control circuit (330) of FIG. 3, can perform an operation based on the error-corrected command (CMD) and the error-corrected address (ADDR) in step S14.

[0091] If error correction decoding fails ("No" in step S13), the control circuit (330) may set a fail flag in step S15. Specifically, the control circuit (330) may set the fail flag even if error correction decoding of either the command (CMD) or the address (ADDR) fails.

[0092] In step S16, the control circuit (330) may generate fail information for a command (CMD) or an address (ADDR). In one embodiment, the fail information may indicate which control information has failed. Additionally, if the parity includes parities for the command (CMD) and the address (ADDR), the fail information may include information indicating whether the error correction decoding of the command (CMD) failed or the error correction decoding of the address (ADDR) failed.

[0093] Below, prior to explaining the signal timing of the control signal and the fail flag, the transmission method of the control signal is specifically explained with reference to FIG. 6.

[0094] FIG. 6 is a timing diagram of a control signal according to an embodiment of the present invention.

[0095] In the example of Fig. 6, the transmission method of control signals is explained by taking the case where control information is received through two control signals (CA[1:0]).

[0096] Control signals (CA[1:0]) can be received in parallel by the memory device. While the control signals (CA[1:0]) are being received, the memory device can receive a toggling control clock signal (CA_CLK). The memory device can obtain control information from the control signals (CA[1:0]) based on the control clock signal (CA_CLK).

[0097] For example, the memory device can acquire two bits in one period (CY) of the control clock signal (CA_CLK) by sampling the control signals (CA[1:0]) at the rising edge of the control clock signal (CA_CLK). The memory device can acquire a control signal containing multiple bits over multiple unit periods (T21-T25).

[0098] The period during which control signals are received can be divided into multiple unit periods (T21-T25). A unit period may correspond to one or more cycles (CY) of the control clock signal (CA_CLK). In the example of FIG. 6, a unit period may correspond to four cycles of the control clock signal (CA_CLK). The memory device may obtain an 8-bit signal from the control signals (CA[1:0]) received in a unit period. However, the number of control signals received in parallel and the number of cycles (CY) included in one period are not limited to this.

[0099] A memory device can obtain a command, an address, and a parity from control signals received during multiple unit periods. The control signal may include a header and a body following the header. The body may be any one of a command, an address, and a parity. The header may include information indicating whether the body is a command, an address, or a parity.

[0100] In the example of FIG. 6, a header may be received during the first period (T21). For example, the header may include header bits (H[7:0]) received during the first period (T21). The header may indicate whether control signals (CA[1:0]) received during unit periods after the first period (T21) are commands, addresses, or parities. However, the length of the header is not limited to 8 bits.

[0101] The body received during the second to fifth periods (T22-T25) may include a command, an address, or a parity. For example, the body may include body bits (B1[7:0], B2[7:0], B3[7:0], B4[7:0]) received during the second to fifth periods (T22-T25).

[0102] In one embodiment, the sizes of the command, address, and parity may differ from each other. The memory device may obtain the command, address, or parity from control signals (CA[1:0]) received during a number of unit periods determined based on the header.

[0103] FIG. 7 is a timing diagram of a control signal and a fail flag signal according to an embodiment of the present invention.

[0104] Referring to FIG. 7, the memory device can receive control signals (CA[X:0]) and generate a fail flag. The fail flag remains in a reset state until a failure of the control signal is detected, and can be set when a failure of the control signal is detected.

[0105] Specifically, the memory device may receive control signals (CA[X:0]) during a first period (T31). For example, the control signals (CA[X:0]) received during the period may include a command header (CMD_H), a command (CMD), an address header (ADDR_H), an address (ADDR), a parity header (PAR_H), and a parity (PAR).

[0106] The memory device can perform error correction of the command and address during the second period (T32). For example, a memory interface circuit (310), such as described with reference to FIG. 3, can obtain a command (CMD), an address (ADDR), and a parity (PAR) based on headers (CMD_H, ADD_H, PAR_H) of control signals (CA[X:0]). And, an ECC decoder circuit (320), described with reference to FIG. 3, can perform error correction of the command (CMD) and the address (ADDR) based on the parity (PAR).

[0107] During the first and second periods (T31, T32), the fail flag may remain in a reset state. If the error correction of the command and address passes (ECC pass), the fail flag may remain in a reset state even after the second period (T32). However, if the error correction of the command or address fails (ECC fail), the memory device may set the fail flag after the second period (T32).

[0108] Hereinafter, with reference to FIGS. 8 and FIGS. 9, the operation of the memory device with the fail flag set is described in detail.

[0109] FIG. 8 is a flowchart illustrating the operation of a memory device according to an embodiment of the present invention.

[0110] In step S21, the memory device, for example, the memory interface circuit (310) described with reference to FIG. 3, can receive control signals (CA[X:0]) from the memory controller.

[0111] In step S22, the memory interface circuit (310) can obtain control information including a command (CMD), an address (ADDR), and parity. For example, the memory interface circuit (310) can obtain control information including multiple bits by sampling control signals (CA[X:0]) with a control clock signal (CA_CLK).

[0112] In step S23, the memory device, for example, the ECC decoder circuit (320) of FIG. 3, can perform error correction decoding for the control information and determine whether to pass the error correction decoding.

[0113] If error correction decoding fails (in step S23, "No"), in step S24, the memory device, e.g., the control circuit (330) of FIG. 3, may ignore the command (CMD).

[0114] If the error correction decoding is passed (in step S23, "Yes"), in step S25 the control circuit (330) can determine whether the command (CMD) is a status read command.

[0115] If the command (CMD) is not a status lead command ("No" in step S25), the control circuit (330) in step S24 may ignore the command (CMD). That is, the control circuit (330) may discard the command without executing the action directed by the command (CMD).

[0116] If the command (CMD) is a status read command (in step S25, "Yes"), in step S26, the control circuit (330) can output fail data through the memory interface circuit (310) in response to the status read command.

[0117] In one embodiment, the fail data may include a fail flag value. In one embodiment, the fail data may further include fail information generated in step S16 described with reference to FIG. 4.

[0118] In step S27, the control circuit (330) can reset the fail flag.

[0119] FIG. 9 is a timing diagram of a control signal and a fail flag signal according to an embodiment of the present invention.

[0120] Referring to FIG. 9, the memory device can transmit and receive control signals (CA[X:0]) and a control clock signal (CA_CLK) with the memory controller. Additionally, the memory device can generate a fail flag.

[0121] In the example of FIG. 9, the first period (T41), the second period (T42), and the third period (T43) are shown in chronological order.

[0122] With the fail flag set, the memory device may receive a Status read command during the first period (T41). For example, the memory device may receive a command header (CMD_H), a command (CMD), a parity header (PAR_H), and a parity (PAR) in sequence during the first period (T41). The memory device may obtain the command (CMD) and the parity (PAR) based on the headers (CMD_H, PAR_H), and perform error correction decoding of the command using the parity (PAR) after the first period (T41).

[0123] If error correction decoding of a control signal received during the first period (T41) fails, or if the command included in the control signal is not a status read command, the memory device may ignore the command. However, if error correction decoding succeeds and the command is a status read command, the memory device may provide a response to the status read command to the memory controller during the second period (T42).

[0124] According to an embodiment of the present invention, a memory device, for example, a control circuit (330) described with reference to FIG. 3, may output a response to a status read command through a control signal line that transmits control signals (CA[X:0]). For example, the response may include status information (Status) and fail data (Fail_D). The status information may indicate the status of the memory device, for example, whether the memory device is in a busy state or a ready state. The fail data (Fail_D) may include a set fail flag value and fail information.

[0125] However, the present invention is not limited to this. For example, the control device (330) may include a fail flag value in the reserved bit of the 8-bit status information transmitted during a unit period.

[0126] According to an embodiment of the present invention, the memory device can transmit fail data through the first pins (P11) described with reference to FIG. 3. For example, the control signal line can support bidirectional communication between the memory controller and the memory device. The memory device can output control signals (CA[X:0]) including a response through the first pins (P11) and simultaneously output a control clock signal (CA_CLK) through the second pin (P12).

[0127] Therefore, since the memory device can notify the memory device of failure status and failure information through the first pins (P11) without adding a separate signal pin for a fail alert, excessive design changes to the memory device are not required, and the area occupied by the signal pin can be reduced.

[0128] The memory device may reset the fail flag after the second period (T42). If error correction decoding for the control signals (CA[X:0]) received after the fail flag is reset is successful, the memory device may execute the command included in the control signals (CA[X:0]).

[0129] For example, the memory device may receive a command header (CMD_H), a command (CMD), a parity header (PAR_H), and a parity (PAR) in sequence during the third period (T43). If the memory device succeeds in error correction decoding of the control signals (CA[X:0]) received during the third period (T43), it may execute the command (CMD) included in the control signals (CA[X:0]).

[0130] For example, the memory controller can determine which control information has failed based on fail information received from the memory device, and can retransmit the failed control information to the memory device.

[0131] On the other hand, if a failure occurs in a control signal received by the memory device, there is a high probability that subsequent control signals will also fail. For example, if the timing of the control signals (CA[X:0]) and the control clock signal (CA_CLK) becomes misaligned and causes a failure in the control signal, the likelihood of subsequent control signals failing increases.

[0132] In one embodiment, the memory controller can improve the timing margin of the control signals (CA[X:0]) by reducing the frequency of the control signals (CA[X:0]) and the control clock signal (CA_CLK). However, if the frequency of the control signals (CA[X:0]) is reduced, the transmission period of the control signals (CA[X:0]) may be extended, and furthermore, the input / output efficiency of the data signal may be reduced.

[0133] According to an embodiment of the present invention, a memory controller may perform training of a control signal in response to a fail flag received from a memory device before retransmitting a control signal that has failed. Training of a control signal may refer to an operation to improve the timing margin on the control signal bus. For example, the memory controller may delay the control clock signal (CA_CLK) so that the rising edge of the control clock signal (CA_CLK) is located in the middle of the eye pattern of the control signal. For example, training of a control signal may be controlled by a processor (430) such as that described with reference to FIG. 3.

[0134] In one embodiment, the memory controller may start training by transmitting control signals (CA[X:0]) to the memory device during the third period (T43), which include a training command (Training CMD) comprising a command header (CMD_H), a command (CMD), a parity header (PAR_H), and parity (PAR). After transmitting the training command to the memory device, the memory controller transmits a predetermined signal to the memory device through a control signal line, receives a response to the predetermined signal from the memory device through the control signal line, and can control the delay of the control clock signal (CA_CLK) based on the response.

[0135] In one embodiment, a memory controller, e.g., the processor (430) of FIG. 3, can control the second frequency of the control signals (CA[X:0]) and control clock signal (CA_CLK) transmitted in the third period (T43) to be lower than the first frequency of the control signals (CA[X:0]) and control clock signal (CA_CLK) transmitted in the first and second periods (T41, T42). In the example of FIG. 9, the second period (CY2) of the control clock signal (CA_CLK) transmitted in the third period (T43) may be longer than the first period (CY1) of the control clock signal (CA_CLK) transmitted in the first and second periods (T41, T41).

[0136] When the second frequency is lowered, the timing margin may be increased even if the timing is off, and the likelihood of the training command being successfully transmitted to the memory device may be increased. Once the training command is successfully transmitted, the processor (430) can restore the second frequency to the first frequency and perform training.

[0137] Meanwhile, there may be cases where the status read command transmitted to the memory device fails after the control signal fails. If the memory device fails to receive the status read command normally, it may be difficult for the memory device to transmit fail information.

[0138] According to an embodiment of the present invention, a memory controller can obtain fail information by detecting a state in which a memory device has not received a status read command normally, reducing the frequency of a control signal and a control clock signal, and retransmitting the status read command.

[0139] FIG. 10 is a diagram showing the interaction between a memory controller and a memory device according to an embodiment of the present invention.

[0140] The memory device of FIG. 10 may correspond to the memory device (300) described with reference to FIG. 3, and the memory controller of FIG. 10 may correspond to the memory controller (400) described with reference to FIG. 3.

[0141] In step S31, the memory controller may transmit control signals to the memory device. The control signals may be transmitted in parallel through a control signal line, which is a signal line different from the data signals. According to an embodiment of the present invention, the control signals may include at least a command (CMD) and the parity of the command. The control signals may include a command (CMD), an address (ADDR), and the parity of the command and the address.

[0142] In step S32, the memory device receives the control signal through the control signal line and can perform error correction decoding. For example, the memory device can detect and correct errors in the command (CMD) and address (ADDR) using the parity included in the control signal.

[0143] If error correction of at least one of the command (CMD) and address (ADDR) fails, in step S33 the memory device may set a fail flag and store fail information. Additionally, the memory device may ignore the control signal received in step S31.

[0144] Even if a fail flag is set on a memory device, the memory controller may not be able to detect whether a failure has occurred in the memory device until fail information is transmitted to the memory controller.

[0145] In step S34, the memory controller may transmit control signals to the memory device. The memory device may perform error correction decoding of the control signals, but may ignore the control signals if error correction decoding fails or if the command that succeeded in error correction decoding is not a status read command.

[0146] In step S35, the memory controller can detect a state in which there is no response to control signals transmitted thereafter, starting from the control signal transmitted in step S31. For example, the memory controller can detect a timeout state in which no response is received even after a set period has elapsed since transmitting a control signal.

[0147] In step S36, the memory controller may transmit a control signal including a status read command and parity to the memory device. If the memory device successfully receives the status read command, it may transmit fail data to the memory controller in response to the status read command. However, if error correction decoding based on the control signal fails, the memory device may ignore the control signal.

[0148] In step S37, the memory controller, for example, the processor (430) of FIG. 3, can detect a timeout state after transmitting a control signal including the state read command.

[0149] In step S38, the processor (430) can reduce the frequency of the control signal and the control clock signal. And, in step S39, the processor (430) can retransmit the control signal including the status read command to the memory device.

[0150] If the memory device successfully receives the status read command, the memory device may transmit fail data to the memory controller in response to the status read command, as described with reference to FIGS. 8 and 9.

[0152] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention.

Claims

Claim 1 A memory device comprising: one or more first pins; a plurality of second pins; a memory interface circuit that obtains control information from one or more control signals received from the one or more first pins, obtains data from a plurality of data signals received from the plurality of second pins, and obtains a command and parity from the control information by interpreting headers included in the control information; a memory cell array that stores the data; an ECC (Error Correction Circuit) decoder circuit that corrects an error in the command using the parity; and a control circuit that controls the memory device based on the error-corrected command in a reset state of a fail flag. Claim 2 In claim 1, the control circuit is a memory device that sets the fail flag when the error correction of the command fails. Claim 3 In paragraph 2, the control circuit ignores the error correction failed command when the fail flag is set, and ignores the error correction command except when the error correction command is a status read command. Claim 4 In paragraph 2, the control circuit generates state information including the fail flag in response to a state read command when the fail flag is set, and the memory interface circuit outputs one or more control signals including the state information through one or more first pins. Claim 5 A memory device according to claim 1, wherein the memory interface circuit further obtains an address from the control information based on the headers, the ECC decoder circuit further corrects an error in the address using the parity, and the control circuit further uses the error-corrected address to control the memory cell array. Claim 6 In paragraph 5, the control circuit is a memory device that sets the fail flag when at least one of the command and the address fails to error correction. Claim 7 In claim 6, the memory interface circuit generates fail information indicating a command or address that failed to error correction when the fail flag is set, and outputs a response including the fail information through one or more first pins in response to a status read command. Claim 8 In paragraph 5, the control circuit is a memory device that resets the fail flag after the fail information signal is output. Claim 9 In claim 1, a memory device in which the frequency of one or more control signals is lower than the frequency of the plurality of data signals. Claim 10 A memory controller comprises: one or more first pins; a plurality of second pins; a processor that generates a command to control a memory device; a first ECC (Error Correction Code) circuit that generates a first parity by performing error correction encoding on the command; and a controller interface circuit that provides one or more control signals, including the command and the first parity, to the memory device through the one or more first pins, and inputs and outputs data signals to and from the memory device through the plurality of second pins, wherein the controller interface circuit receives a fail signal indicating a failure of the one or more control signals from the memory device and performs training on the one or more control signals in response to the fail signal. Claim 11 In paragraph 10, the processor provides a status read command to the memory device through the one or more first pins after the one or more control signals are output, and the memory controller receives the fail signal as a response to the status read command through the one or more first pins. Claim 12 In claim 11, the processor changes the frequency of a signal output to one or more first pins from a first frequency to a second frequency lower than the first frequency when a response to the status read command is not received within a set period, and retransmits the status read command to the memory device through one or more first pins. Claim 13 In claim 10, the processor is a memory controller that, when the training is completed, retransmits the failed command through the one or more first pins based on the fail information. Claim 14 In claim 10, the memory controller further includes a third pin for outputting a first clock signal for sampling the one or more control signals, and the processor changes the frequency of the one or more control signals and the first clock signal from a first frequency to a second frequency lower than the first frequency, provides a training command to the memory device through the one or more first pins, changes the frequency of the one or more control signals and the first clock signal from the second frequency to the first frequency based on a first response of the memory device to the training command, transmits a predetermined signal to the memory device through the one or more first pins, receives a second response to the signal from the memory device through the one or more first pins, and performs the training by controlling the delay of the first clock signal based on the second response. Claim 15 In claim 10, the processor further generates an address associated with the command, the first ECC circuit further generates a second parity by performing error correction encoding on the address, and the at least one control signal further includes the address and the second parity in the memory controller. Claim 16 In claim 10, the memory controller further comprises a second ECC circuit that performs error correction encoding and error correction decoding for data included in the data signals. Claim 17 A method of operation of a memory device comprising: receiving at least one control signal including a command, an address, and a parity from a controller through at least one control signal line; performing Error Correction Code (ECC) decoding of the command and the address using the parity; setting a fail flag and generating fail information when the error correction of at least one of the command and the address fails; providing a response including the fail information through the at least one control signal line in response to a status read command from the controller and resetting the fail flag; and receiving a training command from the controller and providing a response through the at least one control signal line. Claim 18 In paragraph 17, the above-described operation method further comprises the step of discarding commands excluding the state read command when the above-described fail flag is set. Claim 19 A method of operation according to claim 17, wherein the parity comprises a first parity for the command and a second parity for the address, and the fail information comprises information indicating a command or address that failed to correct an error. Claim 20 In claim 17, the above-described operating method further comprises the step of obtaining the command, the address, and the parity based on a plurality of headers included in the one or more control signals.

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