Puf-based multi-layer security element and method of generating security key comprising the same

Abstract

One embodiment of the present invention is for enhancing the security level by generating a security key using a stacked security element capable of increasing entropy and complexity, and provides a stacked security element and a method for generating a security key using the same, characterized by comprising: a substrate; an electrical PUF layer formed on one side of the substrate; and an optical PUF layer formed on the other side of the substrate.

Description

Technology Field

[0001] The present invention relates to a security device, and more specifically, to a security device based on a PUF.

[0002] The present invention was derived through the following research project.

[0003] [Assignment No.] GRRC Sungkyunkwan 2023-B03

[0004] [Project Management Agency Name] Gyeonggi Regional Cooperation Research Center (GRRC)

[0005] [Research Project Name] Gyeonggi Regional Cooperation Research Center (GRRC) Project

[0006] [Research Project Title] Development of Laser-based Heat Treatment and Etching Process Technology

[0007] [Name of Project Performing Organization] Sungkyunkwan University

[0008] [Project Period] July 1, 2024 – June 30, 2025 Background Technology

[0009] As the Internet of Things (IoT) becomes more widespread, various devices that provide convenience in daily life are emerging. However, with security incidents such as hacking and personal information leaks occurring frequently, resolving these issues has become an essential task.

[0010] To address these challenges, security techniques that utilize the inherent characteristics of the hardware itself are being researched, one of which is the Physical Unclonable Function (PUF), also known as the "Physical Unclonable Function."

[0011] PUF refers to a technology that implements a unique security ID within a chip by utilizing physical variations occurring in semiconductor chips, optical patterns, and nanomaterials during the semiconductor manufacturing process. As such, minute non-uniformities arising during semiconductor manufacturing make perfect replication impossible; even when using identical circuits, mask layouts, and process steps, differences occur in many aspects, ranging from device characteristics like transistors, capacitors, and resistors to circuit characteristics like gate latency. PUF measures these physical variations using electrical, optical, or electromagnetic methods and converts them into unique digital response values.

[0012] In addition, PUF utilizes a CRP (Challenge-Response Pair) structure. This leverages the property that when a specific input value called a challenge value is provided, it always returns the same output value called a response value. Since the value determined in this way outputs the same value every time it is generated, it can be used as unique chip information, and there is no need to store the encryption key separately.

[0013] Unlike conventional methods that required storing cryptographic keys, PUF-based solutions are resistant to reverse engineering attacks because they do not need to store keys. Furthermore, since unique PUF response values ​​can be generated for each semiconductor chip, unduplicateable IDs can be created and used to verify the integrity of hardware devices. Additionally, as a low-power or lightweight security solution, it offers the advantage of being applicable even in resource-constrained environments, such as IoT devices or smart cards.

[0014] However, these PUF technologies present several technical challenges in terms of design and application. Currently, most PUF implementations lack complexity, making them vulnerable to machine learning attacks. In other words, if an attacker collects sufficient Challenge-Response data, they can learn the response patterns within a fixed circuit and predict the PUF's response values. Furthermore, due to low entropy, similar or repetitive response values ​​may be derived for different challenge values. Therefore, these limitations are challenges that must be overcome in designs utilizing PUF technology. Prior art literature

[0015] Republic of Korea Published Patent No. 10-2016-0096462 The problem to be solved

[0016] The technical problem to be solved by the present invention is to provide a PUF-based stacked security device. More specifically, the present invention provides a PUF-based stacked security device capable of exponentially increasing entropy and complexity by utilizing both sides of a substrate, and a method for generating a security key using the same.

[0017] The technical problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art to which the present invention belongs from the description below. means of solving the problem

[0018] To achieve the above technical objective, one embodiment of the present invention provides a stacked security device comprising: a substrate; an electrical PUF layer formed on one surface of the substrate; and an optical PUF layer formed on the other surface of the substrate.

[0019] The above electrical PUF layer may be located on the matte surface of the substrate, and the above optical PUF layer may be located on the glossy surface of the substrate.

[0020] The above electrical PUF layer may be characterized by comprising: a conductive polymer layer; an insulating layer located on the conductive polymer layer; and an electrode layer located on the insulating layer.

[0021] The conductive polymer layer may be characterized by being formed of random patterned PEDOT:PSS clusters.

[0022] The above optical PUF layer may be characterized by having a random pattern formed on the glossy surface of the substrate by a laser ablation method.

[0023] The above-described stacked security element may be characterized by generating a security key by combining the first response value of the electrical PUF layer and the second response value of the optical PUF layer in a stepwise manner.

[0024] Combining the first response value of the electrical PUF layer and the second response value of the optical PUF layer in a stepwise manner may be characterized by generating a security key by combining the third response value obtained by expanding the dimension of the first response value of the electrical PUF layer and the second response value of the optical PUF layer.

[0025] To achieve the above technical objective, another embodiment of the present invention provides a method for generating a security key using a stacked security element, characterized by comprising: a step of deriving a first response value from the electrical PUF layer; a step of deriving a second response value from the optical PUF layer; a step of deriving a third response value by expanding the dimension of the first response value; and a step of combining the third response value and the second response value in a stepwise manner.

[0026] The step of deriving a first response value from the above electrical PUF layer may be characterized by deriving a response value by arbitrarily arranging measurement values ​​obtained by a multiaxial electrode probing method.

[0027] The step of combining the third response value and the second response value may be characterized by performing an XOR operation with respect to the second response value using the third response value as an operand. Effects of the invention

[0028] According to an embodiment of the present invention, the stacked security device of the present invention can exponentially increase entropy and complexity and significantly enhance the security level by utilizing both sides of the substrate and combining the response values ​​of the PUF layers on each side in a stepwise manner.

[0029] The effects of the present invention are not limited to the effects described above, and should be understood to include all effects that can be inferred from the configuration of the invention described in the detailed description of the invention or the claims. Brief explanation of the drawing

[0030] Figures 1 and 2 are schematic diagrams of the structure of a stacked security element of the present invention. Figure 3 is a schematic diagram of the structure of the electrical PUF layer of the present invention. FIG. 4 is a flowchart of a method for generating a security key using a stacked security element of the present invention. Figures 5 and 6 are schematic diagrams of a method for generating a security key using a stacked security element of the present invention. Figures 7 and 8 are schematic diagrams of a multi-axis measurement method for deriving response values ​​from an electrical PUF layer of the present invention. Figure 9 is (a) a graph showing the current and voltage between electrode pairs of the electrical PUF layer and (b) a graph showing the voltage at which the lowest current flows when the electrical PUF layer is measured using a multi-axis measurement method. Figure 10 is a graph measuring the stability of a security key generated using the stacked security element of the present invention. Specific details for implementing the invention

[0031] The present invention will be described below with reference to the attached drawings. However, the present invention may be implemented in various different forms and is therefore not limited to the embodiments described herein. Furthermore, in order to clearly explain the present invention in the drawings, parts unrelated to the explanation have been omitted, and similar parts throughout the specification have been given similar reference numerals.

[0032] Throughout the specification, when it is stated that a part is "connected (connected, in contact, combined)" with another part, this includes not only cases where they are "directly connected," but also cases where they are "indirectly connected" with other members interposed between them. Furthermore, when it is stated that a part "includes" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but rather allows for the inclusion of additional components.

[0033] The terms used herein are merely for describing specific embodiments and are not intended to limit the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, terms such as “comprising” or “having” are intended to indicate the presence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0034] Embodiments of the present invention will be described in detail below with reference to the attached drawings.

[0036] A stacked security element according to one embodiment of the present invention will be described with reference to FIGS. 1 to 3.

[0037] Figures 1 and 2 are schematic diagrams of the structure of a stacked security element of the present invention.

[0038] Figure 3 is a schematic diagram of the structure of the electrical PUF layer of the present invention.

[0039] Referring to FIGS. 1 and 2, a stacked security element according to one embodiment of the present invention may include a substrate (300); an electrical PUF layer (200) formed on one side of the substrate; and an optical PUF layer (400) formed on the other side of the substrate.

[0040] The above electrical PUF layer (200) may be characterized by being located on the matte surface of the substrate (300), and the above optical PUF layer (400) may be located on the glossy surface of the substrate (300).

[0041] The above substrate (300) is characterized by utilizing both sides and may include silicon (Si) or silicon oxide (Si / SiO2), etc. However, it is not limited to the above examples.

[0042] For example, the substrate (300) according to the present invention may be a silicon oxide film (Si / SiO2).

[0043] The above electrical PUF layer (200) can be located on the matte surface of the substrate.

[0044] Referring to FIG. 3, the electrical PUF layer (200) may be characterized by comprising: a conductive polymer layer (210); an insulating layer (220) located on the conductive polymer layer (210); and an electrode layer (230) located on the insulating layer (220).

[0045] The conductive polymer layer (210) may be characterized by being formed of randomly patterned PEDOT:PSS clusters. The randomly arranged PEDOT:PSS serves to distinguish between '0' and '1' electrical characteristics that vary depending on whether the electrode layers (230) are connected.

[0046] The above conductive polymer layer (210) has the effect of reducing predictability because the position, size, shape, thickness, etc. of the randomly arranged PEDOT:PSS cluster are not standardized.

[0047] The insulating layer (220) may be located on the conductive polymer layer (210).

[0048] The insulating layer (220) is characterized by blocking the flow of current and may include SU-8, Al2O3, or HfO2, etc. However, it is not limited to the above examples.

[0049] For example, the insulating layer (220) in the present invention may be SU-8.

[0050] The insulating layer (220) serves to determine whether the electrode layers (230) are connected by restricting the flow of current only to the desired area. The connection between the electrode layers (230) may be characterized by being connected only in the parts where the insulating layer (220) is absent, and in this case, whether the electrode layers (230) are connected may be determined by whether a polymer is located between the holes of the insulating layer (220).

[0051] The electrode layer (230) may be located on the insulating layer (220).

[0052] The electrode layer (230) may be made of common metals used as electrodes, such as Ti / Au, Ni, and Al, and is not limited to the above examples.

[0053] For example, the electrode layer (230) according to the present invention may be Ti / Au.

[0054] The electrode layer (230) serves to measure and verify electrical characteristics. '1' signifies an electrically connected case, and since current flows easily in this case, the current can increase linearly with increasing voltage. '0' signifies an electrically unconnected case, and since the resistance is high and the flow of current is restricted in this case, the current flow may not move around 0 V due to the reverse electric field. A random key of the electrical PUF layer (200) can be formed using the '1' and '0' distinguished through these electrical characteristics. Additionally, complexity can be increased by making it impossible to physically distinguish between '0' and '1' as the exact location of the hole in the insulating layer (220) is obscured by the electrode layer (230).

[0055] The optical PUF layer (400) may be located on the glossy surface of the substrate (300).

[0056] The optical PUF layer (400) may be characterized by forming a random crater pattern on the glossy surface of the substrate (300) using a laser ablation method.

[0057] The stacked security element of the present invention may be characterized by generating a security key by cascading the first response value of the electrical PUF layer (200) and the second response value of the optical PUF layer (400).

[0058] In order to combine the first response value of the electrical PUF layer and the second response value of the optical PUF layer in a stepwise manner, the dimension of the first response value is expanded to obtain a third response value, and then the third response value and the second response value are combined to generate a security key.

[0059] By extending the dimension of the first response value to the third response value and combining it stepwise with the second response value, the response values ​​of the two PUF layers are connected to a single CRP mechanism, thereby maximizing entropy and increasing security strength.

[0061] Referring to FIGS. 4 to 8, a method for generating a security key using a stacked security element according to another embodiment of the present invention will be described.

[0062] FIG. 4 is a flowchart of a method for generating a security key using a stacked security element of the present invention.

[0063] Figures 5 and 6 are schematic diagrams of a method for generating a security key using a stacked security element of the present invention.

[0064] Figures 7 and 8 are schematic diagrams of a multi-axis measurement method for deriving response values ​​from an electrical PUF layer of the present invention.

[0065] Referring to FIGS. 4 to 6, a method for generating a security key using a stacked security element according to an embodiment of the present invention may include: a step of deriving a first response value from the electrical PUF layer (200); a step of deriving a second response value from the optical PUF layer (400); a step of deriving a third response value by expanding the dimension of the first response value; and a step of combining the third response value and the second response value.

[0066] Referring to FIGS. 7 and 8, the step of deriving a first response value from the electrical PUF layer (200) may be characterized by deriving a response value by arbitrarily listing measurement values ​​by multiaxial electrode probing.

[0067] The challenge value of the above electrical PUF layer can be generated by a random number generator, but is not limited to the above example.

[0068] The above multiaxial electrode probing method refers to a method of measuring by connecting electrodes in four different conversion methods, which may be horizontal (H), vertical (V), diagonal from the top left to the bottom right (Diagonal 1, D1), and diagonal from the top right to the bottom left (Diagonal 2, D2). In this case, the H and V methods may be 90 bits, and the D1 and D2 methods may be 81 bits. Each bit may represent data measured from a pair of electrode layers (230).

[0069] The above multi-axis measurement method may be characterized by modifying the challenge value by arbitrarily rearranging each quarter bit of the challenge value into a single conversion method.

[0070] At this time, the computational complexity for obtaining the above challenge value can be expressed as follows. O represents the approximate rate of increase of the amount of computation.

[0071] [Equation 1]

[0072]

[0073] In the step of deriving the first response value from the electrical PUF layer (200), by measuring in the four ways and arranging them randomly in sequential order, the complexity of the stacked security element is greatly increased and the security strength is increased.

[0074] The step of deriving a second response value from the optical PUF layer (400) may be characterized by using a CCD sensor (500). However, it is not limited to the above example.

[0075] The step of deriving a second response value from the optical PUF layer (400) can convert an optical random pattern into digital data using the CCD sensor (500). At this time, the CCD sensor (500) may be characterized by detecting an optical random pattern formed on the glossy surface of the substrate using a laser ablation method, converting such an analog signal into a voltage signal, and then converting it again into '0' and '1'.

[0076] At this time, the number of bits of the second response value can be expressed as follows. N represents the number of bits of the second response value, N1 represents the number of horizontal bits, and N2 represents the number of vertical bits.

[0077] [Equation 2]

[0078]

[0079] At this time, the computational complexity for the second response value can be expressed as follows, as a combination of optical challenge values ​​that must be searched to obtain the second response value.

[0080] [Equation 3]

[0081]

[0082] The step of deriving a third response value by expanding the dimension of the first response value may be characterized by expanding it to combine it cascadedly with the second response value derived from the optical PUF layer (400).

[0083] The optical layer (400) can freely set the number of bits according to the resolution for detecting images, but since the number of bits that the electrical PUF layer (200) can have is limited, the first response value has a lower absolute number of pixels compared to the second response value. Therefore, it can be characterized by combining in a stepwise manner by expanding the dimension to match the number of bits so that the complexity of the bits is not lost. At this time, the first response value can be expanded to a larger dimension, such as 3x3 or 4x4, to obtain high entropy while satisfying the NIST TEST, but is not limited to the above examples.

[0084] For example, the third response value according to the present invention can extend the dimension of the first response value to a 4x4 form.

[0085] By extending the dimension of the first response value to derive the third response value, the loss of entropy that can be obtained from the operation between the second response value derived from the optical PUF layer (400) and the response value derived from the electrical PUF layer (200) with a low absolute pixel count can be minimized.

[0086] The step of combining the third response value and the second response value may be characterized by performing an XOR operation with respect to the second response value using the third response value as an operand.

[0087] In the step of combining the third response value and the second response value, the third response value acts as an operand, and the response values ​​of the two PUF layers are connected to a single CRP mechanism, thereby maximizing entropy and increasing security strength.

[0088] In this case, the overall computational complexity obtained by combining the second and third response values ​​and connecting them into a single CRP mechanism can be expressed as follows. O represents the approximate rate of increase of the amount of computation, and N represents the number of bits of the stepwise combined response values.

[0089] [Equation 4]

[0090]

[0092] <Manufacturing Example 1> Method for forming an electrical PUF layer

[0093] A PEDOT solution was coated onto a matte surface of a substrate (Si / SiO2) under specific conditions. Subsequently, a glass plate with a random stain pattern created by spraying ink was positioned on the PEDOT-coated substrate at a distance of 1 mm. The PEDOT-coated substrate was irradiated with an IR laser at various angles, such as 0, 33, and 66 degrees. SU-8 was deposited on the PEDOT-coated substrate irradiated with the IR laser and patterned to be partially connected to the top electrode. A Ti / Au top electrode was deposited using an E-beam evaporator and then etched to form an electrical PUF layer.

[0095] <Manufacturing Example 2> Method for manufacturing an optical PUF layer

[0096] A crater was formed by randomly irradiating an IR laser onto the glossy surface of a substrate (Si / SiO2). At this time, laser conditions were optimized and applied such that the bit uniformity converged to 0.5.

[0097] <Experimental Example 1> Experiment to measure the electrical difference between '0' and '1' in an electrical PUF layer

[0098] Figure 9a is a graph showing the current and voltage measured between electrode pairs of the electrical PUF layer. The voltage was applied from -1 to 1 V, and the current was measured. Electrical characteristics varied depending on the random distribution of PEDOT in the conductive polymer layer, and '0' and '1' were extracted based on this. The light green line represents bit '1', and the cyan line represents bit '0'.

[0099] Referring to Fig. 9a, it was confirmed that current flows well in the case of the light green line because the electrodes are connected, and in the case of the cyan line because the electrodes are not connected well, it was confirmed that almost no current flows.

[0100] Figure 9b is a graph showing the voltage at which the lowest current flows when the electrical PUF layer is measured using a multi-axis measurement method. The voltage at which the lowest current flows was indicated by measuring 342 electrode pairs using a multi-axis measurement method.

[0101] Referring to Fig. 9b, it was confirmed that the electrode pairs were electrically connected when the voltage at which the lowest current flows was 0 V, and were not electrically connected when it was not 0 V. Therefore, when distinguishing between the actual '0' and '1', a response value was formed based on the corresponding electrical data graph.

[0103] <Experimental Example 2> Experiment on measuring the stability of a security key generated using a stacked security device

[0104] Figure 10 is a graph measuring the security of a security key generated using the stacked security element of the present invention. Bit uniformity and entropy were evaluated for 30 challenge values ​​using 8 stacked security elements in a multi-axis measurement method.

[0105] Referring to FIG. 10, bit uniformity is highest when '0' and '1' exist in a ratio of 5 to 5, i.e., 0.5, and the closer the entropy is to 1, the more difficult the degree of randomness to predict. The bit uniformity of the security device of the present invention converged to 0.5 and the entropy converged to 1, and the same result was obtained when a second measurement was taken for re-evaluation. It was confirmed that the security device of the present invention can generate a security key that is difficult to predict, and stability was confirmed through the fact that the same result was obtained even upon re-measurement.

[0107] The above-described stacked security device utilizes both sides of the substrate as an electrical PUF layer and an optical PUF layer, respectively, and by combining response values ​​derived from each PUF layer in a stepwise manner, it can maximize entropy and improve encoding capacity by superimposing the randomness of the electrical PUF layer and the randomness of the optical PUF layer, and can strengthen the security level by exponentially increasing complexity.

[0109] The foregoing description of the present invention is for illustrative purposes only, and those skilled in the art will understand that other specific forms can be easily modified without altering the technical spirit or essential features of the present invention. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive. For example, each component described as a single unit may be implemented in a distributed manner, and components described as distributed may likewise be implemented in a combined form.

[0110] The scope of the present invention is defined by the claims set forth below, and all modifications or variations derived from the meaning and scope of the claims and equivalent concepts thereof should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0111] 100: IC chip 200: Electrical PUF layer 210: Conductive polymer layer 220: Insulating layer 230: Electrode layer 300: Substrate 400: Optical PUF layer 500: CCD sensor

Claims

Claim 1 A stacked security device characterized by comprising: a substrate; an electrical PUF layer formed on one side of the substrate; and an optical PUF layer formed on the other side of the substrate. Claim 2 A stacked security device according to claim 1, characterized in that the electrical PUF layer is located on the matte surface of the substrate and the optical PUF layer is located on the glossy surface of the substrate. Claim 3 A stacked security device according to claim 1, wherein the electrical PUF layer comprises: a conductive polymer layer; an insulating layer located on the conductive polymer layer; and an electrode layer located on the insulating layer. Claim 4 A stacked security device according to claim 3, wherein the conductive polymer layer is formed of random patterned PEDOT:PSS clusters. Claim 5 A stacked security device according to claim 1, characterized in that the optical PUF layer has a random pattern formed on the glossy surface of the substrate by a laser ablation method. Claim 6 A stacked security device according to claim 1, characterized by generating a security key by combining the first response value of the electrical PUF layer and the second response value of the optical PUF layer in a stepwise manner. Claim 7 In claim 6, the stacked security device is characterized by combining the first response value of the electrical PUF layer and the second response value of the optical PUF layer in a stepwise manner by combining the third response value obtained by expanding the dimension of the first response value of the electrical PUF layer and the second response value of the optical PUF layer to generate a security key. . Claim 8 A method for generating a security key using a stacked security element according to claim 1, comprising: a step of deriving a first response value from an electrical PUF layer; a step of deriving a second response value from an optical PUF layer; a step of deriving a third response value by expanding the dimension of the first response value; and a step of combining the third response value and the second response value. Claim 9 A method for generating a security key using a stacked security element, wherein, in claim 8, the step of deriving a first response value from the electrical PUF layer is characterized by deriving a response value by randomly arranging measurement values ​​by a multiaxial electrode probing method. Claim 10 A method for generating a security key using a stacked security element, wherein, in claim 8, the step of combining the third response value and the second response value is characterized by performing an XOR operation with respect to the second response value using the third response value as an operand.

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