Flexible film and chip on film comprising same

Abstract

One embodiment of the present invention provides a flexible film comprising: a base film; wiring patterns disposed on an upper surface of the base film; and a lower metal layer disposed on a lower surface corresponding to the opposite side of the upper surface of the base film, wherein the lower metal layer is disposed over the entire lower surface of the base film.

Description

Technology Field

[0001] The present invention relates to a flexible film with improved heat dissipation properties and a chip-on-film comprising the same. Background Technology

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. Various display devices, such as Liquid Crystal Displays (LCDs) and Light Emitting Displays (LEDs), are being utilized. Among these, light-emitting displays can be classified into organic light-emitting displays that use organic light-emitting diodes as light-emitting elements, and light-emitting diode displays that use micro light-emitting diodes as light-emitting elements.

[0003] The display device comprises a display panel including data lines, scan lines, and a plurality of pixels connected to the data lines and scan lines, a scan driving circuit that supplies scan signals to the scan lines, and a data driving circuit that supplies data voltages to the data lines. Accordingly, each of the plurality of pixels receives a data voltage of the data line when a scan line is applied, and emits light with a predetermined brightness according to the applied data voltage.

[0004] The scan driving circuit and the data driving circuit may be formed as a drive integrated circuit (hereinafter referred to as "drive IC"). In this case, the scan driving circuit and the data driving circuit may be attached to a flexible film. A structure in which the drive integrated circuit is placed on a flexible film may be named a chip on film.

[0005] Conventionally, thermal tape was attached to dissipate heat from the chip-on-film, but problems arose during the attachment process, such as the tape lifting or the bending ability of the flexible film being reduced due to the attachment of the thermal tape.

[0006] Recently, research aimed at improving heat dissipation characteristics without attaching thermal tapes has been continuously conducted. The problem to be solved

[0007] One embodiment of the present invention aims to provide a flexible film with improved heat dissipation characteristics by placing a lower metal layer over the entire lower surface of a base film.

[0008] One embodiment of the present invention aims to provide a chip-on-film with improved heat dissipation characteristics by disposing of a lower metal layer over the entire lower surface of a base film. means of solving the problem

[0009] One embodiment of the present invention for achieving the aforementioned technical problem provides a flexible film comprising: a base film; wiring patterns disposed on an upper surface of the base film; and a lower metal layer disposed on a lower surface corresponding to the opposite side of the upper surface of the base film, wherein the lower metal layer is disposed over the entire lower surface of the base film.

[0010] Another embodiment of the present invention provides a chip-on-film comprising: a flexible film; and a driving integrated circuit disposed on the flexible film; wherein the flexible film comprises: a base film; wiring patterns disposed on an upper surface of the base film; and a lower metal layer disposed on a lower surface corresponding to the opposite side of the upper surface of the base film, wherein the lower metal layer is disposed over the entire lower surface of the base film and the driving integrated circuit is disposed on the wiring patterns. Effects of the invention

[0011] A flexible film according to one embodiment of the present invention can have improved heat dissipation characteristics by arranging a lower metal layer over the entire lower surface of a base film.

[0012] In another embodiment of the present invention, the heat dissipation characteristics of the chip-on-film can be improved by placing the lower metal layer over the entire lower surface of the base film.

[0013] In addition to the effects mentioned above, other features and advantages of the present invention are described below, or will be clearly understood by those skilled in the art from such description and explanation. Brief explanation of the drawing

[0014] FIG. 1 is a perspective view showing a display device according to one embodiment of the present invention. FIG. 2 is a plan view showing a chip-on-film according to one embodiment of the present invention. FIG. 3 is a rear view showing a chip-on-film according to one embodiment of the present invention. Figure 4 is a cross-sectional view taken along I-I' of Figure 2. Specific details for implementing the invention

[0015] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to make the disclosure of the present invention complete and to inform those skilled in the art of the scope of the invention.

[0016] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining embodiments of the present invention are exemplary, and therefore the present invention is not limited to the matters shown in the drawings. Throughout the specification, identical components may be referred to by the same reference numerals. Furthermore, in describing the present invention, if it is determined that a detailed description of related known technology may unnecessarily obscure the essence of the present invention, such detailed description is omitted.

[0017] Where terms such as 'comprising,' 'having,' 'consisting of,' etc. are used in this specification, other parts may be added unless the expression 'only' is used. Where a component is expressed in the singular, it includes the plural unless specifically stated otherwise.

[0018] In interpreting the components, they are interpreted to include a margin of error even in the absence of a separate explicit statement.

[0019] For example, when the positional relationship between two parts is described using expressions such as 'on,' 'upper,' 'lower,' or 'next to,' one or more other parts may be located between the two parts unless expressions such as 'immediately' or 'directly' are used.

[0020] Spatially relative terms such as "below" or "beneath," "lower," "above," and "upper" may be used to facilitate the description of the relationship between one element or component and another, as illustrated in the drawings. Spatially relative terms should be understood as terms that include different orientations of the element during use or operation, in addition to the orientations illustrated in the drawings. For example, if an element illustrated in the drawings is flipped, an element described as "below" or "beneath" of another element may be placed "above" of that other element. Therefore, the exemplary term "below" may include both the lower and upper directions. Similarly, the exemplary terms "above" or "upper" may include both the upper and lower directions.

[0021] In the case of an explanation of a temporal relationship, for example, when the temporal sequence is explained using expressions such as 'after', 'following', 'next', or 'before', it may include cases where the sequence is not continuous unless expressions such as 'immediately' or 'directly' are used.

[0022] Although terms such as "first," "second," etc. are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the technical scope of the present invention.

[0023] The term “at least one” should be understood to include all combinations that can be presented from one or more related items. For example, the meaning of “at least one of the first item, the second item, and the third item” may mean not only the first item, the second item, or the third item individually, but also all combinations of items that can be presented from two or more of the first item, the second item, and the third item.

[0024] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0025] In assigning reference numerals to the components of each drawing describing the embodiments of the present invention, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings.

[0026] FIG. 1 is a perspective view showing a display device (1000) according to one embodiment of the present invention.

[0027] Referring to FIG. 1, a display device (1000) according to one embodiment of the present specification includes a display panel (1100), driving integrated circuits (300), flexible films (20), a source circuit board (1400), a flexible cable (1500), a control circuit board (1600), a timing control unit (1700), and a voltage supply unit (1800).

[0028] The display panel (1100) may include a lower substrate (1110) and an upper substrate (1120). The lower substrate (1110) may be formed of a glass substrate or a plastic film, and the upper substrate (1120) may be formed of a glass substrate, a plastic film, an encapsulation film, or a barrier film.

[0029] The display panel (1100) includes a display area and a non-display area provided around the display area. The display area is an area where pixels are formed to display an image. The display panel (1100) is provided with intersecting data lines and scan lines, and each pixel can be connected to either of the data lines and either of the scan lines. The display panel (1100) can be implemented as a liquid crystal display panel or an organic light-emitting display panel.

[0030] Driving integrated circuits (300) can be attached to each of the flexible films (20). The driving integrated circuits (300) can be attached to the flexible film (20) to form a chip-on-film (101). According to one embodiment of the present invention, the driving integrated circuits (300) can correspond to the chips of the chip-on-film (101).

[0031] The flexible film (20), driving integrated circuit (300), and chip-on-film (101) are described in detail in FIGS. 2 and 3.

[0032] Each flexible film (20) can be attached to a lower substrate (1110) and a source circuit board (1400). Each flexible film (20) can be attached to the lower substrate (1110) using an anisotropic conductive film via tape automated bonding (TAB), thereby allowing each driving integrated circuit (300) to be connected to the data lines of the display panel (1100).

[0033] Each driving integrated circuit (300) supplies data voltages to the data lines. Each driving integrated circuit (300) receives digital video data and a data timing control signal from the timing control unit (1700). Each driving integrated circuit (300) converts the digital video data into data voltages according to the data timing control signal and applies them to the data lines.

[0034] The display panel (1100) may include a scan driver that is connected to scan lines and applies scan signals. The scan driver generates scan signals according to a scan timing control signal input from a timing control unit (1700) and applies them to the scan lines. In this case, the scan driver may be formed in a non-display area of ​​the display panel (1100) in a GIP (Gate driver In Panel) manner, including a plurality of transistors. Alternatively, the scan driver may be formed in the form of a driving integrated circuit and mounted on a gate flexible film attached to the lower substrate (1110) of the display panel (1100).

[0035] The source circuit board (1400) may include first connectors (1510) for connecting to first flexible cables (1500). The source circuit board (1400) may be connected to the first flexible cables (1500) through the first connectors (1510). The source circuit board (1400) may be a flexible printed circuit board or a printed circuit board.

[0036] The control circuit board (1600) may include second connectors (1520) for connecting to first flexible cables (1500). The control circuit board (1600) may be connected to the first flexible cables (1500) through the second connectors (1520). In FIG. 1, the source circuit board (1400) and the control circuit board (1600) are illustrated as being connected to a plurality of first flexible cables (1500) through a plurality of first connectors (1510) and a plurality of second connectors (1520), but the embodiments of the present specification are not limited thereto. That is, each of the source circuit board (1400) and the control circuit board (1600) may be connected to a single first flexible cable (1500) through one first connector (1510) and one second connector (1520).

[0037] The timing control unit (1700) receives digital video data and timing signals from an external system-on-chip. The timing signals may include a vertical sync signal, a horizontal sync signal, a data enable signal, and a dot clock.

[0038] The timing control unit (1700) generates control signals to control the operation timing of the driving integrated circuits (300) and the scan driving unit. The control signals include a data timing control signal for controlling the operation timing of the driving integrated circuits (300) and a scan timing control signal for controlling the operation timing of the scan driving unit. The timing control unit (1700) supplies the data timing control signal and digital video data to the driving integrated circuits (300) and supplies the scan timing control signal to the scan driving unit.

[0039] The voltage supply unit (1800) generates various driving voltages from a main power supply applied from the outside and supplies them to the display panel (1100), the scan driving unit, and the driving integrated circuit (300).

[0040] The timing control unit (1700) and the voltage supply unit (1800) may be mounted on the control circuit board (1600). In this case, the timing control unit (1700) and the voltage supply unit (1800) may be formed in the form of a driving integrated circuit. The control circuit board (1600) may be a flexible printed circuit board or a printed circuit board.

[0041] FIG. 2 is a plan view showing a chip-on-film (101) according to one embodiment of the present invention. FIG. 3 is a rear view showing a chip-on-film (101) according to one embodiment of the present invention. FIG. 4 is a cross-sectional view taken along I-I' of FIG. 2.

[0042] Referring to FIGS. 1 to 4, a chip-on-film (101) according to one embodiment of the present invention may include a flexible film (20), a driving integrated circuit (300), and a bump (150).

[0043] According to one embodiment of the present invention, the flexible film (20) may include a base film (100), wiring patterns (110), a lower metal layer (120), a first solder resist layer (130), a second solder resist layer (140), vias (160), and metal pads (170).

[0044] According to one embodiment of the present invention, the base film (100) may be formed from a plastic film. For example, the base film (100) may be a sheet or film comprising, but is not limited to, a cellulose resin such as TAC (triacetyl cellulose) or DAC (diacetyl cellulose), a COP (cycloolefin polymer) or COC (cycloolefin copolymer) such as norbornene derivatives, an acrylic resin such as PMMA (poly(methylmethacrylate), a polyolefin such as PC (polycarbonate), PE (polyethylene) or PP (polypropylene), a PVA (polyvinyl alcohol), PES (poly ether sulfone), PEEK (polyetheretherketone), PEI (polyetherimide), PEN (polyethylenenaphthalate), PET (polyethyleneterephthalate), PI (polyimide), PSF (polysulfone), or a fluoride resin.

[0045] According to one embodiment of the present invention, wiring patterns (110) are disposed on the upper surface of a base film (100). The wiring patterns (110) may include first wiring patterns (110a) having ground wiring or power wiring and a remainder of second wiring patterns (110b). The first wiring patterns (110a) may consist of ground wiring or power wiring.

[0046] The wiring patterns (110) may include a metallic material with excellent electrical conductivity. For example, the wiring patterns (110) may include copper (Cu). However, the present invention is not limited thereto, and the wiring patterns (110) may include at least one metal among copper (Cu), aluminum (Al), chromium (Cr), nickel (Ni), silver (Ag), molybdenum (Mo), gold (Au), titanium (Ti), and alloys thereof.

[0047] One end of the wiring patterns (110) may be connected to a driving integrated circuit (300), and the other end may be connected to metal pads (170). Specifically, the wiring patterns (110) may be formed from the metal pads (170) to the driving integrated circuit (300).

[0048] Referring to FIG. 2, the metal pad (170) may include a first metal pad (170a) and a second metal pad (170b). The first metal pad (170a) may be connected to the first wiring patterns (110a), and the second metal pad (170b) may be connected to the second wiring patterns (110b).

[0049] According to one embodiment of the present invention, the ground wiring may be any one of VSSH ground wiring, VSSD ground wiring, and VSSA ground wiring. For example, the ground wiring of the first wiring patterns (110a) may be VSSH ground wiring or VSSD ground wiring. A ground voltage is applied to the ground wiring from the source circuit board (1400).

[0050] According to one embodiment of the present invention, the power wiring may include at least one of VDDH power wiring, VCCD power wiring, and VCCA power wiring. Power voltage is applied to the power wiring from a source circuit board (1400).

[0051] In other words, the first wiring patterns (110a) according to one embodiment of the present invention may be any one of VSSH ground wiring, VSSD ground wiring, VSSA ground wiring, VDDH power wiring, VCCD power wiring and VCCA power wiring.

[0052] According to one embodiment of the present invention, the lower metal layer (120) may be disposed on the lower surface corresponding to the opposite side of the upper surface of the base film (100). Specifically, the base film (100) may be disposed between the wiring patterns (110) and the lower metal layer (120).

[0053] According to one embodiment of the present invention, the lower metal layer (120) may be disposed over the entire lower surface of the base film (100). Specifically, the lower metal layer (120) may have the same area as the base film (100) in a planar manner. The lower metal layer (120) may overlap with the metal pads (170) in a planar manner.

[0054] According to one embodiment of the present invention, each of the vias (160) penetrating the base film (100) can connect one of the wiring patterns (110) with the lower metal layer (120). Specifically, at least one of the first wiring patterns (110a) having ground wiring or power wiring can be connected to the lower metal layer (120) through the vias (160).

[0055] Since the ground wiring and power wiring are the wirings that generate the most heat, by connecting the first wiring pattern (110a) including the ground wiring or power wiring and the lower metal layer (120) through vias (160), the heat generated in the driving integrated circuit (300) is transferred to the lower metal layer (120) so that heat can be efficiently dissipated.

[0056] According to one embodiment of the present invention, the second wiring patterns (110b) may not be connected to the lower metal layer (120). Specifically, the second wiring patterns (110b) are not connected to the lower metal layer (120) through vias (160). More specifically, the second wiring patterns (110b) and the lower metal layer (120) are spaced apart from each other with a base film (100) in between.

[0057] According to one embodiment of the present invention, the lower metal layer (120) may be a heat dissipation layer. For example, the lower metal layer (120) may include at least one of copper (Cu) and aluminum (Al). The lower metal layer (120) may be made of the same material as the wiring patterns (110) or may be made of a different material.

[0058] According to one embodiment of the present invention, the first solder resist layer (130) may be formed to cover the upper surface of the wiring patterns (110). The first solder resist layer (130) may be a layer formed of solder resist.

[0059] According to one embodiment of the present invention, the second solder resist layer (140) may be formed to cover the lower surface of the lower metal layer (120). The second solder resist layer (140) may be made of the same material as the first solder resist layer (140).

[0060] According to one embodiment of the present invention, vias (160) can penetrate the base film (100). Specifically, each of the vias (160) can connect one of the wiring patterns (110) with the lower metal layer (120). The vias (160) may be made of the same material as the wiring patterns (110) and the lower metal layer (120), or they may be made of a different material.

[0061] According to one embodiment of the present invention, metal pads (170) may be arranged in a planar manner on the outermost edge of a base film (100). The metal pads (170) may be spaced apart from each other. The metal pads (170) may each be connected to wiring patterns (110). Specifically, the metal pads (170) may each be connected to a driving integrated circuit (300) through wiring patterns (110). Accordingly, communication between the driving integrated circuit (300) and an external device and power supply to the driving integrated circuit (300) may be achieved.

[0062] According to one embodiment of the present invention, a driving integrated circuit (300) may be disposed on a flexible film (20). Specifically, the driving integrated circuit (300) may be connected to a wiring pattern (110) of the flexible film (20) through a bump (150). The driving integrated circuit (300) may be disposed on the wiring pattern (110) of the flexible film (20). According to one embodiment of the present invention, a lower metal layer (120) may overlap with the driving integrated circuit (300) in a planar manner.

[0063] Generally, when a chip-on-film is in operation, the temperature of the chip-on-film may rise due to heat generated by the driving integrated circuit, and this may degrade the driving characteristics of the chip-on-film.

[0064] Accordingly, the flexible film (20) and the chip-on-film (101) according to one embodiment of the present invention may include a lower metal layer (120) disposed over the entire lower surface of the base film (100).

[0065] The wiring patterns (110), vias (160), and lower metal layer (120) may comprise the same material. Additionally, any one of the first wiring patterns (110a), the via (160), and the lower metal layer (120) may be integrally formed.

[0066] By placing a lower metal layer (120) over the entire lower surface of the base film (100), the efficiency of transferring heat generated from the driving integrated circuit (300) to the lower metal layer (120) can be improved.

[0067] Specifically, as the first wiring pattern (110a) having ground wiring or power wiring and the lower metal layer (120) are connected by vias (160), heat generated in the driving integrated circuit (300) can be transferred to the lower metal layer (120) to efficiently dissipate heat.

[0068] According to one embodiment of the present invention, a plurality of vias (160) may be arranged in any one of the first wiring patterns (110a). FIG. 2 illustrates a configuration in which a plurality of vias (160) are arranged in one first wiring pattern (110a). Through this, heat generated in the driving integrated circuit (300) can be transferred to the outside more efficiently.

[0069] The present invention described above is not limited by the aforementioned embodiments and attached drawings, and it will be obvious to those skilled in the art that various substitutions, modifications, and changes are possible within the scope of the technical aspects of the present invention. Therefore, the scope of the present invention is defined by the claims set forth below, and all modifications or variations derived from the meaning, scope, and equivalent concepts of the claims should be interpreted as being included within the scope of the present invention. Explanation of the symbols

[0070] 20: Flexible film 101: Chip on Film 100: Base film 110: Wiring pattern (110) 120: Lower metal layer (120) 130: First solder resist layer 140: Second solder resist layer (140) 150: Bump 160: Via 170: Metal pad 300: Driving integrated circuit

Claims

Claim 1 A flexible film comprising: a base film; wiring patterns disposed on an upper surface of the base film; and a lower metal layer disposed on a lower surface corresponding to the opposite side of the upper surface of the base film, wherein the lower metal layer is disposed over the entire lower surface of the base film. Claim 2 A flexible film according to claim 1, further comprising vias penetrating the base film, wherein each of the vias connects any one of the wiring patterns to the lower metal layer. Claim 3 A flexible film according to claim 1, further comprising vias penetrating the base film, wherein the wiring patterns include first wiring patterns having ground wiring or power wiring and a remainder of second wiring patterns, and at least one of the first wiring patterns is connected to the lower metal layer through the vias. Claim 4 In paragraph 3, the ground wiring is a flexible film that is any one of VSSH ground wiring, VSSD ground wiring, and VSSA ground wiring. Claim 5 In paragraph 3, the power wiring comprises at least one of VDDH power wiring, VCCD power wiring, and VCCA power wiring, a flexible film. Claim 6 In paragraph 3, the second wiring patterns and the lower metal layer are a flexible film spaced apart from each other with the base film in between. Claim 7 In claim 1, the wiring patterns and the lower metal layer each comprise at least one of copper and aluminum, forming a flexible film. Claim 8 A chip-on-film comprising: a flexible film; and a driving integrated circuit disposed on the flexible film; wherein the flexible film comprises: a base film; wiring patterns disposed on an upper surface of the base film; and a lower metal layer disposed on a lower surface corresponding to the opposite side of the upper surface of the base film, wherein the lower metal layer is disposed over the entire lower surface of the base film, and the driving integrated circuit is disposed on the wiring patterns. Claim 9 In claim 8, the lower metal layer overlaps with the driving integrated circuit, forming a chip-on-film. Claim 10 A chip-on-film according to claim 8, further comprising vias penetrating the base film, wherein each of the vias connects any one of the wiring patterns to the lower metal layer. Claim 11 A chip-on-film according to claim 8, further comprising vias penetrating the base film, wherein the wiring patterns include first wiring patterns having ground wiring or power wiring and a remainder of second wiring patterns, and at least one of the first wiring patterns is connected to the lower metal layer through the vias. Claim 12 In claim 11, the ground wiring is any one of VSSH ground wiring, VSSD ground wiring and VSSA ground wiring, and the power wiring comprises at least one of VDDH power wiring, VCCD power wiring and VCCA power wiring, a chip-on-film.

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