Semiconductor device

Abstract

A semiconductor device may include: an active structure having an active pattern extending in a first direction parallel to the upper surface of the substrate on a substrate, and an epitaxial pattern disposed on the sidewalls of each of the two ends of the active pattern in the first direction, wherein the bottom surface is disposed at the same height as the bottom surface of the active pattern and comprises a single-crystal semiconductor material; a gate structure embedded on the upper part of the active structure; a bit line structure disposed on the central part of the active structure in the first direction; a contact plug structure disposed on each of the two ends of the active structure; and a capacitor disposed on the contact plug structure.

Description

Technology Field

[0001] The present invention relates to a semiconductor device. More specifically, the present invention relates to a DRAM device. Background Technology

[0002] A DRAM device includes an active pattern extending in a certain direction on a substrate, and a contact plug structure is disposed between a source / drain region formed on the active pattern and a capacitor to electrically connect them. Accordingly, the connection state between the contact plug structure and the active pattern may affect the electrical characteristics of the DRAM device. The problem to be solved

[0003] One objective of the present invention is to provide a semiconductor device having improved electrical characteristics.

[0004] Another objective of the present invention is to provide a method for manufacturing a semiconductor device having improved electrical characteristics. means of solving the problem

[0005] A semiconductor device according to exemplary embodiments for achieving the above-mentioned objective may include: an active structure having an active pattern extending in a first direction parallel to the upper surface of the substrate, and an epitaxial pattern disposed on the sidewalls of each of the two ends of the active pattern in the first direction, wherein the bottom surface is disposed at the same height as the bottom surface of the active pattern and comprises a single-crystal semiconductor material; a gate structure embedded in the upper portion of the active structure; a bit line structure disposed on the central portion of the active structure in the first direction; a contact plug structure disposed on each of the two ends of the active structure; and a capacitor disposed on the contact plug structure.

[0006] A semiconductor device according to other embodiments for achieving the above-mentioned objective comprises: active patterns arranged on a substrate, each having an epitaxial pattern disposed on the first sidewalls of each active pattern, each having a curved shape and each having a first sidewall that extends in a first direction parallel to the upper surface of the substrate and extends in a first direction, each having a straight sidewall that extends in a second direction parallel to the upper surface of the substrate and orthogonal to the first direction; active structures each having an epitaxial pattern disposed on the first sidewalls of each active pattern; a gate structure embedded on the upper portion of the active structures; a bit line structure disposed on the central portion of each active structure in the first direction; and a contact plug structure disposed on each end portion of each active structure in the first direction. It may include a capacitor disposed on the contact plug structure, and the epitaxial patterns disposed on the first sidewalls of each of the active patterns may not overlap each other along the third direction.

[0007] A semiconductor device according to other embodiments for achieving the above-mentioned objective may include: an active pattern having first sidewalls that are opposite each other in a first direction and have a curved shape, extending on a substrate in a first direction parallel to the upper surface of the substrate and having second sidewalls that are opposite each other in a second direction parallel to the upper surface of the substrate and extending in the first direction and have a straight shape; an active structure having an epitaxial pattern disposed on each of the first sidewalls of the active pattern, wherein the lowest side is disposed at the same height as the lower side of the active pattern and includes a single-crystal semiconductor material; a device isolation pattern disposed on the substrate and covering the second sidewalls of the active pattern and the sidewalls of the epitaxial pattern; a gate structure embedded on the upper part of the active structure; a bit line structure disposed on the central part of the active structure in the first direction; a contact plug structure disposed on each of the two ends of the active structure; and a capacitor disposed on the contact plug structure.

[0008] In a method for manufacturing a semiconductor device according to exemplary embodiments for achieving other objectives described above, the upper portion of a substrate may be partially removed to form preliminary active patterns that are each extended in a first direction parallel to the upper surface of the substrate and spaced apart from each other in a second direction parallel to the upper surface of the substrate and intersecting the first direction. A first preliminary device isolation layer may be formed on the substrate and the preliminary active patterns. By partially removing the first preliminary device isolation layer and the preliminary active patterns to form a first opening that exposes the upper surface of the substrate, each of the preliminary active patterns may be separated into active patterns along the first direction. An selective epitaxial growth (SEG) process may be performed to form an epitaxial pattern on the sidewall of each of the active patterns exposed by the first opening in the first direction, wherein each of the active patterns and the epitaxial pattern formed on its sidewall may together form an active structure. A gate structure may be formed within the active structure. A bit line structure can be formed on the central portion of the active structure in the first direction. A contact plug structure can be formed on each of the two end portions of the active structure in the first direction. A capacitor can be formed on the contact plug structure.

[0009] In one embodiment, when forming a first opening that exposes the upper surface of the substrate by partially removing the first pre-device isolation layer and the pre-active patterns, first to third mask films are sequentially stacked on the first pre-device isolation layer, and a second opening is formed that overlaps the first opening in a vertical direction perpendicular to the upper surface of the substrate by partially removing the third mask film and penetrating it, and a dry etching process can be performed on the first to third mask films, the first pre-device isolation layer, and the pre-active patterns.

[0010] In one embodiment, when forming the preliminary active patterns by partially removing the upper portion of the substrate, a recess extending in the first direction may be formed between the preliminary active patterns, and when forming the first preliminary device separator on the substrate and the preliminary active patterns, the first preliminary device separator may be formed to fill the recess.

[0011] In one embodiment, after forming the epitaxial pattern by performing the epitaxial growth process, an anisotropic etching process for the epitaxial pattern can be performed.

[0012] In one embodiment, after forming the epitaxial pattern by performing the epitaxial growth process, a second pre-device separator filling the first opening is formed on the substrate and the first pre-device separator, and a planarization process is performed on the first and second pre-device separators until the upper surfaces of the active patterns are exposed to form a device separation pattern.

[0013] In one embodiment, the first and second pre-element separators may be combined with each other by including the same material.

[0014] In one embodiment, the first opening may be formed in a plurality of numbers spaced apart from each other along each of the first and second directions.

[0015] In one embodiment, the first openings may be formed in a plurality such that each extends in the second direction and is spaced apart from one another along a third direction that is parallel to the upper surface of the substrate and orthogonal to the second direction.

[0016] In one embodiment, the determination direction of the epitaxial pattern may be the same as the determination direction of the active pattern.

[0017] In one embodiment, the determination direction of the epitaxial pattern may be different from the determination direction of the active pattern. Effects of the invention

[0018] An active structure included in a semiconductor device according to exemplary embodiments may have an increased area, and accordingly, the contact area with a contact plug in contact therewith may be increased, thereby reducing the contact resistance between them. Therefore, the semiconductor device may have improved electrical characteristics. Brief explanation of the drawing

[0019] FIG. 1 is a plan view for illustrating a semiconductor device according to exemplary embodiments, FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1, and FIG. 3 is a perspective view for illustrating a first active structure included in the semiconductor device. FIGS. 4 to 26 are perspective views, plan views, and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. FIG. 27 is a plan view for illustrating a semiconductor device according to exemplary embodiments, FIG. 28 includes cross-sectional views cut along the lines A-A' and B-B' of FIG. 27, respectively, and FIG. 29 includes cross-sectional views cut along the lines C-C' and E-E' of FIG. 27, respectively. FIG. 30 is a perspective view for explaining a second active structure included in the semiconductor device. FIGS. 31 to 73 are perspective views, plan views, and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specific details for implementing the invention

[0020] Hereinafter, a semiconductor device and a method for manufacturing the same according to preferred embodiments of the present invention will be described in detail with reference to the attached drawings. Where materials, layers (films), regions, pads, electrodes, patterns, structures, or processes are referred to as "first," "second," and / or "third" in this specification, it is not intended to limit these components but merely to distinguish each material, layer (film), region, electrode, pad, pattern, structure, and process. Accordingly, "first," "second," and / or "third" may be used selectively or interchangeably for each material, layer (film), region, electrode, pad, pattern, structure, and process.

[0021] In the following detailed description of the invention, among the horizontal directions parallel to the upper surfaces of each first and second substrate, two directions that are orthogonal to each other are defined as the first and second directions (D1, D2), respectively; a direction parallel to the upper surfaces of each first and second substrate and forming an acute angle with each first and second direction (D1, D2) is defined as the third direction (D3); and a direction parallel to the upper surfaces of each first and second substrate and orthogonal to the third direction (D3) is defined as the fourth direction (D4). At this time, the fourth direction (D4) also forms an acute angle with each first and second direction (D1, D2). Additionally, a direction perpendicular to the upper surfaces of each first and second substrate is defined as the fifth direction (D5).

[0022] Meanwhile, each of the first to fifth directions (D1, D2, D3, D4, D5) may include not only the direction shown in the drawing but also the opposite direction.

[0023] [Example]

[0024] FIG. 1 is a plan view for illustrating a semiconductor device according to exemplary embodiments, FIG. 2 is a cross-sectional view taken along line A-A' of FIG. 1, and FIG. 3 is a perspective view for illustrating a first active structure included in the semiconductor device.

[0025] Referring to FIGS. 1 to 3, the semiconductor device may include a first active structure (305), a first gate structure (360), a first bit line structure (595), a first contact plug structure, and a first capacitor (840) disposed on a first substrate (300).

[0026] Additionally, the semiconductor device may further include a first element isolation pattern (310), a first spacer structure (665), a fourth spacer (690), a first barrier pattern (685, see FIG. 20), first and second insulating pattern structures (435, 790), fourth and fifth insulating patterns (610, 620), a metal silicide pattern (700), and a second etch stop layer (800).

[0027] The first active structure (305) can be placed on the first substrate (300).

[0028] The first substrate (300) may include, for example, a semiconductor material such as silicon, germanium, silicon-germanium, etc., or a Group III-V compound such as GaP, GaAs, GaSb, etc. According to some embodiments, the first substrate (300) may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0029] The first active structure (305) may include a first active pattern (304) and a first epitaxial pattern (306). In exemplary embodiments, the first active structure (305) may be extended by a certain length in a third direction (D3) on the first substrate (300) and may be arranged in multiple numbers spaced apart from each other along the third direction (D3). Additionally, the first active structure (305) may be arranged in multiple numbers spaced apart from each other along the first direction (D1) or the fourth direction (D4), and the first active structures (305) may be arranged in a zigzag pattern along the first direction (D3). That is, the corresponding end portions of the first active structures (305) arranged in the first direction (D1) toward the third direction (D3) may not be aligned with each other in the first direction (D1).

[0030] The first active pattern (304) included in each first active structure (305) may be extended by a certain length in the third direction (D3). That is, the extension length of the first active pattern (304) in the third direction (D3) may be greater than the width in the fourth direction (D4). In exemplary embodiments, the side walls of each end portion of the first active pattern (304) in the third direction (D3) may have a rounded curved shape when viewed from above.

[0031] In exemplary embodiments, the extension lengths of the plurality of first active patterns (304) in the third direction (D3) and the widths in the fourth direction (D4) may be the same as each other. The first active pattern (304) may comprise a material substantially identical to the first substrate (300).

[0032] The first epitaxial pattern (306) may be disposed on the side walls of both ends of each first active pattern (304) in the third direction (D3). In exemplary embodiments, each first active pattern (304) may include first side walls (301) facing each other in the third direction (D3) and second side walls (303) facing each other in the fourth direction (D4), and the first epitaxial pattern (306) may be disposed on the first side walls (301) facing each other in the third direction (D3) of each first active pattern (304). The first side walls (301) of each first active pattern (304) may have a straight shape extending in the third direction (D3) when viewed from above, and the second side walls (303) of each first active pattern (304) may have a rounded curved shape when viewed from above.

[0033] In exemplary embodiments, the first epitaxial patterns (306) each disposed on the first sidewalls (301) of each first active pattern (304) may not overlap each other in the first direction (D1) and the fourth direction (D4).

[0034] In one embodiment, the first epitaxial pattern (306) may have a constant thickness on the side walls of each end portion in the third direction (D3) of the first active pattern (304), but the concept of the present invention is not limited thereto. Meanwhile, each end portion in the third direction (D3) of the first active structure (305) including the first active pattern (304) and the first epitaxial pattern (306) may have a rounded curved shape when viewed from above.

[0035] In exemplary embodiments, the upper surface of the first epitaxial pattern (306) may be positioned at substantially the same height as the upper surface of the first active pattern (304), and the lower surface of the first epitaxial pattern (306) may be positioned at substantially the same height as the lower surface of the first active pattern (304).

[0036] In exemplary embodiments, the first epitaxial pattern (306) may include a single-crystal semiconductor material such as single-crystal silicon, single-crystal germanium, etc. As described below with reference to FIGS. 4 through 26, the first epitaxial pattern (306) is formed through a selective epitaxial growth (SEG) process using the sidewall of the first active pattern (304) as a seed, so it may include substantially the same semiconductor material.

[0037] In one embodiment, the crystallization direction of the first epitaxial pattern (306) may be different from the crystallization direction of the first active pattern (304), and accordingly, the first epitaxial pattern (306) and the first active pattern (304) may be distinguished from each other. In another embodiment, the crystallization direction of the first epitaxial pattern (306) may be the same as the crystallization direction of the first active pattern (304), and accordingly, the first epitaxial pattern (306) and the first active pattern (304) may not be distinguished from each other.

[0038] In one embodiment, the crystal directions of a plurality of first epitaxial patterns (306) may be the same as each other. In another embodiment, at least some of the crystal directions of a plurality of first epitaxial patterns (306) may be different from the others.

[0039] Accordingly, some of the first epitaxial patterns (306) disposed on the side walls of the first active patterns (304) have a crystallization direction that is the same as the crystallization direction of the first active pattern (304) in contact therewith and are therefore indistinguishable from each other and are merged therewith, and the crystallization directions of the remaining parts of the first epitaxial patterns (306) disposed on the side walls of the first active patterns (304) are different from the crystallization direction of the first active pattern (304) in contact therewith and are therefore indistinguishable from each other, the extension length of the merged first active pattern (304) in the third direction (D3) may be greater than the extension length of each of the remaining first active patterns (304) in the third direction (D3). That is, in this case, the first active patterns (304) may have different extension lengths in the third direction (D3) instead of having the same extension length.

[0040] The first element isolation pattern (310) is placed on the first substrate (300) and can cover the side wall of the first active structure (305).

[0041] Specifically, the first element isolation pattern (310) can cover the upper surface of the portion of the first substrate (300) where the first active structures (305) are not placed, and can cover them by contacting both side walls in the fourth direction (D4) of the first active pattern (304) included in each first active structure (305). Additionally, the first element isolation pattern (310) can cover them by contacting the side walls of the first epitaxial pattern (306) included in each first active structure (305).

[0042] In exemplary embodiments, the upper surface of the first element isolation pattern (310) may be positioned at substantially the same height as the upper surface of the first active structure (305), and the lower surface of the first element isolation pattern (310) may be positioned at substantially the same height as the lower surface of the first active structure (305).

[0043] The first element isolation pattern (310) may include, for example, an oxide such as silicon oxide.

[0044] Referring together with FIG. 12, the first gate structure (360) may be formed within a second recess that extends in a first direction (D1) through the upper portion of the first active structure (305) and the first device isolation pattern (310). In exemplary embodiments, the first gate structure (360) may extend along the first direction (D1) and may be formed in multiple units spaced apart from each other along the second direction (D2).

[0045] The first gate structure (360) may include a first gate electrode (340) and a first gate mask (350) stacked along a fifth direction (D5), and a first gate insulation pattern (330) covering the sidewalls thereof.

[0046] The first gate electrode (340) may include, for example, a metal, a metal nitride, a metal silicide, or polysilicon doped with impurities, the first gate mask (350) may include, for example, an insulating nitride such as silicon nitride, and the first gate insulating pattern (330) may include, for example, an oxide such as silicon oxide or a metal oxide.

[0047] Referring to FIGS. 13 and 14 together, a third opening (440) may be formed to penetrate the insulating film structure (430) and expose the upper surface of the first gate mask (350) and the first gate insulating pattern (330) included in the first active structure (305), the first device isolation pattern (310), and the first gate structure (360), and the upper surface of the central part of the first active structure (305) in the third direction (D3) may be exposed by the third opening (440).

[0048] In exemplary embodiments, the bottom surface of the third opening (440) may be wider than the top surface of the first active structure (305) exposed by the third opening (440). Accordingly, the third opening (440) may also expose the top surface of the first element isolation pattern (310) adjacent to the first active structure (305). Additionally, the third opening (440) may penetrate the top of the first active structure (305) and the top of the first element isolation pattern (310) adjacent thereto, and accordingly, the bottom surface of the third opening (440) may be lower than the top surface of the portion of the first active structure (305) where the third opening (440) is not formed, i.e., the portions of each edge of the first active structure (305) in the third direction (D3).

[0049] The first bit line structure (595) may include a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a fifth mask (485), a first etching stop pattern (565), and a capping pattern (585) that are sequentially stacked in the fifth direction (D5) on the third opening (440) or the first insulating pattern structure (435). At this time, the first conductive pattern (455), the first barrier pattern (465), and the second conductive pattern (475) may form a conductive structure together, and the fifth mask (485), the first etching stop pattern (565), and the capping pattern (585) may form an insulating structure together.

[0050] The first conductive pattern (455) may include, for example, impurity-doped polysilicon, the first barrier pattern (465) may include, for example, a metal nitride such as titanium nitride or, for example, a metal silicon nitride such as titanium silicon nitride, the second conductive pattern (475) may include, for example, a metal such as tungsten, and each of the fifth mask (485), the first etching stop pattern (565) and the capping pattern (585) may include, for example, an insulating nitride such as silicon nitride.

[0051] In exemplary embodiments, the first bit line structure (595) may extend in a second direction (D2) on the first substrate (300) and may be formed in multiple numbers spaced apart from each other along the first direction (D1).

[0052] The fourth and fifth insulating patterns (610, 620) are formed within the third opening (440) and can come into contact with the lower sidewall of the first bit line structure (595). The fourth insulating pattern (610) may include an oxide, for example, silicon oxide, and the fifth insulating pattern (620) may include an insulating nitride, for example, silicon nitride.

[0053] The first insulating pattern structure (435) may be formed below the first bit line structure (595) on the first active structure (305) and the first device isolation pattern (310), and may include first to third insulating patterns (405, 415, 425) sequentially stacked along the fifth direction (D5). At this time, the first and third insulating patterns (405, 425) may include an oxide, for example, silicon oxide, and the second insulating pattern (415) may include an insulating nitride, for example, silicon nitride.

[0054] The first contact plug structure may include a lower contact plug (675), a metal silicide pattern (700), and an upper contact plug (755) sequentially stacked along a fifth direction (D5) on the first active structure (305) and the first element isolation pattern (310).

[0055] The lower contact plug (675) can contact the upper surface of one end portion in the third direction (D3) of the first active structure (305). Specifically, the lower contact plug (675) can contact the upper surface of one end portion in the third direction (D3) of the first active pattern (304) included in the first active structure (305), and the upper surface of the first epitaxial pattern (306) disposed on the side wall thereof.

[0056] Accordingly, compared to the case where the first active structure (305) includes only the first active pattern (304) and does not include the first epitaxial pattern (306), the lower contact plug (675) can contact the upper surface of the first active structure (305) with an increased area, and the contact resistance between the first active structure (305) and the lower contact plug (675) can be reduced.

[0057] In exemplary embodiments, the lower contact plugs (675) may be spaced apart from each other along the second direction (D2) between the first bit line structures (595).

[0058] The lower contact plug (675) may include, for example, polysilicon doped with impurities, and the metal silicide pattern (700) may include, for example, titanium silicide, cobalt silicide, nickel silicide, etc.

[0059] A first barrier pattern (685) may be formed between lower contact plugs (675) adjacent to each other in the second direction (D2) to separate them from each other. The first barrier pattern (685) may include an insulating nitride, for example, silicon nitride.

[0060] The upper contact plug (755) may include a second metal pattern (745) and a second barrier pattern (735) covering the lower surface thereof. The second metal pattern (745) may include a metal such as tungsten, for example, and the second barrier pattern (735) may include a metal nitride such as titanium nitride, for example.

[0061] In exemplary embodiments, the upper contact plugs (755) may be formed in multiple numbers spaced apart from each other along each first and second direction (D1, D2) and may be arranged in a honeycomb or grid shape when viewed from above. Each upper contact plug (755) may have a circular, elliptical, or polygonal shape when viewed from above.

[0062] The first spacer structure (665) may include a first spacer (600) covering the side wall of the first bit line structure (595) and the side wall of the third insulation pattern (425), an air spacer (635) disposed on the lower outer wall of the first spacer (600), and a third spacer (650) covering the outer wall of the air spacer (635), the side wall of the first insulation pattern structure (435), and the upper surface of the fourth and fifth insulation patterns (610, 620).

[0063] Each of the first and third spacers (600, 650) may contain an insulating nitride, such as silicon nitride, for example, and the air spacer (635) may contain air.

[0064] The fourth spacer (690) may be formed on the outer wall of the portion of the first spacer (600) disposed on the upper side wall of the first bit line structure (595), and may cover the top of the air spacer (635) and the upper surface of the third spacer (650). The fourth spacer (690) may include an insulating nitride, for example, silicon nitride.

[0065] Referring together to FIGS. 24 and 25, the second insulating pattern structure (790) may include a sixth insulating pattern (770) disposed on the inner wall of an eighth opening (760) surrounding the upper contact plug (755) when viewed from above, penetrating the upper contact plug (755), a portion of the insulating structure included in the first bit line structure (595), and a portion of the first, third, and fourth spacers (600, 650, 690), and a seventh insulating pattern (780) formed on the sixth insulating pattern (770) to fill the remainder of the sixth opening (760). At this time, the top of the air spacer (635) may be closed by the sixth insulating pattern (770).

[0066] The 6th and 7th insulating patterns (770, 780) may include insulating nitrides, for example, silicon nitride.

[0067] The second etch stop layer (800) can be formed on the sixth and seventh insulating patterns (770, 780), the upper contact plug (755), and the first barrier pattern (685).

[0068] The first capacitor (840) may include a first lower electrode (810), a first dielectric film (820), and a first upper electrode (830) that are sequentially stacked, and the first lower electrode (810) may penetrate the second etch stop film (800) and contact the upper surface of the upper contact plug (755).

[0069] As described above, the semiconductor device may include a first active structure (305), and the first active structure (305) may include a first active pattern (304) and a first epitaxial pattern (306) disposed at each of the two ends toward the third direction (D4). Accordingly, compared to the case where the first active structure (305) does not include the first epitaxial pattern (306), each of the two ends toward the third direction (D3) may have an increased area, and the contact area with the lower contact plug (675) in contact therewith may be increased, thereby reducing the contact resistance between them.

[0070] Accordingly, for example, the electrical connection between the source / drain region formed in the first active structure (305) and the capacitor (840) connected thereto through the first contact plug structure including the lower contact plug (675) can be improved, and the semiconductor device including these can have improved electrical characteristics.

[0071] FIGS. 4 through 26 are perspective views, plan views, and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 4 through 9 are perspective views, FIGS. 10, 13, 16, 20, and 24 are plan views, FIGS. 11, 14-15, 17-19, 21-23, and 25-26 are cross-sectional views cut along the A-A' line of the corresponding plan views, and FIG. 12 is a cross-sectional view cut along the B-B' line of FIG. 10. Meanwhile, FIGS. 4 through 9 are perspective views of the X region of FIG. 10.

[0072] Referring to FIG. 4, a first pad film and a first mask film are sequentially formed on a first substrate (300), and an etching process is performed on the first mask film and the first pad film to form a first mask (20) and a first pad (10), respectively.

[0073] In exemplary embodiments, each first mask (20) and first pad (10) may be extended in a third direction (D3) and may be formed in multiple numbers spaced apart from each other along a first direction (D1).

[0074] The first pad (10) may include an oxide such as silicon oxide, for example, and the first mask (20) may include a semiconductor material such as polysilicon, for example, but the concept of the present invention is not limited thereto.

[0075] Referring to FIG. 5, an etching process using the first mask (20) and the first pad (10) as etching masks can be performed to form a first recess (30) on the first substrate (300).

[0076] In exemplary embodiments, the first recess (30) may be extended in a third direction (D3) and may be formed in multiple numbers spaced apart from each other along the first direction (D1).

[0077] As the first recesses (30) are formed, a plurality of first preliminary active patterns (302) spaced apart from each other in a first direction (D1) by the first recesses (30) may be formed on the first substrate (300), and each of the first preliminary active patterns (302) may extend in a third direction (D3).

[0078] Referring to FIG. 6, a first preliminary device separator (40) that fills the first recesses (30) on the first substrate (300) and the first preliminary active patterns (302) can be formed, and second and third mask films (50, 60) can be sequentially formed on the first preliminary device separator (40).

[0079] The second mask layer (50) may include, for example, a spin-on hard mask (SOH), an amorphous carbon layer (ACL), etc., and the third mask layer (60) may include, for example, plasma-enhanced silicon oxynitride (PE-SiON), but the concept of the present invention is not limited thereto.

[0080] Referring to FIG. 7, a fourth mask film (70) can be formed on a third mask film (60), and a first opening (75) can be formed by partially removing the fourth mask film (70) to expose the upper surface of the third mask film (60).

[0081] The fourth mask film (70) may include, for example, a photoresist film, and the fourth mask film (70) may be partially removed through a photoetching process.

[0082] In exemplary embodiments, the first opening (75) may overlap the first preliminary active pattern (302) in the fifth direction (D5) and may be formed in multiple numbers spaced apart from each other along the third direction (D3) on each of the first preliminary active patterns (302). Accordingly, the first opening (75) may be formed in multiple numbers spaced apart from each other along each of the first and third directions (D1, D3), and some of the first openings (75) may overlap each other in the first direction (D1).

[0083] Each first opening (75) may have a shape such as a rectangle, a rectangle with rounded corners, a circle, or an ellipse when viewed from the top surface.

[0084] Referring to FIG. 8, a dry etching process can be performed, for example, on a structure formed on a first substrate (300).

[0085] As the above dry etching process is performed, the second to fourth mask films (50, 60, 70) can be removed, and the first preliminary device isolation film (40) portion that overlaps the first opening (75) and the fifth direction (D5) and the first preliminary active pattern (302) portion formed underneath it can be removed to form a second opening (45) that exposes the upper surface of the first substrate (300).

[0086] The second opening (45) can penetrate each of the first preliminary active patterns (302) to expose the upper surface of the first substrate (300) and can be formed in multiple numbers spaced apart from each other along the third direction (D3). Accordingly, each of the first preliminary active patterns (302) can be separated into multiple first active patterns (304) spaced apart from each other in the third direction (D3) by the second openings (45).

[0087] In exemplary embodiments, the first active pattern (304) may be formed in multiple numbers spaced apart from each other along each first and third direction (D1, D3).

[0088] Referring to FIG. 9, a Selective Epitaxial Growth (SEG) process can be performed using the sidewall of the first active pattern (304) exposed by the second opening (45) as a seed to form a first epitaxial pattern (306) on the portion of the first active pattern (304) exposed by the second opening (45).

[0089] In exemplary embodiments, the first epitaxial pattern (306) may be formed on the side walls of both ends toward the third direction (D3) of the first active pattern (304) exposed by the second opening (45).

[0090] Meanwhile, a first epitaxial pattern (306) may be formed on the upper surface of the first substrate (300) portion exposed by the second opening (45), but in this case, an anisotropic etching process may be additionally performed on the first epitaxial pattern (306) to remove the portion of the first epitaxial pattern (306) formed on the upper surface of the first substrate (300).

[0091] The second opening (45) can define an area where the first epitaxial pattern (306) is formed by the SEG process by exposing both end portions to the third direction (D3) of the first active pattern (304). That is, the first epitaxial pattern (306) may not be formed on both side walls to the fourth direction (D4) of the first active pattern (304) that are not exposed by the second opening (45), and the first epitaxial pattern (306) may be formed only on each end portion to the third direction (D3) of the first active pattern (304) that is exposed by the second opening (45).

[0092] For example, when the upper surface of the first substrate (300) is patterned through a single etching process to form a plurality of active patterns spaced apart from each other in the first and third directions (D1, D3), and then an SEG process is performed, since an epitaxial pattern is inevitably formed on the entire sidewalls of each active pattern, it is not possible to form the epitaxial pattern only on specific parts of each active pattern, for example, on both ends.

[0093] In addition, since the plurality of active patterns are formed to be spaced apart from each other in the first direction (D1) and the third direction (D3) through a single etching process, a problem may occur in which some of the active patterns are not spaced apart from each other and a bridge is formed during the etching process.

[0094] However, in exemplary embodiments, a first recess (30) is formed on the upper surface of a first substrate (300) to form a plurality of first pre-active patterns (302) that are spaced apart from each other in a first direction (D1) and each extends in a third direction (D3), a first pre-element isolation film (40) that fills the first recess (30) and second to fourth mask films (50, 60, 70) are formed sequentially, and then a fourth mask film (70) is partially removed to form a first opening (75) that overlaps the first pre-active pattern (302) in a fifth direction (D5), and a dry etching process is performed to form a second opening (45) that penetrates the first pre-active pattern (302), so that the first pre-active pattern (302) can be separated into first active patterns (304) that are spaced apart from each other in a third direction (D3).

[0095] Accordingly, only the sidewalls of both ends of each first active pattern (304) toward the third direction (D3) can be exposed by the second opening (45), and the first epitaxial pattern (306) can be formed only on the sidewalls of both ends of each first active pattern (304) toward the third direction (D3) that are exposed.

[0096] In addition, a first etching process is performed on the upper surface of the first substrate (300) to form first preliminary active patterns (302) that are spaced apart from each other in a first direction (D1), and then a second etching process is performed to separate each of the first preliminary active patterns (302) into first active patterns (304) that are spaced apart from each other in a third direction (D3), so that the possibility of a bridge being formed between the first active patterns (304) can be significantly reduced.

[0097] In one embodiment, the crystallization direction of the first epitaxial pattern (306) may be different from the crystallization direction of the first active pattern (304), and accordingly, the first epitaxial pattern (306) and the first active pattern (304) may be distinguished from each other. In another embodiment, the crystallization direction of the first epitaxial pattern (306) may be the same as the crystallization direction of the first active pattern (304), and accordingly, the first epitaxial pattern (306) and the first active pattern (304) may not be distinguished from each other.

[0098] The first active pattern (304) and the first epitaxial pattern (306) can together form the first active structure (305). In exemplary embodiments, the first active structure (305) may be extended in a third direction (D3) and may be formed in multiple units spaced apart from each other along the first direction (D1).

[0099] Afterward, a second pre-element separator is formed to fill the second opening (45) on the first active structure (305) and the first pre-element separator (40), and a planarization process can be performed on it until the upper surface of the first active pattern (304) is exposed.

[0100] In exemplary embodiments, the planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.

[0101] In exemplary embodiments, the second pre-device separator may comprise substantially the same material as the first pre-device separator (40), and thus they may be merged together. Meanwhile, as the planarization process is performed, the upper surfaces of the first pre-device separator (40) and the second pre-device separator may be formed at substantially the same height as the upper surface of the first active pattern (304), and together they may form the first device separation pattern (310).

[0102] The first element isolation pattern (310) is formed on the first substrate (300) and can cover both side walls in the first direction (D1) of each first active pattern (304), and can also contact the side walls of the first epitaxial pattern (306) portions formed on the mutually opposing side walls of the first active patterns (304) adjacent to each other in the third direction (D3).

[0103] Referring to FIGS. 10 to 12, a first active structure (305) and a first device isolation pattern (310) formed on a first substrate (300) can be partially etched to form a second recess extending in a first direction (D1), and then a first gate structure (360) can be formed inside the second recess. In exemplary embodiments, the first gate structure (360) may extend along the first direction (D1) and may be formed in multiple numbers spaced apart from each other along the second direction (D2).

[0104] Referring to FIGS. 13 and 14, an insulating film structure (430) can be formed on a first active structure (305), a first device isolation pattern (310), and a first gate structure (360). The insulating film structure (430) may include first to third insulating films (400, 410, 420) that are sequentially stacked.

[0105] Subsequently, an insulating film structure (430) can be patterned and used as an etching mask to partially etch the upper portion of the first gate mask (350) and the first gate insulating pattern (330) included in the lower first active structure (305), the first device isolation pattern (310), and the first gate structure (360), thereby forming a third opening (440). In exemplary embodiments, the insulating film structure (430) remaining after the etching process may have a circular or elliptical shape when viewed from above and may be formed in multiple numbers spaced apart from each other along the first and second directions (D1, D2) on the first substrate (300). At this time, each insulating film structure (430) may overlap in the fifth direction (D5) with the end portions of the first active structures (305) facing each other in the third direction (D3).

[0106] Referring to FIG. 15, a first conductive film (450), a first barrier film (460), a second conductive film (470), and a fifth mask film (480) can be sequentially stacked on an insulating film structure (430), a first active structure (305) exposed by a third opening (440), a first device isolation pattern (310), and a first gate structure (360), and these can together form a conductive structure film. At this time, the first conductive film (450) can fill the third opening (440).

[0107] Referring to FIGS. 16 and 17, a first etch stop layer and a capping layer can be sequentially stacked on the conductive structure film, and then the capping layer can be etched to form a capping pattern (585), and the first etch stop layer, the fifth mask layer (480), the second conductive layer (470), the first barrier layer (460), and the first conductive layer (450) can be sequentially etched using this as an etching mask.

[0108] In exemplary embodiments, the capping pattern (585) may each extend in a second direction (D2) and may be formed in multiple numbers spaced apart from each other along a first direction (D1).

[0109] As the above etching process is performed, a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a fifth mask (485), a first etching stop pattern (565), and a capping pattern (585) may be formed sequentially on the third opening (440), and a third insulating pattern (425), a first conductive pattern (455), a first barrier pattern (465), a second conductive pattern (475), a fifth mask (485), a first etching stop pattern (565), and a capping pattern (585) may be formed sequentially on the second insulating film (410) of the insulating film structure (430) outside the third opening (440).

[0110] Hereinafter, the first conductive pattern (455), the first barrier pattern (465), the second conductive pattern (475), the fifth mask (485), the first etching stop pattern (565), and the capping pattern (585) that are sequentially stacked will be collectively referred to as the first bit line structure (595). At this time, the first conductive pattern (455), the first barrier pattern (465), and the second conductive pattern (475) can form a conductive structure together, and the fifth mask (485), the first etching stop pattern (565), and the capping pattern (585) can form an insulating structure together. In exemplary embodiments, the first bit line structure (595) can be extended in a second direction (D2) on the first substrate (300) and can be formed in multiple numbers spaced apart from each other along the first direction (D1).

[0111] Referring to FIG. 18, after forming a first spacer film on a first substrate (300) on which a first bit line structure (595) is formed, fourth and fifth insulating films can be sequentially formed on the first spacer film.

[0112] The first spacer film can also cover the sidewall of the third insulation pattern (425) below the portion of the first bit line structure (595) formed on the second insulation film (410), and the fifth insulation film can fill the remaining portion of the third opening (440).

[0113] Subsequently, an etching process may be performed to etch the fourth and fifth insulating films. In exemplary embodiments, the etching process may be performed by a wet etching process using, for example, phosphoric acid (H2PO3), SC1, and hydrofluoric acid (HF) as etchants, and all parts of the fourth and fifth insulating films except for the part formed within the third opening (440) may be removed. Accordingly, most of the surface of the first spacer film, that is, the part of the first spacer film other than the part formed within the third opening (440), may be exposed, and the parts of the fourth and fifth insulating films remaining within the third opening (440) may form the fourth and fifth insulating patterns (610, 620), respectively.

[0114] Afterward, a second spacer film can be formed on the exposed first spacer film surface and the fourth and fifth insulating patterns (610, 620) formed within the third opening (440), and then anisotropically etched to form a second spacer (630) covering the sidewall of the first bit line structure (595) on the first spacer film surface and the fourth and fifth insulating patterns (610, 620).

[0115] Subsequently, a dry etching process using a capping pattern (585) and a second spacer (630) as an etching mask can be performed to form a fourth opening (640) that exposes the upper surface of the first active structure (305), and the upper surface of the first device isolation pattern (310), the upper surface of the first gate mask (350), and the upper surface of the first gate insulation pattern (330) can also be exposed by the fourth opening (640).

[0116] By the above dry etching process, the first spacer film portion formed on the upper surface of the capping pattern (585) and the upper surface of the second insulating film (410) can be removed, and accordingly, a first spacer (600) covering the side wall of the first bit line structure (595) can be formed. In addition, in the above dry etching process, the first and second insulating films (400, 410) can also be partially removed and remain as first and second insulating patterns (405, 415), respectively, at the bottom of the first bit line structure (595). The first to third insulating patterns (405, 415, 425) sequentially stacked at the bottom of the first bit line structure (595) can together form a first insulating pattern structure (435).

[0117] Referring to FIG. 19, a third spacer film is formed on the upper surface of the capping pattern (585), the upper surface and outer wall of the second spacer (630), a portion of the upper surface of the fourth and fifth insulation patterns (610, 620), and the upper surface of the first active structure (305), the first device isolation pattern (310), the first gate mask (350), and the first gate insulation pattern (330) exposed by the fourth opening (640), and then the third spacer film is anisotropically etched to form a third spacer (650) that covers the side wall of the first bit line structure (595).

[0118] The first to third spacers (600, 630, 650) sequentially stacked along the horizontal direction on the side wall of the first bit line structure (595) may be collectively referred to as a preliminary spacer structure (660).

[0119] Afterward, a first sacrificial film filling the fourth opening (640) is formed on the first substrate (300) to a sufficient height, and then the upper surface of the capping pattern (585) is flattened until the upper surface is exposed, thereby forming a first sacrificial pattern (680) within the fourth opening (640).

[0120] In exemplary embodiments, the first sacrifice pattern (680) may be extended in a second direction (D2) and may be formed in multiple numbers spaced apart from each other by first bit line structures (595) along the first direction (D1). The first sacrifice pattern (680) may include, for example, an oxide such as silicon oxide.

[0121] Referring to FIGS. 20 and 21, a sixth mask (not shown) comprising a plurality of fifth openings that are each extended in a first direction (D1) and spaced apart from each other in a second direction (D2) is formed on a capping pattern (585), a first sacrifice pattern (680), and a preliminary spacer structure (660), and an etching process is performed using this as an etching mask to etch the first sacrifice pattern (680).

[0122] In exemplary embodiments, each of the fifth openings may overlap the area between the first gate structures (360) in the fifth direction (D5). As the etching process is performed, a sixth opening may be formed on the first substrate (300) to expose the upper surface of the first active structure (305) and the first device isolation pattern (310) between the first bit line structures (595), and the first sacrificial pattern (680) extending in the second direction (D2) between the first bit line structures (595) may be separated into a plurality of portions spaced apart from each other along the second direction (D2) by the sixth opening.

[0123] In exemplary embodiments, the sixth opening may expose together the upper surface of one end portion toward the third direction (D3) of each first active pattern (304) included in the first active structure (305) and the upper surface of the portion of the first epitaxial pattern (306) formed on the side wall thereof. Accordingly, the area in which the sixth opening exposes the upper surface of the first active structure (305) may be increased compared to the case where the first active structure (305) includes only the first active pattern (304) and not the first epitaxial pattern (306).

[0124] After removing the sixth mask, the lower contact plug membrane filling the sixth opening can be formed to a sufficient height, and the upper surface can be flattened until the upper surface of the capping pattern (585), the first sacrifice pattern (680), and the reserve spacer structure (660) is exposed. Accordingly, the lower contact plug membrane can be converted into a plurality of lower contact plugs (675) spaced apart from each other by the first sacrifice pattern (680) along the second direction (D2) between the first bit line structures (595).

[0125] As the sixth opening exposes an increased area of ​​the upper surface of the first active structure (305), the lower contact plug (675) formed within the sixth opening can come into contact with the upper surface of the first active structure (305) over an increased area. That is, the lower contact plug (675) comes into contact not only with the upper surface of the end portion toward the third direction (D3) of the first active pattern (304) but also with the upper surface of the first epitaxial pattern (306) formed on its side wall, so that it can come into contact with the first active structure (305) containing these over an increased area.

[0126] Afterward, the first sacrifice pattern (680) can be removed to form a seventh opening, and then a first barrier pattern (685) that fills the seventh opening can be formed. In exemplary embodiments, the first barrier pattern (685) can overlap the first gate structure (360) in the fifth direction (D5).

[0127] Referring to FIG. 22, the upper part of the lower contact plug (675) is removed to expose the upper part of the preliminary spacer structure (660) formed on the side wall of the first bit line structure (595), and then the upper parts of the second and third spacers (630, 650) of the exposed preliminary spacer structure (660) can be removed.

[0128] Afterward, the upper part of the lower contact plug (675) can be further removed. Accordingly, the upper surface of the lower contact plug (675) can be lower than the upper surface of the second and third spacers (630, 650).

[0129] Subsequently, by forming a fourth spacer film on the first bit line structure (595), the preliminary spacer structure (660), the first barrier pattern (685), and the lower contact plug (675) and anisotropically etching it, a fourth spacer (690) can be formed that covers the upper portion of the preliminary spacer structure (660) formed on each of the two side walls in the first direction (D1) of the first bit line structure (595), and accordingly, the upper surface of the lower contact plug (675) can be exposed.

[0130] Subsequently, a metal silicide pattern (700) can be formed on the upper surface of the exposed lower contact plug (675). In exemplary embodiments, the metal silicide pattern (700) can be formed by forming a first metal film on the capping pattern (585), the first barrier pattern (685), the fourth spacer (690), and the lower contact plug (675), heat treating the first metal film, and then removing the unreacted portion from the first metal film.

[0131] Referring to FIG. 23, after forming a second barrier film (730) on a capping pattern (585), a first barrier pattern (685), a fourth spacer (690), a metal silicide pattern (700), and a lower contact plug (675), a second metal film (740) can be formed on the second barrier film (730) to fill the space between the first bit line structures (595).

[0132] Afterward, a planarization process may be additionally performed on the upper surface of the second metal film (740). The planarization process may include, for example, a chemical mechanical polishing (CMP) process and / or an etch back process.

[0133] Referring to FIGS. 24 and 25, an upper contact plug (755) can be formed by patterning the second metal film (740) and the second barrier film (730), and an eighth opening (760) can be formed between the upper contact plugs (755).

[0134] The eighth opening (760) can be formed by partially removing the second metal film (740) and the second barrier film (730), as well as the capping pattern (585), the first barrier pattern (685), the preliminary spacer structure (660), and the fourth spacer (690).

[0135] The upper contact plug (755) may include a second metal pattern (745) and a second barrier pattern (735) covering the lower surface thereof. In exemplary embodiments, the upper contact plug (755) may have a shape such as a circle, ellipse, polygon, or rounded polygon when viewed from above, and may be arranged, for example, in a honeycomb pattern along the first and second directions (D1, D2).

[0136] Meanwhile, the lower contact plug (675), metal silicide pattern (700), and upper contact plug (755) sequentially stacked on the first substrate (300) can together form a first contact plug structure.

[0137] Referring to FIG. 26, the second spacer (630) included in the preliminary spacer structure (660) exposed by the eighth opening (760) is removed to form an air gap, and after forming the sixth insulation pattern (770) on the bottom and side wall of the eighth opening (760), the seventh insulation pattern (780) that fills the remaining part of the eighth opening (760) can be formed.

[0138] The 6th and 7th insulation patterns (770, 780) can together form a 2nd insulation pattern structure (790).

[0139] The top of the air gap can be covered by the sixth insulation pattern (770), and thus an air spacer (635) can be formed. The first spacer (600), the air spacer (635), and the third spacer (650) can together form a first spacer structure (665).

[0140] Referring again to FIGS. 1 to 3, a second etch stop layer (800) and a first mold layer are sequentially stacked on an upper contact plug (755) and a second insulating pattern structure (790), and after forming a ninth opening that exposes the upper surface of the upper contact plug (755) by partially removing the first mold layer and the second etch stop layer (800), a first lower electrode (810) can be formed within the ninth opening.

[0141] After removing the first mold film and forming a first dielectric film (820) on the surface of the first lower electrode (810), a first upper electrode (830) can be formed on the first dielectric film (820) to form a first capacitor (840).

[0142] Subsequently, the manufacturing of the semiconductor device can be completed by additionally forming upper wirings.

[0143] FIG. 27 is a plan view for illustrating a semiconductor device according to exemplary embodiments, FIG. 28 includes cross-sectional views cut along the lines A-A' and B-B' of FIG. 27, respectively, and FIG. 29 includes cross-sectional views cut along the lines C-C' and E-E' of FIG. 27, respectively. FIG. 30 is a perspective view for illustrating a second active structure included in the semiconductor device.

[0144] Since the semiconductor device described above includes substantially identical or similar components to the semiconductor device described with reference to FIGS. 1 to 3, a detailed description thereof is omitted.

[0145] Referring to FIGS. 27 to 30, the semiconductor device may include a second active structure (1105), a second gate structure (1160), a second bit line structure (1300), a second spacer structure (1800), a buffer structure (1218), a buried pattern (1330), a second contact plug structure (1268), a second barrier pattern (1430), a third contact plug structure (1425), a landing pad (1460), and a second capacitor (1510) disposed on a second substrate (1100).

[0146] Additionally, the semiconductor device may further include a second element isolation pattern (1110), a second mold film (1170), a third mold film (1175), a fourth mold (1185), a fifth spacer (1230), and an eighth insulation pattern (1470).

[0147] The second active structure (1105) may include a second active pattern (1104) and a second epitaxial pattern (1106). In exemplary embodiments, the second active structure (1105) may be extended by a certain length in a third direction (D3) and may be arranged in multiple numbers spaced apart from each other along a first direction (D1) to form a row of the second active structure. Additionally, the rows of the second active structure may be arranged in multiple numbers spaced apart from each other along a second direction (D2) to form an array of the second active structure.

[0148] In exemplary embodiments, the second active structures (1105) included in each row of the second active structures may be aligned with each other in a first direction (D1). That is, the corresponding ends of the second active structures (1105) included in each row of the second active structures may be arranged on the same line along the first direction (D1).

[0149] The second active pattern (1104) included in each second active structure (1105) may be extended by a certain length in the third direction (D3). That is, the extension length of the second active pattern (1104) in the third direction (D3) may be greater than the width in the fourth direction (D4). In exemplary embodiments, each end portion of the second active pattern (1104) in the third direction (D3) may have a rounded curve shape when viewed from above.

[0150] In exemplary embodiments, the extension lengths of the plurality of second active patterns (1104) in the third direction (D3) and the widths in the fourth direction (D4) may be the same as each other.

[0151] The second epitaxial pattern (1106) may be disposed on the sidewalls of each end portion of each second active pattern (1104) in the third direction (D3). In exemplary embodiments, each second active pattern (1104) may include first sidewalls (1101) facing each other in the third direction (D3) and second sidewalls (1103) facing each other in the fourth direction (D4), and the second epitaxial pattern (1106) may be disposed on the first sidewalls (1101) facing each other in the third direction (D3) of each second active pattern (1104). The first side walls (1101) of each second active pattern (1104) may have a straight shape extending in the third direction (D3) when viewed from above, and the second side walls (1103) of each second active pattern (1104) may have a rounded curved shape when viewed from above.

[0152] In exemplary embodiments, the second epitaxial patterns (1106) each disposed on the first sidewalls (1101) of each second active pattern (1104) may not overlap each other in the first direction (D1) and the fourth direction (D4).

[0153] In one embodiment, the second epitaxial pattern (1106) may have a constant thickness on the side walls of each end portion in the third direction (D3) of the second active pattern (1104), but the concept of the present invention is not limited thereto. Meanwhile, the side walls of each end portion in the third direction (D3) of the second active structure (1105) including the second active pattern (1104) and the second epitaxial pattern (1106) may have a rounded curved shape when viewed from above.

[0154] In exemplary embodiments, the uppermost surface of the second epitaxial pattern (1106) may be positioned at substantially the same height as the uppermost surface of the second active pattern (1104), and the lowermost surface of the second epitaxial pattern (1106) may be positioned at substantially the same height as the lower surface of the second active pattern (1104).

[0155] In exemplary embodiments, the second epitaxial pattern (1106) may comprise substantially the same material as the second active pattern (1104), namely, a single-crystal semiconductor material. In one embodiment, the crystal direction of the second epitaxial pattern (1106) may differ from the crystal direction of the second active pattern (1104), and thus the second epitaxial pattern (1106) and the second active pattern (1104) may be distinguished from each other. In another embodiment, the crystal direction of the second epitaxial pattern (1106) may be the same as the crystal direction of the second active pattern (1104), and thus the second epitaxial pattern (1106) and the second active pattern (1104) may not be distinguished from each other.

[0156] In one embodiment, the crystal directions of a plurality of second epitaxial patterns (1106) may be the same as each other. In another embodiment, at least some of the crystal directions of a plurality of second epitaxial patterns (1106) may be different from the others. If some of the second epitaxial patterns (1106) are merged with a second active pattern (1104) in contact with them and are indistinguishable from each other, the second active pattern (1104) may have different extension lengths instead of having the same extension length in the third direction (D3) as the others of the second active patterns (1104).

[0157] An impurity region structure (1107) may be formed on the upper portions of each end portion toward the third direction (D3) of the second active structure (1105). At this time, the impurity region structure (1107) may include a first impurity region (1107a) formed in the second active pattern (1104) and a second impurity region (1107b) formed in the second epitaxial pattern (1106). The impurity region structure (1107) may include, for example, n-type impurities or p-type impurities.

[0158] In exemplary embodiments, the upper surface of the central portion of the second active structure (1105) toward the third direction (D3) and the upper surface of the second element separation pattern (1110) portion adjacent thereto in the first direction (D1) may be lower than the upper surface of each end portion of the second active structure (1105) toward the third direction (D3) and the upper surface of the second element separation pattern (1110) portion adjacent thereto in the first direction (D1).

[0159] The second gate structure (1160) may be extended in a first direction (D1) by penetrating the upper portion of the second active structure (1105) and the second device isolation pattern (1110), and may be arranged in multiple units spaced apart from each other along the second direction (D2). The second gate structure (1160) may include a third conductive pattern (1130), a fourth conductive pattern (1140), and a second gate mask (1150) sequentially stacked along the fifth direction (D5), and may further include a second gate insulating pattern (1120) covering the sidewalls thereof and the lower surface of the third conductive pattern (1130). At this time, the third and fourth conductive patterns (1130, 1140) may together form a second gate electrode.

[0160] The third conductivity pattern (1130) may include, for example, a metal, a metal nitride, a metal silicide, etc., and the fourth conductivity pattern (1140) may include, for example, polysilicon doped with n-type impurities or p-type impurities.

[0161] In one embodiment, two second gate structures (1160) spaced apart from each other in a second direction (D2) can pass through the upper part of one second active structure (1105).

[0162] The second contact plug structure (1268) may be formed on the central portion of the second active structure (1105) and may include a second pad (1240), an ohmic contact pattern (1250), and a fourth metal pattern (1260) sequentially stacked along the fifth direction (D5). In exemplary embodiments, the second contact plug structure (1268) may be formed in multiple numbers spaced apart from each other along each of the first and second directions (D1, D2). The second pad (1240) may include, for example, impurity-doped polysilicon, the ohmic contact pattern (1250) may include, for example, a metal silicide such as cobalt silicide, nickel silicide, titanium silicide, etc., and the fourth metal pattern (1260) may include, for example, a metal such as tungsten, niobium, copper, aluminum, etc.

[0163] The second mold film (1170), the third mold film (1175), and the fourth mold (1185) may be placed on the second active structure (1105) and the second device isolation pattern (1110). Each of the second and third mold films (1170, 1175) may extend in a first direction (D1) and may be arranged in multiple numbers spaced apart from each other along a second direction (D2).

[0164] The fourth mold (1185) may be formed in multiple numbers spaced apart from each other along each of the first and second directions (D1, D2) and may be positioned between the second and third mold films (1170, 1175) below the second bit line structure (1300).

[0165] In exemplary embodiments, the upper surfaces of the second and third mold films (1170, 1175) and the upper surface of the fourth mold (1185) may be formed at substantially the same height as each other. Additionally, the lower surface of the fourth mold (1185) may be lower than the lower surfaces of the second and third mold films (1170, 1175).

[0166] The second mold film (1170) and the third mold film (1175) may include an insulating nitride, for example, silicon nitride, and the fourth mold (1185) may include an oxide, for example, silicon oxide.

[0167] The buffer structure (1218) may be disposed between the second bit line structure (1300), the second and third mold films (1170, 1175), and the fourth mold (1185), and may include first to third buffers (1195, 1205, 1215) stacked sequentially along the fifth direction (D5). In exemplary embodiments, the buffer structure (1218) may be disposed in multiple numbers spaced apart from each other along each of the first and second directions (D1, D2). The first buffer (1195) may include an oxide, for example, silicon oxide, the second buffer (1205) may include a high dielectric material, and the third buffer (1215) may include a nitride, for example, silicon nitride.

[0168] The second bit line structure (1300) can be extended in a second direction (D2) and can be arranged in multiple units spaced apart from each other along the first direction (D1). At this time, the second bit line structure (1300) can overlap the central part of the second active structure (1105) along the fifth direction (D5), and a second contact plug structure (1268) can be formed between them. Additionally, the second bit line structure (1300) can contact the upper surface of the buffer structure (1218).

[0169] The second bit line structure (1300) may include a third barrier pattern (1270), a fifth metal pattern (1280), and a seventh mask (1290) sequentially stacked along a fifth direction (D5). The third barrier pattern (1270) may include a metal nitride, for example, titanium nitride, or a metal silicon nitride, for example, titanium silicon nitride; the fifth metal pattern (1280) may include a metal, for example, tungsten; and the seventh mask (1290) may include an insulating nitride, for example, silicon nitride.

[0170] The embedded pattern (1330) may be placed on the portion of the second device isolation pattern (1110) adjacent to the first direction (D1) in the central portion of each second active structure (1105), and may be placed between the second contact plug structures (1268) adjacent to each other in the first direction (D1). The embedded pattern (1330) may be arranged in multiple numbers so as to be spaced apart from each other in the second direction (D2) between the second bit line structures (1300) adjacent to each other in the first direction (D1), each extending in the second direction (D2). Additionally, the embedded pattern (1330) may be arranged in multiple numbers so as to be spaced apart from each other in the first direction (D1) between the second gate structures (1160) adjacent to each other in the second direction (D2), each extending in the first direction (D1).

[0171] In exemplary embodiments, the lower surface of the embedded pattern (1330) may be positioned at substantially the same height as the lower surface of the central portion of each second active structure (1105) and the lower surface of the second contact plug structure (1268), and may be higher than the upper surface of the fourth conductive pattern (1140) included in the second gate structure (1160). Additionally, the upper surface of the embedded pattern (1330) may be lower than the upper surfaces of the two end portions of each second active structure (1105).

[0172] The buried pattern (1330) may include insulating nitrides such as silicon nitride, silicon carbonitride, etc.

[0173] The fifth spacer (1230) may be disposed on the side wall of the second mold film (1170) and the buffer structure (1218). However, in some cases, the fifth spacer (1230) may not be formed. The fifth spacer (1230) may include, for example, an insulating nitride such as silicon nitride.

[0174] The second spacer structure (1800) may include a sixth spacer (1310), a seventh spacer (1350), a third etch stop pattern (1375), and an eighth spacer (1385) stacked along the first direction (D1) from the side wall toward the first direction (D1) of the second bit line structure (1300).

[0175] In exemplary embodiments, each of the sixth and seventh spacers (1310, 1350) may extend in a second direction (D2).

[0176] In exemplary embodiments, the sixth spacer (1310) may contact each of the two side walls in the first direction (D1) of the second contact plug structure (1268) and each of the two side walls in the first direction (D1) of the second bit line structure (1300). Additionally, the sixth spacer (1310) may contact each of the two side walls in the first direction (D1) of the second and third buffers (1205, 1215) included in the buffer structure (1218), and the upper surface of each of the two end portions in the first direction (D1) of the first buffer (1195).

[0177] Accordingly, the lower surface of the sixth spacer (1310) can be formed at substantially the same height as the upper surface of the central portion of each second active structure (1105), the upper surface of the second element separation pattern (1110) portion adjacent thereto in the first direction (D1), and the lower surface of the embedded pattern (1330).

[0178] In exemplary embodiments, the seventh spacer (1350) may contact each of the two side walls in the first direction (D1) of the sixth spacer (1310), and each of the two side walls in the first direction (D1) of the first buffer (1195) included in the buffer structure (1218). Additionally, the seventh spacer (1350) may contact the upper surface of each of the two end portions in the first direction (D1) of the fourth mold (1185) and the upper surface of each of the two end portions in the first direction (D1) of the embedded pattern (1330).

[0179] Accordingly, the lowest surface of the seventh spacer (1350) can be positioned at substantially the same height as the upper surface of the buried pattern (1330) and can be higher than the lowest surface of the sixth spacer (1310).

[0180] The third etching prevention pattern (1375) and the eighth spacer (1385) can be sequentially stacked on each side wall in the first direction (D1) of the seventh spacer (1350), each side wall in the first direction (D1) of the fourth mold (1185), both side walls and the top surface in the second direction (D2) of the second and third mold films (1170, 1175), and the outer wall in the second direction (D2) of the fifth spacer (1230).

[0181] In exemplary embodiments, the lower surface of the third etching prevention pattern (1375) and the lower surface of the eighth spacer (1385) may be formed at substantially the same height as the upper surface of the end portion of each second active structure (1105), and thus may be higher than the lower surface of the seventh spacer (1350).

[0182] Each of the sixth spacer (1310) and the eighth spacer (1385) may include an insulating nitride, for example, silicon nitride, and each of the seventh spacer (1350) and the third etching stop pattern (1375) may include an oxide, for example, silicon oxide.

[0183] The third contact plug structure (1425) is positioned on each of the aforementioned ends of the second active structure (1105) to contact the impurity region structure (1107) and may be formed in multiple numbers spaced apart from each other along each of the first and second directions (D1, D2).

[0184] In exemplary embodiments, the third contact plug structure (1425) may include a lower portion having a first width in a first direction (D1) and an upper portion disposed on the lower portion having a second width in the first direction (D1) that is smaller than the first width. In this case, the lower portion of the third contact plug structure (1425) may contact the second active structure (1105) and the second element isolation pattern (1110) adjacent thereto.

[0185] The second active structure (1105) may further include a second epitaxial pattern (1106) disposed at each end portion toward the third direction (D3) as well as the second active pattern (1104), and thus may have an increased area compared to including only the second active pattern (1104). Accordingly, the contact area between the third contact plug structure (1425) and the second active structure (1105) is increased, and the contact resistance between them may be reduced.

[0186] The upper side wall of the third contact plug structure (1425) can be covered by the eighth spacer (1385). In exemplary embodiments, the lower surface of the third etching stop pattern (1375) and the lower surface of the eighth spacer (1385) can come into contact with the upper surface of the upper edge portion of the third contact plug structure (1425).

[0187] The third contact plug structure (1425) may include, for example, polysilicon doped with impurities.

[0188] The second barrier pattern (1430) may be placed on the embedment pattern (1330) and may also be placed on the portion of the eighth spacer (1385) placed on the second and third mold films (1170, 1175). In exemplary embodiments, the second barrier pattern (1430) may be formed in multiple numbers spaced apart from each other along each of the first and second directions (D1, D2).

[0189] The second barrier pattern (1430) may include a lower portion having a first width in a first direction (D1), and an upper portion disposed on the lower portion having a second width greater than the first width in the first direction (D1). At this time, the lower portion and the upper portion of the second barrier pattern (1430) may be disposed at heights corresponding to the lower portion and the upper portion of the third contact plug structure (1425), respectively.

[0190] The lower surface of the lower part of the second barrier pattern (1430) may contact the upper surface of the embedded pattern (1330), and the side wall of the lower part of the second barrier pattern (1430) in the first direction (D1) may contact the outer wall of the seventh spacer (1350). Additionally, the side wall of the upper part of the second barrier pattern (1430) in the first direction (D1) may contact the eighth spacer (1385), and the side wall of the upper part of the second barrier pattern (1430) in the second direction (D2) may contact the third contact plug structure (1425).

[0191] The second barrier pattern (1430) may include an insulating nitride, such as silicon nitride, silicon carbonitride, etc.

[0192] The landing pads (1460) may contact the upper surface of the third contact plug structure (1425) and may be arranged in multiple numbers spaced apart from each other along each of the first and second directions (D1, D2). In exemplary embodiments, the landing pads (1460) may have a shape such as a circle, ellipse, polygon, or rounded polygon when viewed from above, and may be arranged in a honeycomb pattern. The landing pads (1460) may include metal, metal nitride, etc.

[0193] The eighth insulation pattern (1470) can cover the side walls of the landing pads (1460) and can also partially penetrate the upper portion of the second bit line structure (1300), the third contact plug structure (1425), and the second barrier pattern (1430). The eighth insulation pattern (1470) may include an insulating nitride, for example, silicon nitride.

[0194] The second capacitor (1510) may include a second lower electrode (1480), a second dielectric film (1490), and a second upper electrode (1500) that are sequentially stacked, and the second lower electrode (1480) may contact the upper surface of the landing pad (1460).

[0195] In the semiconductor device according to exemplary embodiments, the second bit line structure (1300) may be electrically connected to the central portion of the second active structure (1105) through the second contact plug structure (1268), and the second capacitor (1510) may be electrically connected to the terminal portion of the second active structure (1105) through the landing pad (1460) and the third contact plug structure (1425).

[0196] FIGS. 31 to 73 are perspective views, plan views, and cross-sectional views for illustrating a method of manufacturing a semiconductor device according to exemplary embodiments. Specifically, FIGS. 31 to 33 are perspective views, FIGS. 34, 37, 40, 43, 46, 49, 52, 55, 62, 65, 68 and 71 are plan views, FIGS. 35, 38, 41, 44, 47, 50, 53, 56, 58, 60, 63, 66, 69 and 72 include cross-sectional views cut along the A-A' and B-B' lines of the corresponding plan views, respectively, and FIGS. 36, 39, 42, 45, 48, 51, 54, 57, 59, 61, 64, 67, 70 and 73 include cross-sectional views cut along the C-C' and E-E' lines of the corresponding plan views, respectively. FIGS. 31 to 33 are perspective views of the Y region of FIG. 34.

[0197] Meanwhile, the method for forming a second active structure described with reference to FIGS. 31 to 33 includes processes that are substantially identical or similar to the processes included in the method for forming a first active structure described with reference to FIGS. 4 to 9, so a redundant description thereof is omitted.

[0198] In addition, the method for forming structures described with reference to FIGS. 34 to 73 and FIGS. 27 to 30 includes substantially identical or similar processes to the method for forming structures described with reference to FIGS. 10 to 26 and FIGS. 1 to 3, so a redundant description thereof is omitted.

[0199] Referring to FIG. 31, processes substantially identical or similar to those described with reference to FIG. 4 through 7 can be performed.

[0200] Accordingly, an etching process can be performed on the upper surface of the second substrate (1100) to form a plurality of second preliminary active patterns (1102) spaced apart from each other in a first direction (D1), and each second preliminary active pattern (1102) can be extended in a third direction (D3).

[0201] Additionally, a third preliminary device separator (42) may be formed on the second substrate (1100) and the second preliminary active patterns (1102), and second to fourth mask films (50, 60, 70) may be formed sequentially on the third preliminary device separator (42).

[0202] Meanwhile, the fourth mask film (70) can be partially removed to form a tenth opening (77) that exposes the upper surface of the third mask film (60). At this time, the tenth opening (77) may be extended in the first direction (D1) and may be formed in multiple numbers spaced apart from each other along the second direction (D2).

[0203] Referring to FIG. 32, processes substantially identical or similar to those described with reference to FIG. 8 can be performed.

[0204] Accordingly, a third preliminary device isolation film (42) portion that overlaps the 10th opening (77) and the 5th direction (D5), and a second preliminary active pattern (1102) portion formed underneath it can be removed through a dry etching process to form a 11th opening (47) that exposes the upper surface of the second substrate (1100).

[0205] The eleventh opening (47) can penetrate each second preliminary active pattern (1102) to expose the upper surface of the second substrate (1100). In exemplary embodiments, the eleventh opening (47) may extend in a first direction (D1) and may be formed in multiple numbers spaced apart from each other along a second direction (D2). Accordingly, each second preliminary active pattern (1102) may be separated into multiple second active patterns (1104) spaced apart from each other in a third direction (D3) by the eleventh openings (47), and the second active patterns (1104) may be spaced apart from each other along each first and third direction (D1, D3).

[0206] Referring to FIG. 33, processes substantially identical or similar to those described with reference to FIG. 9 can be performed.

[0207] Accordingly, by performing an SEG process using the sidewall of the second active pattern (1104) exposed by the first opening (47) as a seed, a second epitaxial pattern (1106) can be formed on the portion of the second active pattern (1104) exposed by the first opening (47).

[0208] In exemplary embodiments, the second epitaxial pattern (1106) may be formed on the sidewalls of each end portion in the third direction (D3) of the second active pattern (1104) exposed by the first opening (47). However, the second epitaxial pattern (1106) may be formed on the upper surface of the second substrate (1100) exposed by the first opening (47), but in this case, for example, an anisotropic etching process may be additionally performed on the second epitaxial pattern (1106) to remove the portion of the second epitaxial pattern (1106) formed on the upper surface of the second substrate (1100).

[0209] In one embodiment, the crystallization direction of the second epitaxial pattern (1106) may be different from the crystallization direction of the second active pattern (1104), and accordingly, the second epitaxial pattern (1106) and the second active pattern (1104) may be distinguished from each other. In another embodiment, the crystallization direction of the second epitaxial pattern (1106) may be the same as the crystallization direction of the second active pattern (1104), and accordingly, the second epitaxial pattern (1106) and the second active pattern (1104) may not be distinguished from each other.

[0210] The second active pattern (1104) and the second epitaxial pattern (1106) can together form a second active structure (1105). In exemplary embodiments, the second active structure (1105) may be extended by a certain length in a third direction (D3) and may be formed in multiple units spaced apart from each other along each of the first and third directions (D1, D3).

[0211] Second active structures (1105) arranged to be spaced apart from each other along the first direction (D1) can together define a second active structure row, and the second active structure rows can be formed in multiple numbers spaced apart from each other along the second direction (D2) or the third direction (D3) to define a second active structure array.

[0212] Afterward, a fourth pre-element separator is formed to fill the first opening (47) on the second active structure (1105) and the third pre-element separator (42), and a planarization process can be performed on the second active pattern (1104) until the upper surface of the second active pattern (1104) is exposed. In exemplary embodiments, the fourth pre-element separator may comprise substantially the same material as the third pre-element separator (42), and accordingly, they may be merged together and form a second element separation pattern (1110) as the planarization process is performed.

[0213] The second device isolation pattern (1110) is formed on the second substrate (1100) and can cover both side walls in the first direction (D1) of each second active pattern (1104), and can also cover the side walls of the second epitaxial pattern (1106) formed on the side walls of each end portion in the third direction (D3) of each second active pattern (1104).

[0214] Referring to FIGS. 34 to 36, after removing the upper portion of the second active structure (1105) and the second device isolation pattern (1110) to form a third recess, a second gate insulating film can be formed on the inner wall of the third recess and on the upper surface of the second active structure (1105) and the second device isolation pattern (1110).

[0215] Additionally, a third conductive film can be formed on the second gate insulating film and then the upper portion thereof can be removed to form a third conductive pattern (1130), and a fourth conductive film can be formed on the third conductive pattern (1130) and the second gate insulating film and then the upper portion thereof can be removed to form a fourth conductive pattern (1140).

[0216] Afterward, a second gate mask film is formed on the fourth conductive pattern (1140) and the second gate insulating film, and a planarization process is performed on the second gate mask film and the second gate insulating film until the upper surface of the second active structure (1105) and the second device isolation pattern (1110) is exposed, thereby forming the second gate mask (1150) and the second gate insulating pattern (1120), respectively.

[0217] The second gate insulation pattern (1120) formed within the third recess, the third and fourth conductive patterns (1130, 1140), and the second gate mask (1150) can together form a second gate structure (1160).

[0218] In exemplary embodiments, the second gate structure (1160) may be extended in a first direction (D1) and may be formed in multiple numbers spaced apart from each other along a second direction (D2). In one embodiment, two second gate structures (1160) spaced apart from each other in a second direction (D2) may be formed on the upper part of a second active structure (1105). Hereinafter, the portion formed between the two second gate structures (1160) in the second active structure (1105) will be referred to as the central portion, and the portion formed on the opposite side of the central portion with respect to each second gate structure (1160) will be referred to as the end portion.

[0219] Referring to FIGS. 37 to 39, second and third mold films (1170, 1175) can be formed on the second active structure (1105), the second device isolation pattern (1110), and the second gate structure (1160), and a 12th opening (1177) can be formed between them.

[0220] In exemplary embodiments, each of the second and third mold films (1170, 1175) may be extended in a first direction (D1), and accordingly, the second opening (1177) may also be extended in the first direction (D1). In this case, the second mold film (1170) may cover the upper surface of two second gate structures (1160) penetrating the upper part of the second active structure (1105) and the upper surface of the central part of the second active structure (1105), and the third mold film (1175) may cover the upper surface of the second element separation pattern (1110) portion between the rows of the second active structures adjacent to each other in the second direction (D2).

[0221] In one embodiment, the second mold film (1170) may not cover the portion of the second gate insulating pattern (1120) adjacent to the end portion of the second active structure (1105) of each second gate structure (1160), and the third mold film (1175) may be spaced apart from the end portion of each second active structure (1105) in the second direction (D2).

[0222] Subsequently, an etching process is performed using the second and third mold films (1170, 1175) as an etching mask to remove the upper portions of the second active structure (1105), the second device isolation pattern (1110), and the second gate insulation pattern (1120) exposed by the 12th opening (1177), and accordingly, the 12th opening (1177) can be extended downward. During the etching process, the upper portions of each end portion of the second active structure (1105) can be removed.

[0223] Subsequently, an impurity region structure (1107) can be formed by performing a doping process, such as a gas phase doping (GPD) process, on the upper portions of the second active structure (1105) exposed by the 12th opening (1177). At this time, the impurity region structure (1107) may include a first impurity region (1107a) formed in the second active pattern (1104) and a second impurity region (1107b) formed in the second epitaxial pattern (1106).

[0224] Referring to FIGS. 40 to 42, a fourth mold film (1180) filling the 12th opening (1177) is formed on the second active structure (1105), the second device isolation pattern (1110), the second gate insulation pattern (1120), and the second and third mold films (1170, 1175), and then a planarization process can be performed thereon, so that the fourth mold film (1180) is formed within the 12th opening (1177) and can be extended along the first direction (D1).

[0225] Afterwards, first to third buffer films (1190, 1200, 1210) are sequentially stacked along the fifth direction (D5) on the second to fourth mold films (1170, 1175, 1180), and a third opening (1220) is formed that exposes the upper surfaces of the second active structure (1105) and the second device isolation pattern (1110) by penetrating these and the second mold film (1170) formed below them.

[0226] In exemplary embodiments, the 13th opening (1220) may extend in a first direction (D1) and may expose the central portion of each second active structure (1105) included in the row of the second active structures, the portion of the second element isolation pattern (1110) adjacent thereto in the first direction (D1), and the portion of the second gate insulation pattern (1120) adjacent thereto in the second direction (D2).

[0227] Subsequently, a fifth spacer film can be formed on the second active structure (1105), the second device isolation pattern (1110), and the second gate insulation pattern (1120) exposed by the first to third buffer films (1190, 1200, 1210) and the third opening (1220), and an anisotropic etching process can be performed thereon to form the fifth spacer (1230) on each sidewall toward the second direction (D2) of the third opening (1220).

[0228] Subsequently, the upper portion of the central part of the second active structures (1105) exposed by the 13th opening (1220), the adjacent second element isolation pattern (1110) portion, and the adjacent second gate insulation pattern (1120) portion can be removed, and accordingly, the 13th opening (1220) can be extended downward along the 5th direction (D5).

[0229] Referring to FIGS. 43 to 45, a second pad film, an ohmic contact film, and a fourth metal film can be sequentially formed within the 13th opening (1220).

[0230] The above ohmic contact film can be formed by forming a third metal film on the second pad film and then performing a heat treatment process thereon, thereby causing the third metal film and the second pad film to react with each other.

[0231] Afterwards, a flattening process may be further performed on the upper surface of the fourth metal film, and accordingly, the upper surface of the fourth metal film may be formed at substantially the same height as the upper surface of the third buffer film (1210).

[0232] Subsequently, a third barrier film, a fifth metal film, and a seventh mask film are sequentially stacked along a fifth direction (D5) on the third buffer film (1210), the fourth metal film, and the fifth spacer (1230), and after forming a seventh mask (1290) by patterning the seventh mask film, an etching process is performed using the seventh mask as an etching mask to pattern the fifth metal film, the third barrier film, and the third buffer film (1210), and furthermore, the fourth metal film, the ohmic contact film, and the second pad film can also be patterned.

[0233] Accordingly, the second pad film, the ohmic contact film, and the fourth metal film can each be converted into a second pad (1240), an ohmic contact pattern (1250), and a fourth metal pattern (1260), respectively, and together can form a second contact plug structure (1268). In exemplary embodiments, the second contact plug structure (1268) may be formed in multiple numbers spaced apart from each other along the first direction (D1) within the third opening (1220).

[0234] Additionally, the third barrier film and the fifth metal film can be converted into a third barrier pattern (1270) and a fifth metal pattern (1280), respectively. The third barrier pattern (1270), the fifth metal pattern (1280), and the seventh mask (1290), which are sequentially stacked along the fifth direction (D5), can together form a second bit line structure (1300). In exemplary embodiments, the second bit line structure (1300) can be extended in the second direction (D2) and can be formed in multiple units spaced apart from each other along the first direction (D1).

[0235] At this time, the second bit line structure (1300) can overlap the upper surface of the central portion of each second active structure (1105) arranged in the second direction (D2), and a second contact plug structure (1268) can be interposed between them to electrically connect them to each other.

[0236] Meanwhile, the second and third buffer membranes (1200, 1210) can be patterned and remain as the second and third buffers (1205, 1215), respectively, at the bottom of the second bit line structure (1300).

[0237] Referring to FIGS. 46 to 48, a second bit line structure (1300), a second contact plug structure (1268), second and third buffers (1205, 1215), a first buffer film (1190), a fifth spacer (1230), and a second active structure (1105), a second device isolation pattern (1110), and a second gate insulation pattern (1120) exposed by a first opening (1220) can be formed by forming a sixth spacer film and performing an anisotropic etching process thereon to form a sixth spacer (1310) on the sidewalls of the second bit line structure (1300), the second contact plug structure (1268), and the second and third buffers (1205, 1215).

[0238] Subsequently, an etching process, such as a dry etching process or a wet etching process, can be performed on the first buffer film (1190) to form the first buffer (1195), and the first buffer (1195) may remain below the second buffer (1205) and the sixth spacer (1310). The first to third buffers (1195, 1205, 1215) stacked sequentially along the fifth direction (D5) can together form a buffer structure (1218). In exemplary embodiments, the buffer structure (1218) may be formed in multiple numbers so as to be spaced apart from each other by the second contact plug structure (1268) and the fifth spacer (1230) along the second direction (D2) below the second bit line structure (1300).

[0239] As the above etching process is performed, the upper surface of the second to fourth mold films (1170, 1175, 1180) that do not overlap with the second bit line structure (1300) and the fifth direction (D5) may be exposed.

[0240] Referring to FIGS. 49 to 51, a buried pattern (1330) can be formed within the 13th opening (1220).

[0241] In exemplary embodiments, the buried pattern (1330) can be formed by forming a buried film that fills the 13th opening (1220) on the second bit line structure (1300), the 6th spacer (1310), the first buffer (1195), the 2nd to 4th mold films (1170, 1175, 1180), the 5th spacer (1230), the second active structure (1105), the second device isolation pattern (1110), and the second gate insulation pattern (1120), and by performing an etching process on the upper part of the buried film.

[0242] Accordingly, a buried pattern (1330) that contacts the lower side wall of the sixth spacer (1310) formed on the side wall of the second contact plug structure (1268) can be formed on the second active structure (1105), the second element isolation pattern (1110), and the second gate insulation pattern (1120) exposed by the 13th opening (1220).

[0243] The embedded pattern (1330) may be formed in multiple numbers so as to be spaced apart from each other by the lower portions of the second contact plug structure (1268) and the sixth spacer (1310) along the first direction (D1) within each of the 13 openings (1220). In exemplary embodiments, the upper surface of the embedded pattern (1330) may be formed at substantially the same height as the upper surface of the second active structure (1105) and the second element isolation pattern (1110).

[0244] Referring to FIGS. 52 to 54, the upper part of the embedded pattern (1330) is removed, for example, through an etch back process to form a 14th opening (1365), and then a 7th spacer (1350) is formed on the outer wall of a 6th spacer (1310) formed on each of the two side walls in the first direction (D1) of the 2nd bit line structure (1300) and the 2nd contact plug structure (1268), and an etching process can be performed using the 2nd bit line structure (1300), the 2nd contact plug structure (1268), and the 6th and 7th spacers (1310, 1350) as an etching mask.

[0245] Accordingly, the upper portions of the fourth mold film (1180), the second active structure (1105), and the second device isolation pattern (1110) may be partially removed to form a fifth opening (1360). During the etching process, the fourth mold film (1180) extending in the first direction (D1) may be converted into a plurality of fourth molds (1185) spaced apart from each other along the first direction (D1), and each fourth mold (1185) may be formed below the buffer structure (1218).

[0246] Referring to FIGS. 55 to 57, the upper surfaces and sidewalls of the second active structure (1105) and the second device isolation pattern (1110) exposed by the 14th and 15th openings (1365, 1360), the upper surface of the buried pattern (1330), the upper surface of the second bit line structure (1300), the seventh spacer (1350), the fourth mold (1185), the sidewalls of the fifth spacer (1230) and the second gate insulation pattern (1120), and the upper surfaces and sidewalls of the second and third mold films (1170, 1175) can be sequentially stacked with the third etch stop film (1370) and the eighth spacer film (1380).

[0247] Subsequently, a second sacrificial film that fills the 14th and 15th openings (1365, 1360) on the 8th spacer film (1380) may be formed, for example, through a coating process, and the upper part of the second sacrificial film may be removed, for example, through an etch-back process to form a second sacrificial pattern (1390). In one embodiment, the upper surface of the second sacrificial pattern (1390) may be formed at substantially the same height as the upper surfaces of the second active structure (1105) and the second device isolation pattern (1110), but the concept of the present invention is not limited thereto.

[0248] The second sacrifice pattern (1390) may include, for example, a spin-on-hard mask (SOH), an amorphous carbon film (ACL), etc.

[0249] Referring to FIGS. 58 and 59, a third sacrificial film can be formed on the eighth spacer film (1380) and the second sacrificial pattern (1390), and an anisotropic etching process can be performed thereon to form a third sacrificial pattern (1400) on the upper sidewall of the eighth spacer film (1380).

[0250] The third sacrifice pattern (1400) may include, for example, an oxide such as silicon oxide.

[0251] Referring to FIGS. 60 and 61, the second sacrifice pattern (1390) can be removed, for example, through an ashing process and / or a stripping process to form a 16th opening (1410) that exposes the surface of the lower part of the 8th spacer membrane (1380).

[0252] Afterward, the lower part of the 8th spacer film (1380) exposed by the 16th opening (1410) can be further removed through a stripping process including, for example, a wet etching process using phosphoric acid (1H3PO4) to expose the surface of the lower part of the 3rd etching stop film (1370).

[0253] During the above strip process, the upper surface of the embedded pattern (1330) may not be removed as it is covered by the third etching stop layer (1370), and the remaining portion of the eighth spacer layer (1380) may not be removed as it is covered by the third sacrifice pattern (1400).

[0254] Referring to FIGS. 62 to 64, the lower portion of the third etch blocking film (1370) exposed by the 16th opening (1410) can be removed through a stripping process including, for example, a wet etching process using hydrofluoric acid (HF), thereby exposing the upper surfaces and sidewalls of the second active structure (1105) and the second device isolation pattern (1110), and the upper surface of the buried pattern (1330).

[0255] Meanwhile, during the stripping process, the third sacrificial pattern (1400) formed on the side wall of the eighth spacer membrane (1380) can also be removed.

[0256] Referring to FIGS. 65 to 67, after removing etching residues by performing a cleaning process, for example, through a wet etching process on the inner wall of the 16th opening (1410), a third contact plug structure film (1420) that fills the space between the 16th opening (1410) and the 2nd bit line structures (1300) is formed on the 2nd active structure (1105), the 2nd device isolation pattern (1110), the buried pattern (1330), and the 8th spacer film (1380), and the third contact plug structure film (1420) can be flattened until the upper surface of the 2nd bit line structure (1300) is exposed.

[0257] During the above planarization process, the upper portions of the third etch stop film (1370) and the eighth spacer film (1380) formed on the upper surface of the second bit line structure (1300) are also removed to form the third etch stop pattern (1375) and the eighth spacer (1385), respectively. Accordingly, the sixth spacer (1310), the seventh spacer (1350), the third etch stop pattern (1375), and the eighth spacer (1385) can be sequentially stacked on each of the two side walls facing the first direction (D1) of the second bit line structure (1300), and together they can form the second spacer structure (1800).

[0258] Meanwhile, the third contact plug structure film (1420) may be formed between adjacent second bit line structures (1300) in the first direction (D1) and extended in the second direction (D2), and may be formed in multiple numbers spaced apart from each other along the first direction (D1). At this time, the third contact plug structure film (1420) may contact the upper surfaces of the second active structure (1105), the second element isolation pattern (1110), and the buried pattern (1330), the side wall of the lower part of the seventh spacer (1350), and the side wall of the eighth spacer (1385).

[0259] Referring to FIGS. 68 to 70, an etching mask having a 17 opening extending in a first direction (D1) is formed on a second bit line structure (1300), a second spacer structure (1800), and a third contact plug structure film (1420), and an etching process using the mask is performed to etch the third contact plug structure film (1420) to form a 18 opening.

[0260] In exemplary embodiments, the 17th opening may overlap the central portions of the second active structures (1105) arranged in the first direction (D1) and the third mold film (1175) along the fifth direction (D5), and accordingly, the 18th opening may expose the upper surface of the embedded pattern (1330) and the upper surface of the portion of the eighth spacer (1385) formed on the third mold film (1175).

[0261] As the above etching process is performed, the third contact plug structure film (1420) extending in the second direction (D2) can be separated into a plurality of third contact plug structures (1425) spaced apart from each other along the second direction (D2), and each third contact plug structure (1425) can come into contact with the upper surface of each end portion of the second active structure (1105).

[0262] That is, each third contact plug structure (1425) can contact the upper surfaces of the second epitaxial pattern (1106) formed on the side wall of the second active pattern (1104) in the third direction (D3) of the second active structure (1105), and as the second active structure (1105) further includes the second epitaxial pattern (1106), the third contact plug structure (1425) can contact the second active structure (1105) over an increased area, and the contact resistance between them can be reduced.

[0263] Afterwards, a second barrier pattern (1430) that fills the 18th opening can be formed.

[0264] Referring to FIGS. 71 to 73, a landing pad film is formed on a second bit line structure (1300), a second spacer structure (1800), a third contact plug structure (1425), and a second barrier pattern (1430). Then, a fourth recess is formed by removing the landing pad film and the second bit line structure (1300), the second spacer structure (1800), the third contact plug structure (1425), and the second barrier pattern (1430) formed underneath it, and then an eighth insulating pattern (1470) that fills the fourth recess can be formed.

[0265] Accordingly, the landing pad membrane may be separated into a plurality of landing pads (1460) spaced apart from each other along the first and second directions (D1, D2), and each landing pad (1460) may contact the upper surface of the third contact plug structure (1425). In exemplary embodiments, the landing pads (1460) may be arranged in a honeycomb pattern when viewed from above. Alternatively, the landing pads (1460) may be arranged in a different pattern, for example, a grid pattern, when viewed from above.

[0266] Referring again to FIGS. 27 to 30, a second lower electrode (1480) can be formed on a landing pad (1460), and a second dielectric film (1490) can be formed on the second lower electrode (1480) and the eighth insulating pattern (1470), and then a second upper electrode (1500) can be formed on the second dielectric film (1490).

[0267] The second lower electrode (1480), the second dielectric film (1490), and the second upper electrode (1500) stacked sequentially can together form a second capacitor (1510).

[0268] The manufacturing of the semiconductor device can be completed by performing the aforementioned processes.

[0269] As described above, although the present invention has been explained with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the claims.

[0270] As described above, although the present invention has been explained with reference to preferred embodiments, those skilled in the art will understand that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention as described in the claims. Explanation of the symbols

[0271] 10, 1240: 1st and 2nd pads 20, 485, 1290: 1st, 5th, 7th masks 30: First Recess 40: First preliminary element separator 42: Third preliminary element separator 50, 60, 70: 2nd to 4th mask films 75, 45, 440, 640: 1st to 4th openings 77, 47, 1177, 1220, 1365, 1360, 1410: 10th to 16th openings 300, 1100: 1st and 2nd substrates 302: 1st Preliminary Active Pattern 304, 1104: 1st and 2nd active patterns 305, 1105: 1st and 2nd active structures 306, 1106: 1st and 2nd Epitaxial Patterns 310, 1110: First and second element isolation patterns 330, 1120: 1st and 2nd gate insulation patterns 340: First gate electrode 350, 1150: 1st and 2nd Gate Masks 360, 1160: 1st and 2nd Gate Structures 400, 410, 420: First to third insulating films 405, 415, 425, 610, 620, 770, 780, 1470: 1st to 8th insulation patterns 430: Insulating membrane structure 435, 790: 1st and 2nd insulation pattern structures 450, 470: 1st, 2nd Challenge Screen 455, 475, 1130, 1140: 1st to 4th challenge patterns 460, 730: 2nd, 2nd barrier membrane 465, 735, 1270: First to third barrier patterns 480: 5th mask barrier 565, 1375: 1st and 3rd etching stop patterns 585 capping pattern 595, 1300: 1st and 2nd bit line structures 600, 630, 650, 690, 1230, 1310, 1350, 1385: 1st to 8th spacers 635: Air Spacer 660: Spare spacer structure 665, 1800: 1st and 2nd spacer structures 675: Lower contact plug 680, 1390, 1400: 1st to 3rd sacrifice patterns 685, 1430: 1st and 2nd barrier patterns 700: Metal silicide pattern 740: Second metal film 745, 1260, 1280: 2nd, 4th, and 5th metal patterns 755: Upper contact plug 760: The 8th opening 800, 1370: 2nd and 3rd etching stops 810, 1480: 1st and 2nd lower electrodes 820, 1490: 1st and 2nd dielectric membranes 830, 1500: 1st and 2nd upper electrodes 840, 1510: 1st and 2nd capacitors 1107: Impurity region structure 1107a, 1107b: 1st and 2nd impurity regions 1170, 1175, 1180: 1st to 3rd mold films 1180: 4th mold film 1185: 4th Mold 1190, 1200, 1210: 1st to 3rd buffer membranes 1195, 1205, 1215: 1st to 3rd buffers 1218: Buffer structure 1250: Ohmic Contact Pattern 1268, 1425: Second and third contact plug structures 1330: Landfill pattern 1420: Third contact structure membrane 1460: Landing pad

Claims

Claim 1 A semiconductor device comprising: an active pattern extending in a first direction parallel to the upper surface of the substrate on a substrate; an active structure having an epitaxial pattern disposed on the sidewalls of each of the two ends of the active pattern in the first direction, wherein the lowest surface is disposed at the same height as the lower surface of the active pattern and comprises a single-crystal semiconductor material; a gate structure embedded on the upper portion of the active structure; a bit line structure disposed on the central portion of the active structure in the first direction; a contact plug structure disposed on each of the two ends of the active structure; and a capacitor disposed on the contact plug structure. Claim 2 In claim 1, the active pattern comprises first sidewalls facing each other in the first direction, and second sidewalls facing each other in a second direction parallel to the upper surface of the substrate and intersecting the first direction, and the epitaxial pattern is a semiconductor device disposed on each of the first sidewalls of the active pattern. Claim 3 A semiconductor device according to claim 1, wherein each of the first sidewalls of the active pattern has a rounded curved shape when viewed from above, and each of the second sidewalls of the active pattern has a straight shape extended in the first direction when viewed from above. Claim 4 A semiconductor device according to claim 1, wherein the epitaxial pattern comprises a single-crystal semiconductor material identical to the active pattern. Claim 5 In paragraph 4, the semiconductor device in which the determination direction of the epitaxial pattern is the same as the determination direction of the active pattern. Claim 6 A semiconductor device according to claim 4, wherein the determination direction of the epitaxial pattern is different from the determination direction of the active pattern. Claim 7 A semiconductor device according to claim 1, wherein the active structures are arranged in a plurality of units spaced apart from each other along a second direction that is parallel to the upper surface of the substrate and intersects the first direction, and the plurality of active structures are arranged in a zigzag pattern along the second direction. Claim 8 A semiconductor device according to claim 7, wherein the determination direction of the epitaxial pattern included in the first active structure among the plurality of active structures is different from the determination direction of the active pattern included in the first active structure. Claim 9 A semiconductor device comprising: active patterns arranged on a substrate, each having a curved shape and each having first sidewalls extending in a first direction parallel to the upper surface of the substrate and each having a curved shape and second sidewalls extending in a straight shape in a second direction parallel to the upper surface of the substrate and orthogonal to the first direction and each having a curved shape; active structures each having an acute angle with each of the first and second directions and each having an epitaxial pattern disposed on the first sidewalls of each of the active patterns; a gate structure embedded on the upper portion of the active structures; a bit line structure disposed on the central portion of each of the active structures in the first direction; a contact plug structure disposed on each of the two end portions of each of the active structures in the first direction; and a capacitor disposed on the contact plug structure, wherein the epitaxial patterns disposed on the first sidewalls of each of the active patterns do not overlap each other along the third direction. Claim 10 A semiconductor device comprising: an active pattern having, on a substrate, first sidewalls having a curved shape that are opposite to each other in a first direction and extending in a first direction parallel to the upper surface of the substrate, and second sidewalls having a straight shape that are opposite to each other in a second direction parallel to the upper surface of the substrate and intersecting in the first direction and extending in the first direction; an active structure having an epitaxial pattern disposed on each of the first sidewalls of the active pattern, wherein the lowest side is disposed at the same height as the lower side of the active pattern and comprises a single-crystal semiconductor material; a device isolation pattern disposed on the substrate and covering the second sidewalls of the active pattern and the sidewalls of the epitaxial pattern; a gate structure embedded on the upper part of the active structure; a bit line structure disposed on the central part of the active structure in the first direction; a contact plug structure disposed on each of the two ends of the active structure; and a capacitor disposed on the contact plug structure.

Images