Integrated chip and method of manufacturing the same

Abstract

The integrated chip includes a barrier layer comprising a first conductive material on a semiconductor substrate. The integrated chip includes a lower electrode layer comprising a second conductive material different from the first conductive material, on the barrier layer. The integrated chip includes a dielectric layer on the lower electrode layer. The integrated chip includes an upper electrode layer on the dielectric layer. The integrated chip includes an encapsulation layer comprising a first dielectric material that encapsulates the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer. The integrated chip includes a spacer layer comprising a second dielectric material different from the first dielectric material, on the upper surface of the barrier layer. The encapsulation layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer.

Description

Technology Field

[0001] Reference to related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 788,293 filed on April 14, 2025, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0003] Many electronic devices today include electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile memory stores data while power is supplied, whereas non-volatile memory can retain data even when power is cut off. Resistive random access memory (RRAM) is one of the promising candidates for next-generation non-volatile memory due to its simple structure and compatibility with complementary metal-oxide semiconductors (CMOS). Brief explanation of the drawing

[0004] Aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. The drawings are illustrated to clearly illustrate relevant aspects of the embodiments. The drawings may illustrate relationships between various structures and / or elements within the embodiments. Note that the drawings are not necessarily drawn to scale. In some cases, the dimensions of various features may be increased or decreased at will for clarity of discussion. FIG. 1 illustrates a cross-sectional view of some embodiments of a memory cell including a spacer layer covering the sidewalls of an upper electrode layer, the sidewalls of a data storage layer, and the sidewalls of a lower electrode layer. FIG. 2 shows a cross-sectional view of some embodiments of a memory cell in which a capping layer is located between an upper electrode layer and a data storage layer, and a spacer layer covers the side walls of the capping layer. FIG. 3 illustrates a plan view of some embodiments of a memory cell. FIG. 4 illustrates cross-sectional views of some embodiments of an integrated chip including memory cells. FIG. 5 illustrates cross-sectional views of some embodiments of a memory cell. FIG. 6 illustrates cross-sectional views of some embodiments of an integrated chip in which the integrated chip includes a memory region and a logic region. FIG. 7 illustrates a cross-sectional view of some embodiments of an integrated chip in which a plurality of memory cells are laterally spaced apart in a memory region. FIG. 8 illustrates cross-sectional views of some embodiments of a memory cell. FIGS. 9 and 10 illustrate cross-sectional views of some embodiments of a memory cell having two spacer layers surrounding the memory cell. FIGS. 11 and 12 illustrate cross-sectional views of some embodiments of a memory cell in which a lower electrode layer is laterally resized at the sidewalls of the lower electrode layer. FIGS. 13 and 14 illustrate cross-sectional views of some embodiments of a memory cell in which the lower electrode layer has substantially no lateral recesses in the sidewalls of the lower electrode layer. FIGS. 15 to 25 illustrate cross-sectional views of some embodiments of a method for forming an integrated chip including a memory cell. FIGS. 26 to 30 illustrate cross-sectional views of some embodiments of a method for forming a memory cell. FIGS. 31 to 38 illustrate cross-sectional views of some embodiments of a method for forming a memory cell. FIG. 39 illustrates a flowchart of some embodiments of a method for forming an integrated chip including a memory cell. Specific details for implementing the invention

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the provided invention. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature on or above a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features do not come into direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is intended for simplification and clarification, and such repetition itself does not affect the relationship between the various embodiments and / or configurations discussed.

[0006] Additionally, spatial terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein for ease of explanation when describing the relationship between one element or feature and another element or feature as shown in the drawings. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations shown in the drawings. The device may be oriented differently (rotated 90 degrees or other orientations), and the spatially relative terms used herein may likewise be interpreted accordingly. In some embodiments, the terms “approximately” and / or “about” may be interpreted to mean + / - 10% or + / - 5%, whereas in other embodiments, the terms “approximately” and / or “about” may be interpreted to mean within the normal manufacturing tolerances of a given fab manufacturing flow.

[0007] An integrated chip includes transistors on and / or along a semiconductor substrate. Conductive interconnects are on the transistors and coupled to the transistors. A memory cell is on the conductive interconnects and coupled to the transistors by the conductive interconnects. The memory cell includes a lower electrode layer coupled to the conductive interconnects, a data storage layer (e.g., a memory layer) on the lower electrode layer, and an upper electrode layer on the data storage layer. The data storage layer may be placed in a first state (e.g., a high resistance state) to store a first logic value (e.g., 0) in the memory cell. The data storage layer may be placed in a second state (e.g., a low resistance state) to store a second logic value (e.g., 1) in the memory cell.

[0008] The encapsulation layer extends over the upper electrode layer and along the sidewalls of the upper electrode layer, the data storage layer, and the lower electrode layer. In some cases, the encapsulation layer comprises an oxygen-containing dielectric material (e.g., silicon oxide). Consequently, in some cases, portions of the upper electrode layer and / or the lower electrode layer may be oxidized when forming the encapsulation layer. Such oxidation may reduce the performance and / or reliability of the memory cell.

[0009] In various embodiments of the present disclosure, a spacer layer is formed on the sidewalls of the lower electrode layer, the sidewalls of the data storage layer, and the sidewalls of the upper electrode layer before the encapsulation layer is formed to protect the upper electrode layer and the lower electrode layer from oxidation during the formation of the encapsulation layer. The spacer layer can reduce oxidation of the upper electrode layer and / or the lower electrode layer during the formation of the encapsulation layer. As a result, the performance and / or reliability of the memory cell can be improved.

[0010] FIG. 1 illustrates a cross-sectional view (100) of some embodiments of a memory cell (106) comprising a spacer layer (118) covering the sidewalls of an upper electrode layer (114), the sidewalls of a data storage layer (112), and the sidewalls of a lower electrode layer (110). FIG. 2 illustrates a cross-sectional view (200) of some embodiments of a memory cell (106) in which a capping layer (202) is located between the upper electrode layer (114) and the data storage layer (112), and a spacer layer (118) covers the sidewalls of the capping layer (202). FIG. 3 illustrates a top view (300) of some embodiments of a memory cell (106). In some embodiments, the cutting line A-A' of FIG. 3 corresponds to the cutting line A-A' of FIG. 1 and / or FIG. 2.

[0011] A memory cell (106) is located on a conductive interconnect (104) (e.g., a conductive line) and a dielectric layer (102). The memory cell (106) comprises a barrier layer (108), a lower electrode layer (110), a data storage layer (112) (e.g., a memory layer), an upper electrode layer (114), a hard mask layer (116), and a spacer layer (118). The barrier layer (108) is coupled to the conductive interconnect (104) and is located on the upper surface of the dielectric layer (102) and on the upper surface of the conductive interconnect (104). The lower electrode layer (110) is located on the upper surface of the barrier layer (108) and is coupled to the conductive interconnect (104) by the barrier layer (108). The data storage layer (112) is located on the upper surface of the lower electrode layer (110). The upper electrode layer (114) is located on the upper surface of the data storage layer (112). The hard mask layer (116) is on the upper surface of the upper electrode layer (114). The dielectric layer (122) is on the memory cell (106). A conductive interconnect (124) (e.g., a conductive via) penetrates the dielectric layer (122) and the hard mask layer (116) and extends to the upper electrode layer (114).

[0012] Data can be stored by the memory cell (106) by adjusting the resistance of the data storage layer (112), which can be achieved by applying a voltage across the data storage layer (112). For example, a first voltage can be applied across the data storage layer (112) to put the data storage layer (112) into a first state (e.g., high resistance state) to store a first logic value (e.g., 0) in the memory cell (106). A second voltage different from the first voltage can be applied across the data storage layer (112) to put the data storage layer (112) into a second state (e.g., low resistance state) to store a second logic value (e.g., 1) in the memory cell (106).

[0013] The spacer layer (118) is on the top surface of the barrier layer (108), the sidewalls of the lower electrode layer (110), the sidewalls of the data storage layer (112), the sidewalls of the upper electrode layer (114), and the sidewalls of the hard mask layer (116). In some embodiments, the spacer layer (118) laterally surrounds the lower electrode layer (110), the data storage layer (112), the upper electrode layer (114), and the hard mask layer (116) in a ring-shaped closed path (e.g., as shown in FIG. 3).

[0014] The encapsulation layer (120) encapsulates the spacer layer (118), the hard mask layer (116), the upper electrode layer (114), the data storage layer (112), the lower electrode layer (110), and the barrier layer (108). The encapsulation layer (120) is spaced apart from the sidewalls of the lower electrode layer (110), the sidewalls of the data storage layer (112), and the sidewalls of the upper electrode layer (114) by the spacer layer (118). Thus, the spacer layer (118) can prevent the lower electrode layer (110) and the upper electrode layer (114) from being oxidized during the formation of the encapsulation layer (120).

[0015] By reducing oxidation of the lower electrode layer (110) and the upper electrode layer (114), the performance and / or reliability of the memory cell (106) can be improved. For example, the effective area of ​​the memory cell (106) (corresponding to the capacitance of the memory cell (106)) can be increased, the forming voltage (e.g., voltage for writing the memory cell) can be reduced, the bit error rate can be reduced, the set / reset shot count (e.g., the number of voltage pulses applied to set / reset the memory cell) can be reduced, the set / reset shot count stability can be improved, the set / reset speed can be improved, the natural yield (e.g., the amount of memory cells functioning properly without repair) can be improved, the repair rate (e.g., the amount of memory cells functioning properly after repair) can be improved, and / or the structural integrity of the memory cell (106) can be improved.

[0016] The spacer layer (118) comprises an oxygen-free dielectric material or a low-oxygen dielectric material to further reduce oxidation of the upper electrode layer (114), the capping layer (202), and the lower electrode layer (110). For example, in some embodiments, the spacer layer (118) contains an atomic percentage of oxygen lower than that of the encapsulation layer (120). In some embodiments, the atomic percentage of oxygen in the spacer layer (118) is less than 20%, less than 15%, or some other suitable value. In some embodiments, the spacer layer (118) is substantially oxygen-free (e.g., the atomic percentage of oxygen in the spacer layer (118) is less than 4%, less than 2%, less than 1%, less than 0.5%, or some other suitable value). In some embodiments, the oxygen-free dielectric material is silicon nitride, silicon carbide, silicon carbonitride, or some other suitable material or comprises such. In some embodiments, the low-oxygen dielectric material is silicon oxynitride, silicon oxycarbonate, silicon oxycarbonite, or some other suitable material, or includes the same.

[0017] In some embodiments, the memory cell (106) is a resistive random access memory (RRAM) cell in which the data storage layer (112) comprises a high-k dielectric material. In these embodiments, a first voltage may be applied across the data storage layer to form a conductive filament having an oxygen vacancy within the data storage layer (112) to reduce the resistance of the data storage layer (112), thereby storing a second logic value (e.g., "1") within the memory cell (106). Additionally, a second voltage may be applied across the data storage layer (112) to destroy the conductive filament within the data storage layer (112) to increase the resistance of the data storage layer (112), thereby storing a first logic value (e.g., "0") in the memory cell (106). In some embodiments where the memory cell is an RRAM cell, the memory cell (106) further includes a capping layer (202) between the data storage layer (112) and the upper electrode layer (114), as illustrated in FIG. 2. The capping layer (202) can help provide oxygen vacancies (forming conductive filaments) to the data storage layer (112).

[0018] In some other embodiments, the memory cell (106) is a phase change random access memory (PCRAM) cell in which the data storage layer (112) comprises a chalcogenide material. In some other embodiments, the memory cell is a magnetoresistive random access memory (MRAM) cell in which the electrode layers (110, 114) comprise ferromagnetic materials and the data storage layer (112) comprises a tunnel barrier dielectric material. In some other embodiments, the memory cell (106) is a ferroelectric random access memory (FeRAM) cell in which the data storage layer (112) comprises a ferroelectric material.

[0019] The barrier layer (108) comprises a first conductive material. In some embodiments, the barrier layer (108) comprises tantalum, titanium, ruthenium, aluminum, cobalt, molybdenum, rhodium, tantalum nitride, titanium nitride, ruthenium nitride, aluminum nitride, cobalt nitride, molybdenum nitride, rhodium nitride, tungsten nitride, manganese nitride, nickel nitride, tin nitride, magnesium nitride, or some other suitable material. In some embodiments, the thickness of the barrier layer (108) is within a range of about 5 Angstroms to about 140 Angstroms, about 10 Angstroms to about 130 Angstroms, about 20 Angstroms to about 100 Angstroms, or some other suitable thickness.

[0020] The lower electrode layer (110) comprises a second conductive material different from the first conductive material. In some embodiments, the lower electrode layer (110) comprises ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, titanium; an alloy of any of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; a nitride of any of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; or some other suitable material. In some embodiments, the thickness of the lower electrode layer (110) is within a range of about 20 Angstroms to about 200 Angstroms, about 75 Angstroms to about 200 Angstroms, about 100 Angstroms to about 200 Angstroms, or some other suitable thickness.

[0021] In some embodiments, the data storage layer (112) comprises, for example, a high-k dielectric material such as hafnium oxide, zirconium oxide, lanthanum oxide, gadolinium oxide, yttrium oxide, aluminum oxide, some other high-k dielectric material, or some other suitable material. In some embodiments, the thickness of the data storage layer (112) is within the range of about 10 Angstroms to about 100 Angstroms, about 10 Angstroms to about 90 Angstroms, about 10 Angstroms to about 80 Angstroms, or some other suitable thickness.

[0022] The capping layer (202) comprises a third conductive material. In some embodiments, the capping layer (202) comprises titanium, hafnium, platinum, aluminum, tantalum, zirconium, nickel, iridium, or some other suitable material. In some embodiments, the thickness of the capping layer (202) is within the range of about 25 Angstroms to about 200 Angstroms, about 50 Angstroms to about 200 Angstroms, about 75 Angstroms to about 200 Angstroms, or some other suitable thickness.

[0023] The upper electrode layer (114) comprises a fourth conductive material different from the third conductive material. In some embodiments, the upper electrode layer (114) comprises ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, titanium; an alloy of any of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; a nitride of any of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; or some other suitable material. In some embodiments, the thickness of the upper electrode layer (114) is within a range of about 25 Angstroms to about 200 Angstroms, about 50 Angstroms to about 200 Angstroms, about 75 Angstroms to about 200 Angstroms, or some other suitable thickness.

[0024] In some embodiments, the hard mask layer (116) comprises silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, some metal nitride, or some other suitable material.

[0025] The encapsulation layer (120) comprises a dielectric material different from that of the spacer layer (118). In some embodiments, the encapsulation layer (120) comprises tetraethyl orthosilicate (TEOS) silicon dioxide or some other suitable material. In some embodiments, the dielectric layer (102) and / or the dielectric layer (122) comprises a low-k dielectric material, an ultra-low-k dielectric material (e.g., having a dielectric constant k of less than 2.5), or some other suitable material. In some embodiments, the conductive interconnect (104) and / or the conductive interconnect (124) comprises copper, aluminum, tungsten, titanium, tantalum, or some other suitable material.

[0026] FIG. 4 illustrates a cross-sectional view (400) of some embodiments of an integrated chip including a memory cell (106).

[0027] A transistor (404) is disposed on and / or along a semiconductor substrate (402). The transistor (404) includes a first source / drain, a second source / drain, and a gate structure. Depending on the context, the source / drain(s) may refer to the source or drain individually or collectively. In some embodiments, the gate structure of the transistor (404) (and / or the conductive interconnect (412) coupled to the gate structure of the transistor (404)) forms a word line of a memory array comprising memory cells (106).

[0028] A dielectric structure (406) comprising a plurality of dielectric layers is on a semiconductor substrate (402). A plurality of conductive interconnects (e.g., conductive lines, conductive vias, conductive pads, conductive contacts, etc.) are within the dielectric structure (406). In some embodiments, a conductive interconnect (414) is coupled to a first source / drain of a transistor (404) and forms a source line of a memory array.

[0029] The dielectric layer (102) is on the dielectric structure (406). The conductive interconnect (104) is on the interconnect structure (408) and is coupled to the second source / drain of the transistor (404) by the conductive interconnect structure (408). A plurality of conductive interconnects, including the conductive interconnect (410), are on the conductive interconnect (124) and are coupled to the conductive interconnect (124). In some embodiments, the conductive interconnect (410) forms a bit line of the memory array.

[0030] In some embodiments, the transistor (404) is a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), a bipolar junction transistor (BJT), a fin field-effect transistor (Fin FET), a gate-all-around field-effect transistor (GAA FET), or some other suitable device.

[0031] FIG. 5 illustrates a cross-sectional view (500) of some embodiments of a memory cell (106) in which a diffusion blocking dielectric layer (502) is located between the encapsulation layer (120) and the dielectric layer (102).

[0032] A diffusion-blocking dielectric layer (502) is located on the dielectric layer (102) and the conductive interconnect (104). The diffusion-blocking dielectric layer (502) can help prevent the diffusion of atoms from the conductive interconnect (104) to the layers placed above. The diffusion-blocking dielectric layer (502) has an opening inside directly above the conductive interconnect (104) where the barrier layer (108) contacts the conductive interconnect (104). The opening is defined by the side walls (502a, 502b) of the diffusion-blocking dielectric layer (502).

[0033] A barrier layer (108) is conformally placed over a conductive interconnect (104) and a diffusion-blocking dielectric layer (502). For example, the barrier layer (108) is on a first upper surface (502c), a second upper surface (502d), a sidewall (502a), and a sidewall (502b) of the diffusion-blocking dielectric layer (502). The barrier layer (108) extends from the sidewall (502a) of the diffusion-blocking dielectric layer (502) to the sidewall (502b) on the upper surface of the conductive interconnect (104).

[0034] The lower electrode layer (110), data storage layer (112), capping layer (202), and upper electrode layer (114) are conformally placed on the barrier layer (108) in a stack and thus have similar shapes. For example, the lower electrode layer (110) is on the first sidewall (unlabeled) of the barrier layer (108), the second sidewall (unlabeled) of the barrier layer (108), and the upper surface (unlabeled) of the barrier layer (108) from the first sidewall to the second sidewall of the barrier layer (108). The hard mask layer (116) follows the upper electrode layer (114) but has a substantially flat upper surface.

[0035] The spacer layer (118) is on the first upper surface of the barrier layer (108) (e.g., on the first ridge of the barrier layer (108) placed over the first portion of the diffusion-blocking dielectric layer (502)) and on the second upper surface of the barrier layer (108) (e.g., on the second ridge of the barrier layer (108) placed over the second portion of the diffusion-blocking dielectric layer (502). In some embodiments, the bottom surface of the spacer layer (118) is on the upper surface (110a) of the lower electrode layer (110). In some embodiments, the bottom surface of the spacer layer (118) is on the upper surface (112a) of the data storage layer (112).

[0036] FIG. 6 illustrates a cross-sectional view (600) of some embodiments of an integrated chip in which the integrated chip includes a memory region (602) and a logic region (604).

[0037] The memory cell (106) is located within the memory region (602) of the integrated chip. In some embodiments, the logic region (604) is adjacent to the memory region (602). The transistors within the logic region (604) are laterally spaced from the transistors within the memory region (602). For example, transistor (614) is laterally spaced from transistor (404). Similarly, the conductive interconnects within the logic region (604) are laterally spaced from the memory cell (106) and from the conductive interconnects within the memory region (602). For example, the conductive interconnect structure (606) is laterally spaced from the conductive interconnect structure (408), the conductive line (608) is laterally spaced from the conductive line (104), the conductive via (610) is laterally spaced from the conductive via (124) and the memory cell (106), and the conductive line (612) is laterally spaced from the conductive line (410). The conductive via (610) extends from the conductive line (612), through the dielectric layer (122), through the encapsulation layer (120), through the diffusion blocking dielectric layer (502), to the conductive line (608). In some embodiments, the top surface of the conductive via (124) and the top surface of the conductive via (610) are aligned approximately vertically. The bottom surface of the conductive via (610) is below the bottom surface of the conductive via (124).

[0038] FIG. 7 illustrates a cross-sectional view (700) of some embodiments of an integrated chip in which a plurality of memory cells are laterally spaced apart from a memory region (602).

[0039] For example, the memory cell (702) is located within the memory region (602) and is laterally spaced from the memory cell (106). The memory cell (106) is formed by a first portion of the barrier layer (108) (e.g., a first barrier structure), a first portion of the lower electrode layer (110) (e.g., a first lower electrode), a first portion of the data storage layer (112) (e.g., a first data storage structure), a first portion of the capping layer (202) (e.g., a first capping structure), a first portion of the upper electrode layer (114) (e.g., a first upper electrode), a first portion of the hard mask layer (116) (e.g., a first hard mask structure), and a first portion of the spacer layer (118) (e.g., a first spacer structure) (e.g., includes these). The memory cell (702) is formed by a second portion of the barrier layer (108) (e.g., a second barrier structure), a second portion of the lower electrode layer (110) (e.g., a second lower electrode), a second portion of the data storage layer (112) (e.g., a second data storage structure), a second portion of the capping layer (202) (e.g., a second capping structure), a second portion of the upper electrode layer (114) (e.g., a second upper electrode), a second portion of the hard mask layer (116) (e.g., a second hard mask structure), and a second portion of the spacer layer (118) (e.g., a second spacer structure) (e.g., including these). The encapsulation layer (120) is conformally placed over the memory cell (106), the memory cell (702), and the diffusion blocking dielectric layer (502) between the memory cells (106, 702).

[0040] A memory cell (702) is on a conductive line (704) which is on a transistor (708) and coupled to the transistor (708) by a conductive interconnect structure (710). A conductive via (706) is on a memory cell (702) and coupled to the memory cell (702). In some embodiments, a conductive line (410) is on both the conductive via (124) and the conductive via (706) and coupled to them (e.g., the conductive line (410) is a shared bit line). In some other embodiments, a separate conductive line (not shown) is on the conductive via (706) and coupled to the conductive via (706) and isolated from the conductive line (410).

[0041] FIG. 8 illustrates a cross-sectional view (800) of some embodiments of a memory cell (106) in which the lower electrode layer (110) is located between the spacer layer (118) and the barrier layer (108).

[0042] A spacer layer (118) is on the upper surface (110a, 110b) of the lower electrode layer (110). An encapsulation layer (120) covers the sidewalls of the lower electrode layer (110). The spacer layer (118) is formed on the upper surface (110a, 110b) of the lower electrode layer (110) before the lower electrode layer (110) is etched. Thus, the spacer layer (118) can protect the upper electrode layer (114) and the capping layer (202) from oxidation during the etching of the lower electrode layer (110) and subsequent processes. Thus, the performance and / or reliability of the memory cell (106) can be improved.

[0043] FIG. 9 illustrates a cross-sectional view (900) of some embodiments of a memory cell (106) in which two spacer layers protect the memory cell (106). FIG. 10 illustrates a cross-sectional view (1000) of some other embodiments of a memory cell (106) in which two spacer layers protect the memory cell (106).

[0044] The spacer layer (902) is located between the spacer layer (118) and the layers (202, 114, 116). In some embodiments (e.g., as shown in FIG. 9), the spacer layer (902) is on the upper surface of the data storage layer (112) and covers the sidewalls of the hard mask layer (116), the sidewalls of the upper electrode layer (114), and the sidewalls of the capping layer (202). In some embodiments (e.g., as shown in FIG. 10), the spacer layer (902) is on the upper surfaces of the lower electrode layer (110) and further covers the sidewalls of the data storage layer (112).

[0045] In some embodiments (e.g., as illustrated in FIG. 9), the spacer layer (902) can protect the upper electrode layer (114) and the capping layer (202) from oxidation during the etching of the data storage layer (112) and the lower electrode layer (110), and the spacer layer (118) can protect the data storage layer (112) and the lower electrode layer (110) during the deposition of the encapsulation layer (120). In some embodiments (e.g., as illustrated in FIG. 10), the spacer layer (902) can protect the upper electrode layer (114), the capping layer (202), and the data storage layer (112) from oxidation during the etching of the lower electrode layer (110), and the spacer layer (118) can protect the lower electrode layer (110) during the deposition of the encapsulation layer (120). Therefore, the performance and / or reliability of the memory cell (106) can be improved.

[0046] In some embodiments, the spacer layer (902) and the spacer layer (118) comprise the same dielectric material. In some other embodiments, the spacer layer (118) comprises a first dielectric material, and the spacer layer (902) comprises a second dielectric material different from the first dielectric material.

[0047] FIGS. 11 and FIGS. 12 respectively illustrate cross-sectional views (1100, 1200) of some embodiments of a memory cell (106) in which the lower electrode layer (110) is laterally resized at the sidewalls of the lower electrode layer (110).

[0048] The lower electrode layer (110) is "undercut" (e.g., laterally recessed) along the sidewalls of the lower electrode layer (110) so that the sidewalls of the lower electrode layer (110) are substantially offset from the sidewalls of the data storage layer (112), the sidewalls of the capping layer (202), the sidewalls of the upper electrode layer (114), and the sidewalls of the hard mask layer (116). The spacer layer (118) extends below the portion of the data storage layer (112) where the lower electrode layer (110) is laterally recessed. Lateral recessing of the lower electrode layer (110) may occur during the etching of the lower electrode layer (110). In some embodiments, the width of the undercut (1206) (e.g., lateral offset between the sidewalls of the lower electrode layer (110) and the sidewalls of the data storage layer (112)) is about 10 Angstroms to about 100 Angstroms, about 20 Angstroms to about 100 Angstroms, about 50 Angstroms to about 100 Angstroms, or within some other range.

[0049] In some embodiments, material removed from the lower electrode layer (110) during etching of the lower electrode layer (110) (at the lateral recess “undercut”) is deposited (e.g., “risputtered”) on the sidewalls of the data storage layer (112). In some embodiments, this material forms a layer (1104) (e.g., a metal oxide layer) on the sidewalls of the data storage layer (112). In some embodiments, this lower electrode material may diffuse into the data storage layer (112) through the sidewalls of the data storage layer (112), and accordingly, the edge portions (1106) of the data storage layer (112) further contain the lower electrode material (e.g., atoms of the lower electrode material) within the dielectric material of the data storage layer (112).

[0050] In some embodiments, in addition to the conductive material of the barrier layer (108), the edge portions (1108) of the barrier layer (108) further comprise atoms from one or more etching gases used in the etching of the lower electrode layer (110) (e.g., the edge portions (1108) of the barrier layer (108) further comprise one or more of oxygen, fluorine, chlorine, bromine, and iodine). In some embodiments, these edge portions (1108) of the barrier layer (108) have an increased thickness due to the added material (e.g., the thickness of the edge portions (1108) is greater than the thickness of the central portion of the barrier layer (108) extending between the edge portions (1108). In some embodiments, as illustrated in FIG. 12, the edge portions (1108) of the barrier layer (108) cover portions of the sidewalls of the lower electrode layer (110) due to the increased thickness of the barrier layer (108) at the edge portions (1108). The spacer layer (118) contacts the barrier layer (108) at the edge portions (1108) of the barrier layer (108).

[0051] In some embodiments, the edge portions (1110) (e.g., sidewall regions) of the upper electrode layer (114) and the edge portions (1112) of the capping layer (202) are oxidized (e.g., further containing oxygen). This may occur during the etching of the lower electrode layer (110). In some embodiments, oxidation of the sidewalls of the upper electrode layer (114) and the capping layer (202) along the sidewalls of the upper electrode layer (114) and the capping layer (202) may occur during the etching of the lower electrode layer (110). In some embodiments, the width (1208) of the oxidized portions (1110) and / or the oxidized portions (1112) is within the range of about 50 to about 150 Angstroms, about 75 to 150 Angstroms, about 100 to 150 Angstroms, or some other width.

[0052] In some embodiments, the thickness of the lower electrode layer (110) is less than 75 Angstroms, less than 50 Angstroms, or some other thickness.

[0053] In some embodiments, the barrier layer (1202) is located between the conductive interconnect (104) and the dielectric layer (102). In some embodiments, the barrier layer (1204) is located between the conductive interconnect and the layers (122, 120, 116, 114). In some embodiments, the barrier layer (1202) and / or the barrier layer (1204) comprises tantalum, tantalum nitride, or some other suitable material.

[0054] In some cases, the width of the undercut of the lower electrode layer (110) (e.g., lateral offset), the width of the oxidized portions (1110, 1112), the thickness of the layer (1104), and / or the width of the portion (1106) can be determined using transmission electron microscopy (TEM) or some other suitable method.

[0055] FIGS. 13 and FIGS. 14 respectively show cross-sectional views (1300, 1400) of some embodiments of a memory cell (106) in which there is substantially no "undercut" (e.g., lateral recesses in FIG. 11, 1102) in the lower electrode layer (110).

[0056] Accordingly, the sidewalls of the lower electrode layer (110) are substantially aligned with the sidewalls of the data storage layer (112), the sidewalls of the capping layer (202), the sidewalls of the upper electrode layer (114), and the sidewalls of the hard mask layer (116). For example, the sidewalls of the lower electrode layer (110) are laterally offset from the sidewalls of the data storage layer (112), the sidewalls of the capping layer (202), the sidewalls of the upper electrode layer (114), and the sidewalls of the hard mask layer (116) by about 1 Angstrom to about 50 Angstroms, less than 50 Angstroms, less than 30 Angstroms, less than 20 Angstroms, less than 10 Angstroms, less than 5 Angstroms, less than 5 Angstroms, or some other suitable value (e.g., width 1306).

[0057] In some embodiments, the undercut of the lower electrode layer (110) may be reduced by reducing the exposure of the lower electrode layer (110) to oxygen during the etching of the lower electrode layer (110) (e.g., by reducing the oxygen exposure time or reducing the oxygen concentration during exposure), as described in more detail with reference to FIG. 19. In some embodiments, reducing the exposure of the lower electrode layer (110) to oxygen during the etching of the lower electrode layer (110) may also reduce the oxidation of the capping layer (202) and the upper electrode layer (114) (e.g., by reducing the width of the oxidized portion (1110) and the oxidized portion (1112) of the capping layer (202). For example, the widths of the portions (1110) and / or portions (1112) may be reduced by more than 30%, more than 50%, more than 60%, or some other amount. In some embodiments, the width (1308) of the oxidized portion (1110) and / or the oxidized portion (1112) is less than about 100 Angstroms, less than about 75 Angstroms, less than about 50 Angstroms, less than about 25 Angstroms, less than about 5 Angstroms, or some other width.

[0058] In some embodiments, the undercut of the lower electrode layer (110) may be reduced by increasing the thickness of the lower electrode layer (110) so that the thickness of the lower electrode layer (110) is substantially large. The thickness of the lower electrode layer (110) is greater than the thickness of the data storage layer (112). In some embodiments, the thickness of the lower electrode layer (110) is greater than or approximately equal to the thickness of the barrier layer (108). In some embodiments, the thickness of the lower electrode layer (110) is greater than 75 Angstroms, greater than 90 Angstroms, greater than 100 Angstroms, within the range of about 75 Angstroms to about 200 Angstroms, within the range of about 100 Angstroms to about 200 Angstroms, or some other suitable thickness.

[0059] In some embodiments, reducing the undercut of the lower electrode layer (110) may prevent or reduce the deposition of lower electrode atoms on the data storage layer (112) (e.g., reducing or removing the layer (1104) and reducing or removing the portion (1106) of the data storage layer (112). In some embodiments, reducing the undercut of the lower electrode layer (110) may reduce the width of the edge portion (1108) of the barrier layer (108) containing the etchant.

[0060] FIGS. 15 to 25 illustrate cross-sectional views (1500 to 2500) of some embodiments of a method for forming an integrated chip including a memory cell (106), wherein the memory cell (106) includes a spacer layer (118) covering the sidewalls of an upper electrode layer (114), the sidewalls of a data storage layer (112), and the sidewalls of a lower electrode layer (110). Although FIGS. 15 to 25 are described in relation to the method, it should be understood that the structure disclosed in FIGS. 15 to 25 is not limited to this method and may be separated as a structure independent of the method.

[0061] As illustrated in the cross-sectional view (1500) of FIG. 15, transistors are formed on and / or along the semiconductor substrate (402). For example, transistors (404, 708) are formed in the memory region (602), and transistor (614) is formed in the logic region (604). Additionally, dielectric layers are formed on the semiconductor substrate (402). For example, a dielectric structure (406) and a dielectric layer (102) are formed on the semiconductor substrate (402). Additionally, conductive interconnects are formed on the transistors and coupled to the transistors. For example, an interconnect structure (408) and a conductive line (104) are formed on and coupled to the transistor (404) within the memory region (602). An interconnect structure (710) and a conductive line (704) are formed on and coupled to the transistor (708) within the memory region (602). The interconnect structure (606) and the conductive line (608) are formed on the transistor (614) within the logic area (604) and coupled thereto.

[0062] As illustrated in the cross-sectional view (1600) of FIG. 16, a diffusion blocking dielectric layer (502) is deposited over the dielectric layer (102) and the conductive lines (104, 704). In some embodiments, the diffusion blocking dielectric layer (502) comprises silicon oxide, silicon carbide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbonitride, boron nitride, aluminum nitride, or some other suitable material and is deposited by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or some other suitable process.

[0063] As illustrated in the cross-sectional view (1700) of FIG. 17, the diffusion blocking dielectric layer (502) is etched to form openings (1702) within the diffusion blocking dielectric layer (502) over the conductive lines (e.g., conductive lines (104, 704)) in the memory region (602) so as not to cover portions of the conductive lines in the memory region (602). In some embodiments, the sidewalls of the diffusion blocking dielectric layer (502) forming the openings (1702) are angled as a result of the etching.

[0064] In some embodiments, a masking layer (1704) is formed on the diffusion-blocking dielectric layer (502), and etching is performed along the masking layer (1704). In some embodiments, the masking layer (1704) comprises a photoresist, a hard mask material, or some other suitable material. The masking layer may be removed during and / or after etching. In some embodiments, the etching comprises a dry etching process, such as a plasma etching process, a reactive ion etching process, an ion beam etching process, or some other suitable process.

[0065] As illustrated in the cross-sectional view (1800) of FIG. 18, a barrier layer (108) is conformally deposited on the diffusion-blocking dielectric layer (502) and on the conductive lines (e.g., conductive lines (104, 704)) within the memory region (602). A lower electrode layer (110) is conformally deposited on the barrier layer (108). A data storage layer (112) is conformally deposited on the lower electrode layer (110). In some embodiments, a capping layer (202) is conformally deposited on the data storage layer (112). An upper electrode layer (114) is conformally deposited on the capping layer (202).

[0066] In some embodiments, the lower electrode layer (110) is deposited to have a substantially large thickness. Increasing the thickness of the lower electrode layer (110) can reduce lateral recessing (e.g., "undercutting") of the lower electrode layer (110) during etching of the lower electrode layer (110) and reduce the amount of lower electrode material (e.g., 1104, 1106 of FIG. 11) deposited on the data storage layer (112) during etching of the lower electrode layer (110). Thus, the performance and / or reliability of the memory cell can be improved. For example, the effective area of ​​the memory cell can be increased, the bit error rate (BER) of the memory cell can be reduced, the natural yield can be improved, the repair rate can be improved, etc. The thickness of the lower electrode layer (110) is greater than the thickness of the data storage layer (112). In some embodiments, the thickness of the lower electrode layer (110) is greater than or approximately equal to the thickness of the barrier layer (108). In some embodiments, the thickness of the lower electrode layer (110) is greater than 75 Angstroms, greater than 90 Angstroms, greater than 100 Angstroms, or some other thickness.

[0067] In some embodiments, the lower electrode layer (110) comprises ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, titanium; an alloy of any of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; a nitride of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0068] In some embodiments, the thickness of the barrier layer (108) is about 5 angstroms to about 140 angstroms, about 10 angstroms to about 100 angstroms, about 25 angstroms to about 75 angstroms, or within some other suitable range. In some embodiments, the barrier layer (108) comprises tantalum, titanium, ruthenium, aluminum, cobalt, molybdenum, rhodium, tantalum nitride, titanium nitride, ruthenium nitride, aluminum nitride, cobalt nitride, molybdenum nitride, rhodium nitride, tungsten nitride, manganese nitride, nickel nitride, tin nitride, magnesium nitride, or some other suitable material and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0069] In some embodiments, the thickness of the data storage layer (112) is within a range of about 10 Angstroms to about 100 Angstroms, about 10 Angstroms to about 90 Angstroms, about 10 Angstroms to about 80 Angstroms, or some other suitable range. In some embodiments, the data storage layer (112) comprises, for example, a high-k dielectric such as hafnium oxide, zirconium oxide, lanthanum oxide, gadolinium oxide, yttrium oxide, aluminum oxide, some other high-k dielectric material, or some other suitable material, and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0070] In some embodiments, the thickness of the capping layer (202) is about 25 Angstroms to about 200 Angstroms, about 50 Angstroms to about 175 Angstroms, about 50 Angstroms to about 150 Angstroms, or within some other suitable range. In some embodiments, the capping layer (202) comprises titanium, hafnium, platinum, aluminum, tantalum, zirconium, nickel, iridium, or some other suitable material and is deposited by a CVD process, a PVD process, an ALD process, or some other suitable process.

[0071] In some embodiments, the thickness of the upper electrode layer (114) is about 20 Angstroms to about 200 Angstroms, about 30 Angstroms to about 170 Angstroms, about 50 Angstroms to about 150 Angstroms, or within some other suitable range. In some embodiments, the upper electrode layer (114) is ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, titanium; an alloy of any of ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium; It includes ruthenium, rhodium, palladium, osmium, iridium, platinum, gold, silver, copper, aluminum, tungsten, tantalum, and titanium nitrides, or some other suitable materials, and is deposited by a CVD process, PVD process, ALD process, or some other suitable process.

[0072] As illustrated in the cross-sectional view (1900) of FIG. 19, a hard mask layer (116) is deposited on an upper electrode layer (114), and the hard mask layer (116) is etched to form individual hard mask structures from the hard mask layer (116). The hard mask structures are located directly above the conductive lines (104, 704). In some embodiments, the hard mask layer (116) comprises silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, some metal nitride, or some other suitable material, and is deposited by a CVD process, a PVD process, and an ALD process, or some other suitable process. In some embodiments, a masking layer (not shown) is formed on the hard mask layer, and the hard mask layer (116) is etched along the masking layer. In some embodiments, the etching includes a dry etching process or some other suitable process.

[0073] Next, to form layer stacks (1902, 1904) on conductive lines (104, 704), an upper electrode layer (114), a capping layer (202), a data storage layer (112), and a lower electrode layer (110) are etched according to a patterned hard mask layer (116) (e.g., according to individual hard mask structures remaining after etching the hard mask layer (116)). Etching stops at a barrier layer (108). In some embodiments, the etching includes a plasma etching process or some other suitable process. The gas used during etching includes oxygen gas, halogen (e.g., fluorine, chlorine, bromine, iodine) gas, a combination thereof, or some other suitable gas. In some embodiments, the etching includes an ashing process using oxygen plasma for cleaning after etching.

[0074] In some embodiments, the upper electrode layer (114) and / or the capping layer (202) may be oxidized during the etching of the lower electrode layer (110). In some embodiments, the lower electrode layer (110) may be recessed laterally (e.g., undercut) during the etching of the lower electrode layer (110), and atoms removed from the lower electrode layer (110) during the etching of the lower electrode layer (110) may be deposited on and / or diffused into the data storage layer (112).

[0075] Oxidation of the upper electrode layer (114), oxidation of the capping layer (202), undercut of the lower electrode layer (110), and / or deposition of the lower electrode material on the data storage layer (112) can be reduced by reducing the oxygen gas concentration, reducing the voltage used to generate plasma from the oxygen gas, and / or reducing the duration of exposure of the lower electrode layer (110) to the oxygen gas during the etching of the lower electrode layer (110). For example, in some embodiments, the time during which the lower electrode layer (110) is exposed to the electrode etching gas (e.g., oxygen-containing gas) during the etching of the lower electrode layer (110) is shorter than the time during which the barrier etching gas (e.g., oxygen gas, halogen gas, combined gas, or some other suitable etching gas) is exposed during the etching of the barrier layer (108). In some embodiments, the etching gas used during the etching of the lower electrode layer (110) comprises oxygen and halogen, and the oxygen portion is reduced such that more than half (e.g., 50%) of the etching gas is halogen and less than half of the etching gas is oxygen. In some embodiments, the oxygen portion of the etching gas is reduced such that more than 3 / 4 (e.g., 75%) of the etching gas is halogen and less than 1 / 4 (e.g., 25%) of the etching gas is oxygen. In some embodiments, the voltage applied to generate the etching plasma during the etching of the lower electrode layer (110) is zero or some other suitable low voltage.

[0076] Additionally, reducing the ashing time or skipping the ashing process entirely can reduce oxidation of the layers (114, 202), reduce undercutting of the lower electrode layer (110), and reduce or prevent deposition of lower electrode atoms on the data storage layer (112). Accordingly, in some embodiments, the ashing process is skipped (e.g., the ashing time is zero). In some embodiments where a short ashing process is performed, the voltage applied during ashing of the lower electrode layer (110) is zero or some other suitable low voltage.

[0077] By reducing oxidation of various layers of the memory cell and reducing undercutting of the lower electrode layer (110), the performance and / or reliability of the memory cell can be improved. For example, the effective area of ​​the memory cell (106) can be increased, the forming voltage (e.g., voltage for writing the memory cell) can be reduced, the bit error rate can be reduced, the set / reset shot count (e.g., number of voltage pulses applied to set / reset the memory cell) can be reduced, the set / reset shot count stability can be improved, the set / reset speed can be improved, the natural yield (e.g., amount of memory cells functioning properly without repair) can be improved, the repair rate (e.g., amount of memory cells functioning properly after repair) can be improved, and / or the structural integrity of the memory cell (106) can be improved.

[0078] In some embodiments, atoms of the etching gas may diffuse into exposed portions of the barrier layer (108) during etching. Thus, in some embodiments, the exposed portions of the barrier layer (108) may contain oxygen, fluorine, chlorine, bromine, iodine, combinations thereof, etc. In some embodiments, the exposed portions of the barrier layer (108) may have increased thickness as a result of the etching gas diffusion.

[0079] In some embodiments, etching of the upper electrode layer (114) and / or etching of the capping layer (202) uses low-oxygen or oxygen-free etching processes to further reduce oxidation of the upper electrode layer (114) and / or capping layer (202).

[0080] As illustrated in the cross-sectional view (2000) of FIG. 20, a spacer layer (118) is conformally deposited on the layer stacks (1902, 1904) and the barrier layer (108). The spacer layer (118) covers the sidewalls of the hard mask layer (116), the sidewalls of the upper electrode layer (114), the sidewalls of the capping layer (202), the sidewalls of the data storage layer (112), the sidewalls of the lower electrode layer (110), and the upper surface of the barrier layer (108).

[0081] In some embodiments, the spacer layer (118) comprises an oxygen-free dielectric material. For example, in some embodiments, the spacer layer (118) comprises silicon nitride, silicon carbide, silicon carbonitride, or some other suitable material. In some embodiments, the spacer layer (118) comprises a substantially low-oxygen dielectric material in which the atomic percentage of oxygen is less than 20%, less than 15%, less than 10%, or some other suitable value. For example, in some embodiments, the spacer layer (118) comprises silicon oxynitride, silicon oxycarbide, silicon oxycarbonitride, or some other suitable material having a low atomic percentage of oxygen. Forming the spacer layer (118) of an oxygen-free or low-oxygen dielectric material can help reduce oxidation of the layers on which the spacer layer (118) is deposited.

[0082] As illustrated in the cross-sectional view (2100) of FIG. 21, the spacer layer (118) is etched to remove the spacer layer (118) from the upper surfaces of the hard mask layer (116) and from portions of the barrier layer (108), thereby forming spacer structures on the sidewalls of each of the layer stacks (1902, 1904) from the spacer layer (118). For example, the first spacer structure covers the sidewalls of the layer stack (1902), and the second spacer structure covers the sidewalls of the layer stack (1904).

[0083] In some embodiments, the etching includes a dry etching process or some other suitable process. In some embodiments, the etching is performed without forming a masking layer on the spacer layer (118) (e.g., the etching is a blanket etching process). In some embodiments, the etching may remove small portions of the hard mask layer (116) and / or barrier layer (108).

[0084] As illustrated in the cross-sectional view (2200) of FIG. 22, the barrier layer (108) is etched along the layer stacks (1902, 1904) (e.g., along the hard mask layer (116)) and along the spacer layer (118) to separate the barrier layer (108) into individual barrier structures corresponding to individual memory cells. For example, the etching forms individual memory cells (106, 702) from the layer stacks (1902, 1904) and the barrier layer (108).

[0085] In some embodiments, the etching includes a dry etching process or some other suitable process. The etching stops at the diffusion blocking dielectric layer (502). For example, the etching has a high selectivity for the barrier layer (108) compared to the diffusion blocking dielectric layer (502) (for example, the barrier layer (108) has a substantially higher etching rate than the diffusion blocking dielectric layer (502)). In some embodiments, the etching may remove small portions of the diffusion blocking dielectric layer (502). Since the etching has little effect on the diffusion blocking dielectric layer (502), the thickness of the diffusion blocking dielectric layer (502) may not be substantially affected, and thus the diffusion blocking capability of the diffusion blocking dielectric layer (502) may not be substantially reduced.

[0086] The spacer layer (118) protects the lower electrode layer (110), data storage layer (112), capping layer (202), and upper electrode layer (114) during the etching of the barrier layer (108). Thus, oxidation of the lower electrode layer (110), capping layer (202), and / or upper electrode layer (114) during the etching of the barrier layer (108) can be reduced. As a result, the performance and / or reliability of the memory cells can be further improved.

[0087] As illustrated in the cross-sectional view (2300) of FIG. 23, an encapsulation layer (120) is conformally deposited over memory cells (106, 702) and a diffusion blocking dielectric layer (502) to encapsulate the memory cells (106, 702). In some embodiments, the encapsulation layer (120) comprises silicon dioxide or some other suitable material formed by a CVD process using tetraethyl orthosilicate (TEOS) and oxygen. In some embodiments, an oxygen-containing gas is used in a cleaning process prior to the deposition of the encapsulation layer (120).

[0088] The spacer layer (118) protects the lower electrode layer (110), data storage layer (112), capping layer (202), and upper electrode layer (114) during the cleaning process and deposition of the encapsulation layer (120). Thus, oxidation of the lower electrode layer (110), capping layer (202), and / or upper electrode layer (114) can be further reduced. As a result, the performance and / or reliability of the memory cells can be further improved.

[0089] As illustrated in the cross-sectional view (2400) of FIG. 24, a dielectric layer (122) is deposited on the encapsulation layer (120). In some embodiments, the dielectric layer comprises a low-k dielectric material, an ultra-low-k dielectric material (e.g., having a dielectric constant k of less than 2.5), or some other suitable material, and is deposited by a CVD process, a PVD process, and an ALD process, or some other suitable process.

[0090] As illustrated in the cross-sectional view (2500) of FIG. 25, conductive interconnects are formed on memory cells within a memory region (602) and coupled thereto. For example, a conductive via (124) and a conductive via (706) are formed on memory cells (106, 702) and coupled thereto. Additionally, in some embodiments, a conductive line (410) is formed on the conductive vias (124, 706) and coupled thereto. Additionally, conductive interconnects are formed within a logic region (604). For example, a conductive via (610) is formed on a conductive line (608) and coupled thereto, and a conductive line (612) is formed on a conductive via (610) and coupled thereto.

[0091] In some embodiments, conductive interconnects are formed by etching a dielectric layer (122), an encapsulation layer (120), a hard mask layer (116) (for conductive vias (124, 706)), and a diffusion blocking dielectric layer (502) (for conductive vias (610)) to form openings therein, and by depositing one or more conductive materials (e.g., copper, aluminum, tungsten, titanium, tantalum, etc.) into the openings by one or more deposition processes.

[0092] FIGS. 26 to 30 illustrate cross-sectional views (2600 to 3000) of some embodiments of a method for forming a memory cell (106) in which a lower electrode layer (110) is located between a spacer layer (118) and a barrier layer (108). Although FIGS. 26 to 30 are described in relation to the method, it should be understood that the structure disclosed in FIGS. 26 to 30 is not limited to this method and may be separated as a structure independent of the method.

[0093] As illustrated in the cross-sectional view (2600) of FIG. 26, following the deposition of layers (108, 110, 112, 202, 114) and the formation of individual hard mask structures from the hard mask layer (116), the upper electrode layer (114), the capping layer (202), and the data storage layer (112) are etched along the patterned hard mask layer (116) to form layer stacks (2602, 2604). The etching stops at the lower electrode layer (110).

[0094] As illustrated in the cross-sectional view (2700) of FIG. 27, the spacer layer (118) is conformally deposited on the layer stacks (2602, 2604) (e.g., on the hard mask layer (116), upper electrode layer (114), capping layer (202), and data storage layer (112)) and on the lower electrode layer (110). The spacer layer (118) covers the sidewalls of the hard mask layer (116), the sidewalls of the upper electrode layer (114), the sidewalls of the capping layer (202), the sidewalls of the data storage layer (112), and the upper surface of the lower electrode layer (110).

[0095] As illustrated in the cross-sectional view (2800) of FIG. 28, the spacer layer (118) is etched to remove the spacer layer (118) from the upper surface of the hard mask layer (116) and from a portion of the lower electrode layer (110), thereby forming a spacer structure on the layer stack (2602, 2604) (e.g., on the sidewalls of the data storage layer (112), the sidewalls of the capping layer (202), and the sidewalls of the upper electrode layer (114).

[0096] As illustrated in the cross-sectional view (2900) of FIG. 29, the lower electrode layer (110) and the barrier layer (108) are etched according to the hard mask layer (116) and the spacer layer (118) to separate the lower electrode layer (110) into individual lower electrodes and the barrier layer (108) into individual barrier structures. The etching forms memory cells (106, 702) from the layer stacks (2602, 2604) and the etched layers (110, 108).

[0097] The spacer layer (118) protects the sidewalls of the upper electrode layer (114), the capping layer (202), and the data storage layer (112) during the etching of the lower electrode layer (110). As a result, oxidation of the protected layers can be reduced, and thus the performance and / or reliability of the memory cells can be improved.

[0098] As shown in the cross-sectional view (3000) of FIG. 30, an encapsulation layer (120) is conformally deposited over memory cells (106, 702) and a diffusion blocking dielectric layer (502) to encapsulate the memory cells (106, 702).

[0099] The spacer layer (118) protects the sidewalls of the upper electrode layer (114), the capping layer (202), and the data storage layer (112) during the deposition of the encapsulation layer (120). As a result, oxidation of the protected layers can also be reduced, and thus the performance and / or reliability of the memory cells can be improved.

[0100] FIGS. 31 to 38 illustrate cross-sectional views (3100 to 3800) of some embodiments of a method in which two spacer layers protect the layers of a memory cell (106) to form a memory cell (106). Although FIGS. 31 to 38 are described in relation to the method, it should be understood that the structure disclosed in FIGS. 31 to 38 is not limited to this method and may be separated as a structure independent of the method.

[0101] As illustrated in the cross-sectional view (3100) of FIG. 31, following the deposition of layers (108, 110, 112, 202, 114) and the formation of individual hard mask structures from the hard mask layer (116), the upper electrode layer (114) and the capping layer (202) are etched along the patterned hard mask layer (116) to form layer stacks (3102, 3104). In some embodiments, the etching stops at the data storage layer (112). In some other embodiments, the data storage layer (112) is etched, and the etching stops at the lower electrode layer (110) (see, for example, FIG. 10).

[0102] As illustrated in the cross-sectional view (3200) of FIG. 32, a first spacer layer (902) is conformally deposited on the layer stacks (3102, 3104) (e.g., on the hard mask layer (116), the upper electrode layer (114), and the capping layer (202). The first spacer layer (902) covers the sidewalls of the hard mask layer (116), the sidewalls of the upper electrode layer (114), the sidewalls of the capping layer (202), and the upper surface of the data storage layer (112).

[0103] In some embodiments, the spacer layer (118) comprises a low-oxygen dielectric material or an oxygen-free dielectric material and is deposited by a CVD process, a PVD process, and an ALD process, or some other suitable process.

[0104] As illustrated in the cross-sectional view (3300) of FIG. 33, the first spacer layer (902) is etched to remove the first spacer layer (902) from the upper surface of the hard mask layer (116) and from a portion of the data storage layer (112), thereby forming first spacer structures on the sidewalls of the layer stacks (3102, 3104) (e.g., on the sidewalls of the upper electrode layer (114) and the sidewalls of the capping layer (202).

[0105] In some embodiments, the etching includes a dry etching process or some other suitable process. In some embodiments, the etching is performed without forming a masking layer on the spacer layer (118) (e.g., the etching is a blanket etching process). In some embodiments, the etching may remove small portions of the hard mask layer (116) and / or the data storage layer (112).

[0106] FIGS. 31 to 33 illustrate a first spacer layer (902) formed by depositing a first spacer layer on the upper electrode layer (114) and the capping layer (202) after etching the upper electrode layer (114) and the capping layer (202), but in some other embodiments, the first spacer layer (902) is formed gradually during the etching of the upper electrode layer (114) and the etching of the capping layer (202) by performing a cyclic deposition etching process.

[0107] As illustrated in the cross-sectional view (3400) of FIG. 34, the data storage layer (112), the lower electrode layer (110), and the barrier layer (108) are etched according to the hard mask layer (116) and the spacer layer (118) to separate the data storage layer (112) into individual data storage structures and the lower electrode layer (110) into individual lower electrodes. The data storage structures and lower electrodes also form layer stacks (3102, 3104).

[0108] The first spacer layer (902) protects the sidewalls of the upper electrode layer (114) and the sidewalls of the capping layer (202) during the etching of the data storage layer (112) and the lower electrode layer (110). As a result, oxidation of the protected layers can be reduced, and thus the performance and / or reliability of the memory cells can be improved.

[0109] As illustrated in the cross-sectional view (3500) of FIG. 35, a second spacer layer (118) is conformally deposited on a hard mask layer (116), a first spacer layer (902), a data storage layer (112), a lower electrode layer (110), and a barrier layer (108). The second spacer layer (118) covers the sidewalls of the first spacer layer (902), the sidewalls of the data storage layer (112), the sidewalls of the lower electrode layer (110), and the upper surface of the barrier layer (108).

[0110] In some embodiments, the second spacer layer (118) includes a low-oxygen dielectric material or an oxygen-free dielectric material to reduce oxidation of the layers on which the second spacer layer (118) is deposited.

[0111] As illustrated in the cross-sectional view (3600) of FIG. 36, the second spacer layer (118) is etched to remove the second spacer layer (118) from the upper surface of the hard mask layer (116) and from portions of the barrier layer (108), thereby forming second spacer structures on the sidewalls of the first spacer layer (902), the sidewalls of the data storage layer (112), and the sidewalls of the lower electrode layer (110).

[0112] As illustrated in the cross-sectional view (3700) of FIG. 37, the barrier layer (108) is etched along the hard mask layer (116) and the spacer layer (118) to separate the barrier layer (108) into individual barrier structures. The etching also forms memory cells (106, 702).

[0113] The second spacer layer (118) protects the sidewalls of the data storage layer (112) and the sidewalls of the lower electrode layer (110) during the etching of the barrier layer (108).

[0114] As shown in the cross-sectional view (3800) of FIG. 38, an encapsulation layer (120) is conformally deposited over memory cells (106, 702) and a diffusion blocking dielectric layer (502) to encapsulate the memory cells (106, 702).

[0115] The second spacer layer (118) protects the sidewalls of the data storage layer (112) and the sidewalls of the lower electrode layer (110) during the deposition of the envelope layer (120).

[0116] FIG. 39 illustrates a flowchart of some embodiments of a method (3900) for forming an integrated chip including a memory cell, wherein the memory cell includes a spacer layer covering the sidewalls of an upper electrode layer, the sidewalls of a data storage layer, and the sidewalls of a lower electrode layer. Although the method (3900) is illustrated and described below as a series of operations or events, it will be understood that the illustrated order of such operations or events should not be interpreted as limiting. For example, some operations may occur in a different order and / or simultaneously as operations or events different from those illustrated and / or described herein. Furthermore, not all illustrated operations may be required to implement one or more aspects or embodiments of the detailed description of this specification. Also, one or more of the operations illustrated in this specification may be performed in one or more separate operations and / or steps.

[0117] In block (3902), a barrier layer is deposited on a conductive interconnect, a lower electrode layer is deposited on the barrier layer, a data storage layer is deposited on the lower electrode layer, and an upper electrode layer is deposited on the data storage layer. The lower electrode layer is deposited with a substantially large thickness to reduce undercutting of the lower electrode layer during subsequent etching of the lower electrode layer. FIG. 18 illustrates a cross-sectional view (1800) of some embodiments corresponding to block (3902).

[0118] In block (3904), an upper electrode layer, a data storage layer, and a lower electrode layer are etched to form a memory stack. Oxygen gas exposure during the etching of the lower electrode layer (e.g., oxygen gas concentration, oxygen exposure time, voltage applied during oxygen gas exposure, etc.) is reduced to reduce oxidation of the upper electrode layer and reduce undercutting of the lower electrode layer. Additionally, the ashing process time after etching is reduced or eliminated, and the voltage applied during ashing is reduced or becomes zero to further reduce oxidation of the upper electrode layer and further reduce undercutting of the lower electrode layer. FIG. 19 illustrates a cross-sectional view (1900) of some embodiments corresponding to block (3904).

[0119] In block (3906), a spacer layer is formed to cover the sidewalls of the memory stack. For example, the spacer layer is deposited on the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer. Next, the spacer layer is etched to define the spacer layer. FIGS. 20 to 21 illustrate cross-sectional views (2000 to 2100) of some embodiments corresponding to block (3906).

[0120] In block (3908), the barrier layer is etched to form a memory cell from the memory stack, the spacer layer, and the barrier layer. FIG. 22 illustrates a cross-sectional view (2200) of some embodiments corresponding to block (3908).

[0121] In block (3910), an encapsulation layer is deposited over the memory cell. The spacer layer protects the sidewalls of the upper electrode layer and the lower electrode layer from oxidation during the deposition of the encapsulation layer. FIG. 23 illustrates a cross-sectional view (2300) of some embodiments corresponding to block (3910).

[0122] Accordingly, the present disclosure relates to an integrated chip and a method for forming an integrated chip, wherein the integrated chip comprises one or more spacer layers on a memory cell and the sidewalls of the memory cell to protect the memory cell during processing.

[0123] Accordingly, in some embodiments, the present disclosure relates to an integrated chip. The integrated chip comprises a barrier layer comprising a first conductive material on a semiconductor substrate. The integrated chip comprises a lower electrode layer comprising a second conductive material different from the first conductive material, on the barrier layer. The integrated chip comprises a dielectric layer on the lower electrode layer. The integrated chip comprises an upper electrode layer on the dielectric layer. The integrated chip comprises an encapsulation layer comprising a first dielectric material that encapsulates the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer. The integrated chip comprises a spacer layer comprising a second dielectric material different from the first dielectric material, on the upper surface of the barrier layer. The encapsulation layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer. In some embodiments, the spacer layer contacts the upper surface of the barrier layer, the sidewalls of the lower electrode layer, and the sidewalls of the dielectric layer. In some embodiments, the spacer layer is a first spacer layer. In some embodiments, the integrated chip further comprises a second spacer layer on the upper surface of the dielectric layer. In some embodiments, the second spacer layer covers the sidewalls of the upper electrode layer, and the first spacer layer covers the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the second spacer layer. In some embodiments, the thickness of the lower electrode layer is greater than the thickness of the dielectric layer and greater than the thickness of the barrier layer. In some embodiments, the spacer layer is substantially oxygen-free. In some embodiments, the second dielectric material contains oxygen, the first dielectric material is silicon dioxide, and the atomic percentage of oxygen in the second dielectric material is smaller than the atomic percentage of oxygen in the silicon dioxide of the first dielectric material. In some embodiments, the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer are substantially aligned.In some embodiments, the sidewalls of the lower electrode layer are laterally offset by 1 Angstrom to 50 Angstroms from the sidewalls of the dielectric layer and the sidewalls of the upper electrode layer. In some embodiments, the integrated chip further comprises a transistor on a semiconductor substrate, a first conductive interconnect coupled to a first source / drain of the transistor, a capping layer between the dielectric layer and the upper electrode layer, and a hard mask layer on the upper electrode layer. A barrier layer is on the upper surface of the first conductive interconnect. The capping layer comprises a third conductive material. The upper electrode layer comprises a fourth conductive material different from the third conductive material. An encapsulation layer encapsulates the capping layer and the hard mask layer. The encapsulation layer is spaced apart from the sidewalls of the capping layer and the sidewalls of the hard mask layer by a spacer layer.

[0124] In other embodiments, the present disclosure relates to a method for forming an integrated chip. The method comprises the step of depositing a barrier layer comprising a first conductive material on a semiconductor substrate. The method comprises the step of depositing a lower electrode layer comprising a second conductive material different from the first conductive material on the barrier layer. The method comprises the step of depositing a data storage layer on the lower electrode layer. The method comprises the step of depositing an upper electrode layer on the data storage layer. The method comprises the step of etching the upper electrode layer, the data storage layer, and the lower electrode layer. The method comprises the step of depositing a spacer layer comprising a first dielectric material on the upper surface of the barrier layer, along the sidewalls of the lower electrode layer, along the sidewalls of the data storage layer, along the sidewalls of the upper electrode layer, and on the upper electrode layer. The method comprises the step of etching the spacer layer to remove the spacer layer from the upper electrode layer. The method comprises the step of etching the barrier layer along the spacer layer. The method comprises the step of depositing an encapsulation layer comprising a second dielectric material different from a first dielectric material onto an upper electrode layer, along the sidewalls of a spacer layer, and along the sidewalls of a barrier layer. The spacer layer covers the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer during the deposition of the encapsulation layer. In some embodiments, the duration for which the lower electrode layer is exposed to a first etching gas during the etching of the lower electrode layer is shorter than the duration for which the barrier layer is exposed to a second etching gas during the etching of the barrier layer. In some embodiments, the etching gas used during the etching of the lower electrode layer comprises oxygen and a halogen, wherein the halogen constitutes more than half of the etching gas and the oxygen constitutes less than half of the etching gas. In some embodiments, the sidewalls of the upper electrode layer are oxidized after the etching of the lower electrode layer, and the width of the oxidized area of ​​the lower electrode layer is less than 100 Angstroms.In some embodiments, the sidewalls of the lower electrode layer are laterally offset from the sidewalls of the data storage layer and the sidewalls of the upper electrode layer after etching the lower electrode layer, and the offset is less than 50 Angstroms. In some embodiments, tetraethyl orthosilicate (TEOS) and oxygen are used for the deposition of the encapsulation layer. In some embodiments, the method further includes the step of forming a hard mask layer on the upper electrode layer. In some embodiments, the upper electrode layer, the data storage layer, and the lower electrode layer are etched along the hard mask layer. In some embodiments, a spacer layer is deposited along the sidewalls of the hard mask layer and on the upper surface of the hard mask layer. In some embodiments, etching the spacer layer removes the spacer layer from the hard mask layer. In some embodiments, a barrier layer is etched along the spacer layer and the hard mask layer. In some embodiments, an encapsulation layer is deposited on the upper surface of the hard mask layer. In some embodiments, the spacer layer is a first spacer layer. In some embodiments, the method further comprises the step of depositing a second spacer layer on the upper surface of the data storage layer, on the sidewalls of the upper electrode layer, and on the upper electrode layer. In some embodiments, the method further comprises the step of etching the second spacer layer to remove the spacer layer from the upper electrode layer. In some embodiments, the data storage layer and the lower electrode layer are etched after the etching of the second spacer layer. In some embodiments, the first spacer layer is deposited on the second spacer layer and on the sidewalls of the second spacer layer after the etching of the data storage layer and the lower electrode layer. In some embodiments, the central portion of the barrier layer comprises a first conductive material, and the edge portions of the barrier layer comprise the first conductive material and one or more of oxygen, fluorine, chlorine, bromine, and iodine after the etching of the lower electrode layer, and the spacer layer contacts the barrier layer at the edge portions of the barrier layer.In some embodiments, the edge portions of the barrier layer have a greater thickness than the central portion of the barrier layer. In some embodiments, a portion of the second conductive material is on the sidewalls of the data storage layer after etching of the lower electrode layer.

[0125] In other embodiments, the present disclosure relates to a method for forming an integrated chip, the method comprising the step of forming a barrier layer comprising a first conductive material on a semiconductor substrate. The method comprises the step of forming a lower electrode layer comprising a second conductive material different from the first conductive material on the barrier layer. The method comprises the step of forming a dielectric layer on the lower electrode layer. The method comprises the step of forming an upper electrode layer on the dielectric layer. The method comprises the step of forming a spacer layer comprising a first dielectric material on the upper surface of the barrier layer. The method comprises the step of encapsulating the upper electrode layer, the dielectric layer, the lower electrode layer, the barrier layer, and the spacer layer with an encapsulation layer comprising a second dielectric material different from the first dielectric material. The encapsulation layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer.

[0126] The foregoing outlines the features of various embodiments to enable those skilled in the art to better understand the aspects of the present disclosure. Those skilled in the art should recognize that the present disclosure can be readily used as a basis for designing or modifying other processes and structures to perform the same purpose and / or achieve the same advantages as the embodiments introduced herein. Furthermore, those skilled in the art should recognize that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and replacements without departing from the spirit and scope of the present disclosure.

[0127] Examples

[0128] Example 1. In integrated chips,

[0129] A barrier layer comprising a first conductive material on a semiconductor substrate;

[0130] A lower electrode layer comprising a second conductive material different from the first conductive material, on the barrier layer above;

[0131] Dielectric layer above the lower electrode layer;

[0132] Upper electrode layer above the dielectric layer;

[0133] An encapsulation layer comprising a first dielectric material encapsulating the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer; and

[0134] A spacer layer comprising a second dielectric material different from the first dielectric material on the upper surface of the barrier layer.

[0135] An integrated chip comprising, wherein the encapsulation layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer.

[0136] Example 2. An integrated chip in Example 1, wherein the spacer layer is in contact with the upper surface of the barrier layer, the sidewalls of the lower electrode layer, and the sidewalls of the dielectric layer.

[0137] Example 3. In Example 1, the spacer layer is a first spacer layer, and the integrated chip is,

[0138] A second spacer layer on the upper surface of the above dielectric layer

[0139] An integrated chip further comprising, wherein the second spacer layer covers the sidewalls of the upper electrode layer, and the first spacer layer covers the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the second spacer layer.

[0140] Example 4. An integrated chip in Example 1, wherein the thickness of the lower electrode layer is greater than the thickness of the dielectric layer and greater than the thickness of the barrier layer.

[0141] Example 5. An integrated chip in Example 1, wherein the spacer layer is substantially oxygen-free.

[0142] Example 6. An integrated chip in Example 1, wherein the second dielectric material contains oxygen, the first dielectric material is silicon dioxide, and the atomic percentage of oxygen in the second dielectric material is smaller than the atomic percentage of oxygen in the silicon dioxide of the first dielectric material.

[0143] Example 7. An integrated chip in Example 1, wherein the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer are substantially aligned.

[0144] Example 8. An integrated chip in Example 1, wherein the sidewalls of the lower electrode layer are laterally offset by 1 Angstrom to 50 Angstroms from the sidewalls of the dielectric layer and the sidewalls of the upper electrode layer.

[0145] Example 9. In Example 1,

[0146] A transistor on the semiconductor substrate above;

[0147] A first conductive interconnect coupled to the first source / drain of the transistor - the barrier layer is on the upper surface of the first conductive interconnect - ;

[0148] A capping layer between the dielectric layer and the upper electrode layer - the capping layer comprises a third conductive material, and the upper electrode layer comprises a fourth conductive material different from the third conductive material - ; and

[0149] Hard mask layer on the upper electrode layer above

[0150] Includes more,

[0151] An integrated chip, wherein the above-mentioned encapsulation layer also encapsulates the capping layer and the hard mask layer, and the encapsulation layer is spaced apart from the sidewalls of the capping layer and the sidewalls of the hard mask layer by the spacer layer.

[0152] Example 10. In a method for forming an integrated chip,

[0153] A step of depositing a barrier layer comprising a first conductive material on a semiconductor substrate;

[0154] A step of depositing a lower electrode layer comprising a second conductive material different from the first conductive material on the barrier layer;

[0155] A step of depositing a data storage layer on the lower electrode layer;

[0156] A step of depositing an upper electrode layer on the data storage layer;

[0157] A step of etching the upper electrode layer, the data storage layer, and the lower electrode layer;

[0158] A step of depositing a spacer layer comprising a first dielectric material on the upper surface of the barrier layer, along the sidewalls of the lower electrode layer, along the sidewalls of the data storage layer, along the sidewalls of the upper electrode layer, and on the upper electrode layer;

[0159] A step of etching the spacer layer to remove the spacer layer from the upper electrode layer;

[0160] A step of etching the barrier layer according to the spacer layer; and

[0161] A step of depositing an encapsulation layer comprising a second dielectric material different from the first dielectric material on the upper electrode layer, along the sidewalls of the spacer layer and along the sidewalls of the barrier layer.

[0162] A method for forming an integrated chip comprising, wherein the spacer layer covers the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer during the deposition of the encapsulation layer.

[0163] Example 11. A method for forming an integrated chip in Example 10, wherein the duration during which the lower electrode layer is exposed to a first etching gas during the etching of the lower electrode layer is shorter than the duration during which the barrier layer is exposed to a second etching gas during the etching of the barrier layer.

[0164] Example 12. A method for forming an integrated chip in Example 10, wherein the etching gas used during the etching of the lower electrode layer comprises oxygen and a halogen, wherein the halogen constitutes more than half of the etching gas and the oxygen constitutes less than half of the etching gas.

[0165] Example 13. A method for forming an integrated chip, wherein, in 10, the sidewalls of the upper electrode layer are oxidized after etching the lower electrode layer, and the width of the oxidized region of the lower electrode layer is less than 100 Angstroms.

[0166] Example 14. A method for forming an integrated chip in Example 10, wherein the sidewalls of the lower electrode layer are laterally offset from the sidewalls of the data storage layer and the sidewalls of the upper electrode layer after etching of the lower electrode layer, and the offset is less than 50 Angstroms.

[0167] Example 15. In Example 10,

[0168] Step of forming a hard mask layer on the upper electrode layer

[0169] A method for forming an integrated chip, further comprising: an upper electrode layer, a data storage layer, and a lower electrode layer are etched along the hard mask layer; a spacer layer is deposited along the sidewalls of the hard mask layer and on the upper surface of the hard mask layer; etching the spacer layer removes the spacer layer from the hard mask layer; a barrier layer is etched along the spacer layer and the hard mask layer; and an encapsulation layer is deposited on the upper surface of the hard mask layer.

[0170] Example 16. In Example 10, the spacer layer is a first spacer layer, and the method is,

[0171] A step of depositing a second spacer layer on the upper surface of the data storage layer, on the sidewalls of the upper electrode layer, and on the upper electrode layer; and

[0172] Step of etching the second spacer layer to remove the spacer layer from the upper electrode layer.

[0173] Includes,

[0174] A method for forming an integrated chip, wherein the data storage layer and the lower electrode layer are etched after the etching of the second spacer layer, and the first spacer layer is deposited on the second spacer layer and on the sidewall of the second spacer layer after the etching of the data storage layer and the lower electrode layer.

[0175] Example 17. A method for forming an integrated chip in Example 10, wherein the central portion of the barrier layer comprises the first conductive material, the edge portions of the barrier layer comprise the first conductive material and one or more of oxygen, fluorine, chlorine, bromine, and iodine after etching of the lower electrode layer, and the spacer layer contacts the barrier layer at the edge portions of the barrier layer.

[0176] Example 18. A method for forming an integrated chip in Example 17, wherein the edge portions of the barrier layer have a greater thickness than the central portion of the barrier layer.

[0177] Example 19. A method for forming an integrated chip in Example 10, wherein a portion of the second conductive material is on the sidewalls of the data storage layer after etching the lower electrode layer.

[0178] Example 20. In a method for forming an integrated chip,

[0179] A step of forming a barrier layer comprising a first conductive material on a semiconductor substrate;

[0180] A step of forming a lower electrode layer comprising a second conductive material different from the first conductive material on the barrier layer;

[0181] A step of forming a dielectric layer on the lower electrode layer;

[0182] A step of forming an upper electrode layer on the dielectric layer;

[0183] A step of forming a spacer layer comprising a first dielectric material on the upper surface of the barrier layer; and

[0184] A step of encapsulating the upper electrode layer, the dielectric layer, the lower electrode layer, the barrier layer, and the spacer layer with an encapsulation layer comprising a second dielectric material different from the first dielectric material.

[0185] A method for forming an integrated chip comprising, wherein the encapsulation layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer.

Claims

Claim 1 An integrated chip comprising: a barrier layer comprising a first conductive material on a semiconductor substrate; a lower electrode layer comprising a second conductive material different from the first conductive material on the barrier layer; a dielectric layer on the lower electrode layer; an upper electrode layer on the dielectric layer; an encapsulating layer comprising a first dielectric material encapsulating the upper electrode layer, the dielectric layer, the lower electrode layer, and the barrier layer; and a spacer layer comprising a second dielectric material different from the first dielectric material on the upper surface of the barrier layer, wherein the encapsulating layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer. Claim 2 An integrated chip according to claim 1, wherein the spacer layer is in contact with the upper surface of the barrier layer, the sidewalls of the lower electrode layer, and the sidewalls of the dielectric layer. Claim 3 An integrated chip according to claim 1, wherein the spacer layer is a first spacer layer, and the integrated chip further comprises a second spacer layer on the upper surface of the dielectric layer, wherein the second spacer layer covers the sidewalls of the upper electrode layer, and the first spacer layer covers the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the second spacer layer. Claim 4 An integrated chip according to claim 1, wherein the thickness of the lower electrode layer is greater than the thickness of the dielectric layer and greater than the thickness of the barrier layer. Claim 5 An integrated chip according to claim 1, wherein the spacer layer is oxygen-free. Claim 6 An integrated chip according to claim 1, wherein the second dielectric material contains oxygen, the first dielectric material is silicon dioxide, and the atomic percentage of oxygen in the second dielectric material is smaller than the atomic percentage of oxygen in the silicon dioxide of the first dielectric material. Claim 7 An integrated chip according to claim 1, wherein the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer are aligned. Claim 8 An integrated chip according to claim 1, comprising: a transistor on the semiconductor substrate; a first conductive interconnect coupled to a first source / drain of the transistor, wherein the barrier layer is on the upper surface of the first conductive interconnect; a capping layer between the dielectric layer and the upper electrode layer, wherein the capping layer comprises a third conductive material and the upper electrode layer comprises a fourth conductive material different from the third conductive material; and further comprising a hard mask layer on the upper electrode layer, wherein the encapsulation layer also encapsulates the capping layer and the hard mask layer, and the encapsulation layer is spaced apart from the sidewalls of the capping layer and the sidewalls of the hard mask layer by the spacer layer. Claim 9 A method for forming an integrated chip comprises: a step of depositing a barrier layer comprising a first conductive material on a semiconductor substrate; a step of depositing a lower electrode layer comprising a second conductive material different from the first conductive material on the barrier layer; a step of depositing a data storage layer on the lower electrode layer; a step of depositing an upper electrode layer on the data storage layer; a step of etching the upper electrode layer, the data storage layer, and the lower electrode layer; a step of depositing a spacer layer comprising a first dielectric material on the upper surface of the barrier layer, along the sidewalls of the lower electrode layer, along the sidewalls of the data storage layer, along the sidewalls of the upper electrode layer, and on the upper electrode layer; a step of etching the spacer layer to remove the spacer layer from the upper electrode layer; and a step of etching the barrier layer along the spacer layer. A method for forming an integrated chip, comprising the step of depositing an encapsulation layer including a second dielectric material different from the first dielectric material on the upper electrode layer, along the sidewalls of the spacer layer and along the sidewalls of the barrier layer, wherein during the deposition of the encapsulation layer, the spacer layer covers the sidewalls of the upper electrode layer, the sidewalls of the data storage layer, and the sidewalls of the lower electrode layer. Claim 10 A method for forming an integrated chip, comprising: forming a barrier layer comprising a first conductive material on a semiconductor substrate; forming a lower electrode layer comprising a second conductive material different from the first conductive material on the barrier layer; forming a dielectric layer on the lower electrode layer; forming an upper electrode layer on the dielectric layer; forming a spacer layer comprising the first dielectric material on the upper surface of the barrier layer; and encapsulating the upper electrode layer, the dielectric layer, the lower electrode layer, the barrier layer, and the spacer layer with an encapsulation layer comprising a second dielectric material different from the first dielectric material, wherein the encapsulation layer is spaced apart from the sidewalls of the lower electrode layer, the sidewalls of the dielectric layer, and the sidewalls of the upper electrode layer by the spacer layer.

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