Memory devices with controller configured to select one of various reference schemes and methods for operating the same

Abstract

A semiconductor device comprises: a first memory array including a plurality of first nominal memory cells, a plurality of first reference memory cells, and a plurality of second reference memory cells; a second memory array including a plurality of second nominal memory cells, a plurality of third reference memory cells, and a plurality of fourth reference memory cells; an input / output (I / O) circuit physically interposed between the first memory array and the second memory array along a first lateral direction; and a controller operably coupled to the I / O circuit, the first memory array, and the second memory array. Based on a plurality of control signals, the controller is configured to select a reference signal from one of the third reference memory cells, the fourth reference memory cells, or the second nominal memory cells, thereby enabling the I / O circuit to detect a data signal from one of the first nominal memory cells.

Description

Technology Field

[0001] This application claims the benefit and priority of U.S. Provisional Application No. 63 / 788,391 filed on April 14, 2025, and for all purposes, the full text of this Provisional Application is incorporated herein by reference. Background Technology

[0002] The semiconductor industry has experienced rapid growth due to the continuous increase in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density has been driven by repeated reductions in the minimum feature size, which allows more components to be integrated within a given area. means of solving the problem

[0003] In one aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device comprises: a first memory array comprising a plurality of first nominal memory cells, a plurality of first reference memory cells, and a plurality of second reference memory cells; a second memory array comprising a plurality of second nominal memory cells, a plurality of third reference memory cells, and a plurality of fourth reference memory cells; an input / output (I / O) circuit physically interposed between the first memory array and the second memory array along a first transverse direction; and a controller operably coupled to the I / O circuit, the first memory array, and the second memory array. Based on a plurality of control signals, the controller is configured to select a reference signal from one of the third reference memory cells, the fourth reference memory cells, and the second nominal memory cells, thereby enabling the I / O circuit to detect a data signal from one of the first nominal memory cells.

[0004] In another aspect of the present disclosure, a semiconductor device is disclosed. The semiconductor device comprises: a first memory array comprising a plurality of first memory cells each configured to store a first data bit based on a respective first variable resistor, a plurality of second memory cells each configured to store a first reference resistor, and a plurality of third memory cells each configured to store a second reference resistor; a second memory array comprising a plurality of fourth memory cells each configured to store a second data bit based on a respective second variable resistor, a plurality of fifth memory cells each configured to store a third reference resistor, and a plurality of sixth memory cells each configured to store a fourth reference resistor; and a controller, wherein the controller receives a plurality of control signals; and is configured to select, based on a logical combination of the plurality of control signals, one of the third reference resistor, the fourth reference resistor, and the second data bit to compare with the first data bit, or (ii) one of the first reference resistor, the second reference resistor, and the first data bit to compare with the second data bit.

[0005] In another aspect of the present disclosure, a method is disclosed. The method comprises the step of receiving at least a first control signal and a second control signal, wherein the logic combination of the first control signal and the second control signal is configured to select one of at least a first reference scheme, a second reference scheme, and a third reference scheme. The method comprises the step of comparing a first reference signal provided by a first reference cell among a plurality of first reference cells of a first memory array and a second memory cell among a plurality of second memory cells of a second memory array with a first data signal provided by a second memory cell among the second memory cells, by activating a first reference cell among a plurality of first reference cells among the logic combinations corresponding to the first reference scheme. The method includes the step of comparing a second reference signal provided by one of the second reference cells with a second data signal provided by another second memory cell among the second memory cells by activating one of the second reference cells among the plurality of second reference cells of the first memory array and another second memory cell among the plurality of second memory cells of the second memory array, based on a second logical combination among the logical combinations corresponding to a second reference scheme. The method includes the step of comparing a third data signal provided by one of the first memory cells with a fourth data signal provided by another second memory cell among the second memory cells by activating one of the first memory cells among the plurality of first memory cells of the first memory array and another second memory cell among the plurality of second memory cells of the second memory array, based on a third logical combination among the logical combinations corresponding to a third reference scheme. Brief explanation of the drawing

[0006] The embodiments of the present disclosure are best understood from the following detailed description when read together with the accompanying drawings. In accordance with standard practice in the industry, it should be noted that various features are not drawn to actual scale. In practice, the dimensions of various features may be increased or decreased at will for clarity of description. FIG. 1 illustrates an exemplary block diagram of a memory device according to some embodiments. FIG. 2 illustrates an exemplary circuit diagram of one memory cell of the memory device of FIG. 1 according to some embodiments. FIG. 3 illustrates an exemplary schematic diagram of the memory device of FIG. 1 according to some embodiments. FIG. 4 illustrates another exemplary schematic diagram of the memory device of FIG. 1 according to some embodiments. FIG. 5 illustrates an exemplary circuit diagram of a memory controller of the memory device of FIG. 1 according to some embodiments. FIGS. 6 through 8 illustrate examples when a segmented reference scheme is applied according to some embodiments. FIGS. 9 to 11 illustrate examples when a global reference scheme is applied according to some embodiments. FIGS. 12 to 15 illustrate examples where a quasi-reference scheme is applied according to some embodiments. FIGS. 16 to 18 illustrate examples when a local reference scheme is applied according to some embodiments. FIG. 19 illustrates an exemplary flowchart of a method for operating a memory device according to some embodiments. Specific details for implementing the invention

[0007] The disclosure below provides many different embodiments or examples for implementing various features of the invention provided. To simplify the disclosure, specific examples of components and devices are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following detailed description, the formation of the first feature on or above the second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features do not come into direct contact. Additionally, the disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for the purpose of simplification and clarification, and such repetition itself does not affect the relationship between the various embodiments and / or configurations disclosed.

[0008] Additionally, spatial relative terms such as "below," "bottom," "lower," "above," "above," "top," and "bottom" may be used herein for ease of explanation to describe the relationship between one element or feature exemplified in the drawings and other element(s) or feature(s). Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the drawings. The device may be oriented differently (rotated 90° or rotated to a different orientation), and accordingly, the spatial relative terms used herein may be interpreted in the same way.

[0009] Some (e.g., non-volatile) memory devices, such as magnetic random-access memory (MRAM) devices, phase-change random-access memory (PCRAM) devices, and resistive random-access memory (RRAM) devices, store data bits by programming the respective resistors of their memory cells. Generally, in a read operation, a data bit (or signal) is read from one of these memory cells and compared with a reference value, such as a reference voltage or reference current. The result of the comparison is provided as an output data bit (or signal). In modern memory devices with programmable resistors, different reference schemes or structures may be used to provide the aforementioned reference values ​​that are compared with the data bits received from the memory cells to provide the output data bits.

[0010] For example, a memory device may include one or more (global) reference memory cell sets. According to scaling trends, a memory device may include multiple memory arrays, each of which includes at least one global reference memory cell set. Each global reference memory cell set may be shared by 128 or more different word lines, where each word line is connected to many different memory cells via bit lines. Each reference memory cell set is configured to provide reference values ​​for all memory cells connected to the 128 or more different word lines. However, a single reference memory cell set cannot closely track or follow too many different memory cells, at least in part, due to column loading effects such as bit line and source line resistance variations. Therefore, in memory devices having global reference memory cell sets, the primary concern is yield loss and / or a higher read error rate.

[0011] As another example, a memory device may include one or more sets of (local) reference memory cells. Each set of local reference memory cells is utilized per word line. The area occupied by the sets of reference memory cells is approximately 8% of the memory device area, as in a memory device having, for example, a common source line (CSL) of 4 columns and a multiplexer for 32 columns. Additionally, due to the large number of local reference memory cells, a large amount of reference trim code is included. The reference trim code storage occupies approximately 3% of the memory device area. Therefore, in memory devices having sets of local reference memory cells, the primary concern is area overhead.

[0012] The present disclosure provides various embodiments of a memory device having a plurality of reference schemes or structures that can be selectively or otherwise adaptively applied based on multiple process variations (e.g., bit line / source line variation, read disturbance, read margin, etc.). As such, a memory device as disclosed herein can balance the trade-off between yield loss, error rate, and device area.

[0013] For example, while reading a selected memory cell, the memory device may selectively apply one of a plurality of reference schemes to one of the selected memory cells. The memory device may include a first memory array, a second memory array, and a memory controller. Each of the memory arrays may include a plurality of (e.g., nominal) memory cells, each configured to store a data bit (or data signal), and a plurality of (e.g., reference) memory cells, each configured to store a reference value (or reference signal). According to some embodiments, some of the reference memory cells may be configured as one of a plurality of global reference memory cell sets (corresponding to a global reference scheme), some of the reference memory cells may be configured as one of a plurality of segmented reference memory cell sets (corresponding to a segmented reference scheme), some of the reference memory cells may be configured as one of a plurality of local reference memory cell sets (corresponding to a local reference scheme), and some of the nominal memory cells may be configured or mobilized as one of a plurality of quasi-reference memory cell sets (corresponding to a quasi-reference scheme).

[0014] The memory controller may be operably coupled to a first memory array through a number of first (e.g., word line) drivers and to a second memory array through a number of second (e.g., word line) drivers. Each of the first or second word line drivers is operably coupled to a number of memory cells through a respective word line. When a word line driver is selected (e.g., activated), the corresponding word line is assigned. In this way, the memory controller may then access the corresponding memory cells to retrieve a stored data bit or reference value. Additionally, in some embodiments, the memory controller may operably select one of reference schemes based on a plurality of control or enable signals (e.g., REFG_EN signal, QSI_EN signal, LOC_EN signal). Based on a logical combination of these control signals (associated with each of the reference schemes), the memory controller can activate one of the word line drivers and then activate the corresponding reference memory cell or the corresponding nominal memory cell to provide reference values ​​of these cells to be compared with the read data bit.

[0015] FIG. 1 illustrates an exemplary block diagram of a memory circuit (or device) (100) according to various embodiments of the present disclosure. As illustrated, the memory circuit (100) includes a plurality of memory arrays (110, 115, etc.), a plurality of word line (WL) driver circuits (120, 125, etc.), an input / output (I / O) circuit (130), and a memory controller (140). The block diagram of FIG. 1 is simplified for illustrative purposes, and accordingly, it should be understood that the memory circuit (100) may include any various other components, such as a sinker circuit, a source line (SL) driver, a pre-charge circuit, etc., while remaining within the scope of the present disclosure, according to some embodiments of the present disclosure.

[0016] In some embodiments, memory arrays (110, 115) may operably share an I / O circuit (130) and a memory controller (140). For example, the memory controller (140) may operate the memory array (110) through a WL driver circuit (120) and operate the memory array (115) through a WL driver circuit (125). In some embodiments, the I / O circuit (130) may be physically positioned between the memory arrays (110, 115) along a first lateral direction (e.g., Y-axis), and the WL driver circuit (120) and the WL driver circuit (125) are each physically positioned next to the memory array (110) and the memory array (115) along a second lateral direction (e.g., X-axis). Additionally, the memory controller (140) may be physically positioned along the second lateral direction next to the I / O circuit (130) and along the first lateral direction between the WL driver circuit (120) and the WL driver circuit (125). Depending on this arrangement, the memory arrays (110, 115) may sometimes be referred to as the upper memory array (or upper memory bank) and the lower memory array (or lower memory bank), respectively. However, it should be understood that the components of the memory circuit (100) may be arranged in any other way while remaining within the scope of the present disclosure.

[0017] Each of the memory arrays (110, 115) may include a plurality of storage circuits or memory cells. For example, in FIG. 1, the upper memory array (110) includes a plurality of storage circuits or memory cells (140), and the lower memory array (115) includes a plurality of storage circuits or memory cells (145), and these may be arranged in two-dimensional or three-dimensional arrays. In some embodiments, each of the memory cells (140, 145) includes an RRAM cell configured to store a data bit corresponding to either a high resistance state (high resistance) or a low resistance state (low resistance). However, each of the memory cells (140, 145) may include memory cells of any various other configurations while remaining within the scope of the present disclosure. For example, each of the memory cells (140, 145) may include an MRAM cell, a spintronic memory cell, or an OTP memory cell.

[0018] As illustrated in FIG. 2 below, each of the memory cells (140, 145) can be implemented as a 1 transistor 1 resistor (1T1R) structure, for example, as a resistor having a variable resistor connected in series with the transistor. Each of the memory cells (140, 145) can be coupled to a corresponding word line (WL), a corresponding bit line (BL), and a corresponding source line (SL). For example, each of the memory cells (140, 145) is placed at the intersection of a combination of a corresponding bit line (BL) and a corresponding source line (SL) and a corresponding word line (WL).

[0019] As illustrated in the exemplary example of FIG. 1, the upper memory array (110) comprises a plurality of word lines (WL) each arranged across multiple array rows. U )(for example, WL U [0], WL U [1]… WL U[Y-1]) is included, and the lower memory array (115) comprises a plurality of word lines (WL) each arranged across multiple array rows. L )(for example, WL L [0], WL L [1]… WL L Includes [Y-1]). The number "Y" can be any integer. It should be understood that the number of word lines (WL) (or rows) of the memory arrays (110, 115) may differ. Word lines (WL) (WL U [0] to WL U [Y-1] and WL L [0] to WL L [Y-1]) Each can be extended in a second transverse direction. The upper memory array (110) comprises a plurality of bit lines (BL) each arranged across multiple array columns. U )(For example, BL U [0], BL U [1]… BL U [X-1]) and multiple source lines (SL U )(For example, SL U [0], SL U [1]… SL U [X-1]) further includes, and the lower memory array (115) comprises a plurality of bit lines (BL) each arranged across multiple array columns. L )(For example, BL L [0], BL L [1]… BL L [X-1]) and multiple source lines (SL L )(For example, SL L [0], SL L [1]… SL L Includes [K-1]). The number "X" can be any integer. It should be understood that the number of bit lines (BL) / source lines (SL) of the memory arrays (110, 115) may differ. Bit line (BL)(BL U [0] to BL U [X-1] and BL L[0] to BL L [X-1]) and source line (SL)(SL U [0] to SL U [X-1] and SL L [0] to SL L [X-1]) Each can be extended in a first transverse direction perpendicular to the second transverse direction.

[0020] The memory controller (140) is a hardware component capable of controlling operations (e.g., read, write) of the upper memory array (110) through the WL driver circuit (120) and / or I / O circuit (130), and controlling operations (e.g., read, write) of the lower memory array (115) through the WL driver circuit (125) and / or I / O circuit (130). The WL driver circuits (120, 125) and the I / O circuit (130) may each be implemented as one or more logic circuits, one or more analog circuits, or a combination thereof. In some embodiments, the WL driver circuits (120, 125) may each include a circuit configured to provide voltage or current (e.g., a WL assertion signal having one or more pulses) through an asserted word line among the word lines (WL) of the memory array. The I / O circuit (130) may include a circuit configured to provide or sense voltage or current through each bit line (BL) of the memory arrays (110, 115). Additionally, the I / O circuit (130) may include a circuit configured as a current source coupled to the memory arrays (110, 115) through their respective source lines (SL). In some other embodiments, the memory circuit (100) includes more, fewer, or different components than those shown in FIG. 1. For example, the memory circuit (100) may further include a timing controller capable of providing control signals or clock signals to synchronize the operations of the WL driver circuits (120–125) and the I / O circuit (130).

[0021] As will be discussed below, some of the memory cells (140) of the upper memory array (110) are nominal memory cells (sometimes nominal memory cells (140)) that store each data bit. N It may be configured as (referred to as ), and some of the memory cells (140) of the upper memory array (110) may be reference memory cells (sometimes reference memory cells (140)) that store respective reference values. R It may be configured as (referred to as ). Likewise, some of the memory cells (145) of the lower memory array (115) may be configured as nominal memory cells (sometimes nominal memory cells (145)) that store each data bit. N It may be configured as (referred to as ), and some of the memory cells (145) of the lower memory array (115) may be reference memory cells (sometimes reference memory cells (145)) that store respective reference values. R It may be configured as reference memory cells (referred to as ). According to various embodiments of the present disclosure, reference memory cells (140 R , 145 R ) may be included in any of the global reference memory cell set, segmented reference memory cell set, or local reference memory cell set mentioned above, and nominal memory cells (140 N , 145 N ) can be included within the quasi-reference memory cell set mentioned above.

[0022] FIG. 2 illustrates an exemplary circuit diagram of a memory cell (140 or 145) (Fig. 1) according to some embodiments of the present disclosure. In FIG. 2, in some embodiments, the memory cell (140 / 145) includes a selector transistor and a variable resistor (sometimes referred to as a “1T1R” configuration) connected in series. However, it should be noted that the circuit diagram of FIG. 2 is provided for illustrative purposes only and is not intended to limit the scope of the present disclosure.

[0023] As illustrated, the memory cell (140 / 145) includes a variable resistor (210) and a selector transistor (220) connected in series. The variable resistor (210) may provide a switchable or programmable resistance state between a low resistance state (LRS) and a high resistance state (HRS). The resistance state may represent a data value (e.g., logic "1" or logic "0") stored by the memory cell (140 / 145). Programming the memory cell (140 / 145) to HRS (e.g., logic 0) is sometimes referred to as performing a RESET operation, and programming the memory cell (140 / 145) to LRS (e.g., logic 1) is sometimes referred to as performing a SET operation.

[0024] Additionally, the first terminal of the variable resistor (210) is connected to the bit line (BL), the second terminal of the variable resistor (210) is connected to the first source / drain terminal of the selector transistor (220), the gate terminal of the selector transistor (220) is connected to the word line (WL), and the second source / drain terminal of the selector transistor (220) is connected to the source line (SL), which is typically connected to ground. With this configuration, the selector transistor (220) can be activated (e.g., turned on) by assigning the word line (WL), such as by applying a signal having a logic 1 to the gate terminal of the selector transistor (220). Upon activation, another signal may be applied or present on the bit line (BL) to read or write the variable resistor (210).

[0025] For example, during a read operation of a memory cell (140 / 145), current may flow from the source (SL) to the bit line (BL) through an activated selector transistor (220) and a variable resistor (210). When programmed in the LRS, the current may be relatively high; when programmed in the HRS, the current may be relatively low. The current may be supplied to a sense amplifier (of the I / O circuit (130)), and the sense amplifier may compare the current with a reference value (e.g., a reference current) from a reference memory cell or a mobilized nominal memory cell. The reference memory cell may have a resistance that is the average of the HRS and LRS, which can be used as a reference value. Subsequently, the sense amplifier may compare the current output from the selected nominal memory cell with the current output from the reference memory cell / mobilized nominal memory cell to determine whether the data bit stored by the selected nominal memory cell is the same as logic 0 or logic 1.

[0026] The variable resistor (210) typically comprises a resistive switching element / variable resistive dielectric layer interposed between an upper electrode and a lower electrode. In some embodiments, the upper electrode comprises titanium (Ti) and tantalum nitride (TaN), the lower electrode comprises titanium nitride (TiN), and the variable resistive dielectric layer comprises, for example, nickel oxide (NiO), titanium oxide (TiO), hafnium oxide (HfO), zirconium oxide (ZrO), zinc oxide (ZnO), tungsten oxide (WO3), aluminum oxide (Al2O3), tantalum oxide (TaO), molybdenum oxide (MoO), or copper oxide (CuO). In some embodiments, the lower electrode may be formed in a lower metallization layer among the metallization layers, and the upper electrode may be formed in an upper metallization layer among the metallization layers. Additionally, a top electrode via (TEVA) can be formed on the top electrode and a bottom electrode via (BEVA) can be formed below the bottom electrode, so that the variable resistor (210) can be connected to other structures / components such as a selector transistor (220), a bit line (BL), etc.

[0027] FIG. 3 illustrates an exemplary schematic diagram of the memory circuit (100) illustrated in FIG. 1 according to some embodiments. Hereinafter, the example of FIG. 3 is referred to as the memory circuit (300). It should be understood that the schematic diagram of FIG. 3 is provided for illustrative purposes only and is not intended to limit the scope of the present disclosure. Accordingly, the memory circuit (300) may include any various other suitable components while remaining within the scope of the present disclosure.

[0028] As illustrated, the I / O circuit (130) may include a sensing amplifier (132), a first multiplexer (134), and a second multiplexer (136). The sensing amplifier (132) may be operablely coupled to an upper memory array (110) through the first multiplexer (134) and operablely coupled to a lower memory array (115) through the second multiplexer (136). Additionally, the sensing amplifier (132) may be coupled to memory cells (140) through bit lines (BL) of the upper memory array (110) and to memory cells (145) through bit lines (BL) of the lower memory array (115). The bit lines (BL) of the upper and lower memory arrays (110, 115) extend along the Y-axis. As a non-limiting example, the number of bit lines (BL) of each of the upper and lower memory arrays coupled to one sensing amplifier (132) may be equal to 32.

[0029] Each of the upper memory array (110) and the lower memory array (115) of the memory circuit (300) includes a plurality of data word lines (WL) extending along the X-axis. In a non-limiting example, the memory array (110) has 512 data word lines (WL U )(WL U It may include _D), and the memory array (115) has 512 data word lines (WL L )(WL L It may include _D). Data word lines (WL U _D) Each is a nominal memory cell (140) configured to store each data bit. N It can be coupled to a set of ) and data word lines (WL L _D) Each is a nominal memory cell (145) configured to store each data bit. N Can be coupled to a set of ). Data word lines (WL U _D / WL L_D) Nominal memory cells coupled to each (140 N / 145 N The number of sets of ) can be equal to the number of bit lines (BL) (or source lines (SL)), for example, 32.

[0030] Each of the upper memory array (110) and lower memory array (115) of the memory circuit (300) includes a plurality of segmented reference word lines (WL) extending along the X-axis. Across each of the memory arrays, the segmented reference word lines (WL) may be arranged along the Y-axis at intervals of a predefined number (N) of data word lines (WL_D). In other words, each of the segmented reference word lines (WL) may be placed in the middle of each set of data word lines (WL_D) (along the Y-axis), the number of which is equal to N. Such sets of data word lines (WL_D) are sometimes referred to as data word line segments, reference segments, or segments. Equally, this N may also refer to the number of data word lines (WL_D) in each segment of the memory array.

[0031] In a non-limiting example where the upper memory array (110) contains 512 data word lines (WL_D) and N=32, the upper memory array (110) has 16 segmented reference word lines (WL) since 512 / 32=16. U It may include _REFS) or 16 segments. Additionally, 16 segmented reference word lines (WL U As each _REFS) is placed in the middle of the corresponding segment among the 16 segments, the segmented reference word lines (WL U Among _REFS), adjacent ones are 32(N) data word lines (WL U They are separated from each other by _D). In other words, the upper memory array (110) consists of 16 data word lines (WL UIncludes a set of _D) and 16 data word lines (WL U _D) 16 segmented reference word lines (WL) each placed in the middle of the corresponding set among the sets U Includes _REFS).

[0032] Likewise, in the example where the lower memory array (115) contains 512 data word lines (WL_D) and N=32, the lower memory array (115) contains 16 segmented reference word lines (WL L It may include _REFS) or 16 segments, and segmented reference word lines (WL L Among _REFS), adjacent ones are 32 (N) data word lines (WL L They are separated from each other by _D). In other words, the upper memory array (115) consists of 16 data word lines (WL L Includes a set of _D) and 16 data word lines (WL L _D) 16 segmented reference word lines (WL) each placed in the middle of the corresponding set among the sets L Includes _REFS). Segmented reference word lines (WL U _REFS / WL L _REFS) can be numbered with parameters (M) which can be any integer from 0 to 15, and this will be discussed in more detail below.

[0033] In another non-limiting example where the upper and lower memory arrays each contain 512 data word lines (WL_D) and N=16, the upper / lower memory arrays (110 / 115) contain 32 segmented reference word lines (WL) (as 512 / 16=32). U / L It may include _REFS) or 32 segments, and segmented reference word lines (WL U / L Among _REFS), adjacent ones are 16(N) data word lines (WL U / LThey are separated from each other by _D). In another non-limiting example where the upper and lower memory arrays each contain 512 data word lines (WL_D) and N=64, the upper / lower memory arrays (110 / 115) contain 8 segmented reference word lines (WL) (as 512 / 64=8). U / L It may include _REFS) or 8 segments, and segmented reference word lines (WL U / L Among _REFS), adjacent ones are 64 (N) data word lines (WL U / L They are separated from each other by _D).

[0034] Each of the upper memory array (110) and the lower memory array (115) of the memory circuit (300) includes a single global reference word line (WL) extending along the X-axis. The global reference word line (WL) may be positioned along the edge of the corresponding memory array extending along the X-axis. For example, the upper memory array (110) may have a single global reference word line (WL) positioned at the edge closest to the I / O circuit (130) (along the Y-axis). U It may include _REFG), and the lower memory array (115) has one global reference word line (WL) placed at the edge closest to the I / O circuit (130) (along the Y-axis). L It may include _REFG).

[0035] In some embodiments, segmented reference word lines (WL U _REFS) Each is a reference memory cell (140) configured to store a reference value. R Coupled to each set of ) (one of the segmented reference memory cell sets of the upper memory array (110)), and segmented reference word lines (WL L _REFS) Each is a reference memory cell (145) configured to store a reference value. RIt is coupled to each set of ) (one of the segmented reference memory cell sets of the lower memory array (115). In some embodiments, the global reference word line (WL U _REFG) are reference memory cells (140) each configured to store a reference value. R Each set of ) is coupled to the global reference memory cell set of the upper memory array (110), and the global reference word line (WL L _REFG) are reference memory cells (145) each configured to store a reference value. R Each set of ) is coupled to the global reference memory cell set of the lower memory array (115).

[0036] FIG. 4 illustrates another exemplary schematic diagram of the memory circuit (100) illustrated in FIG. 1 according to some embodiments. Hereinafter, the example of FIG. 4 is referred to as the memory circuit (400). The memory circuit (400) is a global reference word line (WL U _REFG) is placed at the edge of the memory array (110) furthest from the I / O circuit (130) (along the Y-axis) and the global reference word line (WL L It is substantially similar to the memory circuit (300), except that _REFG) is placed at the edge of the memory array (115) furthest from the I / O circuit (130) (along the Y-axis). Therefore, the description is not repeated.

[0037] FIG. 5 illustrates an exemplary circuit diagram of a memory controller (140) (Fig. 1) according to some embodiments. Generally, the memory controller (140) has a nominal memory cell (e.g., 140 N or 145 NIt is configured to receive at least control signals, such as a REFG_EN signal, a QSI_EN signal, a LOC_EN signal, etc., to determine the reference scheme applied while reading ). According to some embodiments, the reference scheme may be one of a segmented reference scheme, a global reference scheme, a quasi-reference scheme, and a local reference scheme.

[0038] In the exemplary circuit diagram of FIG. 5, a memory controller (140) coupled to memory arrays (110, 115) via WL driver circuits (120, 125) includes an upper portion (510) and a lower portion (515). In some embodiments, the components of the upper portion (510) and the lower portion (515) are substantially similar to each other, and thus the discussion below will focus on the differences. Additionally, the upper portion (510) and the lower portion (515) may operably share the REFG_EN signal, QSI_EN signal, LOC_EN signal, and some other control signals (e.g., A, SEL, XE, etc.), but each receives specific control signals (e.g., HBNK_TOP and HBNK_BOT). It should be understood that the circuit diagram of FIG. 5 is provided for exemplary purposes and is not intended to limit the scope of the present disclosure. Accordingly, the memory controller (140) may include any various other suitable components while remaining within the scope of the present disclosure.

[0039] The upper portion (510) includes logic circuits (520, 522, 524, 526, 528, 530, 532, 534, 536). The logic circuit (520) is configured to receive a QSI_EN signal and another signal (SEL[2:0]). The QSI_EN signal is configured to enable a quasi-reference scheme, and the SEL[2:0] signal is configured to indicate how many data word lines (WL_D) are included in a single segment while the quasi-reference scheme is enabled, which will be discussed below. The logic circuit (522) is configured to receive a LOC_EN signal and at least another control signal (HBNK_TOP). The LOC_EN signal is configured to enable a local reference scheme, and the HBNK_TOP signal is configured to indicate whether to access (e.g., read) the data bits of the upper memory array (110). A logic circuit (524) (e.g., an OR gate) is configured to receive an address signal (A[13:5]) and an output (SELD0[8:0]) from a logic circuit (520). In some embodiments, all bits of the SELD signal are provided with logic 0 except that a quasi-reference scheme is applied, which will be discussed below. A logic circuit (530) (e.g., a decoder) is configured to receive one of the outputs (A_I0[13:5]) from the logic circuit (524), the HBNK_TOP signal, and the outputs (XEP0) from the logic circuit (522).

[0040] In some embodiments, the logic circuit (530) may provide a plurality of decoded signals, e.g., 531, 532, 533, 534. The upper memory array (110) has 512 data word lines (WL U In the example having _D), the signal (534) (sometimes referred to as XD0[3:0]) consists of 128 data word lines (WL U Configured to identify one of four groups each having _D); and 128 WL UFollowing the selection of one of the four groups of _D, the signal (533) (sometimes referred to as XC0[3:0]) consists of 32 data word lines (WL U Configured to identify one of four groups each having _D); and 32 WL U Following the selection of one of the four groups of _D, the signal (532) (sometimes referred to as XB0[3:0]) consists of eight data word lines (WL U Configured to identify one of four groups each having _D); and 8 WL U Following the selection of one of the four groups of _D, the signal (531) (sometimes referred to as XA0[7:0]) selects these eight WL U It is configured to identify which of _D is selected or which corresponding WL driver (of the WL driver circuit (120)) should be activated.

[0041] Referring still to the upper part (510) of the memory controller (140), the logic circuit (526) (e.g., an inverter) is configured to receive the QSI_EN signal. The logic circuit (528) (e.g., an AND gate) is configured to receive the outputs from the logic circuit (522) and the other output of the logic circuit (526). The logic circuit (532) (e.g., an inverter) is configured to receive the REFG_EN signal. The logic circuit (534) (e.g., an AND gate) is configured to receive the REFG_EN signal and the output (REFP0) from the logic circuit (528). The logic circuit (536) (e.g., an AND gate) is configured to receive the REFG_EN signal and a logically inverted version of the REFP0 signal. In some embodiments, if the corresponding memory array (e.g., 110) is configured to provide data bits, the REFP signal (e.g., REFP0) may be provided with a logic 0. In other words, if the corresponding memory array is configured to provide reference values, a logic 1 may be provided to the REFP signal. In some embodiments, the logic circuit (534) is configured to generate an output (REFG_P0) that can indicate whether a global reference scheme is applied to the upper memory array (110); and the logic circuit (536) is configured to generate an output (REFS_P0) that can indicate whether a segmented reference scheme is applied to the upper memory array (110). Thus, if a logic 0 is provided to the REFP signal (e.g., REFP0), the REFG_P signal (e.g., REFG_P0) and REFS_P (e.g., REFS_P0) are both output as logic 0 through the AND gates (534–536).

[0042] Likewise, the lower part (515) includes logic circuits (540, 542, 544, 546, 548, 550, 552, 554, 556), which are similar to each of the logic circuits (520, 522, 524, 526, 528, 530, 532, 534, 536) of the upper part (510). The difference is that the logic circuit (542) (of the lower part (515)) is configured to receive a different control signal (HBNK_BOT), and the logic circuit (550) is configured to receive the HBNK_BOT signal. The HBNK_BOT signal is configured to indicate whether to access (e.g., read) the data bits of the lower memory array (115). In some embodiments, when a segmented reference scheme or a global reference scheme is applied, the HBNK_TOP signal and the HBNK_BOT signal are logically inverted from each other. For example, the HBNK_TOP signal and the HBNK_BOT signal may be provided as logical 1 and logical 0, respectively, which correspond to the nominal memory cell (140) of the upper memory array (110). N ) causes the data bits to be provided, and the reference memory cell (145) of the lower memory bank (115) R ) allows this to provide a reference value. In another example, the HBNK_TOP signal and the HBNK_BOT signal may be provided as logical 0 and logical 1, respectively, which are the nominal memory cells (145) of the lower memory array (115). N ) provides data bits, and the reference memory cell (140) of the upper memory bank (110) R ) allows this to provide a standard value.

[0043] The signals processed / output by the logic circuits (540 to 550) of the lower part (515) are similar to the signals from the upper part (510). For the purpose of example, signals from the upper part (510) are numbered "0", e.g. SELD0[8:0], XEP0, REFP0, A_I0[13:5], REFG_P0, REFS_P0, XA0[7:0], XB0[3:0], XC0[3:0], and XD0[3:0], and signals from the lower part (515) are numbered "1", e.g. SELD1[8:0], XEP1, REFP1, A_I1[13:5], REFG_P1, REFS_P1, XA1[7:0], XB1[3:0], XC1[3:0], and XD1[3:0]. Sometimes, XA1[7:0], XB1[3:0], XC1[3:0], and XD1[3:0] are referred to as signals (554, 553, 552, 551), respectively.

[0044] According to some embodiments of the present disclosure, based on different logic combinations of the aforementioned control signals (e.g., REFG_EN signal, QSI_EN signal, LOC_EN signal), the memory controller (140) may apply respective reference schemes to the memory array (110 or 115). For example, in the discussion below, FIGS. 6 through 8 provide an example in which a segmented reference scheme is applied, where the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logic 0, logic 0, and logic 0, respectively; FIGS. 9 through 11 provide an example in which a global reference scheme is applied, where the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logic 1, logic 0, and logic 0, respectively; FIGS. 12 through 15 provide an example in which a quasi-reference scheme is applied, where the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logic 0, logic 1, and logic 0, respectively; FIGS. 16 through 18 provide examples in which the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logic 0, logic 0, and logic 1, respectively, and a local reference scheme is applied.

[0045] First, referring to FIG. 6 (in conjunction with FIG. 7 and 8), a table summarizing the respective logical values ​​of the REFG_EN signal, QSI_EN signal, and LOC_EN signal corresponding to the segmented reference scheme, and other (intermediate or output) signals are provided. The first row and the second row of the table refer to the signals present in the upper part (510) and the lower part (515), respectively. As illustrated, the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logical 0, logical 0, and logical 0, respectively. This logic combination of the REFG_EN signal, QSI_EN signal, and LOC_EN can activate or otherwise function specific logic circuits of the memory controller (140), for example, 520, 522, 524, 530, 540, 542, 544, 550, 548, and 556, as highlighted in FIG. 7, which describes the circuit diagram of the memory controller (140) (Fig. 5) through annotation. In the examples of FIGS. 6 through 8, the HBNK_TOP signal and the HBNK_BOT signal are provided with logic 1 and logic 0, respectively, so that the upper memory array (110) provides data bits and the lower memory array (115) provides reference values.

[0046] As illustrated in FIGS. 6 and 7, the decoded signals (XA0 to XD0) provided to the WL driver circuit (120) are all activated, while the decoded signals (XA1 to XD1) provided to the WL driver circuit (125) are partially activated. For example, only the XC1 and XD1 signals are activated. This is because when a segmented reference scheme is applied, only one segmented reference word line (WL_REFS) must be selected. Given an example where the above-mentioned N (the number of data word lines (WL_D) of each segment) is provided as 32, the lower memory array (115) may include 16 (= 512 / 32) segments, each of which may include a segmented reference word line (WL_REFS) coupled to a respective set of segmented reference memory cells. To select one of these 16 segments (or one of the 16 segmented reference word lines (WL_REFS)), resolution can be simply provided by the XC1 and XD1 signals. When logic 1, logic 0, logic 0, and logic 0 are provided to the HBNK_TOP signal, HBNK_BOT signal, LOC_EN signal, and QSI_EN signal, respectively, logic circuits (542 to 548) can provide a REFP1 signal of logic 1. When the REFG_EN signal is provided as logic 0, logic circuit (556) can provide a REFS_P1 of logic 1 through logic circuit (552). Along with the decoded address signals (XC1 and XD1 signals), one of the drivers of the WL driver circuit (125), which is operably coupled to the segmented reference word line (WL_REFS) of the selected segment, can be activated. Therefore, this enabled driver can assign the segmented reference word line (WL_REFS) of the selected segment.

[0047] In some embodiments, the upper memory array (110) and the lower memory array (115) each share the same segmentary array. For example, when N is provided as 32, both the upper memory array (110) and the lower memory array (115) each have 512 data word lines (WL_D) and have 16 segments. Each of these 16 segments has 32 data word lines (WL_D), and a segmented reference word line (WL_REFS) is placed in the middle. Additionally, each of these 16 segments (or the included segmented reference word line (WL_REFS)) may be numbered by a parameter (M) which may be any integer from 0 to 15. Additionally, in some embodiments, the memory controller (140) may apply the same parameter (M) to both the memory array (110) (e.g., configured to provide data bits) and the memory array (115) (e.g., configured to provide reference values). For example, when a nominal memory cell placed along one of the data word lines (WL_D) (in the M-th segment) of one of the memory arrays (110 or 115) is selected to have its data bit read, the memory controller (140) may select a reference memory cell placed along the segmented reference word line (WL_REFS) of the M-th segment of the other memory array (110 or 115) to provide a reference value.

[0048] FIG. 8 shows one nominal memory cell (140) of the upper memory array (110). N While a data bit of ) is selected to be read, one reference memory cell (145) of the lower memory array (115) R This illustrates an example where the reference value of ) is used to compare with the data bit. In FIG. 8, each circle corresponds to one of the memory cells (140 or 145). As shown, WL UData word line (WL) referenced as _D[N×(M+1)-1] U A single nominal memory cell (140) coupled to _D) N ) is selected to be read by activating one of the drivers of the WL driver circuit (120) (e.g., driver (820) of FIG. 8). In some embodiments, the memory controller (140) provides its reference value by activating one of the drivers of the WL driver circuit (125) (e.g., driver (825) of FIG. 8), WL L Segmented reference word line (WL) referenced as _REFS[M] L A single reference memory cell (145) coupled to _REFS) R ) can be selected. In some embodiments, the word lines (WL of the upper memory array (110) U _D, WL U _REFS, WL U Each _REFG) can be coupled to its respective driver among the plurality of drivers of the WL driver circuit (120), and the word lines (WL) of the lower memory array (115) L _D, WL L _REFS, WL L Each _REFG) can be coupled to its respective driver among the plurality of drivers of the WL driver circuit (125). Nominal memory cell (140) in the M segment of the array (110) N Any one of ) (i.e., WL U _D[N×(M+1)-2] to WL U Other data word lines such as _D[N×M] (WL U When there is a coupled to _D), the memory controller (140) WL L Reference memory cells coupled to _REFS[M] (145 R It should be noted that you can still choose one of the following.

[0049] Next, referring to FIG. 9 (in conjunction with FIG. 10 and 11), a table summarizing the respective logic values ​​of the REFG_EN signal, QSI_EN signal, and LOC_EN signal corresponding to the global reference scheme, and other (intermediate or output) signals are provided. The first row and the second row of the table refer to the signals present in the upper part (510) and the lower part (515), respectively. As illustrated, the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logic 1, logic 0, and logic 0, respectively. This logic combination of the REFG_EN signal, QSI_EN signal, and LOC_EN can enable or otherwise function specific logic circuits of the memory controller (140), for example, 520, 522, 524, 530, 540, 542, 544, 548, 550, and 554, as highlighted in FIG. 10, which describes the circuit diagram of the memory controller (140) (Fig. 5) through annotations. In the examples of FIGS. 9 through 11, the HBNK_TOP signal and the HBNK_BOT signal are provided with logic 1 and logic 0, respectively, so that the upper memory array (110) provides data bits and the lower memory array (115) provides reference values.

[0050] As illustrated in FIGS. 9 and 10, the decoded signals (XA0 to XD0) provided to the WL driver circuit (120) are all enabled, while the decoded signals (XA1 to XD1) provided to the WL driver circuit (125) are all disabled. This is because when the global reference scheme is applied, only the global reference word line (WL_REFG) must be selected. That is, no segment should be selected. When logic 1, logic 0, logic 0, and logic 0 are provided to the HBNK_TOP signal, HBNK_BOT signal, LOC_EN signal, and QSI_EN signal, respectively, the logic circuits (542 to 548) can provide a logic 1 REFP1 signal. When the REFG_EN signal is provided as logic 1, the logic circuit (554) can provide a logic 1 REFG_P1 signal. With all decoded address signals (XA1 to XD1 signals) deactivated, one of the drivers of the WL driver circuit (125), which is operably coupled to the global reference word line (WL_REFG), can be activated. Thus, this activated driver can assert the global reference word line (WL_REFG).

[0051] FIG. 11 shows one nominal memory cell (140) of an upper memory array (110). N While a data bit of ) is selected to be read, one reference memory cell (145) of the lower memory array (115) R This illustrates an example where the reference value of ) is used to compare with the data bit. In FIG. 11, each circle corresponds to one of the memory cells (140 or 145). As illustrated, WL U Data word line (WL) referenced as _D[N×(M+1)-1] U A single nominal memory cell (140) coupled to _D) N) is selected to be read by activating one of the drivers of the WL driver circuit (120) (e.g., driver (1120) of FIG. 11). In some embodiments, the memory controller (140) activates one of the drivers of the WL driver circuit (125) (e.g., driver (1125) of FIG. 11) to read the global reference word line (WL L A reference memory cell (145) coupled to _REFG) R ) can be selected to provide a reference value for this. In some embodiments, the word lines (WL of the upper memory array (110) U _D, WL U _REFS, WL U Each _REFG) can be coupled to its respective driver among the plurality of drivers of the WL driver circuit (120), and the word lines (WL) of the lower memory array (115) L _D, WL L _REFS, WL L Each _REFG) can be coupled to its respective driver among the multiple drivers of the WL driver circuit (125).

[0052] Next, referring to FIG. 12 (in conjunction with FIG. 13 through 15), a table summarizing the respective logic values ​​of the REFG_EN signal, QSI_EN signal, and LOC_EN signal corresponding to the quasi-reference scheme, and other (intermediate or output) signals are provided. The first and second rows of the table refer to the signals present in the upper part (510) and the lower part (515), respectively. As illustrated, the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logic 0, logic 1, and logic 0, respectively. This logic combination of the REFG_EN signal, QSI_EN signal, and LOC_EN can enable or otherwise function specific logic circuits of the memory controller (140), for example, 520, 522, 524, 530, 540, 542, 544, and 550, as highlighted in FIG. 13, which describes the circuit diagram of the memory controller (140) (Fig. 5) through annotations. In the examples of FIG. 12 and 13, a logic 1 is provided to both the HBNK_TOP signal and the HBNK_BOT signal so that the upper memory array (110) provides data bits and the lower memory array (115) provides reference values, thereby enabling its own memory cells (145 N Changes the use of one of the ) or causes it to be mobilized.

[0053] As illustrated in FIGS. 12 and 13, the decoded signals (XA0 to XD0) provided to the WL driver circuit (120) are all activated, while the decoded signals (XA1 to XD1) provided to the WL driver circuit (125) are also all activated. This is because any of the data word lines (WL_D) of the memory array configured to provide a reference value can be selected when a quasi-reference scheme is applied. When a logic 1 is provided to both the HBNK_TOP signal and the HBNK_BOT signal, the logic circuits (528, 548) can provide the REFP0 signal and REFP1 signal of logic 0, which ultimately provide the REFG_P0 signal, REFS_P0 signal, REFG_P1 signal, and REFS_P1 signal of logic 0. That is, the global reference memory cell set or the segmented reference memory cell set in either the upper memory array (110) or the lower memory array (115) will not be activated.

[0054] Additionally, in some embodiments, when a quasi-reference scheme is applied (e.g., by providing a QSI_EN signal of logic 1), the SEL[2:0] signal must be provided to indicate the value of N mentioned above. The SEL[2:0] signal can indicate up to eight different N values. For example, when SEL[2:0]=(000), N=1; when SEL[2:0]=(001), N=16; when SEL[2:0]=(010), N=32; when SEL[2:0]=(011), N=64; and when SEL[2:0]=(100), N=512. When N is specified, the number of segments (of the data word lines (WL_D)) can be determined. In the example of FIG. 12, SEL[2:0] is provided as (001), and accordingly, N is provided as 16. In some embodiments, the memory controller (140) may divide the data word lines of a memory array configured to provide a reference value (e.g., 115) into 32 (512 / 16) segments. Each of these segments is numbered by a parameter (M).

[0055] Continuing with the example where the memory array has 512 data word lines (WL_D) and N=16, the memory array may have 32 segments, each of which is referenced by M. Thus, M can be any integer from 0 to 31. Given 512 data word lines (WL_D) within each memory array, Table I below shows different combinations of the SEL[2:0] signal (e.g., corresponding to N) and their corresponding segmentary values ​​(e.g., range of M, number of data word lines within each segment, number of segments, etc.).

[0056] SEL[2:0] N Range of M Number of data WLs within each segment Number of segments 000 1 0~511 1 512 001 16 0~31 16 32 010 32 0~15 32 16 011 64 0~7 64 8 100 512 0 512 1

[0058] In some embodiments, data word lines (WL of one of the memory arrays (e.g., 110)) to provide SEL[2:0] signals and data bits for determining N. U Based on an address signal (e.g., A[13:5]) for selecting one of _D), the memory controller (140) can identify the value of the parameter (M). In other words, the memory controller (140) can identify the data word line (WL U The M segment to which _D) belongs can be identified. Next, the memory controller (140) uses the value of parameter (M) to identify the data word lines (WL) of another memory array (e.g., 115) among the memory arrays. L It is possible to select which segment of _D) is intended to provide a reference value. The memory controller (140) may select the Mth segment of the memory array (115). Additionally, the memory controller (140) may select a data word line (WL) within the Mth segment of the memory array (115) based on the most significant bit (MSB) of N. L You can select _D).

[0059] For example, a data word line (WL of the memory array (110) U When _D[0]) is selected to provide a data bit and N is provided as 1, the value of parameter (M) is determined to be 0. That is, the 0th segment of the memory array (110) is selected. Next, the memory controller (140) selects the 0th segment of the memory array (115) and, to provide a reference value, a data word line (WL) (within the 0th segment of the memory array (115)). L You can additionally select _D[0]). In another example, the data word line (WL of the memory array (110) UWhen _D[0]) is selected to provide a data bit and N is provided as 16, the value of parameter (M) is determined as 0 (the 0th segment of the memory array (110)). The memory controller (140) selects the 0th segment of the memory array (115) and, to provide a reference value, a data word line (WL) (within the 0th segment of the memory array (115)). L You can additionally select _D

[15] ). In another example, the data word line (WL of the memory array (110)) U When _D[0]) is selected to provide a data bit and N is provided as 32, the value of parameter (M) is determined as 0 (the 0th segment of the memory array (110)). The memory controller (140) selects the 0th segment of the memory array (115) and, to provide a reference value, a data word line (WL) (within the 0th segment of the memory array (115)). L You can additionally select _D

[31] ).

[0060] FIGS. 14 and FIGS. 15 illustrate examples in which different values ​​of N are provided (e.g., via the SEL[2:0] signal). For clarity, in FIG. 14 or FIG. 15, segmented or global reference word lines are not shown in the memory array (110 or 115). In FIG. 14, N is provided as a smaller value, whereas in FIG. 15, N is provided as a larger value. Also, in FIG. 14, a nominal memory cell (140) of the first segment of the upper memory array (110) to provide data bits N When ) is selected, the first segment of the lower memory array (115) is selected, and the mobilized data word line (WL) within the first segment of the lower memory array (115) L A nominal memory cell (145) coupled to _D) N) is selected to provide a reference value, and in FIG. 15, a nominal memory cell (140) of the 0th segment of the upper memory array (110) to provide a data bit N When ) is selected, the 0th segment of the lower memory array (115) is selected, and the mobilized data word line (WL) within the 0th segment of the lower memory array (115) L A nominal memory cell (145) coupled to _D) N ) is selected to provide a reference value.

[0061] Next, referring to FIG. 16 (in conjunction with FIG. 17 and 18), a table summarizing the respective logic values ​​of the REFG_EN signal, QSI_EN signal, and LOC_EN signal corresponding to the local reference scheme, and other (intermediate or output) signals are provided. The first and second rows of the table refer to the signals present in the upper part (510) and lower part (515), respectively. As illustrated, the REFG_EN signal, QSI_EN signal, and LOC_EN signal are provided as logic 0, logic 0, and logic 1, respectively. This logic combination of the REFG_EN signal, QSI_EN signal, and LOC_EN signal can activate or otherwise function specific logic circuits of the memory controller (140), for example, 520, 522, 524, and 530, as highlighted in FIG. 17, which describes the circuit diagram of the memory controller (140) (Fig. 5) through annotations. In the examples of FIGS. 16 to 18, the HBNK_TOP signal and the HBNK_BOT signal are provided with a logic 1 and a logic 0, respectively, so that the upper memory array (110) also provides a reference value for the data bit.

[0062] As illustrated in FIGS. 16 and 17, the decoded signals (XA0 to XD0) provided to the WL driver circuit (120) are all enabled, while the decoded signals (XA1 to XD1) provided to the WL driver circuit (125) are all disabled. This is so that when a local reference scheme is applied, the data word line (WL) provides both the data bit and the reference value. U This is because one of _D) must be selected. That is, no segment should be selected. If logic 1, logic 0, logic 1, and logic 0 are provided to the HBNK_TOP signal, HBNK_BOT signal, LOC_EN signal, and QSI_EN signal, respectively, logic circuits (542 to 548) may provide a REFP1 signal of logic 0. If the REFG_EN signal is provided as logic 0, logic circuits (554, 556) may provide both the REFG_P1 signal and the REFS_P1 signal of logic 0. Likewise, both the REFG_P0 signal and the REFS_P0 signal are provided as logic 0. With all decoded address signals (XA0 to XD0 signals) activated, the data word line (WL U One of the drivers of the WL driver circuit (120), which is operably coupled to _D), can be activated. Accordingly, this activated driver is a data word line (WL U _D) can be attributed.

[0063] FIG. 18 shows one nominal memory cell (140) of an upper memory array (110). N )(140 N1 A data bit of ) is selected to be read, and another nominal memory cell (140) of the upper memory array (110) N )(140 N2This illustrates an example where the data bit of ) is selected as a reference value. The reference value is used to compare with the data bit. In FIG. 18, each circle corresponds to one of the memory cells (140 or 145). As illustrated, WL U Data word line (WL) referenced as _D[N×(M+1)-1] U Memory cell (140) coupled to _D) N1 ) is selected to be read by activating one of the drivers of the WL driver circuit (120) (e.g., driver (1820) of FIG. 18). In some embodiments, the memory controller (140) activates the same driver to read the same data word line (WL U Memory cell (145) coupled to _D[N×(M+1)-1]) N2 ) can be selected to provide its data bits as a reference value. In some embodiments, the word lines (WL of the upper memory array (110) U _D, WL U _REFS, WL U Each _REFG) can be coupled to its respective driver among the plurality of drivers of the WL driver circuit (120), and the word lines (WL) of the lower memory array (115) L _D, WL L _REFS, WL L Each _REFG) can be coupled to its respective driver among the multiple drivers of the WL driver circuit (125).

[0064] FIG. 19 illustrates a flowchart of an exemplary method (1900) for operating a memory device comprising a memory controller configured to select one of various reference schemes while performing a read operation, according to some embodiments. For example, at least some of the operations of the method (1900) may be performed by the memory controller (140) discussed in relation to FIGS. 1 through 18. Accordingly, in the description of the method (1900) below, at least the reference numbers used in FIGS. 1 through 18 may be reused. It should be noted that the method (1900) is merely illustrative and is not intended to limit the present disclosure. Accordingly, it is understood that additional operations may be provided before, during, and after the method (1900) of FIG. 19, and that some other operations may be described here only briefly.

[0065] The method (1900) begins with an operation (1910) of receiving a first control signal, a second control signal, and a third control signal. In some embodiments, a logical combination of the first to third control signals is configured to select one of a first reference scheme, a second reference scheme, a third reference scheme, and a fourth reference scheme. For example, a memory controller (140) coupled to an upper memory array (110) and a lower memory array (115), respectively, via a WL driver circuit (120) and a WL driver circuit (125), may receive a REFG_EN signal, a QSI_EN signal, and a LOC_EN signal. Based on a logical combination of the REFG_EN signal, the QSI_EN signal, and the LOC_EN signal corresponding to one of a segmented reference scheme, a global reference scheme, a quasi-reference scheme, and a local reference scheme, the memory controller (140) may select a corresponding memory cell (e.g., 140 N , 140 R , 145 N , 145 RTo provide a reference value by turning on ) the corresponding word line (e.g., WL U _D, WL L _D, WL U _REFS, WL L _REFS, WL U _REFG, WL L The driver of the WL driver circuit (120) or the WL driver circuit (125) can be activated to assert _REFG).

[0066] The method (1900) proceeds to an operation (1920) of comparing a first reference signal provided by one of the first reference memory cells of the first memory array and a second nominal memory cell of one of the second nominal memory cells of the second memory array with a first data signal provided by one of the second nominal memory cells, by activating one of the first reference memory cells of the first memory array and one of the second nominal memory cells of the second memory array based on a first logic combination of first to third control signals; The method (1900) proceeds to an operation (1930) of comparing a second reference signal provided by one of the second reference memory cells among the second reference memory cells with a second data signal provided by another of the second nominal memory cells among the second nominal memory cells by activating one of the second reference memory cells among the plurality of second reference memory cells of the first memory array and another second nominal memory cell among the plurality of second nominal memory cells of the second memory array based on a second logic combination of the first to third control signals; The method (1900) proceeds to an operation (1940) of comparing a third data signal provided by one of the first nominal memory cells of the first memory array and another second nominal memory cell of the second nominal memory array with a fourth data signal provided by another second nominal memory cell of the second nominal memory cells, by activating one of the first nominal memory cells of the first memory array and another second nominal memory cell of the second memory array based on a third logic combination of the first to third control signals;Alternatively, the method (1900) proceeds to an operation (1950) of comparing a fifth data signal provided by another second nominal memory cell among the second nominal memory cells among the second nominal memory cells with a sixth data signal provided by another second nominal memory cell among the second nominal memory cells, by activating another second nominal memory cell among the plurality of second nominal memory cells among the plurality of second nominal memory cells among the second memory array based on a fourth logic combination of first to third control signals.;

[0067] Continuing from the above example, the first and second memory arrays may each be non-limiting examples of the lower memory array (115) and the upper memory array (110). Additionally, the first nominal memory cells are data word lines (WL L Nominal memory cells (145) coupled to one of _D) N ) may be; and the second nominal memory cells are data word lines (WL U Nominal memory cells (140) coupled to one of _D) N ) may be; and the first reference memory cells are segmented reference word lines (WL L Reference memory cells (145) coupled to one of the _REFS) R ) may be; and the second reference memory cells are global reference word lines (WL L Reference memory cells (145) coupled to _REFG) R It can be.

[0068] Additionally, in operation (1920), the first logic combination of the first to third control signals may correspond to a segmented reference scheme. When the segmented reference scheme is applied by the memory controller (140), the memory controller (140) nominal memory cells (140) N A data signal provided by one of ), segmented reference word lines (WL LReference memory cells (145) coupled to a corresponding one among _REFS) R It can be compared with a reference signal provided by one of the following. For details, refer to the examples illustrated in FIGS. 6 through 8.

[0069] In operation (1930), the first logic combination of the first to third control signals may correspond to a global reference scheme. When the global reference scheme is applied by the memory controller (140), the memory controller (140) nominal memory cells (140 N A data signal provided by one of the global reference word lines (WL L Reference memory cells (145) coupled to _REFG) R It can be compared with a reference signal provided by one of the following. For details, refer to the examples illustrated in FIGS. 9 through 11.

[0070] In operation (1940), the first logic combination of the first to third control signals may correspond to a quasi-reference scheme. When the quasi-reference scheme is applied by the memory controller (140), the memory controller (140) nominal memory cells (140 N The data signal provided by one of ) data word lines (WL L Nominal memory cells (145) coupled to one of _D) N It can be compared with a reference signal provided by one of the following. For details, refer to the examples illustrated in FIGS. 12 through 15.

[0071] In operation (1950), the first logic combination of the first to third control signals may correspond to a local reference scheme. When the local reference scheme is applied by the memory controller (140), the memory controller (140) nominal memory cells (140 N A data signal provided by one of the ) nominal memory cells (140 NIt can be compared with a reference signal provided by the other one of ), and these two nominal memory cells (140 N ) are data word lines (WL U It is jointly coupled to one of _D). For details, refer to the examples illustrated in FIGS. 16 to 18.

[0072] As used herein, the terms “about” and “approximately” refer to a given quantity value that may vary based on a specific technical node associated with the semiconductor device. Based on a specific technical node, the term “about” may refer to a given quantity value that varies within, for example, 10 to 30% of the value (e.g., ±+10%, ±20%, or ±30% of the value).

[0073] To enable those skilled in the art to better understand the aspects of the present disclosure, the features of several embodiments have been outlined above. Those skilled in the art should be aware that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also be aware that such equivalent configurations do not depart from the spirit and scope of the present disclosure, and that those skilled in the art may make various changes, substitutions, and modifications to the present invention without departing from the spirit and scope of the present disclosure.

[0074] Examples

[0075] Example 1. In a semiconductor device,

[0076] A first memory array comprising a plurality of first nominal memory cells, a plurality of first reference memory cells, and a plurality of second reference memory cells;

[0077] A second memory array comprising a plurality of second nominal memory cells, a plurality of third reference memory cells, and a plurality of fourth reference memory cells;

[0078] An input / output (I / O) circuit physically interposed between the first memory array and the second memory array along the first transverse direction; and

[0079] A controller operably coupled to the above I / O circuit, the first memory array, and the second memory array

[0080] Includes,

[0081] A semiconductor device in which, based on a plurality of control signals, the controller is configured to select a reference signal from one of the third reference memory cells, the fourth reference memory cells, and the second nominal memory cells, thereby enabling the I / O circuit to detect a data signal from one of the first nominal memory cells.

[0082] Example 2. In Example 1,

[0083] A plurality of first drivers operably coupled between the controller and the first memory array; and

[0084] A plurality of second drivers operably coupled between the controller and the second memory array

[0085] A semiconductor device including additional

[0086] Example 3. In Example 2,

[0087] The above controller also,

[0088] To retrieve the above reference signal, a corresponding second driver among the above second drivers is activated;

[0089] A semiconductor device configured to activate a corresponding first driver among the first drivers in order to retrieve the above data signal.

[0090] Example 4. In Example 1,

[0091] A semiconductor device in which the first reference memory cells are alternately arranged with respect to the first nominal memory cells along the first transverse direction, and the third reference memory cells are alternately arranged with respect to the second nominal memory cells along the first transverse direction.

[0092] Example 5. In Example 4,

[0093] A semiconductor device in which the second reference memory cells are arranged along a first edge of the first memory array extending in a second transverse direction perpendicular to the first transverse direction, and the fourth reference memory cells are arranged along a second edge of the second memory array extending in the second transverse direction.

[0094] Example 6. In Example 5,

[0095] A semiconductor device in which the I / O circuit is positioned along the first lateral direction opposite the first edge of the first memory array, and the I / O circuit is positioned along the first lateral direction opposite the second edge of the second memory array.

[0096] Example 7. In Example 5,

[0097] A semiconductor device in which the first edge is positioned along the first transverse direction opposite the I / O circuit and the first memory array, and the second edge is positioned along the first transverse direction opposite the I / O circuit and the second memory array.

[0098] Example 8. In Example 1,

[0099] A semiconductor device in which the above plurality of control signals include a first control signal and a second control signal.

[0100] Example 9. In Example 8,

[0101] A semiconductor device in which, when both the first control signal and the second control signal are provided in a first logic state, the controller is configured to cause the I / O circuit to retrieve the reference signal from one of the third reference memory cells.

[0102] Example 10. In Example 9,

[0103] A semiconductor device in which, when the first control signal and the second control signal are provided in a second logic state and the first logic state, respectively, the controller is configured to cause the I / O circuit to retrieve the reference signal from one of the fourth reference memory cells.

[0104] Example 11. In Example 10,

[0105] A semiconductor device in which, when the first control signal and the second control signal are provided in the first logic state and the second logic state, respectively, the controller is configured to cause the I / O circuit to retrieve the reference signal from one of the second reference memory cells.

[0106] Example 12. In a semiconductor device,

[0107] A first memory array comprising a plurality of first memory cells each configured to store a first data bit based on a first variable resistor, a plurality of second memory cells each configured to store a first reference resistor, and a plurality of third memory cells each configured to store a second reference resistor;

[0108] A second memory array comprising a plurality of fourth memory cells each configured to store a second data bit based on a second variable resistor, a plurality of fifth memory cells each configured to store a third reference resistor, and a plurality of sixth memory cells each configured to store a fourth reference resistor; and

[0109] controller

[0110] Includes,

[0111] The above controller is:

[0112] Receiving multiple control signals;

[0113] A semiconductor device configured to, based on a logical combination of the plurality of control signals, (i) select one of the third reference resistor, the fourth reference resistor, and the second data bit to compare with the first data bit, or (ii) select one of the first reference resistor, the second reference resistor, and the first data bit to compare with the second data bit.

[0114] Example 13. In Example 12,

[0115] A semiconductor device in which the first memory array and the second memory array are physically positioned next to each other along a first transverse direction.

[0116] Example 14. In Example 13,

[0117] The plurality of first memory cells are formed as a plurality of first segments extending along a second lateral direction perpendicular to the first lateral direction;

[0118] The plurality of second memory cells are formed as a plurality of second segments extending along the second transverse direction;

[0119] The plurality of fourth memory cells are formed as a plurality of third segments extending along the second transverse direction;

[0120] The plurality of fifth memory cells are formed as a plurality of fourth segments extending along the second transverse direction;

[0121] The first segments and the second segments are arranged alternately with respect to each other along the first transverse direction;

[0122] A semiconductor device in which the third segments and the fourth segments are arranged alternately with respect to each other along the first transverse direction.

[0123] Example 15. In Example 14,

[0124] The plurality of third memory cells are formed as a single fifth segment extending along the second transverse direction;

[0125] The plurality of sixth memory cells are formed as a single sixth segment extending along the second transverse direction;

[0126] The fifth segment is arranged along the first transverse direction on one side of the entire first segments and the second segments;

[0127] A semiconductor device in which the sixth segment is arranged on one side of the entirety of the third segments and the fourth segments along the first transverse direction.

[0128] Example 16. In Example 12,

[0129] A semiconductor device in which, when both the first control signal and the second control signal among the control signals are provided in a first logic state, the controller is configured to cause the sensing amplifier to retrieve the second reference resistor to be compared with the second data bit or the fourth reference resistor to be compared with the first data bit.

[0130] Example 17. In Example 16,

[0131] A semiconductor device configured such that when the first control signal and the second control signal are provided in a second logic state and the first logic state, respectively, the controller causes the sensing amplifier to retrieve the first reference resistor to be compared with the second data bit or the third reference resistor to be compared with the first data bit.

[0132] Example 18. In Example 17,

[0133] A semiconductor device configured such that when the first control signal and the second control signal are provided in the first logic state and the second logic state, respectively, the controller causes the sensing amplifier to retrieve the first data bit to be compared with the second data bit or the second data bit to be compared with the first data bit.

[0134] Example 19. In the method,

[0135] A step of receiving at least a first control signal and a second control signal - the logical combination of the first control signal and the second control signal is configured to select one of at least a first reference scheme, a second reference scheme, and a third reference scheme -;

[0136] A step of comparing a first reference signal provided by the first reference memory cell among the first reference memory cells and a second nominal memory cell among the second nominal memory cells of the second memory array with a first data signal provided by the first reference memory cell among the first reference memory cells, based on a first logic combination among the logic combinations corresponding to the first reference scheme;

[0137] A step of comparing a second reference signal provided by one of the second reference memory cells among the second reference memory cells with a second data signal provided by the other of the second nominal memory cells among the second nominal memory cells by activating one of the second reference memory cells among the plurality of second reference memory cells of the first memory array and another of the second nominal memory cells among the plurality of second nominal memory cells of the second memory array based on a second logic combination among the logic combinations corresponding to the second reference scheme; and

[0138] A step of comparing a third data signal provided by the first nominal memory cell among the first nominal memory cells with a fourth data signal provided by the other second nominal memory cell among the second nominal memory cells by activating one first nominal memory cell among the plurality of first nominal memory cells of the first memory array and another second nominal memory cell among the plurality of second nominal memory cells of the second memory array based on a third logic combination among the logic combinations corresponding to the third reference scheme above.

[0139] A method including

[0140] Example 20. In Example 19,

[0141] The first nominal memory cells are alternately arranged with respect to the first reference memory cells along the first transverse direction, and

[0142] A method in which the second reference memory cells are arranged along the edge of the first memory array extending in a second transverse direction perpendicular to the first transverse direction.

Claims

Claim 1 A semiconductor device comprising: a first memory array including a plurality of first nominal memory cells, a plurality of first reference memory cells, and a plurality of second reference memory cells; a second memory array including a plurality of second nominal memory cells, a plurality of third reference memory cells, and a plurality of fourth reference memory cells; an input / output (I / O) circuit physically interposed between the first memory array and the second memory array along a first lateral direction; and a controller operably coupled to the I / O circuit, the first memory array, and the second memory array, wherein, based on a plurality of control signals, the controller is configured to select a reference signal from one of the third reference memory cells, the fourth reference memory cells, and the second nominal memory cells, thereby enabling the I / O circuit to detect a data signal from one of the first nominal memory cells. Claim 2 A semiconductor device according to claim 1, further comprising: a plurality of first drivers operably coupled between the controller and the first memory array; and a plurality of second drivers operably coupled between the controller and the second memory array. Claim 3 In paragraph 2, the controller also, To retrieve the above reference signal, a corresponding second driver among the above second drivers is activated; A semiconductor device configured to activate a corresponding first driver among the first drivers in order to retrieve the above data signal. Claim 4 A semiconductor device according to claim 1, wherein the first reference memory cells are alternately arranged with respect to the first nominal memory cells along the first transverse direction, and the third reference memory cells are alternately arranged with respect to the second nominal memory cells along the first transverse direction. Claim 5 A semiconductor device according to claim 4, wherein the second reference memory cells are arranged along a first edge of the first memory array extending in a second transverse direction perpendicular to the first transverse direction, and the fourth reference memory cells are arranged along a second edge of the second memory array extending in the second transverse direction. Claim 6 A semiconductor device according to claim 1, wherein the plurality of control signals include a first control signal and a second control signal. Claim 7 A semiconductor device according to claim 6, wherein when both the first control signal and the second control signal are provided in a first logic state, the controller is configured to cause the I / O circuit to retrieve the reference signal from one of the third reference memory cells. Claim 8 A semiconductor device comprises: a first memory array including a plurality of first memory cells each configured to store a first data bit based on a first variable resistor, a plurality of second memory cells each configured to store a first reference resistor, and a plurality of third memory cells each configured to store a second reference resistor; a second memory array including a plurality of fourth memory cells each configured to store a second data bit based on a second variable resistor, a plurality of fifth memory cells each configured to store a third reference resistor, and a plurality of sixth memory cells each configured to store a fourth reference resistor; and a controller, wherein the controller comprises: Receiving multiple control signals; A semiconductor device configured to, based on a logical combination of the plurality of control signals, (i) select one of the third reference resistor, the fourth reference resistor, and the second data bit to compare with the first data bit, or (ii) select one of the first reference resistor, the second reference resistor, and the first data bit to compare with the second data bit. Claim 9 A semiconductor device according to claim 8, wherein when both the first control signal and the second control signal among the control signals are provided in a first logic state, the controller is configured to cause the sensing amplifier to retrieve the second reference resistor to be compared with the second data bit or the fourth reference resistor to be compared with the first data bit. Claim 10 In a method, the method comprises the step of receiving at least a first control signal and a second control signal, wherein the logical combination of the first control signal and the second control signal is configured to select one of at least a first reference scheme, a second reference scheme, and a third reference scheme; the step of comparing a first reference signal provided by one of the first reference memory cells among the first reference memory cells with a first data signal provided by one of the second nominal memory cells among the second nominal memory cells, by activating one of the first reference memory cells among the plurality of first reference memory cells of the first memory array and one of the second nominal memory cells among the plurality of second nominal memory cells of the second memory array based on a first logical combination among the logical combinations corresponding to the first reference scheme; and, based on a second logical combination among the logical combinations corresponding to the second reference scheme, one of the second reference memory cells among the plurality of second reference memory cells of the first memory array and another second nominal memory cell among the plurality of second nominal memory cells of the second memory array A method comprising: a step of comparing a second reference signal provided by one of the second reference memory cells with a second data signal provided by another of the second nominal memory cells by activating them; and a step of comparing a third data signal provided by one of the first nominal memory cells with a fourth data signal provided by another of the second nominal memory cells by activating one of the first nominal memory cells of the first memory array and another of the second nominal memory cells of the second memory array based on a third logic combination among the logic combinations corresponding to the third reference scheme.

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