Chip emulating device, system and method for testing computing device components

Abstract

The present disclosure relates to hardware emulation for testing computing devices, and more specifically, to a chip emulating device designed to emulate an integrated circuit (IC) chip to test the printed circuit board (PCB) and associated components of a target computing device prior to the production of the actual chip. The claimed invention provides a chip emulating device, system, and method for testing computing device components that provide improvements in the technical field of hardware testing and verification by accurately emulating integrated circuit behavior across thermal, electrical, and mechanical domains simultaneously, thereby providing increased test efficiency and accuracy. The proposed invention provides simplification of the development process, shortening of time-to-market, and improvement of overall product quality and reliability in the electronics industry.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application claims the benefit of priority to U.S. Patent Application No. 19 / 177,852, filed April 14, 2025, titled “CHIP EMULATING DEVICE, SYSTEM AND METHOD FOR TESTING COMPUTING DEVICE COMPONENTS,” the entire contents of which are incorporated herein by reference.

[0003] Technology field

[0004] The present disclosure relates to hardware emulation for testing computing devices, and more specifically, to a chip emulating device designed to emulate an integrated circuit (IC) chip to test a printed circuit board (PCB) and associated components of a target computing device before the production of the actual chip. Background Technology

[0005] In today's rapidly changing technological environment, the accelerating pace of innovation has dramatically shortened development schedules across the electronics industry. As market demand calls for faster product launches, the time allocated to various manufacturing stages—encompassing both hardware and software development—is becoming increasingly constrained. This acceleration poses significant challenges for engineers who must verify and test complex electronic components under increasingly tight schedules while still maintaining stringent quality standards and performance requirements.

[0006] Traditional methods for testing printed circuit boards (PCBs) and associated components often involve waiting until the actual integrated circuit (IC) chip is manufactured to perform a comprehensive system-level evaluation. This approach can lead to delays in the product development cycle and increased costs if issues are discovered late in the process. While various emulation techniques exist to test the thermal, electrical, and mechanical aspects of devices under development, these techniques typically treat these aspects individually. This isolated approach fails to provide reliable test results because these aspects are highly interconnected in the final product. Consequently, such fragmented emulation techniques often reveal critical design issues only during final product testing after the actual IC chip has been manufactured, making this the most costly and time-consuming time-consuming stage for corrections.

[0007] In particular, testing the thermal management of electronic systems presents a significant challenge to designers and engineers. As computing devices become more powerful and smaller, managing heat dissipation has become a critical factor in ensuring reliable operation. Accurately predicting and testing the thermal behavior of components and the efficiency of cooling solutions before final assembly can help identify potential issues early in the development process.

[0008] Electrical characteristics of integrated circuits, such as power consumption patterns and transient response, also play a crucial role in overall system performance. Testing the operation of power supplies combined with other components on the PCB of a target computing device is essential for optimizing the design and ensuring compatibility among its various components.

[0009] Furthermore, the mechanical aspects of chip packaging and integration with the PCB can have a significant impact on system reliability. For example, factors such as dimensional compatibility between computing device components required to provide proper thermal coupling with cooling elements, as well as more complex factors like board warping that may occur due to pressure or thermal expansion applied to achieve proper thermal coupling, must be thoroughly evaluated during the testing phase.

[0010] Therefore, there is a demand for chip emulation technology that can provide improvements in the technical field of hardware testing and verification. Specifically, there is a demand for solutions that can accurately emulate integrated circuit behavior across thermal, electrical, and mechanical domains simultaneously, thereby providing increased efficiency and accuracy in operation readiness testing. Such solutions will streamline the development process in the electronics industry, shorten time-to-market, and improve overall product quality and reliability. Furthermore, this represents a demand for test systems and methods that include such improved chip emulation capabilities, which advance the aforementioned technical field by enabling more thorough verification of thermal, electrical, and mechanical compatibility across different electronic components of computing devices before final production. Specifically, this provides improved accuracy and reliability when identifying potential problems in the target computing device design, thereby allowing problems to be resolved early in the development cycle with lower modification costs and less modification time.

[0011] To address the aforementioned requirements, the following is proposed.

[0012] According to one aspect of the present disclosure, a chip emulating device for testing a component of a computing device is provided. The chip emulating device may include: a first substrate board configured to be assembled to a target footprint located on a printed circuit board (PCB) of the computing device—the footprint being configured to provide an operable connection between the target chip and the PCB—and a die emulating element operablely connected to the first substrate board—the die emulating element comprising one or more heating elements designed to emulate the thermal behavior of the die of the target chip or at least one component thereof, taking into account predefined power parameters of the computing device when the chip emulating device is assembled on the PCB and power is supplied through it.

[0013] According to another aspect of the present disclosure, a system for testing a component of a computing device is provided. The system may include a printed circuit board (PCB) of the computing device—the PCB comprises a target footprint configured to provide operable connections of a power supply module and a target chip—and a chip emulating device. The chip emulating device may include a first substrate board operablely connected to the PCB through the target footprint; a die emulating element operablely connected to the first substrate board—the die emulating element comprises one or more heating elements designed to emulate the thermal behavior of a die of the target chip or at least one component thereof, taking into account predefined power parameters of the power supply module—and a microcontroller operablely connected to one or more heating elements and configured to control the power consumption thereof, wherein the one or more heating elements are powered by the power supply module.

[0014] According to another aspect of the present disclosure, a method for testing a component of a computing device is provided. The method may include the step of controlling the power consumption of one or more heating elements by operating a microcontroller operably connected thereto when power is supplied through a printed circuit board (PCB) of the computing device, wherein the one or more heating elements are designed to emulate the electrical and thermal behavior of a die of a target chip or at least one component thereof in consideration of predefined power parameters of the computing device, and the microcontroller and the one or more heating elements are assembled on a board operably connected to the PCB through a target footprint configured to provide an operable connection between the target chip and the PCB. The method comprises the step of measuring one or more thermal and electrical parameters of the computing device using one or more sensors; and, through a user interface module, (i) indicating one or more defects in the operation of the computing device based on the one or more measured thermal and electrical parameters; and (ii) may further include the step of providing a suggestion for one or more corrective measures to correct one or more defects based on one or more measured thermal and electrical parameters.

[0015] In some embodiments, the one or more heating elements are further designed to emulate the electrical behavior of a target chip or at least one component thereof, taking into account the power parameters of the computing device.

[0016] In some embodiments, (i) a first substrate board; and (ii) at least one of the die emulating elements is further configured to exhibit deformation characteristics substantially similar to (a) the substrate board of the target chip; and (b) the die of the target chip, respectively, under pressure.

[0017] In some embodiments, the chip emulating device may further include one or more thermal sensors configured to measure the temperature of each of the one or more heating elements; and a microcontroller operably connected to the one or more heating elements and the one or more thermal sensors. The microcontroller may further be configured to control the power consumption of the one or more heating elements; receive the measured temperature of the one or more heating elements from the one or more thermal sensors; and output the measured temperature of the one or more heating elements to a user interface module so as to be provided through a user interface.

[0018] In some embodiments, the one or more heating elements may be positioned on the upper side of the die emulating element, and the one or more heat sensors may each be positioned on the lower side of the die emulating element opposite the one or more heating elements.

[0019] In some embodiments, the first substrate board may have a pinout compatible with the dimensions of the substrate board of the target chip and the target footprint, and the die emulating element may include a second substrate board sized according to the dimensions of the die of the target chip. Each of the one or more heating elements may include a conductive trace formed on the surface of the second substrate board to substantially cover an area on the surface of the second substrate board corresponding to an area of ​​each component of the die of the target chip.

[0020] In some embodiments, the conductive trace may be dimensioned to operate at substantially the same power and thermal density as the expected power and thermal density of each component of the die, respectively, in a predefined operating mode of the target chip, taking into account the predefined power parameters of the computing device.

[0021] In some embodiments, the conductive trace is formed to have at least one of a zigzag shape and a spiral shape characterized by length, width, and height, so as to provide a power density substantially equal to the expected power density of each component of the die in a predefined operating mode of the target chip, taking into account predefined power parameters of the computing device.

[0022] In some embodiments, the die emulating element may be configured to operate with substantially the same power consumption as the expected power consumption of the target chip in a predefined operating mode of the target chip, taking into account predefined power parameters of the computing device.

[0023] In some embodiments, the predefined operating mode of the target chip may require its maximum performance.

[0024] In some embodiments, the microcontroller may be further configured to operate the one or more heating elements to simulate various operation scenarios of a target chip or a component thereof, and the operation scenarios include at least one of: (i) toggling the one or more heating elements in a predefined pattern to test the transient response of a power supply module of a computing device; and (ii) keeping the one or more heating elements active for a predefined period to test the DC power delivery stability and heat dissipation of the computing device.

[0025] In some embodiments, the chip emulating device may further include a structural reinforcing ring attached to a peripheral area of ​​the first substrate board and extending along it.

[0026] In some embodiments, the one or more heating elements may be further designed to emulate the electrical behavior of a target chip or at least one component thereof, taking into account predefined power parameters of a power supply module.

[0027] In some embodiments, the PCB may further include one or more peripheral electronic components assembled thereon. The system may further include: (i) one or more peripheral electronic components; and (ii) electrical test means configured to measure one or more electrical parameters of at least one of the power supply modules; and a user interface module operably connected to the electrical test means and configured to provide a visual interface indicating one or more defects in the operation of each of the one or more peripheral electronic components and the power supply module based on the measured one or more electrical parameters.

[0028] In some embodiments, the system may further include one or more thermal sensors configured to measure the temperature of at least one of (i) a chip emulating device; (ii) one or more peripheral electronic components; and (iii) a power supply module. The system may further include at least one heat sink configured to be thermally coupled to at least one of (i) a chip emulating device; (ii) one or more peripheral electronic components; and (iii) a power supply module and to dissipate heat from it. The system may further include a user interface module operably connected to one or more thermal sensors and configured to provide a visual interface indicating one or more heat dissipation defects based on the measured temperature.

[0029] In some embodiments, the one or more thermal sensors may include one or more thermal sensors operably connected to a microcontroller and configured to measure the temperature of each of the one or more heating elements. The microcontroller may be further configured to receive the measured temperature of the one or more heating elements from the one or more thermal sensors; and to output the measured temperature of the one or more heating elements to a user interface module. The user interface may be configured to indicate the one or more heat dissipation defects based further on the measured temperature of the one or more heating elements.

[0030] In some embodiments, the user interface module may be operably connected to a microcontroller and may be further configured to operate the one or more heating elements through the microcontroller to simulate various operation scenarios of a target chip or its components, and the operation scenarios include at least one of: (i) toggling the one or more heating elements in a predefined pattern to test the transient response of the power supply module; and (ii) keeping the one or more heating elements active for a predefined period to test the direct current (DC) power delivery stability and heat dissipation of the computing device. Brief explanation of the drawing

[0031] The subject matter considered to be the invention is specifically identified and explicitly claimed in the last part of this specification. However, the invention is best understood when read in conjunction with the following accompanying drawings and with reference to the following detailed description, with respect to both the method of operation and the organization, along with its purpose, features, and benefits. FIG. 1 is an isometric view of a printed circuit board (PCB) of a computing device to which a chip emulating device according to some embodiment of the present invention is operably connected. FIG. 2 is a block diagram of a system for testing components of a computing device according to some embodiments of the present invention. FIG. 3a is a top view of a die emulating element (a first (upper) layer of a second substrate board) of a chip emulating device according to some embodiment of the present invention. FIG. 3b is an enlarged top view of a die emulating element (left upper corner of the first (upper) layer of the second substrate board) according to some embodiment of the present invention. FIG. 3c is a top view of a die emulating element (second layer of the second substrate board) according to some embodiment of the present invention. FIG. 3d is an enlarged top view of a die emulating element (the upper left corner of the second layer of the second substrate board) according to some embodiment of the present invention. FIG. 3e is a top view of a die emulating element (the third layer of the second substrate board) according to some embodiment of the present invention. FIG. 3f is an enlarged top view of a die emulating element (the upper left corner of the third layer of the second substrate board) according to some embodiment of the present invention. FIG. 3g is a top view of a die emulating element (the fourth layer of the second substrate board) according to some embodiment of the present invention. FIG. 3h is an enlarged top view of a die emulating element (the upper left corner of the fourth layer of the second substrate board) according to some embodiment of the present invention. FIG. 3i is a top view of a die emulating element (the fifth layer of the second substrate board) according to some embodiment of the present invention. FIG. 3j is a top view of a die emulating element (the sixth layer of the second substrate board) according to some embodiment of the present invention. FIG. 3k is an example of an essential aspect of an interlayer connection between one or more heating elements and one or more thermal sensors according to some embodiments of the present invention. FIG. 31 is a table showing specifications for various drills illustrated in FIG. 3a to FIG. 3k according to some embodiments of the present invention. FIG. 4a is a top view of a first substrate board (first layer) of a chip emulating device according to some embodiment of the present invention. FIG. 4b is a top view of a first substrate board (second layer) of a chip emulating device according to some embodiment of the present invention. FIG. 4c is a top view of a first substrate board (third layer) of a chip emulating device according to some embodiment of the present invention. FIG. 4d is a top view of a first substrate board (fourth layer) of a chip emulating device according to some embodiment of the present invention. FIG. 4e is a top view of a first substrate board (fifth layer) of a chip emulating device according to some embodiment of the present invention. FIG. 4f is a top view of a first substrate board (sixth layer) of a chip emulating device according to some embodiment of the present invention. FIG. 4g is a table showing specifications for various drills shown in FIG. 4a to 4f according to some embodiments of the present invention and a layer stack-up of a first substrate board. FIG. 5 is a flowchart illustrating a method for testing a component of a computing device according to some embodiments of the present invention. For the sake of simplicity and clarity of the example, it will be understood that the elements depicted in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to others for clarity. Additionally, where deemed appropriate, reference numbers may be repeated between drawings to indicate corresponding or similar elements. Specific details for implementing the invention

[0032] Those skilled in the art will recognize that the present invention may be embodied in other specific forms without departing from the spirit or essential nature thereof. Accordingly, the foregoing embodiments should be regarded as illustrative rather than limiting the invention described herein in all respects. Accordingly, the scope of the invention is defined by the appended claims rather than by the foregoing description, and thus all modifications within the scope of the meaning and equivalence of the claims are intended to be accommodated herein.

[0033] In the following detailed description, numerous specific details are presented to provide a thorough understanding of the invention. However, those skilled in the art will understand that the invention may be practiced without these specific details. In other cases, well-known methods, procedures, and components are not described in detail so as not to obscure the invention. Some features or elements described in connection with one embodiment may be combined with features or elements described in connection with another embodiment. For clarity, discussions of identical or similar features or elements may not be repeated.

[0034] Although embodiments of the present invention are not limited in this regard, the terms “plurality” and “a plurality” as used herein may include, for example, “multiple” or “two or more.” The term “plurality” may be used throughout this specification to describe two or more components, devices, elements, units, parameters, etc. The term “set” may include one or more items as used herein.

[0035] As used herein, the terms “printed circuit board (PCB)” and “substrate board” are interchangeable in terms of material composition and functional characteristics, but are distinguished to clearly identify distinct components. As is known in the art, “printed circuit board” generally refers to a stacked sandwich structure of conductive and insulating layers comprising patterns of traces, planes, and other features etched from one or more copper sheet layers laminated on or between sheet layers of non-conductive substrates. Accordingly, as used herein, the terms “printed circuit board,” “PCB,” and “substrate board” (including the “first” substrate board and the “second” substrate board) may refer to the same type of object. In this invention, different terms are used solely to clearly distinguish different elements within the context of the invention.

[0036] It should be further understood that the terms "first" and "second" are used solely to clearly distinguish elements and do not imply any specific order or sequence unless explicitly stated otherwise.

[0037] As used herein, the term “computing device” refers to any device comprising a chip (integrated circuit (IC)) as a main processing or control component when manufactured and assembled. This chip is operably connected to a printed circuit board (PCB) of the “computing device,” and the PCB may include various peripheral electronic components that support the operation of the IC. Furthermore, although referred to herein as a “computing device,” it should be more clear that pre-production testing of this device proposed herein is performed using a chip emulating device instead without the computing component (target chip).

[0038] As used herein, the terms “integrated circuit,” “IC,” “chip,” and similar terms refer to the same type of component and may be used interchangeably. In some embodiments, the IC may be a System on Chip (SoC), Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuit (ASIC), Application-Specific Standard Product (ASSP), or a similar electronic component. Such ICs may perform data processing, memory storage, signal processing, or other functions known in the art.

[0039] Although the present disclosure primarily refers to "pre-production testing" or "testing for operational readiness," it should be further understood that the same techniques proposed herein may be applied to performing tests at other stages, including post-production testing and debugging. Accordingly, the scope of the invention should not be construed as being limited in this regard.

[0040] Unless explicitly stated otherwise, the method embodiments described herein are not limited to a specific order or sequence. Additionally, some of the described method embodiments or elements thereof may occur simultaneously, at the same time, together, or repeatedly.

[0041] The present disclosure addresses the aforementioned requirements and resolves the problems of the prior art by providing a chip emulating device, system, and method for testing components of a computing device. Such a solution can simultaneously provide comprehensive and accurate emulation of integrated circuit behavior across thermal, electrical, and mechanical domains.

[0042] As is known in the industry, a chip typically comprises several key components, including a substrate board and a die.

[0043] In chip design, the substrate board, also known as the package substrate, performs several important functions. It ensures the structural integrity of the assembly by providing mechanical supports for mounting the semiconductor die. Additionally, it provides power and signal communication to the chip by facilitating electrical connections between the chip and external circuitry through a network of conductive traces and vias.

[0044] The die is a critical component that ultimately contains the actual integrated circuit. It is a small block of semiconductor material, typically silicon, from which the functional circuit is fabricated. The die accommodates transistors, capacitors, resistors, and other electronic components that perform the chip's intended functions, such as data processing, memory storage, signal processing, and power management. Once fabricated, the die is mounted onto a substrate board, where it is electrically connected to the external circuit via bonding wires or solder balls.

[0045] As proposed herein, a chip emulating device comprises a first board configured to be assembled on a target footprint of a printed circuit board (PCB) of a computing device. In the context of this disclosure, the “target” footprint should be understood to refer to a footprint on the PCB of a computing device designed to provide an operable connection between the target chip and the PCB (i.e., having the necessary pinout, dimensions, etc.). This configuration enables the chip emulating device to interface with the PCB in a manner similar to the target chip, thereby providing a realistic test environment.

[0046] As further proposed herein, the chip emulating device may further include a die emulating element operably connected to a first substrate board, similar to how an actual die is connected to a substrate board of a target chip. As further proposed, the die emulating element includes one or more heating elements. These heating elements are designed to emulate the thermal behavior of the die of the target chip or at least one component thereof, taking into account predefined power parameters of the computing device (when the chip emulating device is assembled on a PCB and power is supplied therethrough).

[0047] Furthermore, as is understood, by being configured to provide thermal emulation of a target chip in consideration of predefined power parameters of a computing device, the chip emulating device also essentially provides electrical emulation thereof, at least in some respects. For example, in some embodiments, as further described in more detail, a die emulating element may be configured to operate with substantially the same power consumption as the expected power consumption of the target chip in a predefined mode of operation of the target chip, in consideration of predefined power parameters of the computing device. Specifically, the thermal element may be designed to emulate the electrical behavior of the actual die of the target chip or its components, for example, to exhibit the same power consumption and the same power and thermal density as the die or its components, respectively.

[0048] These capabilities enable simultaneous thermal and electrical testing without the need for the actual target chip to be manufactured, thereby providing a more comprehensive evaluation of computing device performance. Furthermore, according to some embodiments of the present invention, by having dimensions and positioning identical (or substantially similar) to the target chip, the chip emulating device enables thermal management testing and evaluation of heat dissipation elements (e.g., heat sinks, cold plates, liquid cooling assemblies, etc.) in a pre-production stage where the target chip has not yet been manufactured. Since the thermal, electrical, and mechanical aspects of the chip design (e.g., dimensions, positioning, etc.) as well as the design of the entire computing device are deeply interrelated, hidden design problems may arise in the final product due to these interrelatedities. Therefore, as further described in more detail, the ability to provide simultaneous thermal, electrical, and mechanical emulation offers technical synergies that significantly improve upon conventional solutions. Accordingly, the disclosed solution can provide improved accuracy and reliability in identifying potential problems in the design of the target computing device. By emulating the behavior of a target chip across multiple regions simultaneously, the present disclosure provides a more realistic and comprehensive test environment compared to traditional methods that deal with thermal, electrical, and mechanical aspects individually.

[0049] To elaborate on and extend the aforementioned capabilities of the proposed chip emulating device, according to another aspect of the present disclosure, a system for testing components of a computing device is proposed. The system integrates the chip emulating device into a larger test framework. In particular, the system includes a PCB of a computing device comprising a power supply module and a target footprint, together with a chip emulating device assembled thereon. The chip emulating device further includes a microcontroller operably connected to a heat element. The microcontroller controls the power consumption of the heat element while the heat element is powered by the power supply module. This arrangement allows for precise control over the behavior of the emulated chip and enables testing of the performance of the power supply module under various load conditions.

[0050] Finally, according to another aspect of the present disclosure, a method for testing a component of a computing device is proposed. The method utilizes the functions of a chip emulating device and system. This includes the steps of operating a microcontroller to control the power consumption of a heat-generating element, measuring thermal and electrical parameters of the computing device using a sensor, and providing feedback through a user interface module. This feedback includes indicating defects in the operation of the computing device and suggesting corrective measures based on the measured parameters. This comprehensive approach enables the early detection and resolution of problems in the design of the computing device.

[0051] By providing such solutions, the present disclosure addresses the need for more efficient and accurate testing methods in the rapidly changing electronics industry. Chip emulating devices, systems, and methods enable thorough verification of thermal, electrical, and mechanical compatibility across different electronic components of computing devices before final production. This approach can significantly reduce development time and costs by enabling the identification and resolution of potential problems early in the development cycle, which is less costly and time-consuming to fix.

[0052] In some embodiments, chip emulating devices and systems may incorporate additional features (described in further detail below) that further enhance test capabilities. These may include thermal sensors for precise temperature measurement, conductive traces specifically designed to accurately emulate the power and thermal density of specific chip components, and the ability to simulate various operating scenarios. These features allow for much more detailed and accurate testing of the performance of computing devices under different operating conditions, thereby further improving the relevant technical field.

[0053] Overall, the present disclosure provides a comprehensive solution to the challenges faced in hardware testing and verification, potentially streamlining the development process in the electronics industry, shortening time to market, and improving overall product quality and reliability.

[0054] Now, refer to FIG. 1, which illustrates an isometric view of a printed circuit board (PCB) (210) of a computing device (200) to which a chip emulating device (100) according to some embodiment of the present invention is operably connected.

[0055] For clarity and brevity, the following description may relate in some respects only to a chip emulating device (e.g., chip emulating device (100)). However, it should be understood that the same principles and descriptions may apply equally to the proposed system (e.g., system (10) illustrated in FIG. 2), as the proposed system may include a chip emulating device in all embodiments discussed herein.

[0056] Furthermore, for clarity and brevity, descriptions of similar or identical components illustrated in the provided drawings may be omitted.

[0057] As illustrated in FIG. 1, in some embodiments, the computing device (200) may include a PCB (210) designed to be operably connected to a target chip (not shown) through a target footprint (not shown), and may include a power supply unit (211) (also referred to herein as a “power supply module”) or additionally mount a plurality of peripheral electronic components (212) thereon. The power supply module (211) may be configured to supply power to the target chip and peripheral components (211) through conductive traces of the PCB (210), as required and defined by the design of the computing device (200).

[0058] A PCB (210) is typically composed of a non-conductive substrate made of glass fiber, composite epoxy, or other laminated material, on which conductive paths are etched or printed. These paths, often made of copper, enable electrical connections between electrical components installed thereon.

[0059] It should be understood that the described configuration of the PCB (210) is provided only as a non-exclusive example. Different, completely different designs and layouts may be used depending on the specific application of the computing device (200). FIG. 1 further illustrates a chip emulating device (100). The chip emulating device (100) may include a substrate board (110) (also referred to herein as the “first” substrate board) operably connected to the PCB (210) via a target footprint (designed for connection with the original target chip). The chip emulating device (100) may further include a die emulating element (120) operably connected to the substrate board (110). In some embodiments, the dimensions and relative positioning of the die emulating element (120) and the substrate board (110) may be the same (or substantially similar) as the dimensions and relative positioning of the die of the target chip and the substrate board. This ensures reliable emulation and allows testing of additional components of the computing device (200), such as a cooling assembly (not shown).

[0060] The die emulating element (100) may include one or more heating elements (122) further designed to emulate the thermal behavior of the die of the target chip or at least one component thereof, taking into account the predefined power parameters of the power supply unit (211).

[0061] As is known in the art, the die of a chip may include a number of components integrated into a single piece of semiconductor material. These components may include, but are not limited to, memory units (e.g., high bandwidth memory (HBM)), multiple cores, etc. As can be seen, in some embodiments, the heat element may be designed to individually emulate each component of the die: for example, it may be designed to have the same overall dimensions within the die layout, as well as to exhibit the same power and thermal density as each component of the actual die, taking into account the predefined power parameters of the power supply (211). Such aspects of emulation are described in more detail below.

[0062] As illustrated, the heating element (122) may be positioned on the upper side of the die emulating element (120). The substrate board (110) may have a pinout compatible with the dimensions of the substrate board (not illustrated) of the target chip and the target footprint. In some embodiments, the die emulating element (120) may include a substrate board (121) (also referred to herein as a “second” substrate board) sized according to the dimensions of the die of the target chip.

[0063] In some embodiments, each heating element (122) may be or may include a conductive trace formed on the surface of the substrate board (121) to substantially cover an area on the surface of the substrate board (121) corresponding to an area of ​​each component of the die of the target chip. As illustrated, the conductive trace of the heating element (122) may be formed to have a zigzag shape (or alternatively a spiral shape or any other shape covering a specific area).

[0064] In some embodiments, the chip emulating device (100) may further include one or more switches (112) (e.g., field-effect transistors (FETs)) and a microcontroller (111). The microcontroller (111) may be operably connected to a heating element (122) through the switch (112) and may be configured to control the power consumption of one or more heating elements by operating the switch (112).

[0065] In some embodiments, the chip emulating device (100) may further include a structural reinforcement ring (130) attached to a peripheral area of ​​the substrate board (110) and extending along it. As is known in the art, a structural reinforcement ring (e.g., structural reinforcement ring (130)) is a component used in semiconductor packaging to improve the mechanical stability of a package, and in the proposed invention, it may be applied to a substrate board (110) on which a die emulating element (120) is assembled. It is typically attached to the surface of the package substrate (e.g., substrate board (110)) and helps to reduce warping that may occur due to differences in thermal expansion between various materials within the package. By providing additional support, the reinforcement ring (130) ensures that the package of the chip emulating device (100) maintains its structural integrity, thereby improving the reliability and performance of the electronic components housed inside. By adding rigidity to the package, the reinforcing ring (130) improves the overall co-planarity of the chip emulating device (100) with respect to the PCB (210). Since distortion of the substrate board (110) or the die emulating element (120) can significantly affect the heat dissipation provided by the cooling means under test, thereby reducing the reliability of the test results, this can be very important for the emulation mode.

[0066] Now, refer to FIG. 2, which is a block diagram of a system (10) for testing components of a computing device (200) according to some embodiments of the present invention.

[0067] In some embodiments, the system (10) may be implemented as a combination of hardware and software modules. Furthermore, the system (10) may be configured to execute one or more instruction code modules (e.g., memory of the microcontroller (111), stored in the user interface module (400) (further described in detail)) to request, receive, analyze, calculate, and generate various data. As further described herein in detail, the system (10) may be configured to execute one or more instruction code modules to perform the steps of the claimed method.

[0068] As illustrated in FIG. 2, arrows may indicate the flow of one or more data elements to and from the system (10) and / or between modules or elements of the system (100). Some arrows have been omitted for clarity.

[0069] As illustrated in FIG. 2 and as described above with reference to FIG. 1, the computing device (200) may include a PCB (210). The PCB (210) may include various peripheral electronic components (212) and a power supply module (211). The system (100) may further include a chip emulating device (100). The PCB (210) may be operablely connected to the chip emulating device (100) through a target footprint (a footprint configured to provide operable connections between the target chip (not shown) and the PCB). The chip emulating device (100) and peripheral components may be configured to be powered by the power supply module (211) through the PCB (210). The chip emulating device (100) may include a substrate board (110) on which a die emulating element (120) is assembled.

[0070] A substrate board (110) can be assembled on a target footprint. A die emulating element (120) can be operably connected to the substrate board (110) and may include a heating element (122) designed to emulate the thermal behavior of a die of a target chip or at least one component thereof, taking into account predefined power parameters of a computing device (200) (power supply module (211)) when the chip emulating device (110) is powered by a power supply module (211) through a PCB (210).

[0071] In some embodiments, the heating element (122) may be further designed to emulate the electrical behavior of the die of the target chip or at least one component thereof, taking into account the power parameters of the computing device (200) (e.g., power supply module (211)), and may be designed to provide the same power consumption and power density as, for example, the die of the target chip or the component of the die of the target chip.

[0072] In some embodiments, the chip emulating device (100) may further include one or more thermal sensors (123) configured to measure the temperature of each heating element (122). In some embodiments, the thermal sensors (123) may be assembled on a substrate board (121).

[0073] In some embodiments, the chip emulating device (100) may further include one or more microcontrollers (111) operably connected to a heating element (122) and a thermal sensor (123). The microcontrollers (111) may be assembled on a substrate board (110) (as shown in FIG. 1). In some embodiments, the microcontrollers (111) may store program instructions, and when executed, the microcontrollers (111) may be configured to control the power consumption of the heating element (122) (e.g., by operating a switch (112)) and receive temperature measurements from the sensor (123) that can be used for further analysis.

[0074] In some embodiments, the system (10) may further include an electrical test means (300). The electrical test means (300) may be configured to measure one or more electrical parameters of one or more peripheral electronic components (212) and / or electrical parameters of a power supply module. Electrical parameters may include, for example, voltage stability, voltage transient response, power efficiency, voltage ripple level, power rail noise spectrum, etc. Common examples of such test means include oscilloscopes, spectrum analyzers, ammeters, voltmeters, etc., which are widely used in PCB and chip design to ensure proper functionality and connectivity of components.

[0075] In some embodiments, the system (10) may further include a user interface module (400) configured to provide a visual interface that is operably connected to an electrical test means (300) and indicates one or more defects (defect indication (402A)) in the operation of each of one or more peripheral electronic components (212) and a power supply module (211) based on one or more measured electrical parameters measured by the electrical test means (300). The user interface module (400) may further be configured to provide suggestions (403A) for one or more corrective measures to correct the one or more defects (for example, an unwanted transient response may be formed in a specific segment of the electrical circuit of the PCB (210) during the test, and the corrective measure to correct this defect may be a suggestion to correct the control loop). The user interface module (400) may include a graphic display or a touchscreen for visually presenting test results and diagnostic information. For example, a touchscreen interface can display real-time data and warnings (defect indication (402A)) to enable a technician to quickly identify and resolve problems in the design of the PCB (210).

[0076] In some embodiments, the microcontroller (111) may be further configured to operate a heating element (122) to simulate various operation scenarios of the target chip or its components (e.g., components of the die described above). In some embodiments, the simulation of the operation scenarios may be activated and monitored using a user interface module (400) which is operably connected to the microcontroller (111) and configured to operate the heating element (122) through the microcontroller (111) to simulate the scenarios (e.g., the module (400) may output an operation scenario (401A) and upload it to the microcontroller (111), and the microcontroller (111) may be configured to operate a switch (112) to simulate the uploaded scenario (401A).

[0077] Operation scenarios may include, for example, (i) toggling the heating element (122) in a predefined pattern (e.g., via a switch (112)) to test the transient response of the power supply module (211) of the computing device (200); and (ii) keeping the heating element (122) active for a predefined period to test the stability of direct current (DC) power delivery.

[0078] To test the transient response, an electrical test means (300), specifically an oscilloscope, may be connected to the output of the power supply module (211). Then, the chip emulating device (100) assembled on the PCB (210) may be operated via a microcontroller (111) to simulate an operation scenario (401A) by toggling a heating element (122), for example, in a predefined pattern (for example, via a switch (112)).

[0079] A predefined pattern may include transitioning between a state where only one heating element (122) is active (e.g., a heating element (122') is responsible for emulating the first core of the die of the target chip) and a state where multiple heating elements (122) are active (e.g., a heating element (122') is responsible for emulating both the first and second cores of the die of the target chip). This may also include transitioning from a state where all heating elements (122) are inactive to a state where all heating elements (122) are active.

[0080] While toggling the heating element (122), voltage fluctuations can be determined using an oscilloscope as a function of the instantaneous current switching. Specifically, the transient response can be determined by voltage fluctuations resulting from the instantaneous current fluctuations, for example, by measuring the voltage during or immediately after the current transient.

[0081] The goal of the design is to have a power supply that provides a sufficiently stable voltage in all operating scenarios. However, in practice, the output voltage of the power supply module (211) can drop significantly in response to sudden changes in current. In a transient response test, the voltage drop can be evaluated in relation to a predefined threshold corresponding to the minimum voltage level required for normal operation of the target chip and other PCB (210) components.

[0082] If the voltage drops below a threshold during the test, the user interface module (400) may indicate that there is a problem with the transient response of the power supply (211) (e.g., a fault indication (402A)) and suggest changing the power supply module (211) to a more powerful one (e.g., a suggestion (403A)).

[0083] As shown above, the system (10) can be configured to test the performance of a thermal management component (e.g., a heat sink, a cold plate, a liquid cooling component, etc.).

[0084] To perform a thermal management test, in some embodiments, the operation scenario may further include keeping the heat element (122) active for a predefined period to test heat dissipation from (a) a chip emulating device (100), specifically the heat element (122); (b) a power supply module (211); and (c) one or more peripheral components (212).

[0085] In some embodiments, the system (10) may further include one or more thermal sensors configured to measure the temperature of at least one of (i) a chip emulating device (100) (e.g., sensor (123)); (ii) one or more peripheral electronic components (212); and (iii) a power supply module (211). A user interface module (400) may be operably connected to the thermal sensor (e.g., sensor (123)) and configured to provide a visual interface that indicates one or more thermal dissipation defects (defect indicator (402A)) based on the measured temperature. Additionally, the user interface module (400) may provide suggestions (403A) for correcting thermal management defects, such as applying a more powerful thermal management system, adjusting the positioning of cooling elements, or using different thermal pads / pastes.

[0086] Specifically, in some embodiments, the microcontroller (111) may be operably connected to a heat sensor (123) and configured to receive the measured temperature of the heating element (122) from it. The microcontroller (111) may be further configured to output the measured temperature of the heating element (122) to a user interface module (400) so that it is provided through a user interface.

[0087] Accordingly, to perform a thermal management test, the system (10) may further include at least one heat sink configured to be thermally coupled to and dissipate heat from at least one of (i) a chip emulating device (100); (ii) one or more peripheral electronic components (212); and (iii) a power supply module (211). Accordingly, a temperature and a heat dissipation fault indicator (indicator (402A)) may indicate the performance of the heat sink under test. The heat dissipation fault indicator may provide a warning, for example, when the measured temperature exceeds a specific predefined threshold (the system (10) may have different thresholds for different thermal sensors depending on the thermal regime requirements of each electronic component).

[0088] According to the present invention, it should be understood that various known types of thermal sensors may be used for thermal management testing. The thermal sensor (123) may be a semiconductor-based thermal sensor or may include one. Additionally or alternatively, an infrared (IR) thermal sensor and / or a thermal camera may be used herein. The user interface module (400) may output temperature measurements in the form of numerical values, charts and / or tables with heat maps.

[0089] It should be understood that the proposed design of a chip emulating device (100) having a heating element (122), a thermal sensor (123), a switch (112), and a microcontroller (111) integrated into a single module provides additional advantages and improvements to the relevant technical field, as it represents a complete solution in which the chip emulating device (100) can be used with different PCBs as well as different design versions of the same PCB (e.g., PCB (210)). For example, when a defect is revealed in the design of the PCB (210) using the proposed system (10), the chip emulating device (100) can be separated from the PCB (210), the defect can be corrected, and then the corrected version of the PCB (210) can be tested with the same chip emulating device (100), thereby providing a convenient and cost-effective debugging process.

[0090] Now, referring to FIGS. 3a through 3k, FIGS. 3a through 3k illustrate various drawings of a die emulating element (120) of a chip emulating device (100) according to some embodiments of the present invention, and FIG. 3l provides a table with a drill chart for specifications for the drills illustrated in FIGS. 3a through 3k.

[0091] It should be understood that the configuration of the chip emulating device (100) illustrated in FIGS. 3a through 3k (die emulating element (120)) and FIGS. 4a through 4g (substrate board (110)) is for illustrative purposes only and should not be considered exclusive in any respect. While the demonstrated design is intended to emulate a target chip of a specific configuration, it should be further understood that the invention is not limited to the configuration of the target chip and that other completely different chip configurations can be successfully emulated using the proposed technology.

[0092] FIG. 3a shows a top view of a die emulating element (120) (a first layer of a substrate board (121)) according to some embodiment of the present invention.

[0093] In the illustrated case, the die emulating element (120) includes a plurality of heat-generating elements configured to emulate different components of the die of the target chip. As mentioned above, each of the heat-generating elements (122) may include a conductive trace formed on the surface of the substrate board (121) so as to substantially cover an area on the surface of the substrate board (121) corresponding to the area of ​​each component of the die of the target chip. For example, the target chip may include two cores, and each core may be emulated by a respective group of conductive traces (122) (a first group of conductive traces (122') shown above, and a second group of conductive traces (122') shown below). The target chip may further include eight memory modules, and each of these memory modules may be emulated using a conductive trace (122''). The die emulating element (110) may further include a conductive trace (122''') configured to emulate other high-power locations inside the die of the target chip.

[0094] To provide thermal and electrical emulation of the components of the target chip (e.g., core, memory module), in some embodiments, the conductive traces (122', 122'', and 122''') may be dimensioned to operate with substantially the same power and thermal density as the expected power and thermal density of each component of the target chip's die (each core, memory module, and other high-power locations within the die) in a predefined operating mode of the target chip, taking into account the predefined power parameters of the computing device (200) (i.e., power supply module (211)).

[0095] Specifically, in some embodiments, it is proposed that the conductive traces (122', 122'' and 122''') in the present invention be formed to have a zigzag shape characterized by length, width and height, so as to provide a power density substantially equal to the expected power density of each component of the die of the target chip (each core, memory module and other high-power locations within the die) in a predefined operating mode of the target chip, for example, taking into account predefined power parameters of the computing device (200) (i.e., power supply module (211)).

[0096] It should be understood that the zigzag shape represents one of the possible embodiments, and that other shapes may be used to cover the area on the top surface of the substrate board (121) that is the same as the area of ​​each component of the die of the target chip. For example, alternatively, a spiral shape may be used, or in another alternative embodiment, dots of each size connected to a conductive trace may be used.

[0097] Since it is important to test the operation of the components of the computing device (200) under extreme conditions, in some embodiments, the predefined operation mode of the target chip that follows when the die emulating element (120) is designed may be a mode that requires the highest performance of the target chip.

[0098] To design a conductive trace (e.g., conductive traces (122', 122'' and 122''')), the following calculation method may be applied.

[0099] To calculate the dimensions of the target conductive trace of the heating element (122), the electrical parameters of each component of the die of the target chip can be used as input. For example, if the voltage and current through the components of the die are known, the resistance and power of the entire component can be calculated and used as the target parameters that the conductive trace of the heating element (122) should represent.

[0100] Therefore, conductive traces must be designed to match the target resistance while having the same power density (power per unit volume).

[0101] The resistance of a conductive trace can be determined using the following formula.

[0102]

[0103] In the above formula is the resistance of the conductive trace material (e.g., in the case of copper) ) and; is the trace width; is the trace length; is the trace height; is the resistance temperature coefficient of the conductive trace material (e.g., in the case of copper ) and; is the target temperature at which the process is expected to stabilize (i.e., the expected temperature of the conductive trace after a predefined operating period corresponding to the temperature of each component of the die of the target chip (e.g., 60°C)).

[0104] Therefore, using this formula, for example, the expected power density between a conductive trace and a component While matching the resistance value of the conductive trace ( To make ) as close as possible to the target resistance of each component of the die, the dimensions of the conductive trace ( , , You can select ).

[0105] Finally, the die emulating element (120) obtained by having the conductive trace (122', 122'', 122''') designed as described above can be configured to operate with substantially the same power consumption as the expected power consumption of the target chip in a predefined operating mode of the target chip (e.g., a mode requiring maximum performance), taking into account the predefined power parameters of the computing device (200) (e.g., power supply module (211)).

[0106] In the case of mechanical emulation, it should be understood that its accuracy can be critical to the reliability of tests such as thermal management tests. This is because, in high-performance computing applications, the die may have relatively large dimensions (e.g., an area of ​​about 1000 to 2000 mm²) and high power (e.g., up to 1 to 1.2 kW), and thus requirements for mechanical tolerances of the coplanarity and flatness of the top surface, which are determined by the thermal management mode, must be taken into account.

[0107] As is known, for the thermal management of various peripheral electronic components (e.g., component (212)), mechanical tolerances and misalignment of different components can be mitigated using thermal pads. A thermal pad is a soft thermally conductive material (e.g., ceramic or silicon injected with metal particles) used to fill the gap between a heat-generating component and a cooling element. Thus, the thermal pad can provide a conformal interface between irregular surfaces, ensuring good thermal contact along the entire heat dissipation area and reducing thermal resistance.

[0108] Unlike peripheral electronic components, the high power dissipation and large surface area of ​​dies designed for high-performance computing do not allow for the use of thermal pads to relax mechanical tolerances. Therefore, it is common to use thermal paste instead of thermal pads.

[0109] Thermal paste is a high-viscosity, thermally conductive compound typically composed of a polymerizable liquid matrix (e.g., epoxy, silicone) and a large volume fraction of filler (e.g., aluminum oxide, boron nitride, zinc oxide particles) that is electrically insulating but thermally conductive. It is used to fill minute gaps between heat-generating components and cooling elements to ensure efficient heat transfer. Thermal paste excels in applications requiring maximum thermal conductivity and precise application, such as CPU and GPU cooling. Unlike pre-formed, easy-to-apply thermal pads, thermal paste is suitable for very fine surface irregularities, providing superior thermal contact. While thermal pads are suitable for filling larger gaps and uneven surfaces, thermal paste is preferred in high-performance scenarios where a thin, highly conductive layer is essential for effective heat dissipation.

[0110] Therefore, in order to provide a reliable test of the thermal management system operation (e.g., the heat dissipation efficiency of the heat sink and cooling plate of the liquid cooling solution) without a target chip (e.g., during the pre-production stage), it is desirable to provide an accurate emulation of its mechanical mode. Specifically, it is desirable to ensure the desired flatness of the top surface of the die emulating element (120) and to avoid or substantially mitigate its warping under pressure and temperature expansion applied (e.g., from the heat sink or cold plate pressing on the top surface). Even a non-uniformity of 30 microns can cause irregularities in the thermal coupling between the heat dissipation area and the cooling element, which reduces the heat dissipation efficiency and can lead to unreliable or incorrect test results.

[0111] To solve the aforementioned problems, one or more of the following embodiments of the present invention are provided.

[0112] First, as described above, in some embodiments, the chip emulating device (100) may have a substrate board (110) and a die emulating element (120) (particularly, a substrate board (121)) that are sized to have the dimensions of the substrate board and the die of the target chip.

[0113] Second, in some embodiments, as also mentioned above, each of the heating elements (122) may be or may include a conductive trace (e.g., traces (122', 122'' and 122''')) formed on the surface of the substrate board (121) of the die emulating element (120). In this way, the top surface of the substrate board (121) is kept substantially flat so that the heating elements (122) do not protrude much over the surface, thereby maintaining the overall dimensions of the chip emulating device identical to the target chip.

[0114] Third, various modifications to the layout design of the substrate board (110, 121) are proposed in relation to generally known layout design approaches in order to provide not only the necessary flatness of the surface of the substrate board (121) but also the overall rigidity of the chip emulating device (100). In particular, as illustrated in FIGS. 3a to 3g and FIGS. 4a to 4e, it is proposed to perform the layout design and further perform photoetching and etching to provide the necessary electrical insulation by etching only thin copper strips along the sides of each conductive trace, while keeping the free space between the conductive traces (e.g., traces (122', 122'' and 122''')) filled with copper. This approach can help to further remove any existing minor protrusions of the heating element (122) over the surface of the substrate board (121) by ensuring that the top layer has the necessary flatness. In some embodiments, the same design approach may be applied to each layer of the substrate board (121, 110) when the laminated layer undergoes lamination to avoid even minor distortions, thereby providing additional technical improvements by increasing the accuracy of the mechanical emulation.

[0115] Fourth, according to the proposed approach, emulating the thermal and electrical behavior of a real chip designed for high-performance computing applications requires supplying relatively high power (e.g., up to 1.2 kW) to the conductive traces of the heating element (122) located on the upper layer of the substrate board (121). This is not a trivial task for PCB layout design considering the aforementioned requirements for chip packaging emulation. In particular, soldering the substrate board (121) to the substrate board (110) must not affect the overall coplanarity and flatness requirements, that is, after soldering, the top surface of the substrate board (121) must be parallel to the top surface of the substrate board (110), and the solder must not protrude above the top surface of the substrate board (121). To address these requirements, the following is proposed.

[0116] In some embodiments, the substrate board (110) may include a conductive pad (e.g., the pad (113) shown in FIG. 4a) which may be sufficiently large and circular in shape to supply the necessary power without overheating. This conductive pad may be positioned so as to extend along the perimeter (side edge) of the substrate board (121) and align with a boundary line defining the overall dimensions of the board (121). When the board (121) is in the required position relative to the board (110), it may extend partially beyond this boundary line toward the center of the board (121). It should be understood that this required position corresponds to the position of alignment between the substrate board and the die of the target chip.

[0117] The substrate board (121) may consequently include a semicircular via (e.g., via (124) shown in FIG. 3a). As is known in the art, a via is a small hole drilled through a PCB, such as the substrate board (121), to create an electrical connection between different layers of the board (121), and is typically plated with a metal, which is copper. The semicircular via (e.g., via (124)) of the substrate board (121) may be aligned with the conductive pad (e.g., pad (113) shown in FIG. 4a) of the substrate board (110) and positioned directly opposite it when the board (121) is aligned with the board (110), as required for emulation. In this way, the substrate board (121) can be soldered to the substrate board (110) by applying solder to the pad of the board (110) and applying it to the side of the semicircular via (124). This ensures that the substrate board (121) remains parallel to the substrate board (110) to prevent any unwanted misalignment. Additionally, the solder remains below the upper surface of the board (121) to satisfy the aforementioned requirements for emulation, allowing a high current to be supplied to the heating element (122) without overheating. The semicircular via (124) can be filled with a conductive material along its entire length to provide a conductive area of ​​the size required for a proper electrical connection. The semicircular via (e.g., via (124)) may be referred to as a "plated half-hole" or "castelate hole" in some embodiments, as discussed herein, which is a technique known in the art for board-on-board connections.

[0118] Fifth, additionally or alternatively, in some embodiments, at least one of (i) a substrate board (110); and (ii) a die emulating element (120) is further configured to exhibit deformation characteristics substantially similar to (a) the substrate board of the target chip; and (b) the die of the target chip, respectively, under pressure. For example, this can be achieved by using a packaging material for the substrate board (110) and / or the die emulating element (120) having mechanical properties similar to the material of the actual chip. For example, the substrate board (110) may have the same dimensions and number of layers as the substrate board of the target chip, and the die emulating element (120) may have silicon, ceramic, or glass packaging.

[0119] FIG. 3b illustrates an enlarged top view of a die emulating element (120) (left upper corner of the first (top) layer of the second substrate board (121)) according to some embodiment of the present invention. As can be seen, the space between the conductive traces is filled with copper (copper filling (128), also referred to in the art as a "copper pour"), leaving a thinly etched strip along the conductive traces to provide the necessary electrical insulation.

[0120] To manufacture a substrate board (121) having a semicircular drill (124), the board may first be designed to have ends of conductive traces (122', 122'', and 122''') to be connected to a substrate board (110) that extend slightly beyond the full dimensions of the board (121), and the layout may be fabricated on a substrate piece having dimensions larger than those determined by the design of the board (121). After photolithography and etching, a target drill may be fabricated at the required location (124B) (indicated by the symbol 'Z' in FIG. 3a through 3k), similar to the process for a standard fully circular via. Then, the edge of the substrate board (121) may be machined (e.g., along path (124A)) to remove unnecessary substrate material and impart the desired semicircular shape to the drill (124).

[0121] Now, refer to FIG. 3c, which shows a top view of a die emulating element (120) (a second layer of the substrate board (121)) according to some embodiment of the present invention, and FIG. 3d, which is an enlarged top view of a die emulating element (120) (a second upper left corner of the substrate board (121)) according to some embodiment of the present invention.

[0122] In creating a chip emulating device that accurately emulates mechanical, electrical, and thermal aspects, the positioning of a thermal sensor (123) for measuring the temperature of a heat element (122) plays an important role. Specifically, the aforementioned requirement for the flatness of the top surface of the substrate board (121) makes it impossible to position the sensor (123) on the top surface.

[0123] Accordingly, in some embodiments, it is proposed that the heat sensor (123) be positioned on the bottom side of the die emulating element (120) (the bottom side of the substrate board (121)) opposite each heating element (122). Various subtle differences in this positioning are described in more detail below.

[0124] As illustrated in FIGS. 3c and 3d, the second layer of the substrate board (121) may include conductive traces (125) for power and information (signal) communication with each of the thermal sensors (123) (for example, thick conductive traces (125) may be configured for power supply and thin traces (125) may be configured for signal communication). As described above, the free space within the second layer is filled with copper (copper filler (126')) to provide surface flatness.

[0125] FIG. 3e illustrates a top view of a die emulating element (120) (a third layer of a substrate board (121)) according to some embodiment of the present invention, and FIG. 3f is an enlarged top view of a die emulating element (120) (a top left corner of a third layer of a substrate board (121)) according to some embodiment of the present invention.

[0126] As described, the third layer of the substrate board (121) can be used to provide a common electrical ground for connecting the heating element (122) and the sensor (123). As with the previous layers, the layer is filled with copper (copper filler (126'')).

[0127] FIG. 3g illustrates a top view of a die emulating element (120) (a fourth layer of a substrate board (121)) according to some embodiment of the present invention, and FIG. 3h is an enlarged top view of a die emulating element (120) (a top left corner of a fourth layer of a substrate board (121)) according to some embodiment of the present invention.

[0128] As illustrated, the fourth layer of the substrate board (121) can be used to mount a thermal sensor (123). For clarity, only two sensors (123) are illustrated, and for the remaining sensor (123), only the footprint (123A) is illustrated. Each of the sensors (123) may have a thermal sensing pad on the side facing the upper layer, that is, toward the location of each heating element (122). As with the other layers, the empty space may be filled with copper (copper filler (126''')). As a non-exclusive example, the thermal sensor (123) may be a sensor manufactured with an industrial standard LM75 form factor and pinout (corresponding to the design illustrated in FIG. 3a through 3k), and may be, for example, a TMP1075 temperature sensor having I2C and SMBus interfaces.

[0129] FIG. 3i illustrates a top view of a die emulating element (120) (a fifth layer of a substrate board (121)) according to some embodiment of the present invention, and FIG. 3j illustrates a top view of a die emulating element (120) (a sixth layer of a substrate board (121)) according to some embodiment of the present invention.

[0130] Since the provided design requires the positioning of the thermal sensor (123) under the heating element (122) on the opposite side of the substrate board (121), this requires additional adjustments to the design of the substrate board (121). Specifically, to perform board-to-board connections and comply with the requirements of mechanical emulation, the bottom surface of the substrate board (121) must be flat. To this end, it is proposed to fabricate fifth and sixth layers having cutouts (127) at the location of the thermal sensor (123). In this way, these layers can compensate for the height of the sensor (123) and provide a flat bottom layer (with no elements protruding therefrom). In some embodiments, it should be understood that additional layers having the same configuration as the fifth and sixth layers may be used depending on the dimensions of the sensor (123).

[0131] FIG. 3k illustrates an essential aspect of interlayer connection between a heating element (122) and a thermal sensor (123). For clarity and brevity, the essential aspect of the interlayer connection is illustrated with reference to a single heating element (122). To illustrate the interlayer connection, the outline of a conductive trace (122') is also shown on the second, third, and fourth layers of the substrate board (121) (indicated as “Layer II”, “Layer III”, and “Layer IV”, respectively), but the trace (122') itself is located only on the first (top) layer.

[0132] Accordingly, in some embodiments, the conductive trace (122') may be operably connected to each switch (112) (not shown) through a semicircular via (124') to provide an electrical connection to the power supply module (211). At the distal end of the conductive trace (122'), the substrate board (121) may have a set of plated vias (128'') connecting the conductive trace (122') to a common ground within the third and fourth layers (indicated as "Layer III" and "Layer IV", respectively) of the substrate board (121), particularly through the semicircular via (124'').

[0133] As illustrated in the provided example, the heat sensor (123) may have dimensions that are significantly smaller than those of the heating element (122). The actual positioning of the heat sensor (123) relative to the heating element (122) represents another essential consideration of the proposed concept.

[0134] A known semiconductor-based thermal sensor solution that can be used as a sensor (123) has specific power supply requirements, particularly Vcc Pin and GND It has requirements regarding the electrical potential between pins. In some embodiments, Vcc The pin can be powered through a conductive trace (125) within the second layer (indicated as "Layer II") of the substrate board (121). To provide perfect conditions for power supply, GNDThe pin must be connected directly to the common ground or as close as possible (e.g., connected to the semicircular via (124'') in the illustrated case).

[0135] However, considering the thermal aspect, positioning the thermal sensor (123) close to the common ground (e.g., close to the via (124'')) will increase thermal interference from it and significantly reduce the accuracy of the temperature measurement.

[0136] Accordingly, while positioning the thermal sensor (123) as far as possible from the common ground (e.g., via (124'')) along the length of the conductive trace (122'), the sensor (123) Vcc Pin and GND It is proposed to connect the sensor (123) to a common ground through the conductive trace (122') of each heating element (122) at a point along the length that provides the electrical potential difference between the pins close to the minimum allowable value specified in the power supply requirements for the normal operation of the sensor (123). In this way, the accuracy of the temperature measurement is maximized within the constraints of the power supply requirements, thereby further contributing to the improvement of the relevant technical field.

[0137] Therefore, of the sensor (123) GND A pin (only the footprint of the sensor (123) is shown) can be connected to a common ground through a conductive trace (122') using, for example, one of the vias (128') (the right via of the vias (128') shown in the "Layer IV" image).

[0138] To improve the accuracy of the temperature measurement, in some embodiments, it is further proposed that the substrate board (121) extends from the upper layer of the substrate board (121) to the layer having the heat sensor (123) and includes a plated via connected at one end to a conductive trace of a heating element (e.g., a conductive trace (122') of a heating element (122)) and at the other end to or substantially close to the heat sensing pad of each heat sensor (123). For example, as illustrated in FIG. 3k, “Layer I” and “Layer IV”, two vias (128’) are connected to a conductive trace (122’) within the first layer (“Layer I”) and extend to the fourth layer (“Layer IV”), where they are positioned substantially in the center of the footprint of the sensor (123) so that when the sensor (123) is mounted on the board (121), the thermal sensing pad (shown as a rectangle around the via (128’)) is adjacent to the via (128’). Accordingly, in the proposed configuration, the via (128’) functions as a thermal conductor that transfers heat from the conductive trace (122’) through the layers of the substrate board (121) to the thermal sensor (123), thereby enabling accurate temperature measurement and providing additional technical improvements.

[0139] FIG. 31 provides a table with a drill chart showing specifications for various drills illustrated in FIG. 3a through 3k according to some embodiments of the present invention.

[0140] Now, referring to FIGS. 4a through 4g, FIGS. 4a through 4f illustrate various drawings of a substrate board (110) of a chip emulating device (100) according to some embodiments of the present invention, FIG. 4g provides a table with a drill chart showing specifications for various drills shown in FIGS. 4a through 4f and a layer stack-up of the substrate board (110).

[0141] FIG. 4a is a top view of a first substrate board (110) (first (upper) layer) of a chip emulating device (100) according to some embodiment of the present invention.

[0142] As illustrated, in some embodiments, the substrate board (110) may include a microcontroller (111) and a switch (112) (e.g., a FET transistor) assembled on its upper (first) layer. For clarity, only a single microcontroller (111) and a switch (112) are illustrated, and for the remaining microcontrollers (111) and switches (112), only footprints (111A, 112A) are illustrated, respectively.

[0143] As mentioned above, in the upper layer, the substrate board (110) also includes a conductive pad (113) configured to be operably connected (e.g., soldered) to each semicircular via (124) of the substrate board (121) in the assembled state, to supply power to a heating element (122), and to provide power and information (signal) communication with a thermal sensor (123). In the illustrated configuration, the first layer of the substrate board (110) is configured to provide power communication to a group of heating elements (122) responsible for emulating the first and second cores (conductive traces (122') shown in FIG. 3a) of the die of the target chip, particularly through each conductive segment (116A, and 116B).

[0144] FIG. 4b is a top view of a first substrate board (110) (second layer) of a chip emulating device (100) according to some embodiment of the present invention.

[0145] In the illustrated embodiment, the second layer of the substrate board (110) may be configured to provide power communication and information (signal) communication to a group of heat elements (122) responsible for emulating the memory module (HBM) of the die of the target chip (conductive trace (122'') shown in FIG. 3a), particularly through conductive segments (116C, 116D) and a conductive trace (114). The conductive segments (116E to 116I) may be configured to provide communication to ground.

[0146] FIG. 4c is a top view of a first substrate board (110) (third layer) of a chip emulating device (100) according to some embodiment of the present invention. In the illustrated embodiment, the third layer of the substrate board (110) may be configured to provide communication with a common ground.

[0147] FIG. 4d is a top view of a first substrate board (110) (fourth layer) of a chip emulating device (100) according to some embodiment of the present invention. In the illustrated embodiment, the fourth layer of the substrate board (110) may be configured to provide communication with a positive supply voltage.

[0148] FIG. 4e is a top view of a first substrate board (110) (fifth layer) of a chip emulating device (100) according to some embodiment of the present invention. In the illustrated embodiment, the fifth layer of the substrate board (110) may be configured to provide communication with both a common ground and a positive supply voltage.

[0149] FIG. 4f is a top view of a first substrate board (110) (sixth (bottom) layer) of a chip emulating device (100) according to some embodiment of the present invention. In the illustrated embodiment, the bottom layer of the substrate board (110) may be configured to provide communication to a PCB (210), specifically to the footprint of the target chip. Communication between the substrate board (110) and the PCB (210) may be performed using known techniques, for example, a ball grid array (BGA) method.

[0150] FIG. 4g is a stack of a table and a substrate board (110) having a drill chart showing specifications for various drills shown in FIG. 4a to 4f according to some embodiments of the present invention.

[0151] Now, refer to FIG. 5, which illustrates a method for testing a component of a computing device (200) according to some embodiments of the present invention.

[0152] As illustrated in step S1005, the proposed method may include the step of controlling the power consumption of a computing device when power is supplied through a printed circuit board (PCB) of a computing device (e.g., a PCB (210) of a computing device (200)), by operating a microcontroller operably connected to one or more heating elements (e.g., heating elements (122) illustrated in FIG. 2 and 3a) (e.g., operating the microcontroller (111) through a user interface module (400) illustrated in FIG. 2), wherein the one or more heating elements (e.g., heating elements (122) illustrated in FIG. 2 and 3a) are designed to emulate the electrical and thermal behavior of a die of a target chip or at least one component thereof (e.g., a core or memory module of the die) by taking into account predefined power parameters of a computing device (e.g., a power supply module (211) of a computing device (200)), and the microcontroller (e.g., FIG. 1, The microcontroller (111) shown in FIGS. 2 and 4a and the one or more heating elements are assembled on a substrate board (e.g., the substrate board (110) shown in FIGS. 1, 2 and 4a) which is operably connected to the PCB through a target footprint configured to provide a dynamic connection between the target chip and the PCB (e.g., the PCB (210) shown in FIGS. 2).

[0153] As illustrated in step S1010, the proposed method may further include the step of measuring one or more thermal and electrical parameters (e.g., heat dissipation, transient response, power transfer stability) of a computing device (e.g., a computing device (200) illustrated in FIG. 2) using one or more sensors (e.g., a thermal sensor (123) illustrated in FIG. 2 and FIG. 3g; or an electrical test means (300)).

[0154] As illustrated in step S1015, the proposed method may further include the step of providing, through a user interface module (e.g., the user interface module (400) illustrated in FIG. 2), (i) an indication of one or more defects in the operation of a computing device (e.g., the computing device (200) illustrated in FIG. 2) based on one or more measured thermal and electrical parameters (e.g., temperature, heat dissipation, transient response, power transfer stability measured by the sensor (123) illustrated in FIG. 2) (e.g., the defect indication (402A) illustrated in FIG. 2); and (ii) a suggestion for one or more corrective measures to correct the one or more defects based on the one or more measured thermal and electrical parameters (e.g., the suggestion (403A) illustrated in FIG. 2).

[0155] As can be seen from the provided description, the claimed invention presents a chip emulation technology that provides improvements in the technical field of hardware testing and verification. Specifically, the invention provides a solution capable of providing increased test efficiency and accuracy by simultaneously and accurately emulating integrated circuit behavior across thermal, electrical, and mechanical domains. The invention proposed herein provides simplification of the development process, shortening of time-to-market, and improvement of overall product quality and reliability in the electronics industry.

[0156] The present invention further advances the aforementioned field of technology by presenting a test system and method that incorporate such improved chip emulation capabilities, thereby enabling more thorough verification of thermal, electrical, and mechanical compatibility across different electronic components of a computing device before final production. Specifically, the proposed device, system, and method provide improved accuracy and reliability in identifying potential problems in the design of a target computing device, enabling the problem to be resolved early in the development cycle, which is less costly and time-consuming to fix.

[0157] Unless explicitly stated otherwise, the method embodiments described herein are not limited to a specific order or sequence. Furthermore, all formulas described herein are intended merely as examples, and any other or different formulas may be used. Additionally, some of the described method embodiments or elements thereof may occur or be performed at the same time.

[0158] Although specific features of the invention have been illustrated and described herein, many modifications, substitutions, changes, and equivalents may come to mind for those skilled in the art. Accordingly, it should be understood that the appended claims are intended to encompass all such variations and changes that fall within the true spirit of the invention.

[0159] Various embodiments have been presented. Each of these embodiments may include features from other presented embodiments, and embodiments not specifically described may include various features described herein.

Claims

Claim 1 A chip emulating device for testing a component of a computing device, comprising: a first board board configured to be assembled to a target footprint located on a printed circuit board (PCB) of the computing device, wherein the footprint is configured to provide an operable connection between the target chip and the PCB; and a die emulating element operablely connected to the first board board, wherein the die emulating element comprises one or more heating elements designed to emulate the thermal behavior of the die of the target chip or at least one component thereof, taking into account predefined power parameters of the computing device, when the chip emulating device is assembled on the PCB and power is supplied through it. Claim 2 A chip emulating device for testing a component of a computing device, wherein the one or more heating elements are further designed to emulate the electrical behavior of the target chip or at least one component thereof, taking into account the power parameters of the computing device. Claim 3 A chip emulating device for testing a component of a computing device, wherein, in claim 1 or 2, (i) the first substrate board; and (ii) at least one of the die emulating elements is further configured to exhibit, under pressure, (a) the substrate board of the target chip; and (b) a deformation characteristic substantially similar to the die of the target chip. Claim 4 A chip emulating device for testing a component of a computing device, wherein, in claim 1 or 2, it further comprises: one or more thermal sensors configured to measure the temperature of each of the one or more heating elements; and a microcontroller operably connected to the one or more heating elements and the one or more thermal sensors, wherein the microcontroller controls the power consumption of the one or more heating elements; receives the measured temperature of the one or more heating elements from the one or more thermal sensors; and outputs the measured temperature of the one or more heating elements to a user interface module so as to be provided through a user interface. Claim 5 A chip emulating device for testing a component of a computing device, wherein, in paragraph 4, one or more heating elements are positioned on the upper side of the die emulating element, and one or more thermal sensors are each positioned on the lower side of the die emulating element opposite to the one or more heating elements. Claim 6 A chip emulating device for testing a component of a computing device, wherein, in claim 1 or 2, the first substrate board has a pinout compatible with the dimensions of the substrate board of the target chip and the target footprint, the die emulating element comprises a second substrate board sized according to the dimensions of the die of the target chip, and each of the one or more heating elements comprises a conductive trace formed on the surface of the second substrate board, substantially covering an area on the surface of the second substrate board corresponding to an area of ​​each component of the die of the target chip. Claim 7 A chip emulating device for testing a component of a computing device, wherein the conductive trace is dimensioned to operate at substantially the same power and thermal density as the expected power and thermal density of each component of the die in the predefined operating mode of the target chip, taking into account the predefined power parameters of the computing device. Claim 8 A chip emulating device for testing a component of a computing device, wherein the conductive trace is formed to have at least one of a zigzag shape and a spiral shape characterized by length, width, and height, and provides a power density substantially equal to the expected power density of each component of the die in the predefined operating mode of the target chip, taking into account the predefined power parameters of the computing device. Claim 9 In claim 7, the predefined operating mode of the target chip is a chip emulating device for testing a component of a computing device that requires its highest performance. Claim 10 A chip emulating device for testing a component of a computing device, wherein, in accordance with claim 1 or 2, the die emulating element is configured to operate with substantially the same power consumption as the expected power consumption of the target chip in a predefined operating mode of the target chip, taking into account the predefined power parameters of the computing device. Claim 11 A chip emulating device for testing a component of a computing device, wherein, in claim 1 or 2, the microcontroller is further configured to operate the one or more heating elements to simulate various operation scenarios of the target chip or its component, and the operation scenarios include at least one of: (i) toggling the one or more heating elements in a predefined pattern to test the transient response of the power supply module of the computing device; and (ii) maintaining the one or more heating elements in an active state for a predefined period to test the DC power delivery stability and heat dissipation of the computing device. Claim 12 A chip emulating device for testing a component of a computing device, wherein, in claim 1 or 2, it further comprises a structural reinforcing ring attached to the peripheral region of the first substrate board and extending along the peripheral region. Claim 13 A system for testing a component of a computing device, comprising: a printed circuit board (PCB) of the computing device—the PCB comprises a target footprint configured to provide operable connections of a power supply module and a target chip—; and a chip emulating device, wherein the chip emulating device comprises: a first substrate board operablely connected to the PCB through the target footprint; a die emulating element operablely connected to the first substrate board—the die emulating element comprises one or more heating elements designed to emulate the thermal behavior of a die of the target chip or at least one component thereof, taking into account predefined power parameters of the power supply module—; and a microcontroller operablely connected to the one or more heating elements and configured to control the power consumption thereof—the one or more heating elements being powered by the power supply module. Claim 14 A system for testing a component of a computing device, wherein the one or more heating elements are further designed to emulate the electrical behavior of the target chip or at least one component thereof, taking into account the predefined power parameters of the power supply module. Claim 15 A system for testing a component of a computing device, wherein, in claim 13 or 14, (i) the first substrate board; and (ii) at least one of the die emulating elements is further configured to exhibit, under pressure, (a) the substrate board of the target chip; and (b) a deformation characteristic substantially similar to that of the die of the target chip. Claim 16 A system further comprising, in claim 13 or 14, that the PCB comprises one or more peripheral electronic components assembled thereon; (i) said one or more peripheral electronic components; and (ii) electrical test means configured to measure one or more electrical parameters of at least one of said power supply modules; and a user interface module operably connected to said electrical test means and configured to provide a visual interface indicating one or more defects in the operation of said one or more peripheral electronic components and said power supply modules, respectively, based on said one or more measured electrical parameters. Claim 17 A system for testing a component of a computing device, wherein the PCB comprises one or more peripheral electronic components assembled thereon; (i) the chip emulating device; (ii) the one or more peripheral electronic components; and (iii) one or more thermal sensors configured to measure the temperature of at least one of the power supply modules; (i) the chip emulating device; (ii) the one or more peripheral electronic components; and (iii) at least one heat sink configured to be thermally coupled to at least one of the power supply modules and to dissipate heat therefrom; and a user interface module operably connected to the one or more thermal sensors and configured to provide a visual interface indicating one or more heat dissipation defects based on the measured temperature. Claim 18 A system for testing a component of a computing device, wherein, in paragraph 17, the one or more thermal sensors include one or more thermal sensors operably connected to the microcontroller and configured to measure the temperature of each of the one or more heating elements, the microcontroller receives the measured temperature of the one or more heating elements from the one or more thermal sensors; is further configured to output the measured temperature of the one or more heating elements to the user interface module, and the user interface is further configured to indicate the one or more heat dissipation defects based on the measured temperature of the one or more heating elements. Claim 19 A system for testing a component of a computing device, wherein, in claim 13 or 14, the user interface module is operably connected to the microcontroller and further configured to operate the one or more heating elements through the microcontroller to simulate various operation scenarios of the target chip or its components, and the operation scenarios include at least one of: (i) toggling the one or more heating elements in a predefined pattern to test the transient response of the power supply module; and (ii) keeping the one or more heating elements active for a predefined period to test the direct current (DC) power delivery stability and heat dissipation of the computing device. Claim 20 A method for testing a component of a computing device, comprising the steps of: controlling the power consumption of one or more heating elements by operating a microcontroller operably connected thereto when power is supplied through a printed circuit board (PCB) of the computing device, wherein the one or more heating elements are designed to emulate the electrical and thermal behavior of a die of a target chip or at least one component thereof in consideration of predefined power parameters of the computing device, and the microcontroller and the one or more heating elements are assembled on a board operably connected to the PCB through a target footprint configured to provide an operable connection between the target chip and the PCB; measuring one or more thermal and electrical parameters of the computing device using one or more sensors; and, through a user interface module, (i) indicating one or more defects in the operation of the computing device based on the measured one or more thermal and electrical parameters; A method for testing a component of a computing device, comprising the step of (ii) providing a suggestion for one or more corrective measures to correct one or more defects based on one or more measured thermal and electrical parameters.

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