Light emitting display device

Abstract

According to embodiments, the light-emitting display device comprises: a display area including a plurality of pixels and scan lines; and a driving unit located outside the display area and connected to the scan lines, wherein the driving unit comprises two scan signal stages arranged in the extension direction of the scan lines; at least two light-emitting signal stages located in at least two columns; a plurality of input signal lines connected to the two scan signal stages; and a pair of first clock signal lines connected to the at least two light-emitting signal stages, wherein the two scan signal stages are connected to the same input signal line among the plurality of input signal lines, and the at least two light-emitting signal stages sharing the pair of first clock signal lines receive different start signals, and the two scan signal stages also receive different start signals.

Description

Technology Field

[0001] The present disclosure relates to a light-emitting display device, and more specifically, to a light-emitting display device comprising a driving unit formed together with a pixel in a panel through the same process. Background Technology

[0002] A display device is a device that displays an image, and includes Liquid Crystal Displays (LCDs), Organic Light Emitting Diode Displays (OLEDs), and Quantum Dot Displays. These display devices are used in a wide variety of electronic devices, such as mobile phones, navigation systems, digital cameras, e-books, portable game consoles, and various terminals.

[0003] Organic light-emitting displays (OLEDs) possess self-luminous characteristics and, unlike liquid crystal displays (LCDs), do not require a separate light source, allowing for reduced thickness and weight. Furthermore, OLEDs offer high-quality characteristics such as low power consumption, high brightness, and fast response speeds. The problem to be solved

[0004] The embodiments are intended to reduce the width / area of ​​the non-display area where an image is not displayed. means of solving the problem

[0005] A light-emitting display device according to one embodiment includes a display area comprising a plurality of pixels and scan lines; and a driving unit located outside the display area and connected to the scan lines, wherein the driving unit includes two scan signal stages arranged in the extension direction of the scan lines; at least two light-emitting signal stages located in at least two columns; a plurality of input signal lines connected to the two scan signal stages; and a pair of first clock signal lines connected to the at least two light-emitting signal stages, wherein the two scan signal stages are connected to the same input signal line among the plurality of input signal lines, and the at least two light-emitting signal stages sharing the pair of first clock signal lines receive different start signals, and the two scan signal stages also receive different start signals.

[0006] The input signal line commonly connected to the two scan signal stages may be a pair of second clock signal lines.

[0007] The above pair of second clock signal lines may be located between the two scan signal stages.

[0008] The two scan signal stages mentioned above may each be included in a first scan signal generating unit and a second scan signal generating unit.

[0009] The above plurality of input signal lines may further include high-voltage wiring or low-voltage wiring.

[0010] The above pair of second clock signal lines, or the above low-voltage wiring, may be located between the two scan signal stages.

[0011] The first scan signal generated by the first scan signal generating unit has one low voltage per frame, and the second scan signal generated by the second scan signal generating unit can have three low voltages per frame.

[0012] The above driving unit may be located only on one side of the above display area.

[0013] The above driving unit may further include additional input signal lines connected to the at least two light-emitting signal stages.

[0014] The at least two light-emitting signal stages located in the at least two columns are each connected to the additional input signal line, and the at least two light-emitting signal stages are arranged in a horizontal direction in which the driving unit is adjacent to the display area, and can be arranged on both sides of the additional input signal line having an extension direction perpendicular to the horizontal direction.

[0015] The above at least two stages for light emission signals may be included in at least two of a first light emission control signal generating unit, a second light emission control signal generating unit, an initialization control signal generating unit, and a bias control signal generating unit.

[0016] The pixel circuit of the display area above can receive a first light emission control signal generated by the first light emission control signal generating unit, a second light emission control signal generated by the second light emission control signal generating unit, a first initialization control signal and a second initialization control signal generated by the initialization control signal generating unit, a bias control signal generated by the bias control signal generating unit, a first scan signal generated by the first scan signal generating unit, and a second scan signal generated by the second scan signal generating unit.

[0017] The light-emitting signal stage within the initialization control signal generating unit that generates the first initialization control signal may be located ahead of the light-emitting signal stage within the initialization control signal generating unit that generates the second initialization control signal. Effects of the invention

[0018] According to the embodiments, the width / area of ​​the non-display area can be reduced by configuring a plurality of driving units located in the non-display area to have a common input signal line. In particular, in a light-emitting display device where a plurality of signal lines must be provided to a single pixel, even if a driving unit generating a plurality of signals is formed in the non-display area using the same process as the pixel, the width / area of ​​the non-display area can be reduced by forming two adjacent driving units symmetrically with respect to the input signal line and forming them to use the input signal line in common. Brief explanation of the drawing

[0019] FIG. 1 is a simplified schematic diagram of a light-emitting display device according to an embodiment. FIG. 2 is a circuit diagram of a pixel located in the display area of ​​a light-emitting display device according to one embodiment. FIG. 3 is a waveform diagram illustrating a plurality of signals applied to the pixel of FIG. 2 and the voltage waveform of the G node accordingly. FIGS. 4 and FIGS. 5 are block diagrams of driving units located in non-display areas on both sides of a display area according to one embodiment. FIG. 6 is a circuit diagram illustrating one stage constituting a light emission control signal generation unit among the driving units of a non-display area according to one embodiment. FIG. 7 is a waveform diagram showing an input signal applied to a stage of a light emission control signal generation unit according to the embodiment of FIG. 6. FIG. 8 is a layout diagram illustrating a structure in which two stages of a light emission control signal generation unit are flip-arranged according to one embodiment. Figures 9 and 10 are cross-sectional views taken along the section lines IX-IX and XX of Figure 8. FIG. 11 is a layout diagram illustrating a structure in which two stages of a light emission control signal generation unit are flip-arranged according to another embodiment. Figures 12 and 13 are cross-sectional views taken along the cross-sectional lines XII-XII and XIII-XIII of Figure 11. FIG. 14 is a simplified diagram illustrating a structure in which two stages of a light emission control signal generation unit are commonly connected to an input signal line according to another embodiment. FIG. 15 is a circuit diagram illustrating one stage constituting a scan signal generating unit among the driving units of a non-display area according to one embodiment. FIG. 16 is a waveform diagram showing an input signal applied to a stage of a scan signal generation unit according to the embodiment of FIG. 15. FIG. 17 is a waveform diagram illustrating a plurality of signals applied to a pixel of FIG. 2 according to another embodiment and the voltage waveform of the G node accordingly. FIG. 18 is a waveform diagram showing an input signal applied to the stage of a scan signal generation unit to generate the signal of FIG. 17. FIG. 19 is a layout diagram illustrating a structure in which two stages of a scan signal generation unit are flipped according to one embodiment. FIG. 20 is a cross-sectional view taken along the cross-sectional line XX-XX of FIG. 19. FIG. 21 is a drawing that clearly illustrates the reduction in width resulting from forming a plurality of stages in a non-display area in one embodiment. FIG. 22 is a cross-sectional view of a part of FIG. 21. Specific details for implementing the invention

[0020] Hereinafter, various embodiments of the present invention will be described in detail with reference to the attached drawings so that those skilled in the art can easily implement the present invention. The present invention may be embodied in various different forms and is not limited to the embodiments described herein.

[0021] To clearly explain the present invention, parts unrelated to the explanation have been omitted, and the same reference numerals are used for identical or similar components throughout the specification.

[0022] Furthermore, the size and thickness of each component shown in the drawings are depicted arbitrarily for convenience of explanation, and thus the present invention is not necessarily limited to what is illustrated. Thicknesses have been enlarged in the drawings to clearly represent various layers and regions. Additionally, for convenience of explanation, the thickness of some layers and regions has been exaggerated in the drawings.

[0023] Furthermore, when it is said that a part, such as a layer, membrane, region, or plate, is "on" or "on" another part, this includes not only the case where it is "directly above" the other part, but also the case where there is another part in between. Conversely, when it is said that a part is "directly above" another part, it means that there is no other part in between. Also, saying that a part is "on" or "on" a reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "on" or "on" in the direction opposite to gravity.

[0024] Furthermore, throughout the specification, when a part is described as "including" a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0025] Additionally, throughout the specification, "planar" means when the subject part is viewed from above, and "cross-sectional" means when the cross-section obtained by vertically cutting the subject part is viewed from the side.

[0026] Throughout the specification, when the term “connected” is used, it does not mean only cases where two or more components are directly connected, but may also include cases where two or more components are indirectly connected through other components, cases where they are physically or electrically connected, as well as cases where each part, which is substantially one and referred to by different names depending on its location or function, is connected to one another.

[0027] Below, we will examine the embodiments in detail through the drawings.

[0028] FIG. 1 is a simplified schematic diagram of a light-emitting display device according to an embodiment.

[0029] In the light-emitting display device (10) according to the present embodiment, a driving unit (200, 250) is formed in a display area (DA) where a plurality of pixels (PX) are formed, and in a non-display area located on both sides of the display area (DA).

[0030] A pixel (PX) of a light-emitting display device largely comprises a pixel circuit section and a light-emitting element section that receives current from the pixel circuit section and emits light. The arrangement of the light-emitting element section can have various arrangements, and the rectangular pixel (PX) shown in FIG. 1 may be a pixel circuit section among the pixels, and the rectangular pixel circuit section may be arranged according to a matrix.

[0031] First, through FIGS. 2 and FIGS. 3, we will examine the pixel (PX) formed in the light-emitting display device according to the embodiment.

[0032] First, let's examine the circuit structure of the pixel through Figure 2.

[0033] FIG. 2 is a circuit diagram of a pixel located in the display area of ​​a light-emitting display device according to one embodiment.

[0034] A single pixel is largely composed of a pixel circuit and a light-emitting element, and the pixel circuit may include a driving transistor (T1) that transmits output current to the anode of the light-emitting element; an input capacitor (Cpr); and a second transistor (T2) connected to a data line (171) that transmits data voltage to the input capacitor.

[0035] A pixel of a light-emitting display device according to the embodiment of FIG. 2 includes a plurality of transistors (T1, T2, T3, T4, T5, T6, T7, T8) connected to a plurality of signal lines (127, 151, 152, 153, 153-1, 154, 155, 156, 171, 172, 173, 179), a plurality of capacitors (Cst, Cpr), and a light-emitting diode. When a pixel is divided into a pixel circuit part and a light-emitting element part, the light-emitting element is a light-emitting diode, and the other transistors and capacitors constitute the pixel circuit part. The light-emitting diode may be an organic light-emitting diode or an inorganic light-emitting diode.

[0036] A plurality of transistors (T1, T2, T3, T4, T5, T6, T7, T8) include a driving transistor (T1; also called the first transistor) that generates an output current to be transmitted to a light-emitting diode, and a data voltage (V) applied to a data line (171). DATA A second transistor (T2) that transmits ) into the pixel, a third transistor (T3) that connects the output electrode and the gate electrode of the driving transistor (T1), and one end of the input capacitor (Cpr) to the reference voltage (V REF A fourth transistor (T4) that changes to ), a fifth transistor (T5) that transmits a driving voltage (ELVDD) to a driving transistor (T1), a sixth transistor (T6) that transmits the output current of the driving transistor (T1) to a light-emitting diode, and an initialization voltage (V) for the anode of the light-emitting diode. INT It includes a seventh transistor (T7) that changes to ), and an eighth transistor (T8) that transmits a bias voltage (Vbias) to a driving transistor (T1).

[0037] A plurality of signal lines (127, 151, 152, 153, 153-1, 154, 155, 156, 171, 172, 173, 179) may include a first scan line (151), a second scan line (152), an initialization control line (153, 153-1), a light emission control line (154, 155), a bias control line (156), a data line (171), a driving voltage line (172), a reference voltage line (173), a bias voltage line (179), and an initialization voltage line (127). The second initialization control line (153-1) may be the same wiring as the first initialization control line (153) connected to the pixel of the next row. The first light-emitting control line (154) and the second light-emitting control line (155) included in the light-emitting control lines (154, 155) may have signals having different timings applied to them.

[0038] The reference voltage line (173) is a reference voltage (V) at the N node where the input capacitor (Cpr) and the second transistor (T2) are connected. REF ...transmits ..., and the driving voltage line (172) transmits the driving voltage (ELVDD) to the driving transistor (T1), the driving low voltage line transmits the driving low voltage (ELVSS) to the cathode, and the initialization voltage line (127) transmits the initialization voltage (V) to the anode. INT It transmits ), and the bias voltage line (179) transmits the bias voltage (Vbias) to the driving transistor (T1).

[0039] Multiple capacitors (Cst, Cpr) include a holding capacitor (Cst) that maintains the voltage of the gate electrode of the driving transistor (T1) constant for one frame and a data voltage (V) transmitted through the second transistor (T2). DATA It includes an input capacitor (Cpr) that transmits ) to one electrode of the driving transistor (T1). In some embodiments, the input capacitor (Cpr) is not included, so the data voltage (V) is directly transmitted. DATA ) may also be transferred to one electrode of the driving transistor (T1).

[0040] The detailed connection relationships of each element included in the pixel are as follows.

[0041] The driving transistor (T1) is the data voltage (V) applied to the gate electrode. DATA A transistor that controls the magnitude of the output current according to ), where the output current is applied to the anode of a light-emitting diode and the data voltage (V DATA The brightness of the light-emitting diode is controlled according to ). To this end, the first electrode of the driving transistor (T1) is connected to the driving voltage line (172) via the fifth transistor (T5) so that the driving voltage (ELVDD) can be applied. In addition, the first electrode of the driving transistor (T1) receives a bias voltage (Vbias) through the eighth transistor (T8), and the voltage of the first electrode of the driving transistor (T1) is maintained at a certain level. Meanwhile, the second electrode (O node) of the driving transistor (T1) is positioned to output current toward the light-emitting diode and is connected to the anode of the light-emitting diode via the sixth transistor (T6). The second electrode of the driving transistor (T1) is connected to the input capacitor (Cpr) and the data voltage (V) input through the second transistor (T2) DATA It receives the voltage. Meanwhile, the gate electrode (G node) of the driving transistor (T1) is connected to the holding capacitor (Cst). Accordingly, the voltage of the gate electrode of the driving transistor (T1) changes according to the voltage stored in the holding capacitor (Cst), and the current output by the driving transistor (T1) changes accordingly. The gate electrode of the driving transistor (T1) and the second electrode are connected by the third transistor (T3).

[0042] The second transistor (T2) is the data voltage (V DATAIt is a transistor that receives ) into the pixel (N node in FIG. 2). The gate electrode of the second transistor (T2) is connected to the first scan line (151), and the first electrode of the second transistor (T2) is connected to the data line (171). The second electrode of the second transistor (T2) is connected to the second electrode (O node) of the driving transistor (T1) through the input capacitor (Cpr). When the second transistor (T2) is turned on according to the first scan signal (GW(n)) transmitted through the first scan line (151), the data voltage (V) transmitted through the data line (171) DATA ) is transferred to the second electrode of the driving transistor (T1) through the input capacitor (Cpr).

[0043] The third transistor (T3) is the data voltage (V DATAIt serves to transfer to the gate electrode of the driving transistor (T1) and the holding capacitor (Cst), and also to compensate for the threshold voltage of the driving transistor (T1) with the voltage stored in the holding capacitor (Cst). The gate electrode of the third transistor (T3) is connected to the second scan line (152), and the first electrode of the third transistor (T3) is connected to the O node and is connected to the second electrode of the driving transistor (T1) and the input capacitor (Cpr), and the first electrode of the third transistor (T3) is connected to the G node and is connected to the gate electrode of the driving transistor (T1) and the holding capacitor (Cst). That is, when the driving transistor (T1) is turned on by the voltage applied to the holding capacitor (Cst) by connecting the driving transistor (T1) to the diode, the negative charge stored in the holding capacitor (Cst) is discharged, and the voltage of the holding capacitor (Cst) increases. Then, when the driving transistor (T1) is turned off at the threshold voltage of the driving transistor (T1) and the voltage no longer decreases, the voltage stored in the holding capacitor (Cst) becomes the threshold voltage value of the driving transistor (T1). With this structure, even if each driving transistor (T1) has a different threshold voltage, each pixel circuit can compensate and operate.

[0044] The fourth transistor (T4) uses the voltage of the first electrode of the input capacitor (Cpr) (or the second electrode of the second transistor (T2)) as a reference voltage (V REF It serves to initialize the fourth transistor (T4). The gate electrode of the fourth transistor (T4) is connected to the first initialization control line (153), the first electrode of the fourth transistor (T4) is connected to the reference voltage line (173), and the second electrode of the fourth transistor (T4) is connected to the first electrode of the input capacitor (Cpr) and the second electrode of the second transistor (T2).

[0045] The fifth transistor (T5) serves to transmit the driving voltage (ELVDD) to the driving transistor (T1). The gate electrode of the fifth transistor (T5) is connected to the first light emission control line (154), the first electrode of the fifth transistor (T5) is connected to the driving voltage line (172), and the second electrode of the fifth transistor (T5) is connected to the first electrode of the driving transistor (T1).

[0046] The sixth transistor (T6) serves to transmit the output current from the driving transistor (T1) to the light-emitting diode. The gate electrode of the sixth transistor (T6) is connected to the second light-emitting control line (155), the first electrode of the sixth transistor (T6) is connected to the second electrode of the driving transistor (T1), and the second electrode of the sixth transistor (T6) is connected to the anode of the light-emitting diode.

[0047] The seventh transistor (T7) initializes the anode of the light-emitting diode to a voltage (V). INT It serves to initialize the 7th transistor (T7). The gate electrode of the 7th transistor (T7) is connected to the second initialization control line (153-1), the first electrode of the 7th transistor (T7) is connected to the anode (A node) of the light-emitting diode, and the second electrode of the 7th transistor (T7) is connected to the initialization voltage line (127). The second initialization control line (153-1) may be the same wiring as the first initialization control line (153) connected to the pixel of the next row.

[0048] The eighth transistor (T8) serves to apply a bias voltage (Vbias) to the first electrode of the driving transistor (T1), thereby preventing the voltage level of the first electrode of the driving transistor (T1) from exceeding a certain range. The gate electrode of the eighth transistor (T8) is connected to the bias control line (156), the first electrode of the eighth transistor (T8) is connected to the bias voltage line (179), and the second electrode of the eighth transistor (T8) is connected to the first electrode of the driving transistor (T1).

[0049] The first holding electrode of the holding capacitor (Cst) is connected to the driving voltage line (172), and the second holding electrode is connected to the G node, that is, the gate electrode of the driving transistor (T1) and the second electrode of the third transistor (T3). As a result, the second holding electrode is equal to the voltage of the gate electrode of the driving transistor (T1), and the voltage of the gate electrode of the driving transistor (T1) is maintained constant for one frame.

[0050] The first electrode of the input capacitor (Cpr) is connected to the N node, that is, the second electrode of the second transistor (T2) and the second electrode of the fourth transistor, and the second electrode is connected to the second electrode (O node) of the driving transistor (T1).

[0051] Meanwhile, the anode (A node) of the light-emitting diode is connected to the second electrode of the sixth transistor (T6) and the first electrode of the seventh transistor (T7), and the cathode is subjected to a driving low voltage (ELVSS).

[0052] A signal with a waveform like that of Fig. 3 can be applied to a pixel having the circuit structure of Fig. 2.

[0053] Figure 3 is a waveform applied to the pixel of Figure 2.

[0054] In Figure 3, for the sake of explanation, the sections are divided into (A), (B), (C), (D), (E), (F), (G), and (H), and section (H) is located before section (A).

[0055] First, let's look at section (H) (hereinafter also referred to as the luminescence section).

[0056] In section (H), only the first light emission control signal (EM1) and the second light emission control signal (EM2) applied to the fifth transistor (T5) and the sixth transistor (T6) are subjected to a low-level turn-on voltage. As a result, the fifth transistor (T5) and the sixth transistor (T6) are turned on, and the driving transistor (T1) receives a driving voltage (ELVDD) and has a structure connected to the light-emitting diode. As a result, an output current is generated according to the driving voltage (ELVDD) and the voltage of the gate electrode (G_node voltage) of the driving transistor (T1), and the output current is delivered to the light-emitting diode. The light-emitting diode displays brightness according to the magnitude of the received output current.

[0057] Subsequently, the first light emission control signal (EM1) changes to a high-level voltage first, entering section (A). At this time, the first initialization control signal (EB1(n)) and the second initialization control signal (EB1(n+1)) are sequentially changed to a low-level voltage. The time difference between the first initialization control signal (EB1(n)) and the second initialization control signal (EB1(n+1)) changing to a low-level voltage is 1H or more, and may vary depending on the embodiment. In section (A), the driving voltage (ELVDD) is not applied to the driving transistor (T1), and the driving transistor (T1) does not generate an output current. Additionally, the voltage of the N node (the second electrode of the second transistor (T2) and the second electrode of the fourth transistor) is set by the fourth transistor (T4) to a reference voltage (V REF It is initialized to ), and the initialization voltage (V) input through the 7th transistor (T7)INT Node A (the anode of the light-emitting diode) is initialized with ). Since the 6th transistor (T6) is turned on during section (A), the initialization voltage (V INT The voltage is transmitted through node A to node O, thereby initializing node O as well. Since the second electrode of the driving transistor (T1), the first electrode of the third transistor (T3), and the second electrode of the input capacitor (Cpr) are connected to node O, they are all also initialized to the initialization voltage (V INT It is initialized to ).

[0058] Then, upon entering section (B), the second scan signal (GC(n)) is first changed to a low-level voltage, and the initialization voltage (V) applied to the O node INT ) is transmitted to the G node, so the G node also initializes the voltage (V INT The gate electrode of the driving transistor (T1) connected to the G node and the second electrode of the holding capacitor (Cst) are also initialized to the initialization voltage (V INT It is initialized to ).

[0059] After that, the second scan signal (GC(n)) repeatedly changes between a high-level voltage and a low-level voltage several times, applies a low-level voltage to the data writing section (section (E)), and thereafter maintains the high-level voltage. Depending on the embodiment, the number of times the second scan signal (GC(n)) changes to a low-level voltage may vary, and it is sufficient to have at least one time before the next light emission section (H).

[0060] After the second light emission control signal (EM2) is changed to a high-level voltage, the first light emission control signal (EM1) is changed from a high-level to a low-level voltage and enters section (C).

[0061] (C) is also called a threshold voltage compensation section, and in section (C), the first light emission control signal (EM1) and the second scan signal (GC(n)) have a low level voltage, and the driving voltage (ELVDD) is applied to the driving transistor (T1) and has a diode connection structure by the third transistor (T3).

[0062] At this time, the voltage of node G is the initialization voltage (V INT Since ), the driving transistor (T1) is turned on, and as the negative charge stored in the holding capacitor (Cst) flows out, the voltage of the holding capacitor (Cst) increases, and then the driving transistor (T1) is turned off at the threshold voltage of the driving transistor (T1). As a result, the holding capacitor (Cst) has a voltage value (Vth) lower than the threshold voltage (Vth) of the driving transistor (T1) based on the driving voltage (ELVDD). ELVDD - Vth) is stored in the G node.

[0063] Meanwhile, in section (C), nodes N and A continue to use the reference voltage (V) by means of the first initialization control signal (EB1(n)) and the second initialization control signal (EB1(n+1)). REF ) and initialization voltage (V INT It continues to be maintained as ).

[0064] Subsequently, the first light emission control signal (EM1), the first initialization control signal (EB1(n)), and the second initialization control signal (EB1(n+1)) change to a high level voltage, thereby entering section (D). At this time, the second scan signal (GC(n)) may also be at a timing where it changes to a high level voltage. In section (D), the operation to compensate for the threshold voltage ends, and it is a section that prepares for the subsequent section (E) (also called the data writing section).

[0065] After that, during the period when the second scan signal (GC(n)) is changed to a low level voltage, the first scan signal (GW(n)) is changed to a low level voltage and enters section (E).

[0066] (E) In section (E), the second transistor (T2) is turned on, and the data voltage (V DATA ) is transmitted to the O node through the input capacitor (Cpr). At this time, since the third transistor (T3) is also turned on by the second scan signal (GC(n)), the data voltage (V) up to the G node. DATA ) is applied. When the data voltage value transmitted to the N node is transmitted to the O and G nodes, it is transmitted with a partial reduction depending on the capacitance of the input capacitor (Cpr). The data voltage value transmitted with this partial reduction (α) is αV DATA When given that, the existing voltage value of node G is V ELVDD - Since it was Vth, the voltage at the final G node of section (E) is V ELVDD - Vth + αV DATA It can have a value.

[0067] As a result, the threshold voltage of the driving transistor (T1) is compensated in the holding capacitor (Cst), and the data voltage is also included.

[0068] After that, the first scan signal (GW(n)) changes to a high-level voltage and enters section (F). At this time, the second scan signal (GC(n)) also changes to a high-level voltage, and the second scan signal (GC(n)) maintains a high level from section (F) to the next section (B).

[0069] (F) In the section, the first initialization control signal (EB1(n)) and the second initialization control signal (EB1(n+1)) are changed to a low level voltage to re-initialize the N node and the A node. Additionally, the bias control signal (EB2(n)) is also changed to a low level voltage to apply a bias voltage (Vbais) to the driving transistor (T1). The bias voltage (Vbais) has a voltage value set to a constant voltage according to the characteristics of the panel, and can have various voltage values ​​for each panel. The bias voltage (Vbais) can be set to have a single fixed voltage value for each panel, and prevents the voltage of the first electrode of the driving transistor (T1) from changing due to surrounding voltage changes.

[0070] After that, the bias control signal (EB2(n)) changes to a high level voltage and enters section (G). In section (G), the second light emission control signal (EM2) is applied at a low level voltage to prepare for entry into the light emission section (H), and the first initialization control signal (EB1(n)) and the second initialization control signal (EB1(n+1)) are maintained at a low level voltage.

[0071] After that, as the first initialization control signal (EB1(n)) and the second initialization control signal (EB1(n+1)) change to a high-level voltage, the first light emission control signal (EM1) changes to a low-level voltage, and the device enters the light emission section ((H) section).

[0072] In section (H), the driving transistor (T1) receives the driving voltage (ELVDD), generates an output current according to the voltage of the G node, and transmits it to the light-emitting diode to emit light with a predetermined brightness.

[0073] To apply a signal with the timing as shown in Fig. 3 to a pixel as shown in Fig. 2 above, the driving unit (200, 250) located on both sides of the display area (DA) is examined in detail through Figs. 4 and 5.

[0074] FIGS. 4 and FIGS. 5 are block diagrams of driving units located in non-display areas on both sides of a display area according to one embodiment.

[0075] First, we will examine the first driving unit (200) located on the left side of the display area (DA) based on FIG. 4.

[0076] The first driving unit (200) includes a total of six driving units, and includes a first light emission control signal generating unit (EM1_D; 2001) that generates a first light emission control signal (EM1), a second light emission control signal generating unit (EM2_D; 2002) that generates a second light emission control signal (EM2), an initialization control signal generating unit (EB1_D; 2003) that generates a first initialization control signal (EB1(n)), a bias control signal generating unit (EB2_D; 2004) that generates a bias control signal (EB2(n)), a first scan signal generating unit (GW_D; 3001) that generates a first scan signal (GW(n)), and a second scan signal generating unit (GC_D; 3002) that generates a second scan signal (GC(n)). Here, the second initialization control signal (EB1(n+1)) applied from the pixel is received from the initialization control signal generation unit (EB1_D; 2003) of the next row.

[0077] The first driving unit (200) located on the left side of the display area (DA) has the first light emission control signal generating unit (EM1_D; 2001), the second light emission control signal generating unit (EM2_D; 2002), the initialization control signal generating unit (EB1_D; 2003), the bias control signal generating unit (EB2_D; 2004), the second scan signal generating unit (GC_D; 3002), and the first scan signal generating unit (GW_D; 3001) arranged in order from the outside in the direction of the display area (DA).

[0078] Meanwhile, in FIG. 5, a second driving unit (250) located to the right of the display area (DA) is shown.

[0079] The second driving unit (250) includes a total of six driving units, identical to the first driving unit (200), and includes a first light emission control signal generating unit (EM1_D; 2005) that generates a first light emission control signal (EM1), a second light emission control signal generating unit (EM2_D; 2006) that generates a second light emission control signal (EM2), an initialization control signal generating unit (EB1_D; 2007) that generates a first initialization control signal (EB1(n)), a bias control signal generating unit (EB2_D; 2008) that generates a bias control signal (EB2(n)), a first scan signal generating unit (GW_D; 3003) that generates a first scan signal (GW(n)), and a second scan signal generating unit (GC_D; 3004) that generates a second scan signal (GC(n)). Here, the second initialization control signal (EB1(n+1)) applied from the pixel is received from the initialization control signal generation unit (EB1_D; 2007) of the next row.

[0080] The second driving unit (250), located to the right of the display area (DA), has the first light emission control signal generating unit (EM1_D; 2005), the second light emission control signal generating unit (EM2_D; 2006), the initialization control signal generating unit (EB1_D; 2007), the bias control signal generating unit (EB2_D; 2008), the second scan signal generating unit (GC_D; 3004), and the first scan signal generating unit (GW_D; 3003) arranged in order from the outside in the direction of the display area (DA).

[0081] That is, referring to FIGS. 4 and 5, a first scan signal generator (GW_D; 3001, 3003) is located at the position closest to the display area (DA), and a second scan signal generator (GC_D; 3002, 3004), a bias control signal generator (EB2_D; 2004, 2008), an initialization control signal generator (EB1_D; 2003, 2007), a second light emission control signal generator (EM2_D; 2002, 2006), and a first light emission control signal generator (EM1_D; 2001, 2005) are arranged sequentially from thereto.

[0082] The same signal generating unit belonging to the first driving unit (200) and the second driving unit (250) is connected to the same signal line and generates the same signal and applies it to the signal line. For example, the first scan signal generating unit (GW_D; 3001, 3003) of the first driving unit (200) and the second driving unit (250) is connected to both ends of the same first scan line (151) and outputs a first scan signal in which the voltage changes at the same timing.

[0083] Since the same signal is output in this manner, depending on the embodiment, only one of the first driving unit (200) and the second driving unit (250) may be included. That is, according to FIGS. 1, 4, and 5, an embodiment is illustrated in which two driving units (200, 250) are formed identically on both sides of the display area (DA) and identical driving units are symmetrically formed on both sides, but depending on the embodiment, a driving unit may be formed only on one side of the display area (DA).

[0084] In addition, identical generating units among the first driving unit (200) and the second driving unit (250) may be removed so that only one generating unit is included, thereby allowing a total of six generating units to be divided and included in the first driving unit (200) and the second driving unit (250). In this case, depending on the embodiment, the first scan signal generating unit (GW_D; 3001, 3003) and the second scan signal generating unit (GC_D; 3002, 3004) may be located in one driving unit, and the first light emission control signal generating unit (EM1_D; 2001, 2005), the second light emission control signal generating unit (EM2_D; 2002, 2006), the initialization control signal generating unit (EB1_D; 2003, 2007), and the bias control signal generating unit (EB2_D; 2004, 2008) may be located in the remaining driving unit. In addition, depending on the embodiment, three generating units may be divided and included in the first driving unit (200) and the second driving unit (250).

[0085] In one embodiment, the first driving unit (200) and the second driving unit (250) may include only two types of stages. That is, a total of six generating units are configured using the first stage and the second stage.

[0086] The first stage may be configured with a first light emission control signal generator (EM1_D; 2001, 2005), a second light emission control signal generator (EM2_D; 2002, 2006), an initialization control signal generator (EB1_D; 2003, 2007), and a bias control signal generator (EB2_D; 2004, 2008), and the second stage may be configured with a first scan signal generator (GW_D; 3001, 3003) and a second scan signal generator (GC_D; 3002, 3004). That is, the first stage and the second stage have the same circuit configuration, but the input signals can be different to form different output signals.

[0087] Since the most representative signal among the signals generated by the first stage is a light emission control signal, the first stage may also be referred to as one stage of the light emission control signal generation unit. Additionally, since the most representative signal among the signals generated by the second stage is a scan signal, the second stage may also be referred to as one stage of the scan signal generation unit.

[0088] First, below, we will examine a signal generation unit including a first stage through FIGS. 6 to 14.

[0089] Below, we first examine the circuit configuration of a first stage (hereinafter also referred to as a stage for light emission signals) that can be configured with a first light emission control signal generating unit (EM1_D; 2001, 2005), a second light emission control signal generating unit (EM2_D; 2002, 2006), an initialization control signal generating unit (EB1_D; 2003, 2007), and a bias control signal generating unit (EB2_D; 2004, 2008) through FIG. 6.

[0090] FIG. 6 is a circuit diagram illustrating one stage constituting a light emission control signal generation unit among the driving units of a non-display area according to one embodiment.

[0091] Each stage for a light-emitting signal according to the present embodiment includes a high-level output unit (2551), a low-level output unit (2552), a first node first control unit (2553), a first node second control unit (2554), a second node first control unit (2555), a second-1 node maintenance unit (2556), a third node control unit (2557), a first connection unit (2558), a second connection unit (2559), and an initialization unit (2560).

[0092] The core structure of each stage for light emission signals is as follows.

[0093] The high-level output section (2551) is a section that outputs a high voltage (VGH) of the light-emitting signal, and the low-level output section (2552) is a section that outputs a low voltage (VGL) of the light-emitting signal. The high-level output section (2551) and the low-level output section (2552) are connected to an output terminal (Out). When the high voltage (VGH) is output from the high-level output section (2551), the low-level output section (2552) does not output, and when the low voltage (VGL) is output from the low-level output section (2552), the high-level output section (2551) does not output.

[0094] The high-level output section (2551) is controlled according to the voltage of the first node (EM_QB), and the voltage of the first node (EM_QB) is controlled by the first node first control section (2553) and the first node second control section (2554).

[0095] The low-level output section (2552) is controlled according to the voltage of the second node (SR_Q), and the voltage of the second node (SR_Q) is controlled by the second node first control section (2555). Specifically, the low-level output section (2552) is connected to the second node (SR_Q) by the second connection section (2559) and is controlled according to the voltage of the second-1 node (SR_Q_F). However, since the second 12 transistor (T212) included in the second connection section (2559) receives a low voltage (VGL) as a control terminal and maintains a turned-on state, the low-level output section (2552) is effectively controlled according to the voltage of the second node (SR_Q).

[0096] The first node second control unit (2554) is controlled by the voltage of the third node (SR_QB), and the voltage of the third node (SR_QB) is controlled by the third node control unit (2557). Specifically, the first node second control unit (2554) is connected to the third node (SR_QB) by the first connection unit (2558) and is controlled according to the voltage of the third-1 node (SR_QB_F). However, since the second 11 transistor (T211) included in the first connection unit (2558) receives a low voltage (VGL) as a control terminal and maintains a turned-on state, the first node second control unit (2554) is effectively controlled according to the voltage of the third node (SR_QB).

[0097] The light-emitting signal stage of FIG. 6 receives two clock signals (EM_CLK1, EM_CLK2), and the light-emitting signal stage of the next row is connected so that the two clock signals are input interchangeably. Additionally, although the light-emitting signal stage of FIG. 6 is shown as receiving an FLM signal through the input terminal, if there is a preceding light-emitting signal stage (previous light-emitting signal stage), the output of the preceding light-emitting signal stage can be input to the input terminal.

[0098] A detailed look at each part of the stage for each light emission signal is as follows.

[0099] The high-level output section (2551) includes a second-level transistor (T209), the gate electrode of the second-level transistor (T209) is connected to the first node (EM_QB), the input electrode is connected to the high-voltage (VGH) terminal, and the output electrode is connected to the output terminal (Out). As a result, when the voltage of the first node (EM_QB) is low, the high voltage (VGH) is output to the output terminal (Out), and when the voltage of the first node (EM_QB) is high, the second-level transistor (T209) is turned off and does not produce any output.

[0100] The low-level output section (2552) includes the 210 transistor (T210), the gate electrode of the 210 transistor (T210) is connected to the 2-1 node (SR_Q_F), the input electrode is connected to the low voltage (VGL) terminal, and the output electrode is connected to the output terminal (Out). As a result, when the voltage of the 2-1 node (SR_Q_F) is low voltage, the low voltage (VGL) is output to the output terminal (Out), and when the voltage of the 2-1 node (SR_Q_F) is high voltage, the 210 transistor (T210) does not produce any output. The 212 transistor (T212) included in the 2nd connection section (2559) receives the low voltage (VGL) as a control terminal, so the turn-on state is maintained, and thus the voltage of the 2-1 node (SR_Q_F) has the same voltage as the voltage of the 2nd node (SR_Q). Therefore, the low-level output section (2552) is controlled by the second node (SR_Q).

[0101] We examine the first node first control unit (2553) and the first node second control unit (2554) that control the voltage of the first node (EM_QB).

[0102] The first node first control unit (2553) includes one transistor (transistor 208 (T208)) and one capacitor (capacitor 201 (Ca201)). The gate electrode of transistor 208 (T208) is connected to the second node (SR_Q), the input electrode is connected to the high voltage (VGH), and the output electrode is connected to the first node (EM_QB). Transistor 208 (T208) transmits the high voltage (VGH) to the first node (EM_QB) when the second node (SR_Q) is at a low voltage. Therefore, the first node first control unit (2553) performs the function of changing the voltage of the first node (EM_QB) to the high voltage (VGH). Meanwhile, the two electrodes of the 201 capacitor (Ca201) are respectively connected to the input and output electrodes of the 208 transistor (T208), so that the 201 capacitor (Ca201) is connected between the first node (EM_QB) and the high voltage (VGH) terminal. Therefore, the 201 capacitor (Ca201) serves to store and maintain the voltage of the first node (EM_QB).

[0103] Meanwhile, the first node second control unit (2554) includes two transistors (the 206th transistor (T206) and the 207th transistor (T207)) and one capacitor (the 202nd capacitor (Ca202)). The gate electrode of the 206th transistor (T206) is connected to the first clock input terminal (input terminal to which EM_CLK2 is applied in FIG. 6), the output electrode is connected to the first node (EM_QB), and the input electrode is connected to the fourth node (EM_C). The gate electrode of the 207th transistor (T207) is connected to the 3-1 node (SR_QB_F), the output electrode is connected to the fourth node (EM_C), and the input electrode is connected to the first clock input terminal (input terminal to which EM_CLK2 is applied in FIG. 6). The 211 transistor (T211) included in the first connection section (2558) receives a low voltage (VGL) at the control section, so the turn-on state is maintained, and thus the voltage of the 3-1 node (SR_QB_F) has the same voltage as the voltage of the 3rd node (SR_QB). Therefore, the 207 transistor (T207) is controlled by the 3rd node (SR_QB). Therefore, the 1st node 2nd control section (2554) plays the role of changing the voltage of the 1st node (EM_QB) to the low voltage of the clock signal (EM_CLK2) when the voltage of the 3rd node (SR_QB) and the clock signal (EM_CLK2) input to the 1st clock input section have a low voltage. Meanwhile, the 202nd capacitor (Ca202) is connected between the 3-1st node (SR_QB_F) and the 4th node (EM_C), and the voltage difference between the two nodes can be used to reduce the voltage change across the terminals.

[0104] We examine the second node first control unit (2555) that controls the voltage of the second node (SR_Q).

[0105] The second node first control unit (2555) is composed of a single transistor (the second 201 transistor (T201)). The gate electrode of the second 201 transistor (T201) is connected to the second clock input terminal (input terminal to which EM_CLK1 is applied in FIG. 6), the input electrode is connected to the start signal input terminal (input terminal to which the output of the start signal (FLM) signal or the stage for the light-emitting signal is input), and the output electrode is connected to the second node (SR_Q). When the clock signal (EM_CLK1) applied to the second clock input terminal (input terminal to which EM_CLK1 is applied in FIG. 6) is low voltage, the second 201 transistor (T201) changes the voltage of the second node (SR_Q) to the voltage of the start signal (FLM) or the output signal of the stage for the light-emitting signal. That is, the second node first control unit (2555) plays the role of changing the voltage of the second node (SR_Q) into a carry signal (start signal (FLM) or output signal of the stage for the preceding light-emitting signal) according to the clock signal (EM_CLK1).

[0106] The second 12th transistor (T212) included in the second connection part (2559) receives a low voltage (VGL) as a control unit, so the turn-on state is maintained, and thus the voltage of the second-1 node (SR_Q_F) has the same voltage as the voltage of the second node (SR_Q).

[0107] Since the voltage of the 2-1 node (SR_Q_F) is the voltage that controls the 210 transistor (T210) of the low-level output section (2552), the voltage of the 2-1 node (SR_Q_F) is stored and stabilized through the 2-1 node holding section (2556).

[0108] The 2-1 node holding section (2556) consists of two transistors (202 transistor (T202) and 203 transistor (T203)) and one capacitor (203 capacitor (Ca203)). The gate electrode of the 202 transistor (T202) is connected to the 3rd node (SR_QB), the input electrode is connected to the high voltage (VGH) terminal, and the output electrode is connected to the 5th node (EM_A). The gate electrode of the 203 transistor (T203) is connected to the 2-1 node (SR_Q_F), the input electrode is connected to the 5th node (EM_A), and the output electrode is connected to the 1st clock input terminal (in Fig. 6, the input terminal to which EM_CLK2 is applied). The 203 capacitor (Ca203) is connected to the input electrode and gate electrode of the 203 transistor (T203) and is connected between the 2-1 node (SR_Q_F) and the 5th node (EM_A). By means of the 203 capacitor (Ca203), the 2-1 node maintenance unit (2556) ensures that the voltage of the 2-1 node (SR_Q_F) is maintained constant with respect to the voltage of the 5th node (EM_A), which has a high voltage (VGH) or a clock signal (EM_CLK2) input to the 1st clock input terminal, thereby reducing the voltage variability of the 2-1 node (SR_Q_F).

[0109] We examine the third node control unit (2557) that controls the voltage of the third node (SR_QB).

[0110] The third node control unit (2557) consists of two transistors (the 204th transistor (T204) and the 205th transistor (T205)). The control terminal of the 204th transistor (T204) is connected to the second node (SR_Q), the input terminal is connected to the second clock input terminal (in Fig. 6, the input terminal to which EM_CLK1 is applied), and the output terminal is connected to the third node (SR_QB). According to Fig. 6, the 204th transistor (T204) includes two transistors, each having a control terminal connected to the second node (SR_Q) and operating identically, and has a structure in which the input terminal of one transistor and the output terminal of the other transistor are connected to the sixth node (EM_B). The control terminal of the 205 transistor (T205) is connected to the second clock input terminal (input terminal to which EM_CLK1 is applied in FIG. 6), the input terminal is connected to the low voltage (VGL) terminal, and the output terminal is connected to the third node (SR_QB). The 205 transistor (T205) serves to make the voltage of the third node (SR_QB) low voltage (VGL), and the 204 transistor (T204) serves to change the voltage of the third node (SR_QB) to the voltage of the clock signal (EM_CLK1) when the second node (SR_Q) has low voltage.

[0111] Meanwhile, the initialization unit (2560) includes one transistor (the 213th transistor (T213)) and serves to change the voltage of the second node (SR_Q) to a high voltage (VGH) by means of an ESR signal. That is, the control terminal of the 213th transistor (T213) receives the ESR signal, the input terminal is connected to the high voltage (VGH) terminal, and the output terminal is connected to the second node (SR_Q). Referring to FIG. 7, the ESR signal is a signal that initializes the light-emitting signal stage by having a low voltage when the light-emitting display device is first driven, and can eliminate the flickering phenomenon of pixels that may occur when the light-emitting display device is first driven. The ESR signal can be applied before the clock signals (EM_CLK1, EM_CLK2) are applied, so it has a low voltage before the clock signals (EM_CLK1, EM_CLK2) are applied, and can have a high voltage when the clock signals (EM_CLK1, EM_CLK2) begin to be applied.

[0112] Unlike what was explained above, the input electrode and output electrode can be named in reverse depending on the magnitude of the connected voltage.

[0113] The operation of the light-emitting signal stage having such a configuration is determined by the signals applied to the two clock input terminals and the start signal input terminal, to which two clock signals are respectively applied, and this is examined through FIG. 7.

[0114] FIG. 7 is a waveform diagram showing an input signal applied to a stage of a light emission control signal generation unit according to the embodiment of FIG. 6.

[0115] FIG. 7 illustrates a plurality of start signals (FLM) in addition to two clock signals (EM_CLK1, EM_CLK2) and an ESR signal. That is, the stage for the light emission signal is included in a first light emission control signal generator (EM1_D; 2001, 2005), a second light emission control signal generator (EM2_D; 2002, 2006), an initialization control signal generator (EB1_D; 2003, 2007), and a bias control signal generator (EB2_D; 2004, 2008), and since each generator outputs signals with different timings, different start signals (FLM) are provided for this purpose.

[0116] That is, when the stage for the light emission signal is used as the first light emission control signal generation unit (EM1_D; 2001, 2005), the EM1_FLM signal is input to the start signal input terminal of the stage for the light emission signal as a start signal (FLM) to generate the first light emission control signal (EM1) of FIG. 3. The EM1_FLM signal of FIG. 7 changes between high voltage and low voltage at the same interval as the first light emission control signal (EM1) of FIG. 3, and FIG. 3 also shows that time is required when changing between high voltage and low voltage due to delays, etc. The signal output from the stage for the light emission signal and the signal input to the start signal input terminal may have a time difference of 1H and may be signals having the same waveform. The first light emission control signal generation unit (EM1_D; 2001, 2005) includes a plurality of light emission signal stages, and is configured so that the output of the preceding light emission signal stage is transmitted to the first light emission control line (154) and also input to the start signal input terminal of the next stage light emission signal stage. Accordingly, the start signal input terminal of the first light emission signal stage receives the EM1_FLM signal as the start signal (FLM), but the start signal input terminal of the other light emission signal stages may also receive the output of the preceding light emission signal stage. As a result, the first light emission control signal generation unit (EM1_D; 2001, 2005) can sequentially output the first light emission control signal (EM1) of the same waveform at 1H from a plurality of stages based on the EM1_FLM signal.

[0117] In FIG. 7, the EM1_FLM signal of one frame sequentially has the intervals EM1_FLTE, EM1_FLWE1, and EM1_FLWE1, and the timing (V) at which the clock signals (EM_CLK1, EM_CLK2) begin to be applied syncThe EM1_FLTE section may start from ). During one frame, the EM1_FLM signal may have a high voltage during the EM1_FLTE section, then a low voltage during the EM1_FLTE section, then a high voltage during the EM1_FLWE1 section, and then a low voltage during the remaining section. When clock signals (EM_CLK1, EM_CLK2) begin to be applied, the clock signal (EM_CLK2) input to the first clock input terminal starts with a high voltage and alternately applies low voltage / high voltage, and the clock signal (EM_CLK1) input to the second clock input terminal starts with a low voltage and alternately applies high voltage / low voltage. In the embodiment where the voltage of the clock signal (EM_CLK1, EM_CLK2) changes every 1H, the EM1_FLTE, EM1_FLWE1, and EM1_FLWE1 sections may have widths of 10H, 2H, and 16H, respectively.

[0118] When the stage for the light emission signal is used as a second light emission control signal generation unit (EM2_D; 2002, 2006), the EM2_FLM signal is input to the start signal input terminal of the stage for the light emission signal as a start signal (FLM) to generate the second light emission control signal (EM2) of FIG. 3. The EM2_FLM signal of FIG. 7 changes between high voltage and low voltage at the same interval as the second light emission control signal (EM2) of FIG. 3, and FIG. 3 also shows that time is required when changing between high voltage and low voltage due to delays, etc. The signal output from the stage for the light emission signal and the signal input to the start signal input terminal may have a time difference of 1H and may be signals having the same waveform. The second light emission control signal generation unit (EM2_D; 2002, 2006) includes a plurality of light emission signal stages, and is configured so that the output of the preceding light emission signal stage is transmitted to the second light emission control line (155) and also input to the start signal input terminal of the next stage light emission signal stage. Accordingly, the start signal input terminal of the first light emission signal stage receives the EM2_FLM signal as the start signal (FLM), but the start signal input terminal of the other light emission signal stages may also receive the output of the preceding light emission signal stage. As a result, the second light emission control signal generation unit (EM2_D; 2002, 2006) can sequentially output a second light emission control signal (EM2) of the same waveform at 1H from a plurality of stages based on the EM2_FLM signal.

[0119] In FIG. 7, the EM2_FLM signal of one frame sequentially has the EM2_FLTE and EM2_FLWE intervals, and the timing (V) at which the clock signals (EM_CLK1, EM_CLK2) begin to be applied syncIt has an EM2_FLTE interval starting from ), and during one frame, the EM2_FLM signal has a low voltage during the EM2_FLTE interval, then has a high voltage during the EM2_FLWE interval, and then has a low voltage during the remaining interval. In an embodiment where the clock signals (EM_CLK1, EM_CLK2) have a voltage that changes every 1H, the EM2_FLM signal may have widths of 8H and 16H for the EM2_FLTE and EM2_FLWE intervals, respectively.

[0120] When the stage for the light-emitting signal is used as an initialization control signal generation unit (EB1_D; 2003, 2007), the EB1_FLM signal is input to the start signal input terminal of the stage for the light-emitting signal as a start signal (FLM) to generate the first initialization control signal (EB1(n)) of FIG. 3. The EB1_FLM signal of FIG. 7 changes between high voltage and low voltage at the same interval as the first initialization control signal (EB1(n)) of FIG. 3, and FIG. 3 also shows that time is required when changing between high voltage and low voltage due to delays, etc. The signal output from the stage for the light-emitting signal and the signal input to the start signal input terminal may have a time difference of 1H and may be signals having the same waveform. The initialization control signal generation unit (EB1_D; 2003, 2007) includes a plurality of light-emitting signal stages, and is configured so that the output of the preceding light-emitting signal stage is transmitted to the first initialization control line (153) and also input to the start signal input terminal of the next stage light-emitting signal stage. Accordingly, the start signal input terminal of the first light-emitting signal stage receives the EB1_FLM signal as the start signal (FLM), but the start signal input terminal of the other light-emitting signal stages may also receive the output of the preceding light-emitting signal stage. As a result, the initialization control signal generation unit (EB1_D; 2003, 2007) can output a first initialization control signal (EB1(n)) of the same waveform sequentially every 1H from a plurality of stages based on the EB1_FLM signal.

[0121] In FIG. 7, the EB1_FLM signal of one frame sequentially has the intervals EB1_FLTE, EB1_FLWE1, EB1_FLWE2, and EB1_FLWE3, and the timing (V) at which the clock signals (EM_CLK1, EM_CLK2) begin to be applied syncIt has an EB1_FLTE section starting from ), and during one frame, the EB1_FLTE section has a high voltage, the EB1_FLWE1 section has a low voltage, the EB1_FLWE2 section has a high voltage again, the EB1_FLWE3 section has a low voltage, and the remaining section has a high voltage. In an embodiment where the clock signal (EM_CLK1, EM_CLK2) has a voltage that changes every 1H, the EB1_FLM signal may have widths of 2H, 10H, 8H, and 6H for the EB1_FLTE, EB1_FLWE1, EB1_FLWE2, and EB1_FLWE3 sections, respectively.

[0122] Meanwhile, the initialization control signal generation unit (EB1_D; 2003, 2007) generates a second initialization control signal (EB1(n+1)) in addition to the first initialization control signal (EB1(n)) and applies it to the second initialization control line (153-1).

[0123] Here, the second initialization control signal (EB1(n+1)) is a signal output from the light-emitting signal stage of the next stage initialization control signal generation unit (EB1_D; 2003, 2007) after the first initialization control signal (EB1(n)). That is, the light-emitting signal stage of the initialization control signal generation unit (EB1_D; 2003, 2007) that generates the first initialization control signal (EB1(n)) is located ahead of the light-emitting signal stage of the initialization control signal generation unit (EB1_D; 2003, 2007) that generates the second initialization control signal (EB1(n+1)). Therefore, the first initialization control signal (EB1(n)) is a waveform that leads the second initialization control signal (EB1(n+1)) by 1H.

[0124] In this embodiment, the output signal of one light-emitting signal stage included in the initialization control signal generation unit (EB1_D; 2003, 2007) is transmitted to the start signal input terminal of the light-emitting signal stage of the next stage, the first initialization control line (153) of this stage, and the second initialization control line (153-1) of the previous stage.

[0125] When the stage for the light emission signal is used as a bias control signal generation unit (EB2_D; 2004, 2008), the EB2_FLM signal is input to the start signal input terminal of the stage for the light emission signal as a start signal (FLM) to generate the bias control signal (EB2(n)) of FIG. 3. The EB2_FLM signal of FIG. 7 changes between high voltage and low voltage at the same interval as the bias control signal (EB2(n)) of FIG. 3, and FIG. 3 also shows that time is required when changing between high voltage and low voltage due to delays, etc. The signal output from the stage for the light emission signal and the signal input to the start signal input terminal may have the same waveform and a time difference of 1H. The bias control signal generation unit (EB2_D; 2004, 2008) includes a plurality of light-emitting signal stages, and is configured so that the output of the preceding light-emitting signal stage is not only transmitted to the bias voltage line (179) but also input to the start signal input terminal of the next stage light-emitting signal stage. Accordingly, the start signal input terminal of the first light-emitting signal stage receives the EB2_FLM signal as the start signal (FLM), but the start signal input terminal of the other light-emitting signal stages can also receive the output of the preceding light-emitting signal stage. As a result, the bias control signal generation unit (EB2_D; 2004, 2008) can output a bias control signal (EB2(n)) of the same waveform sequentially every 1H from a plurality of stages based on the EB2_FLM signal.

[0126] In FIG. 7, the EB2_FLM signal of one frame sequentially has the intervals EB2_FLTE and EB2_FLWE, and the timing (V) at which the clock signals (EM_CLK1, EM_CLK2) begin to be applied syncIt has an EB2_FLTE section starting from ), and during one frame, the EB2_FLTE section has a high voltage, the EB2_FLWE section has a low voltage, and the remaining section has a high voltage. In an embodiment where the clock signals (EM_CLK1, EM_CLK2) have a voltage that changes every 1H, the EB2_FLM signal may have widths of 20H and 2H for the EB2_FLTE and EB2_FLWE sections, respectively.

[0127] We will examine the operation of the stage for the light emission signal of Fig. 6 according to the waveform of Fig. 7.

[0128] Since the operation of each signal generation unit is similar, the process is broadly classified into cases where the start signal (FLM) for the light emission signal stage has high voltage and cases where it has low voltage, and the operation is examined in each classification as the voltage level of the clock signal changes.

[0129] First, we examine the operation in the case where a high voltage is applied to the start signal input terminal of the light-emitting signal stage, and the clock signal (EM_CLK2) input to the first clock input terminal has a high voltage and the clock signal (EM_CLK1) input to the second clock input terminal has a low voltage (hereinafter referred to as the first case).

[0130] Due to the high voltage clock signal (EM_CLK2), the 206 transistor (T206) is turned off, and the 1 node (EM_QB) is not changed to a low voltage.

[0131] The 201 transistor (T201) and the 205 transistor (T205) are turned on due to a low voltage clock signal (EM_CLK1).

[0132] A high voltage input to the start signal input terminal through the 201 transistor (T201) is applied to the 2nd node (SR_Q) and the 2-1 node (SR_Q_F), causing the 2nd node (SR_Q) and the 2-1 node (SR_Q_F) to change to a high voltage. Due to the high voltage of the 2-1 node (SR_Q_F), the 210 transistor (T210) is turned off. Additionally, due to the high voltage of the 2nd node (SR_Q), the 208 transistor (T208), the 204 transistor (T204), and the 203 transistor (T203) are turned off.

[0133] Meanwhile, since the 205th transistor (T205) is turned on, a low voltage (VGL) is applied to the 3rd node (SR_QB) and the 3-1st node (SR_QB_F). At this time, the 204th transistor (T204) is turned off because the 2nd node (SR_Q) has a high voltage, so the voltages of the 3rd node (SR_QB) and the 3-1st node (SR_QB_F) are controlled by the 205th transistor (T205) and changed to a low voltage (VGL).

[0134] Due to the low voltage of the third node (SR_QB), the second 202 transistor (T202) is turned on, and a high voltage (VGH) is applied to the fifth node (EM_A), becoming the voltage of one terminal of the second 203 capacitor (Ca203), and boosts the high voltage of the second node (SR_Q) and the second-1 node (SR_Q_F) so that the voltage of the second node (SR_Q) and the second-1 node (SR_Q_F) does not drop. At this time, the second 203 transistor (T203) is in a turned-off state.

[0135] Due to the low voltage of the 3-1 node (SR_QB_F), the 207 transistor (T207) is turned on. When the 207 transistor (T207) is turned on, a high-voltage clock signal (EM_CLK2) is applied to the 4th node (EM_C). As a result, a high voltage (4th node (EM_C)) and a low voltage (3-1 node (SR_QB_F)) are applied across the 202 capacitor (Ca202). Additionally, although the 207 transistor (T207) is turned on, the 206 transistor (T206) is turned off, so the voltage of the 1st node (EM_QB) is not changed. Also, since the 208 transistor (T208) is turned off, the voltage of the 1st node (EM_QB) is not changed to a high voltage (VGH) and maintains the existing voltage level.

[0136] That is, in the case where the stage for the light emission signal is in the first case, the voltage of the first node (EM_QB) is not changed and maintains the existing voltage level. For example, if the stage for the light emission signal was outputting a high voltage (VGH) through the 209 transistor (T209), it can continue to output the high voltage (VGH). At this time, since the second node (SR_Q) and the 2-1 node (SR_Q_F) have high voltages, a low voltage is not output through the 210 transistor (T210).

[0137] Let us examine the second case of the stage for the light emission signal. That is, we examine the operation of the case where a high voltage is applied to the start signal input terminal of the stage for the light emission signal, and the clock signal (EM_CLK2) input to the first clock input terminal has a low voltage, and the clock signal (EM_CLK1) input to the second clock input terminal has a high voltage (hereinafter referred to as the second case).

[0138] First, the 201 transistor (T201) and the 205 transistor (T205) are turned off due to a high-voltage clock signal (EM_CLK1).

[0139] The 201 transistor (T201) is turned off so that the voltages of the 2nd node (SR_Q) and the 2-1 node (SR_Q_F) are not changed. Additionally, the 205 transistor (T205) is turned off so that the voltages of the 3rd node (SR_QB) and the 3-1 node (SR_QB_F) are not changed.

[0140] Meanwhile, the 206 transistor (T206) is turned on due to the low-voltage clock signal (EM_CLK2). At this time, the 207 transistor (T207) is turned on by the voltage of the 3-1 node (SR_QB_F), that is, the voltage stored in the 202 capacitor (Ca202). As a result, the low-voltage clock signal (EM_CLK2) is applied to the 1 node (EM_QB) and changed to a low voltage.

[0141] Therefore, in the case where the stage for the light emission signal is the second case, the voltage of the first node (EM_QB) is changed to a low voltage, and the output of a high voltage (VGH) is started through the second 209 transistor (T209).

[0142] Meanwhile, the second node (SR_Q) and the second-1 node (SR_Q_F) maintain the previously stored voltage, so the second 210 transistor (T210) continues its previously performed operation and does not output a low voltage.

[0143] We examine the third case of the stage for the light emission signal. That is, we examine the operation of the case where a low voltage is applied to the start signal input terminal of the stage for the light emission signal, and the clock signal (EM_CLK2) input to the first clock input terminal has a high voltage and the clock signal (EM_CLK1) input to the second clock input terminal has a low voltage (hereinafter referred to as the third case).

[0144] Due to the high voltage clock signal (EM_CLK2), the 206 transistor (T206) is turned off, and the 1 node (EM_QB) is not changed to a low voltage.

[0145] The 201 transistor (T201) and the 205 transistor (T205) are turned on due to a low voltage clock signal (EM_CLK1).

[0146] A low voltage input to the start signal input terminal through the 201 transistor (T201) is applied to the 2nd node (SR_Q) and the 2-1 node (SR_Q_F), causing the 2nd node (SR_Q) and the 2-1 node (SR_Q_F) to change to a low voltage. Due to the low voltage of the 2-1 node (SR_Q_F), the 210 transistor (T210) turns on and begins to output a low voltage (VGL).

[0147] In addition, due to the low voltage of the second node (SR_Q), the 208 transistor (T208), the 204 transistor (T204), and the 203 transistor (T203) are turned on. Among these, since the 208 transistor (T208) is turned on, the first node (EM_QB) is changed to a high voltage (VGH), and the 209 transistor (T209) is changed to a turned-off state.

[0148] Meanwhile, as the 205th transistor (T205) is turned on, a low voltage (VGL) is applied to the 3rd node (SR_QB) and the 3-1st node (SR_QB_F). At this time, the 204th transistor (T204) is also turned on by the low voltage of the 2nd node (SR_Q), and the voltages of the 3rd node (SR_QB) and the 3-1st node (SR_QB_F) are controlled by the 205th transistor (T205) and the 204th transistor (T204) and are changed to a low voltage (VGL).

[0149] Due to the low voltage of the third node (SR_QB), the 202 transistor (T202) is turned on, and due to the low voltage of the second node (SR_Q), the 203 transistor (T203) is turned on, and the high voltage (VGH) and clock signal (EM_CLK2) are applied to the fifth node (EM_A). As a result, the voltage at one terminal of the 203 capacitor (Ca203) becomes high voltage, and it serves to store and maintain the low voltage of the second node (SR_Q) and the second-1 node (SR_Q_F).

[0150] Due to the low voltage of the 3-1 node (SR_QB_F), the 207 transistor (T207) is turned on. However, since the 206 transistor (T205) is turned off, it does not change the voltage of the 1 node (EM_QB).

[0151] That is, in the case where the stage for the light emission signal is the third case, the voltage of the first node (EM_QB) is changed to a high voltage (VGH) so that the 209 transistor (T209) does not operate, and the second node (SR_Q) and the 2-1 node (SR_Q_F) are changed to a low voltage so that a low voltage (VHL) begins to be output through the 210 transistor (T210).

[0152] Let us examine the fourth case of the stage for the light-emitting signal. That is, the operation of the case in which a low voltage is applied to the start signal input terminal of the stage for the light-emitting signal, and the clock signal (EM_CLK2) input to the first clock input terminal has a low voltage and the clock signal (EM_CLK1) input to the second clock input terminal has a high voltage (hereinafter referred to as the fourth case) is examined.

[0153] First, the 201 transistor (T201) and the 205 transistor (T205) are turned off due to a high-voltage clock signal (EM_CLK1).

[0154] The 201 transistor (T201) is turned off so that the voltages of the 2nd node (SR_Q) and the 2-1 node (SR_Q_F) are not changed. Additionally, the 205 transistor (T205) is turned off so that the voltages of the 3rd node (SR_QB) and the 3-1 node (SR_QB_F) are not changed.

[0155] Meanwhile, the 206 transistor (T206) is turned on due to the low-voltage clock signal (EM_CLK2). At this time, the 207 transistor (T207) is turned on by the voltage of the 3-1 node (SR_QB_F), that is, the voltage stored in the 202 capacitor (Ca202). As a result, the low-voltage clock signal (EM_CLK2) can be applied, but the 208 transistor (T208) remains turned on due to the low voltage of the 2nd node (SR_Q), so the 1st node (EM_QB) continues to have a high voltage (VGH) applied and the voltage does not fluctuate.

[0156] Therefore, in the case where the stage for the light emission signal is the fourth case, the voltage of the first node (EM_QB) is maintained at a high voltage so that the 209 transistor (T209) does not operate, and the second node (SR_Q) and the 2-1 node (SR_Q_F) maintain the previously stored low voltage, so the 210 transistor (T210) continues the previously performed operation and outputs a low voltage.

[0157] Through the basic operation described above, the signal input to the input terminal can be output with a 1H delay.

[0158] V in Fig. 7 sync indicates the position where clock signals (EM_CLK1, EM_CLK2) begin to be applied to the light-emitting display device, and the EM1_FLM signal is set to apply high voltage immediately. However, according to the embodiment, V sync The position of can vary. However, the ESR signal is before the clock signals (EM_CLK1, EM_CLK2) are applied, i.e., V sync It is located to the left.

[0159] FIG. 7 illustrates that when clock signals (EM_CLK1, EM_CLK2) begin to be applied, the clock signal (EM_CLK2) input to the first clock input terminal starts at a high voltage and alternately applies low voltage and high voltage, and the clock signal (EM_CLK1) input to the second clock input terminal starts at a low voltage and alternately applies high voltage and low voltage, and the voltage of the clock signals (EM_CLK1, EM_CLK2) changes every 1H. However, depending on the embodiment, the starting voltage may be different or the interval of variation may be different.

[0160] Below, we examine a structure in which a stage for a light-emitting signal, such as that of Fig. 6, is actually formed on a substrate using Figs. 8 to 10.

[0161] FIG. 8 is a layout diagram illustrating a structure in which two stages of a light emission control signal generation unit are flip-arranged according to one embodiment, and FIG. 9 and FIG. 10 are cross-sectional views cut along the cross-sectional lines IX-IX and XX of FIG. 8.

[0162] Referring to Fig. 8, a structure is illustrated in which two stages for light-emitting signals are arranged on the left and right sides while sharing input signal lines.

[0163] For reference, in Fig. 8, the mark with an x ​​inside the square indicates an opening located in the insulating film, allowing the upper conductive layer and the lower conductive layer to be electrically connected.

[0164] Since the stage for the light emission signal can be included in the first light emission control signal generation unit (EM1_D; 2001, 2005), the second light emission control signal generation unit (EM2_D; 2002, 2006), the initialization control signal generation unit (EB1_D; 2003, 2007), and the bias control signal generation unit (EB2_D; 2004, 2008), the four generation units can be divided into two pairs and configured to be located on the left and right sides while sharing signal lines as shown in FIG. 8. According to an embodiment, a stage for a light-emitting signal belonging to a first light-emitting control signal generating unit (EM1_D; 2001, 2005) and a stage for a light-emitting signal belonging to a second light-emitting control signal generating unit (EM2_D; 2002, 2006) may share a signal line with each other, and a stage for a light-emitting signal belonging to an initialization control signal generating unit (EB1_D; 2003, 2007) and a stage for a light-emitting signal belonging to a bias control signal generating unit (EB2_D; 2004, 2008) may share a signal line with each other.

[0165] In the embodiment of FIG. 8, there are three shared signal lines, each consisting of an ESR wire (2105) to which an ESR signal is applied, a first clock wire (2104) to which a CLK2 clock signal is applied, and a second clock wire (2103) to which a CLK1 clock signal is applied.

[0166] The structure is as follows, focusing on the stage for the light-emitting signal located on the left side of Fig. 8.

[0167] Each transistor included in the stage for the light-emitting signal comprises a semiconductor layer located on a substrate (110), a first gate insulating film (141), and a gate electrode, as shown in FIG. 10. A channel is located in the portion where the semiconductor layer and the gate electrode overlap, and a source region and a drain region are located on both sides of the channel in the semiconductor layer, which are made conductive by plasma treatment or doping. The layered structure consists of a substrate (110), a semiconductor layer, a first gate insulating film (141), a first gate conductive layer, a second gate insulating film (142), a second gate conductive layer, a first interlayer insulating film (143), a source / drain conductive layer, and a second interlayer insulating film (144). The first gate conductive layer contains the gate electrodes of all transistors.

[0168] The gate electrode (G201) of the 201st transistor (T201) is extended and electrically connected to the second clock wiring (2103) to which the CLK1 clock signal is applied. The channel, source, and drain regions are located in the semiconductor layer (C201). One side of the semiconductor layer (C201) is electrically connected to a connection line (2205) to which the output of a stage for a start signal (FLM) or a front-end light emission signal is transmitted, and the other side is connected to a connection part (2301) that is electrically connected to the gate electrode (G204) of the 204th transistor (T204). The connection part (2301) is located in the source / drain conductive layer.

[0169] The gate electrode (G202) of the 202nd transistor (T202) is extended and electrically connected to a connection portion (2302) that connects the 204th transistor (T204) and the 211th transistor (T211). One side of the semiconductor layer (C202) is electrically connected to a high-voltage wiring (2101) to which a high voltage (VGH) is applied, and the other side is electrically connected to a connection portion (2303) that is electrically connected to the 203rd capacitor (Ca203). The connection portion (2303) is located in the source / drain conductive layer. The semiconductor layer (C202) has both ends extended and connected to the semiconductor layer (C203) of the 203rd transistor (T203), the semiconductor layer (C208) of the 208th transistor (T208), the semiconductor layer (C213) of the 213th transistor (T213), and the semiconductor layer (C212) of the 212th transistor (T212).

[0170] The gate electrode (G203) of the 203rd transistor (T203) is extended to form one electrode of the 203rd capacitor (Ca203), and is further extended to the gate electrode of the 210th transistor (T210). One side of the semiconductor layer (C203) is connected to a connection part (2303) and is also connected to one side of the 202nd transistor (T202), and the other side is electrically connected to a connection part (2304) which is electrically connected to the 207th transistor (T207). The connection part (2304) is located in the source / drain conductive layer.

[0171] The gate electrode (G204) of the 204th transistor (T204) is composed of two parts and extends to the gate electrode (G208) of the 208th transistor (T208), and is electrically connected to one side of the 212th transistor (T212) and one side of the 213th transistor (T213) through a connection part (2305). One side of the semiconductor layer (C204) is connected to one side of the 201st transistor (T201) via a connection part (2301), and the other side is electrically connected to one end of the 205th transistor (T205) and the 211th transistor (T211) via a connection part (2306). The connection parts (2305, 2306) are located in the source / drain conductive layer.

[0172] The gate electrode (G205) of the 205th transistor (T205) is extended and electrically connected to the second clock wiring (2103) to which the CLK1 clock signal is applied. One side of the semiconductor layer (C205) is electrically connected to the low voltage wiring (2102) to which the low voltage (VGL) is applied, and the other side is electrically connected to one end of the 204th transistor (T204) and the 211th transistor (T211) through the connection part (2306).

[0173] The gate electrode (G206) of the 206th transistor (T206) is extended and electrically connected to the first clock wiring (2104) to which the CLK2 clock signal is applied, and is also connected to the connection part (2304) and electrically connected to one end of the 203rd transistor (T203) and the 207th transistor (T207). One side of the semiconductor layer (C206) is connected to the connection part (2307) and is connected to one side of the 208th transistor (T208), and the other side is electrically connected to one side of the 207th transistor (T207) and the 202nd capacitor (Ca202) by the connection part (2308). The connection parts (2307, 2308) are located in the source / drain conductive layer.

[0174] The gate electrode (G207) of the 207th transistor (T207) is extended to form one electrode of the 202nd capacitor (Ca202), and is also extended to the other side and connected to the connection part (2309) and connected to one end of the 211th transistor (T211). One side of the semiconductor layer (C207) is connected to the connection part (2304) and connected to the gate electrode (G206) of the 206th transistor (T206) and one end of the 203rd transistor (T203). The other side is connected to the connection part (2308) and is electrically connected to one side of the 206th transistor (T206) and the 202nd capacitor (Ca202).

[0175] The gate electrode (G208) of the 208th transistor (T208) is extended to the gate electrode (G204) of the 204th transistor (T204) and is electrically connected to one side of the 212th transistor (T212) and one side of the 213th transistor (T213) through the connection portion (2305). One side of the semiconductor layer (C208) is connected to the connection portion (2307) and is connected to one side of the 206th transistor (T206), and the other side is electrically connected to a high-voltage wiring (2101) to which a high voltage (VGH) is applied, and is extended to one end of the 202nd transistor (T202) and the 213th transistor (T213).

[0176] The gate electrode (G209) of the 209th transistor (T209) is divided into multiple parts (composed of three gate electrodes in FIG. 11) and is extended to be connected to the 201st capacitor (Ca201). One side of the semiconductor layer (C209) is electrically connected to the high-voltage wiring (2101), and the other side is connected to the output wiring (2201).

[0177] The gate electrode (G210) of the 210th transistor (T210) is divided into multiple parts (composed of three gate electrodes in FIG. 11) and is extended to be connected to one end of the 203rd capacitor (Ca203) and the 212th transistor (T212). One side of the semiconductor layer (C210) is electrically connected to the low-voltage wiring (2102), and the other side is connected to the output wiring (2201).

[0178] The output wiring (2201) is electrically connected to a connecting line (2202) extending to a signal line, and the connecting line (2202) is formed in the second gate conductive layer.

[0179] The gate electrode (G211) of the 211th transistor (T211) is extended and passes through the gate electrode (G212) of the 212th transistor (T212) to be electrically connected to the low-voltage wiring (2102), and one side of the semiconductor layer (C211) is connected to the connection part (2309) and connected to one end of the 207th transistor (T207), and the other side is connected to the connection part (2302) and connected to one end of the 204th transistor (T204) and the 205th transistor (T205).

[0180] The gate electrode (G212) of the 212th transistor (T212) is extended and electrically connected to the low-voltage wiring (2102), and one side of the semiconductor layer (C212) is electrically connected to the gate electrode (G210) of the 210th transistor (T210), and the other side is extended and connected to the semiconductor layer (C213) of the 213th transistor (T213), and is connected to the gate electrodes of the 204th transistor (T204) and the 208th transistor (T208) through the connection part (2305).

[0181] The gate electrode (G213) of the 213th transistor (T213) is extended and electrically connected to the ESR wiring (2105), one side of the semiconductor layer (C213) is electrically connected to the high voltage wiring (2101), and the other side is extended and connected to the semiconductor layer (C213) of the 212th transistor (T212).

[0182] The capacitor (Ca201, Ca202, Ca203) has a cross-sectional structure in which the first gate conductive layer and the second gate conductive layer are the two electrodes, and the second gate insulating film (142) located between them is the dielectric.

[0183] One electrode (2212) of the 201 capacitor (Ca201) is connected to the high-voltage wiring (2101), and the other electrode (2211) is extended and connected to the gate electrode (G209) of the 209 transistor (T209), the 206 transistor (T206), and one end of the 208 transistor (T208).

[0184] One electrode (2222) of the 202 capacitor (Ca202) is connected to one end of the 206 transistor (T206) and the 207 transistor (T207) by means of a connection part (2308), and the other electrode (2221) is extended and connected to the gate electrode (G207) of the 207 transistor (T207).

[0185] The 203 capacitor (Ca203) has one electrode (2232) connected to one end of the 202 transistor (T202) and the 203 transistor (T203) by means of a connection part (2303), and the other electrode (2231) is extended and connected to the gate electrode (G203) of the 203 transistor (T203) and the gate electrode (G210) of the 210 transistor (T210).

[0186] In the embodiment of FIG. 8, there are three shared signal lines, each consisting of an ESR wiring (2105) to which an ESR signal is applied, a first clock wiring (2104) to which a CLK2 clock signal is applied, and a second clock wiring (2103) to which a CLK1 clock signal is applied. Additionally, in the embodiment of FIG. 8, the first clock wiring (2104) and the second clock wiring (2103) are formed in a source / drain conductive layer and are formed as a single layer.

[0187] However, according to the embodiment, the first clock wiring (2104) and the second clock wiring (2103) are formed as a double layer. This is examined through FIGS. 11 to 13.

[0188] FIG. 11 is a layout diagram illustrating a structure in which two stages of a light emission control signal generation unit are flip-arranged according to another embodiment, and FIG. 12 and FIG. 13 are cross-sectional views cut along the cross-sectional lines XII-XII and XIII-XIII of FIG. 11.

[0189] For reference, in Fig. 11, the mark with an x ​​inside the square indicates an opening located in the insulating film, allowing the upper conductive layer and the lower conductive layer to be electrically connected.

[0190] The differences from the embodiments of FIGS. 8 to 10 are explained below, focusing on the differences.

[0191] The embodiments of FIGS. 11 to 13 further include a second source / data conductive layer. As a result, an organic protective film (145) covering the second source / data conductive layer is also further included.

[0192] That is, the layered structure is composed of a substrate (110), a semiconductor layer, a first gate insulating layer (141), a first gate conductive layer, a second gate insulating layer (142), a second gate conductive layer, a first interlayer insulating layer (143), a source / drain conductive layer (also called a first source / drain conductive layer), a second interlayer insulating layer (144), a second source / data conductive layer, and an organic protective layer (145).

[0193] In this embodiment, the first clock wiring (2104) and the second clock wiring (2103) are located in the first source / drain conductive layer. The first-2 clock wiring (2253) and the second-2 clock wiring (2254) are located in the second source / data conductive layer and are electrically connected to the first clock wiring (2104) and the second clock wiring (2103), respectively.

[0194] As shown in Figures 11 to 13, forming the clock wiring in a double layer has the advantage of reducing RC delay because the resistance is lower than when it is formed in a single layer.

[0195] In the embodiments of FIGS. 8 to 13, an embodiment is described in which the signal lines shared between two adjacent light-emitting signal stages are an ESR wiring (2105), a first clock wiring (2104), and a second clock wiring (2103).

[0196] However, depending on the embodiment, there may be more or fewer signal lines between two adjacent light-emitting signal stages.

[0197] Below, we examine an embodiment in which two adjacent light-emitting signal stages share a total of four input signal lines through FIG. 14.

[0198] FIG. 14 is a simplified diagram illustrating a structure in which two stages of a light emission control signal generation unit are commonly connected to an input signal line according to another embodiment.

[0199] FIG. 14 is illustrated as an embodiment in which two adjacent light-emitting signal stages are each included in a first light-emitting control signal generating unit (EM1_D; 2001) and a second light-emitting control signal generating unit (EM2_D; 2002).

[0200] In addition, in FIG. 14, a low-voltage wiring (2102) is further added as an input signal line shared by the light-emitting signal stage. That is, it is illustrated that two adjacent light-emitting signal stages share the low-voltage wiring (2102), ESR wiring (2105), first clock wiring (2104), and second clock wiring (2103).

[0201] Although FIG. 14 illustrates that the light-emitting signal stages included in the first light-emitting control signal generation unit (EM1_D; 2001) and the second light-emitting control signal generation unit (EM2_D; 2002) share input signal lines with each other, depending on the embodiment, the light-emitting signal stages belonging to the initialization control signal generation unit (EB1_D; 2003, 2007) and the bias control signal generation unit (EB2_D; 2004, 2008) may share input signal lines with each other.

[0202] In addition, the stages for the light emission signal on both the left and right sides of the display area (DA) may share input signal lines with each other.

[0203] As described above, if two adjacent light-emitting signal stages share input signal lines, the width occupied by the driving unit (200, 250) can be reduced, and as a result, the area of ​​the driving unit (200, 250) is also reduced, which has the advantage of reducing the area.

[0204] In the above, we have examined a signal generation unit including a first stage (stage for light emission signal) through FIGS. 6 to 14. Below, we will examine a scan signal generation unit including a second stage (also called a stage for scan signal) through FIGS. 15 to 20.

[0205] The pixel illustrated in FIG. 2 needs to receive a first scan signal (GW(n)) and a second scan signal (GC(n)) from two scan signal generating units (a first scan signal generating unit (GW_D; 3001, 3003), a second scan signal generating unit (GC_D; 3002, 3004)). Accordingly, the following will focus on the scan signal stage through FIG. 15 to FIG. 20.

[0206] First, let's look at the circuit configuration of a single scan signal stage through Fig. 15.

[0207] FIG. 15 is a circuit diagram illustrating one stage constituting a scan signal generating unit among the driving units of a non-display area according to one embodiment.

[0208] Each scan signal stage according to the present embodiment includes a high-level output unit (3551), a low-level output unit (3552), a first node first control unit (3555), a first node second control unit (3556), a second node first control unit (3553), a second node second control unit (3554), and a first connection unit (3557).

[0209] The core structure of each scan signal stage is as follows.

[0210] The high-level output section (3551) is a section that outputs the high voltage (VGH) of the scan signal, and the low-level output section (3552) is a section that outputs the low voltage (VGL) of the scan signal. The high-level output section (3551) and the low-level output section (3552) are connected to an output terminal (Out). When the high voltage (VGH) is output from the high-level output section (3551), the low-level output section (3552) does not output, and when the low voltage (VGL) is output from the low-level output section (3552), the high-level output section (3551) does not output.

[0211] The high-level output unit (3551) is controlled according to the voltage of the first node (QB), and the voltage of the first node (QB) is controlled by the first node first control unit (3555) and the first node second control unit (3556).

[0212] The low-level output section (3552) is controlled according to the voltage of the second node (Q), and the voltage of the second node (Q) is controlled by the second node first control section (3553) and the second node second control section (3554). Specifically, the low-level output section (2552) is connected to the second node (Q) by the first connection section (3557) and is controlled according to the voltage of the second-1 node (QF). However, since the 308 transistor (T308) included in the first connection section (3557) receives a low voltage (VGL) as a control terminal and maintains a turned-on state, the low-level output section (3552) is effectively controlled according to the voltage of the second node (Q).

[0213] The scan signal stage of FIG. 15 receives two clock signals (CLK1, CLK2), and the scan signal stage of the next row is connected so that the two clock signals are input interchangeably. Additionally, although the scan signal stage of FIG. 15 is shown receiving a start signal (FLM signal) through the input terminal, if there is a preceding scan signal stage (previous scan signal stage), the output of the preceding scan signal stage can be input to the input terminal.

[0214] A detailed look at each part of the stage for each scan signal is as follows.

[0215] The high-level output section (3551) includes a 306 transistor (T306) and a 301 capacitor (Ca301). The gate electrode of the 306 transistor (T306) is connected to the first node (QB), the input electrode is connected to the high voltage (VGH) terminal, and the output electrode is connected to the output terminal (Out). As a result, when the voltage of the first node (QB) is low, the high voltage (VGH) is output to the output terminal (Out), and when the voltage of the first node (QB) is high, the 306 transistor (T306) is turned off and does not produce any output. One end of the 301 capacitor (Ca301) is connected to the first node (QB) to apply the high voltage (VGH), and the other end is connected to the first node (QB) to maintain the voltage of the first node (QB).

[0216] The low-level output section (3552) includes a 307 transistor (T307) and a 302 capacitor (Ca302). The gate electrode of the 307 transistor (T307) is connected to the 2-1 node (QF), the input electrode is connected to the 1st input terminal to which the 1st clock signal (CLK1) is applied, and the output electrode is connected to the output terminal (Out). As a result, when the voltage of the 2-1 node (QF) is low voltage, the voltage of the 1st clock signal (CLK1) is output to the output terminal (Out), and when the voltage of the 2-1 node (QF) is high voltage, the 307 transistor (T307) does not produce any output. Here, for the second-1 node (QF) to be at a low voltage, the second node (Q) must receive a low voltage as a start signal (FLM), and the low voltage applied to the second-1 node (QF) is stored in the third-02 capacitor (Ca302), and at this time, the voltage of the first clock signal (CLK1) is output to the output terminal (Out). The third-08 transistor (T308) included in the first connection section (3557) receives a low voltage (VGL) as a control terminal, so the turn-on state is maintained, and thus the voltage of the second-1 node (QF) has the same voltage as the voltage of the second node (Q). Therefore, the low-level output section (3552) is controlled by the second node (SR_Q). One end of the 302 capacitor (Ca302) is connected to the output terminal (Out), and the other end is connected to the 2-1 node (QF), serving to store and maintain the voltage of the 2-1 node (QF).

[0217] We examine the first node first control unit (3555) and the first node second control unit (3556) that control the voltage of the first node (QB).

[0218] The first node first control unit (3555) includes the 304 transistor (T304). The gate electrode of the 304 transistor (T304) is connected to the second node (Q), the input electrode is connected to the first input terminal to which the second clock signal (CLK2) is applied, and the output electrode is connected to the first node (QB). As a result, the voltage of the first node (QB) is changed by being controlled according to the voltage of the second node (Q), and in this embodiment, the voltage of the first node (QB) is changed to the high voltage of the clock signal.

[0219] The first node second control unit (3556) includes the third 05 transistor (T305). The gate electrode of the third 05 transistor (T305) is connected to the first input terminal to which the second clock signal (CLK2) is applied, the input electrode receives a low voltage (VGL), and the output electrode is connected to the first node (QB). As a result, the voltage of the first node (QB) is changed to a low voltage (VGL) according to the second clock signal (CLK2) input to the first input terminal.

[0220] We examine the second node first control unit (3553) and the second node second control unit (3554) that control the voltage of the second node (Q).

[0221] The second node first control unit (3553) includes a 301 transistor (T301). The gate electrode of the 301 transistor (T301) is connected to a first input terminal to which a second clock signal (CLK2) is applied, the input electrode is connected to a start signal input terminal (an input terminal to which the output of a stage for a start signal (FLM) signal or a front-end scan signal is input), and the output electrode is connected to the second node (Q). The 301 transistor (T301) may be composed of two transistors, the gate electrodes are connected to the first input terminal in the same way, the input electrode of one transistor is connected to the start signal input terminal, and the output electrode of the other transistor is connected to the second node (Q), and the output electrode of the one transistor and the input electrode of the other transistor may be connected to each other. As a result, the voltage of the second node (Q) is changed to a voltage input to the start signal input terminal according to the second clock signal (CLK2) input to the first input terminal.

[0222] The second node second control unit (3554) includes the 302 transistor (T302) and the 303 transistor (T303). The gate electrode of the 302 transistor (T302) is connected to the first node (QB), the input electrode is applied to a high voltage (VGH), and the output electrode is connected to the input electrode of the 303 transistor (T303). The gate electrode of the 303 transistor (T303) is connected to the second input terminal to which the first clock signal (CLK1) is applied, the input electrode is connected to the output electrode of the 302 transistor (T302), and the output electrode is connected to the second node (Q). As a result, when the first node (QB) is at a low voltage and the first clock signal (CLK1) is at a low voltage, the second node (Q) changes to a high voltage (VGH). Accordingly, when the first node (QB) is at low voltage (VGL), the voltage of the second node (Q) has a high voltage (VGH) value.

[0223] Unlike what was explained above, the input electrode and output electrode can be named in reverse depending on the magnitude of the connected voltage.

[0224] The operation of a scan signal stage having a circuit configuration as shown in Fig. 15 is determined by the signal applied to the two clock input terminals and the start signal input terminal, to which two clock signals are respectively applied.

[0225] First, we will examine the operation of the scan signal stage included in the first scan signal generating unit (GW_D; 3001, 3003) and the second scan signal generating unit (GC_D; 3002, 3004) that generates the first scan signal (GW(n)) and the second scan signal (GC(n)) when the signal shown in FIG. 3 is applied to the pixel through FIG. 16.

[0226] FIG. 16 is a waveform diagram showing an input signal applied to a stage of a scan signal generation unit according to the embodiment of FIG. 15.

[0227] In FIG. 16, a start signal (GW_FLM) and clock signals (GW_CLK1, GW_CLK2) applied to a first scan signal generator (GW_D; 3001, 3003) and a start signal (GC_FLM) and clock signals (GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, GC_CLK6) applied to a second scan signal generator (GC_D; 3002, 3004) are respectively illustrated. In the embodiment of FIG. 16, even though the start signal (GW_FLM) and clock signals (GW_CLK1, GW_CLK2) applied to the first scan signal generator (GW_D; 3001, 3003) and the second scan signal generator (GC_D; 3002, 3004) include a scan signal stage with the same circuit structure as illustrated in FIG. 15, the clock signals are different. As a result, the scan signal stages included in the first scan signal generator (GW_D; 3001, 3003) and the second scan signal generator (GC_D; 3002, 3004) cannot share clock signals with each other.

[0228] When the scan signal stage is used as the first scan signal generation unit (GW_D; 3001, 3003), the GW_FLM signal is input to the start signal input terminal of the scan signal stage as a start signal (FLM) to generate the first scan signal (GW(n)) of FIG. 3. The GW_FLM signal of FIG. 16, like the first scan signal (GW(n)) of FIG. 3, has a low voltage for only 1H of a frame and a high voltage during the remaining period, and FIG. 3 also shows that time is required when changing between high and low voltages due to delays, etc. The signal output from the scan signal stage and the signal input to the start signal input terminal may have the same waveform and have a time difference of 1H. The first scan signal generation unit (GW_D; 3001, 3003) includes a plurality of scan signal stages, and is configured so that the output of the preceding scan signal stage is not only transmitted to the first scan line (151) but also input to the start signal input terminal of the next scan signal stage. Accordingly, the start signal input terminal of the first scan signal stage receives the GW_FLM signal as the start signal (FLM), but the start signal input terminal of the other scan signal stages may also receive the output of the preceding scan signal stage. As a result, the first scan signal generation unit (GW_D; 3001, 3003) can output a first scan signal (GW(n)) of the same waveform sequentially every 1H from a plurality of stages based on the GW_FLM signal.

[0229] Referring to FIG. 16, the GW_FLM signal of one frame sequentially has the GW_FLTE and GW_FLWE intervals, and with the clock signals (GW_CLK1, GW_CLK2), the reference timing (V sync It is aligned according to ), and the reference timing (V syncThe GW_FLTE section begins from ). During one frame, the GW_FLM signal has a high voltage during the GW_FLTE section, and then has a low voltage for a short time during the GW_FLWE section. When clock signals (GW_CLK1, GW_CLK2) begin to be applied, the clock signal (GW_CLK2) input to the first clock input terminal starts with a high voltage and alternately applies low voltage / high voltage, and the clock signal (GW_CLK1) input to the second clock input terminal starts with a low voltage and alternately applies high voltage / low voltage. The voltage of the clock signals (GW_CLK1, GW_CLK2) can be changed every 1H, and in the embodiment of FIG. 16, the GW_FLTE and GW_FLWE sections can have widths of 17H and 1H, respectively.

[0230] When the scan signal stage is used as the second scan signal generation unit (GC_D; 3002, 3004), the GC_FLM signal is input to the start signal input terminal of the scan signal stage as a start signal (FLM) to generate the second scan signal (GC(n)) of FIG. 3. The GC_FLM signal of FIG. 16 has a low voltage during the period in which the second scan signal (GC(n)) of FIG. 3 is applied, and has a high voltage during other periods. The signal output from the scan signal stage and the signal input to the start signal input terminal may have the same waveform and a time difference of 1H. The second scan signal generation unit (GC_D; 3002, 3004) includes a plurality of scan signal stages, and is configured so that the output of the first scan signal stage is not only transmitted to the second scan line (152) but is also input to the start signal input terminal of the next scan signal stage. Accordingly, the start signal input terminal of the first scan signal stage receives the GC_FLM signal as the start signal (FLM), but the start signal input terminal of the other scan signal stage may also receive the output of the preceding scan signal stage. As shown in FIG. 16, a total of six clock signals (GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, GC_CLK6) are applied to the second scan signal generation unit (GC_D; 3002, 3004), and each clock signal differs by 1H. Therefore, one pair of each of the six clock signals has a signal that is inverted from one another. In addition, a pair of clock signals applied to the scan signal stage of this stage is a pair of clock signals that is 1H later than the pair of clock signals applied to the scan signal stage of the preceding stage. As a result, the second scan signal generation unit (GC_D; 3002, 3004) can sequentially output a second scan signal (GC(n)) of the same waveform every 1H in a plurality of stages due to the difference in the applied clock signal.

[0231] In FIG. 16, the GC_FLM signal of one frame sequentially has the GC_FLTE and GC_FLWE intervals, and with the clock signals (GC_CLK1, GC_CLK2), the reference timing (V sync It is aligned according to ), and the reference timing (V sync The GC_FLTE interval starts from ). During one frame, the GC_FLM signal has a high voltage during the GC_FLTE interval, then a low voltage during the GC_FLWE interval, and then a high voltage during the remaining interval. The clock signals (GC_CLK1, GC_CLK2) may change voltage every 3H, and the GC_FLM signal may have widths of 1H and 17H for the GC_FLTE and GC_FLWE intervals, respectively.

[0232] In the second scan signal generation unit (GC_D; 3002, 3004), six clock signals (GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, GC_CLK6) are applied, and the voltage level of two clock signals changes at the same timing. Two clock signals that are inverted to different voltages at the same timing are also referred to as a pair of inverted clock signals below.

[0233] The clock signal (GC_CLK1) is the reference timing (V sync Based on ), it starts with high voltage, and after the GC_SCTE1 period passes, low and high voltages are applied alternately, and the clock signal (GC_CLK2) is the reference timing (V sync Based on ), it starts with low voltage, and after the GC_SCTE1 period passes, high and low voltages are applied alternately. At the clock signal (GC_CLK2), the reference timing (V sync Based on ), the timing at which the first low voltage starts is after the GC_SCTE2 period has passed.

[0234] The clock signal (GC_CLK3) is the reference timing (V syncBased on ), it starts with high voltage, and after the GC_SCTE3 period passes, low and high voltages are applied alternately, and the clock signal (GC_CLK4) is the reference timing (V sync Based on ), it starts with low voltage, and after the GC_SCTE3 period passes, high and low voltages are applied alternately. Reference timing (V) at the clock signal (GC_CLK4) sync Based on ), the timing at which the first low voltage starts is after the GC_SCTE4 period has passed.

[0235] The clock signal (GC_CLK5) is the reference timing (V sync Based on ), it starts with high voltage, and after the GC_SCTE5 period passes, low and high voltages are applied alternately, and the clock signal (GC_CLK6) is the reference timing (V sync Based on ), it starts with low voltage, and after the GC_SCTE5 period passes, high and low voltages are applied alternately. At the clock signal (GC_CLK6), the reference timing (V sync Based on ), the timing at which the first low voltage starts is after the GC_SCTE6 period has passed.

[0236] The voltage of the six clock signals (GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, GC_CLK6) can be changed for each GC_SCWE, and in this embodiment, GC_SCWE can have a length of 3H. In the embodiment of FIG. 16, the GC_SCTE1, GC_SCTE2, GC_SCTE3, GC_SCTE4, GC_SCTE5, and GC_SCTE6 sections can have widths of 1H, 4H, 2H, 5H, 3H, and 6H, respectively.

[0237] In the second scan signal generation unit (GC_D; 3002, 3004), only one pair of inverted clock signals (two clock signals) among the six clock signals are applied to the scan signal stage included in the second scan signal generation unit (GC_D; 3002, 3004), and the following description focuses on the scan signal stage receiving GC_CLK1 and GC_CLK2.

[0238] We will examine the operation of the stage for the scan signal of Fig. 15 according to the waveform of Fig. 16.

[0239] A brief overview of the operation of the scan signal stage is as follows.

[0240] The output of the output terminal (OUT) is output according to the operation of the 306 transistor (T306) and the 307 transistor (T307).

[0241] The 306 transistor (T306) that outputs a high voltage (VGH) outputs a high voltage (VGH) to the output terminal (OUT) when the 305 transistor (T305) is turned on, and the first node (QB) has a low voltage (VGL). The 305 transistor (T305) is turned on only when the second clock signal (CLK2) applied to the first input terminal has a low voltage. Therefore, when the second clock signal (CLK2) applied to the first input terminal has a low voltage, the scan signal stage outputs a high voltage (VGH).

[0242] Meanwhile, when the second clock signal (CLK2) is at a low voltage, the 301 transistor (T301) is also turned on, and the output of the stage for the start signal (FLM) or the front-end scan signal is transmitted to the second node (Q) and the second-1 node (QF) and stored in the 302 capacitor (Ca302). At this time, if the output of the stage for the start signal (FLM) or the front-end scan signal is at a high voltage, the 307 transistor (T307) is not turned on and does not operate. However, if the output of the stage for the start signal (FLM) or the front-end scan signal is at a low voltage, the 307 transistor (T307) is turned on and outputs the first clock signal (CLK1). However, when the second clock signal (CLK2) has a low voltage, a high voltage (VGH) is applied by the 306 transistor (T306), so the output terminal (OUT) of the scan signal stage has a high voltage, but when the second clock signal (CLK2) has a high voltage, the 307 transistor (T307) is turned on by the low voltage stored in the 302 capacitor (Ca302) at that time, and the first clock signal (CLK1), that is, the low voltage, is output.

[0243] Therefore, the scan signal stage is stored in the 302 capacitor (Ca302) when the second clock signal (CLK2) is at a low voltage, and the first clock signal (CLK1) at a low voltage is output through the 307 transistor (T307) when the second clock signal (CLK2) is at a high voltage. Therefore, a signal delayed by one clock signal width (GW_SCWE, GC_SCWE) is output compared to the scan signal stage.

[0244] As described above, according to the input signal illustrated in FIG. 16, the signal illustrated in FIG. 3 is applied to the pixel.

[0245] According to FIG. 16, even if the scan signal stage with the same circuit structure as illustrated in FIG. 15 is included in the start signal (GW_FLM) and clock signal (GW_CLK1, GW_CLK2) applied to the first scan signal generator (GW_D; 3001, 3003) and the second scan signal generator (GC_D; 3002, 3004), the clock signal is different, so the two adjacent scan signal stages cannot share the clock signal with each other. That is, even if the scan signal stage belonging to the first scan signal generator (GW_D; 3001, 3003) and the scan signal stage belonging to the second scan signal generator (GC_D; 3002, 3004) are located adjacent to each other, they must form a separate clock signal line because their clock signals are different. Accordingly, the width / area of ​​the driving unit (200, 250) cannot be reduced by reducing the clock signal lines of the first scan signal generating unit (GW_D; 3001, 3003) and the second scan signal generating unit (GC_D; 3002, 3004). However, as seen in FIGS. 7 to 13, the light-emitting signal stage included in the first light-emitting control signal generating unit (EM1_D; 2001, 2005), the second light-emitting control signal generating unit (EM2_D; 2002, 2006), the initialization control signal generating unit (EB1_D; 2003, 2007), and the bias control signal generating unit (EB2_D; 2004, 2008) belonging to the driving unit (200, 250) can share an input signal line (clock signal line, etc.), so the width / area of ​​the overall driving unit (200, 250) is reduced.

[0246] However, according to the embodiment, the first scan signal generating unit (GW_D; 3001, 3003) and the second scan signal generating unit (GC_D; 3002, 3004) may also share input signal lines. Below, through FIGS. 17 and 18, we examine an example of a signal applied to a pixel and an input signal applied to a scan signal generating unit in an embodiment where the scan signal stage included in the first scan signal generating unit (GW_D; 3001, 3003) and the second scan signal generating unit (GC_D; 3002, 3004) may share input signal lines (such as clock signal lines).

[0247] FIG. 17 is a waveform diagram illustrating a plurality of signals applied to a pixel of FIG. 2 according to another embodiment and a voltage waveform of the G node accordingly, and FIG. 18 is a waveform diagram illustrating an input signal applied to a stage of a scan signal generation unit to generate the signal of FIG. 17.

[0248] In the embodiment of FIG. 3, the first scan signal (GW(n)) has a low voltage applied once per frame, and the second scan signal (GC(n)) has a low voltage three times per frame. However, depending on the embodiment, this is not limited thereto, and the two scan signals may have the same number of low voltages during one frame, and FIG. 17 illustrates an embodiment in which the two scan signals have a low voltage applied once per frame.

[0249] First, unlike Fig. 3, Fig. 17 shows that the second scan signal (GC(n)) is changed to a low voltage only once during one frame, and the length of the changing interval may be 1H.

[0250] In order to generate the second scan signal (GC(n)) of Fig. 17 as shown, unlike Fig. 16, only the start signal (GC_FLM) of Fig. 18 and two clock signals (CLK1, CLK2) are applied.

[0251] Two clock signals (CLK1, CLK2) are input in common to a scan signal stage included in the first scan signal generation unit (GW_D; 3001, 3003) and a scan signal stage included in the second scan signal generation unit (GC_D; 3002, 3004). As a result, the scan signal stage belonging to the first scan signal generation unit (GW_D; 3001, 3003) and the scan signal stage belonging to the second scan signal generation unit (GC_D; 3002, 3004) can share input signals such as the two clock signals (CLK1, CLK2).

[0252] The operation of the scan signal stage for generating the second scan signal (GC(n)) in FIG. 18 may be substantially the same as the scan signal stage for generating the first scan signal (GW(n)) described in FIG. 16, so the description is omitted.

[0253] In the embodiments of FIGS. 17 and 18, an embodiment is illustrated in which the second scan signal (GC(n)) of FIG. 3 is modified to match the first scan signal (GW(n)). However, depending on the embodiment, conversely, the first scan signal (GW(n)) of FIG. 3 may be modified to match the second scan signal (GC(n)) so that it is applied three times in one frame.

[0254] The structure when two clock signals (CLK1, CLK2) are applied to two adjacent scan signal stages is described in detail through FIGS. 19 and 20.

[0255] FIG. 19 is a layout diagram illustrating a structure in which two stages of a scan signal generation unit are flip-arranged according to one embodiment, and FIG. 20 is a cross-sectional view taken along the cross-sectional line XX-XX of FIG. 19.

[0256] For reference, in Fig. 19, the mark with an x ​​inside the square indicates an opening located in the insulating film, allowing the upper conductive layer and the lower conductive layer to be electrically connected.

[0257] In the embodiments of FIGS. 19 and 20, the first clock wiring (3103) and the second clock wiring (3104) are described as signal lines shared between two adjacent scan signal stages.

[0258] In FIG. 19, if the scan signal stage located on one side belongs to the first scan signal generating unit (GW_D; 3001, 3003), the other side belongs to the scan signal stage and the second scan signal generating unit (GC_D; 3002, 3004). Among the input signal lines applied between the two, the first clock wiring (3103) and the second clock wiring (3104) are shared.

[0259] The structure is as follows, focusing on the scan signal stage located on the left side of Fig. 19.

[0260] Each transistor included in the stage for the scan signal comprises a semiconductor layer located on a substrate (110), a first gate insulating film (141), and a gate electrode, as shown in FIG. 20, and a channel is located in the portion where the semiconductor layer and the gate electrode overlap, and a source region and a drain region are located on both sides of the channel in the semiconductor layer, which are plasma treated or doped to become conductive.

[0261] Additionally, in the embodiments of FIGS. 19 and 20, the first clock wiring (3103) and the second clock wiring (3104) are formed as a double layer. As a result, the layered structure consists of a substrate (110), a semiconductor layer, a first gate insulating layer (141), a first gate conductive layer, a second gate insulating layer (142), a second gate conductive layer, a first interlayer insulating layer (143), a source / drain conductive layer (also referred to as the first source / drain conductive layer), a second interlayer insulating layer (144), a second source / data conductive layer, and an organic protective layer (145). The first gate conductive layer contains the gate electrodes of all transistors.

[0262] In this embodiment, the first clock wiring (3103) and the second clock wiring (3104) are located in the first source / drain conductive layer. The first-2 clock wiring (3253) and the second-2 clock wiring (3254) are located in the second source / data conductive layer and are electrically connected to the first clock wiring (3103) and the second clock wiring (3104), respectively. Depending on the embodiment, they may be formed as a single line.

[0263] The following describes each transistor and capacitor included in the scan signal stage.

[0264] The gate electrode (G301) of the 301 transistor (T301) is composed of two parts, extending to one side to the gate electrode (G305) of the 305 transistor (T305), and extending to the other side to be electrically connected to the first clock wiring (3103) to which the CLK2 clock signal is applied. The channel, source, and drain regions are located in the semiconductor layer (C301). One side of the semiconductor layer (C301) is electrically connected to a connection line (3205) to which the output of a stage for a start signal (FLM) or a front-end scan signal is transmitted, and the other side is connected to a connection part (3301) that is electrically connected to the gate electrode (G304) of the 304 transistor (T304), one side of the 308 transistor (T308), and one side of the 303 transistor (T303). The connection part (3301) is located in the source / drain conductive layer.

[0265] The gate electrode (G302) of the 302nd transistor (T302) is extended to one electrode (3211) of the 306th transistor (T306) and the 301st capacitor (Ca301). One side of the semiconductor layer (C302) is electrically connected to a high-voltage wiring (3101) to which a high voltage (VGH) is applied, and the other side is directly connected to one side of the 303rd transistor (T303) and the semiconductor layer. That is, the semiconductor layer (C302) is extended to form an integral part with the semiconductor layer (C303) of the 303rd transistor (T303).

[0266] The gate electrode (G303) of the 303rd transistor (T303) is extended to one side and electrically connected to the second clock wiring (3104) to which the CLK1 clock signal is applied, and is extended to the other side and connected to one side of the 307th transistor (T307). One side of the semiconductor layer (C303) is connected to one side of the 301st transistor (T301) through the connection part (3301), and the semiconductor layer (C303) is extended and directly connected to one side of the 302nd transistor (T302) as a semiconductor layer.

[0267] The gate electrode (G304) of the 304th transistor (T304) is extended to one side and connected to the 301st transistor (T301) and the 303rd transistor (T303) through a connection part (3301), and is extended to the other side and connected to one side of the 308th transistor (T308) through a connection part (3302). One side of the semiconductor layer (C304) is connected to the gate electrode (G301) of the 301st transistor (T301) through a connection part (3303), and the other side is electrically connected to the gate electrode (G302) of the 302nd transistor (T302), the gate electrode (G306) of the 306th transistor (T306), and one side of the 305th transistor (T305) through a connection part (3304). The connection parts (3303, 3304) are located in the source / drain conductive layer.

[0268] The gate electrode (G305) of the 305th transistor (T305) is extended and connected to the gate electrode (G301) of the 301st transistor (T301), and is electrically connected to the first clock wiring (3103) to which a CLK2 clock signal is applied. One side of the semiconductor layer (C305) is electrically connected to the low voltage wiring (3102) to which a low voltage (VGL) is applied, and the other side is electrically connected to the gate electrode (G302) of the 302nd transistor (T302), the gate electrode (G306) of the 306th transistor (T306), and one side of the 304th transistor (T304) through the connection part (3304).

[0269] The gate electrode (G306) of the 306th transistor (T306) is divided into multiple (composed of four gate electrodes in FIG. 19) and is extended to be connected to the gate electrode (G302) of the 301st capacitor (Ca301) and the 302nd transistor (T302). One side of the semiconductor layer (C306) is connected to one electrode (3212) of the 301st capacitor (Ca301) by a connecting electrode (SD306) and is electrically connected to the high-voltage wiring (3101) through the 301st capacitor (Ca301). The other side of the semiconductor layer (C306) is connected to the output wiring (3201). The connecting electrode (SD306) is located in the source / drain conductive layer.

[0270] The gate electrode (G307) of the 307th transistor (T307) is divided into multiple parts (composed of four gate electrodes in FIG. 19), one part forms one electrode (3221) of the 302nd capacitor (Ca302), and is extended and connected to one end of the 308th transistor (T308) by a connection part (3305). One side of the semiconductor layer (C307) is electrically connected to the gate electrode (G303) of the 303rd transistor (T303) by a connection electrode (SD307), and is also connected to the second clock wiring (3104) to which the CLK1 clock signal is applied passing through the gate electrode (G303) of the 303rd transistor (T303). The other side of the semiconductor layer (C307) is connected to the output wiring (3201). The connection electrode (SD307) is located in the source / drain conductive layer.

[0271] The output wiring (3201) is electrically connected to the signal line through the connection line (3202), and the output wiring (3201) is located in the source / drain conductive layer.

[0272] The gate electrode (G308) of the 308th transistor (T308) is extended and electrically connected to a low-voltage wiring (3102) to which a low voltage (VGL) is applied. One side of the semiconductor layer (C308) is electrically connected to the gate electrode (G307) of the 307th transistor (T307) by a connection part (3305), and the other side is electrically connected to the gate electrode (G304) of the 304th transistor (T304) by a connection part (3302).

[0273] The capacitor (Ca301, Ca302) has a cross-sectional structure in which the first gate conductive layer and the second gate conductive layer are the two electrodes, and the second gate insulating film (142) located between them is the dielectric.

[0274] One electrode (3212) of the 301 capacitor (Ca301) is extended and connected to the high voltage wiring (3101), and the other electrode (3211) is located on a part of the gate electrode (G306) of the 306 transistor (T306).

[0275] One electrode (3222) of the 302 capacitor (Ca302) is electrically connected to the output wiring (3201), and the other electrode (3221) is located on a part of the gate electrode (G307) of the 307 transistor (T307).

[0276] In the embodiment of FIG. 19, there are two shared signal lines, each being a first clock line (3103) to which a CLK2 clock signal is applied and a second clock line (3104) to which a CLK1 clock signal is applied. However, depending on the embodiment, a high-voltage line (3101) to which a high voltage (VGH) is additionally applied and a low-voltage line (3102) to which a low voltage (VGL) is applied may also be shared with each other.

[0277] By combining the embodiments of FIGS. 8 to 14 and FIGS. 17 to 20, four generating units including a stage for a light-emitting signal share signal lines with each other, and two generating units including a stage for a scan signal also share signal lines with each other, thereby minimizing the width / area of ​​the driving unit (200, 250).

[0278] The structure of the entire drive unit (200, 250) in such a case is schematically examined through FIGS. 21 and FIGS. 22.

[0279] FIG. 21 is a drawing clearly illustrating the reduction in width resulting from forming a plurality of stages in a non-display area in one embodiment, and FIG. 22 is a cross-sectional view of a part of FIG. 21.

[0280] In FIG. 21, a first driving unit (200) located to the left of the display area (DA) as in FIG. 4 is shown.

[0281] The first driving unit (200) located on the left side of the display area (DA) has the first light emission control signal generating unit (EM1_D; 2001), the second light emission control signal generating unit (EM2_D; 2002), the initialization control signal generating unit (EB1_D; 2003), the bias control signal generating unit (EB2_D; 2004), the second scan signal generating unit (GC_D; 3002), and the first scan signal generating unit (GW_D; 3001) arranged in order from the outside in the direction of the display area (DA).

[0282] However, in the embodiment of FIG. 21, the bias control signal generating unit (EB2_D; 2004) including a stage for a light emission signal and the second scan signal generating unit (GC_D; 3002) including a stage for a scan signal are separated by a certain distance, and a VIA valley is formed in this part.

[0283] A via valley is a portion where at least a part of the organic film has been removed, and a wiring (hereinafter also referred to as ELVSS wiring) through which the voltage applied to the cathode of the light-emitting element (ELVSS voltage) is transmitted may be located therein. In FIG. 22, the cross-sectional structure of the via valley is shown and is formed as a double-layer structure.

[0284] According to FIG. 22, the VIA valley has a structure in which the organic protective film (145) is removed, and the second interlayer insulating film (144) located below it may also have a structure in which it is partially removed.

[0285] The wiring through which the ELVSS voltage is transmitted is composed of a double layer, the first ELVSS wiring (ELVSS1) is located in the first source / drain conductive layer, and the second ELVSS wiring (ELVSS2) is located in the second source / data conductive layer. That is, the first ELVSS wiring (ELVSS1) is covered by a second interlayer insulating film (144), and at least a portion of the first ELVSS wiring (ELVSS1) is exposed through an opening located in the second interlayer insulating film (144). The second ELVSS wiring (ELVSS2) is located thereon, and the second ELVSS wiring (ELVSS2) is electrically connected to the first ELVSS wiring (ELVSS1) through the opening located in the second interlayer insulating film (144). An organic protective film (145) is positioned above the second ELVSS wiring (ELVSS2), and the organic protective film (145) has an opening that continuously exposes the second ELVSS wiring (ELVSS2). Since the organic protective film (145) is positioned only on both sides, it has a valley-like structure and can be called a VIA valley.

[0286] Here, the second interlayer insulating film (144) may be an inorganic film or an organic film.

[0287] In FIG. 22, it is shown that no conductive layer or semiconductor layer is located at the bottom of the first interlayer insulating film (143), but depending on the location, a conductive layer or semiconductor layer may be located in some areas.

[0288] In the embodiments of FIGS. 21 and 22, a driving unit (200, 250) is formed with wiring through which the ELVSS voltage is transmitted via the VIA valley, but as shown in FIG. 21, the width is reduced by Ws compared to the comparative example, and accordingly, the area can be reduced.

[0289] That is, the comparative example and the present embodiment can be compared through Table 1 below as follows.

[0290] Stage for light emission signal Stage for scan signal Comparative example Number of wires per generation unit 4 4 or 10 Total number of wires 16 8 or 12 Examples Number of wires per generation unit 4 4 Total number of wires 12 (decrease of 4) 6 (maximum 6 decrease)

[0291] Here, the comparison example is the case where input signal lines are not shared between adjacent stages.

[0292] In Table 1, the number of wires per generation unit is the number of signal lines required to input to one stage, and the stage for light emission signals has a total of 4 wires (CLK1, CLK2, VGH, VGL), and the stage for scan signals may have a total of 4 wires (CLK1, CLK2, VGH, VGL) or a total of 10 wires (GC_CLK1, GC_CLK2, GC_CLK3, GC_CLK4, GC_CLK5, GC_CLK6, VGH, VGL, GW_CLK1, GW_CLK2). This is the same for the comparative example and the example.

[0293] In the comparative example, since there are a total of 4 stages for light emission signals, a total of 16 stages are required, and since there are a total of 2 stages for scan signals, a total of 8 or 12 stages are required.

[0294] However, in this embodiment, the number of input signal lines is reduced compared to this.

[0295] If two clock wires (CLK1, CLK2) are shared among the four stages for the light-emitting signal, the total number of wires is reduced by four. However, if the high voltage wire (VGH) or low voltage wire (VGL) is also shared, the number of wires is further reduced.

[0296] In addition, if two clock lines (CLK1, CLK2) are shared between two stages for scan signals, a total of two lines or up to six lines are reduced. Furthermore, if the high voltage line (VGH) or low voltage line (VGL) is also shared, the number of lines is further reduced.

[0297] Specifically, one stage can generally be formed to be about 300 µm, and even in the embodiment formed with the minimum width, at least 100 µm is required, so if a total of 6 stages are formed, at least 700 µm is required, so the margin of width for the non-display area may not be large. At this time, considering that the width of one wire is about 12 µm and space is required between adjacent wires for insulation, if the number of wires is reduced by 4, it can be reduced by about 60 µm.

[0298] In particular, if the input signal line is shared even in the scan signal stage, a total reduction of 120㎛ is possible.

[0299] Meanwhile, as in the embodiment of FIG. 14, when power wiring (low-voltage wiring) is shared, an additional reduction of about 12.5 μm per wiring is possible.

[0300] Considering that the width of the driving unit (200, 250) is 700㎛, it can be reduced by 60 to a maximum of 130㎛, and also, since the width can be reduced together on both sides of the display area (DA), a sufficient margin can be created by reducing the width of the driving unit (200, 250) according to the present invention.

[0301] Even if input signal lines are shared only in the light-emitting signal stage, the area of ​​the driving unit (200, 250) can be sufficiently reduced. In particular, since a total of four light-emitting signal stages are formed, two pairs of signal lines can be reduced and only two pairs can be formed, thereby achieving a sufficient reduction in width / area. However, to further reduce the width of the driving unit (200, 250), input signal lines can also be shared in the scan signal stage. Additionally, while only clock signal wiring can be shared, high-voltage wiring or low-voltage wiring can also be shared to form the driving unit (200, 250) with a narrower width.

[0302] In addition, depending on the embodiment, only the stage for the scan signal may share the input signal line, and the stage for the light emission signal may not share the input signal line.

[0303] Although embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims also fall within the scope of the present invention. Explanation of the symbols

[0304] 10: Light-emitting display device 200, 250: Driving unit 151: 1st scan line 152: 2nd scan line 153: 1st Initialization Control Line 153-1: 2nd Initialization Control Line 154, 155: Light emission control line 156: Bias control line 171: Data line 172: Driving voltage line 173: Reference voltage line 179: Bias voltage line 127: Initialization voltage line 2101, 3101: High voltage wiring 2102, 3102: Low voltage wiring 2105: ESR wiring 2103, 2104, 2253, 2254, 3103, 3104, 3253, 3254: Clock wiring 2201, 3201: Output wiring 2551: High-level output section 2552: Low-level output section 2553: First node first control section 2554: 1st Node 2nd Control Unit 2555: 2nd Node 1st Control Unit 2556: 2-1 Node Maintenance Unit 2557: 3 Node Control Unit 2560: Initialization section 3551: High-level output section 3552: Low-level output section 3553: First node first control section 3554: 1st Node 2nd Control Unit 3555: 2nd Node 1st Control Unit 3556: 2nd Node 2nd Control Unit Ca201, Ca202, Ca203, Ca301, Ca302: capacitors Cpr: Input capacitor Cst: Retention capacitor 2001, 2005: First light emission control signal generation unit 2002, 2006: Second light emission control signal generation unit 2003, 2007: Initialization control signal generation unit 2004, 2008: Bias control signal generation unit 3001, 3003: First scan signal generation unit 3002, 3004: Second scan signal generation unit 110: Substrate 141: First gate insulating film 142: Second gate insulating film 143: First interlayer insulating film 144: Second interlayer insulating film 145: Organic protective film

Claims

Claim 1 A light-emitting display device comprising: a display area including a plurality of pixels and scan lines; and a driving unit located outside the display area and connected to the scan lines, wherein the driving unit comprises: two scan signal stages arranged in the extension direction of the scan lines; at least two light-emitting signal stages located in at least two columns; a plurality of input signal lines connected to the two scan signal stages; and a pair of first clock signal lines connected to the at least two light-emitting signal stages, wherein the two scan signal stages are connected to the same input signal line among the plurality of input signal lines, and the at least two light-emitting signal stages sharing the pair of first clock signal lines receive different start signals, and the two scan signal stages also receive different start signals. Claim 2 In claim 1, the input signal line commonly connected to the two scan signal stages is a pair of second clock signal lines, a light-emitting display device. Claim 3 In paragraph 2, the pair of second clock signal lines is a light-emitting display device located between the two scan signal stages. Claim 4 In paragraph 3, the two scan signal stages are each light-emitting display devices included in the first scan signal generating unit and the second scan signal generating unit. Claim 5 In paragraph 3, the plurality of input signal lines further include high-voltage wiring or low-voltage wiring in a light-emitting display device. Claim 6 In paragraph 5, the pair of second clock signal lines, or the low-voltage wiring, is a light-emitting display device located between the two scan signal stages. Claim 7 A light-emitting display device according to claim 4, wherein the first scan signal generated by the first scan signal generating unit has a low voltage once per frame, and the second scan signal generated by the second scan signal generating unit has a low voltage three times per frame. Claim 8 In paragraph 4, the driving unit is a light-emitting display device located only on one side of the display area. Claim 9 In claim 8, the driving unit further comprises an additional input signal line connected to the at least two light-emitting signal stages, in a light-emitting display device. Claim 10 In claim 9, the at least two light-emitting signal stages located in the at least two columns are each connected to the additional input signal line, and the at least two light-emitting signal stages are arranged in a horizontal direction in which the driving unit is adjacent to the display area, and are arranged on both sides of the additional input signal line having an extension direction perpendicular to the horizontal direction, forming a light-emitting display device. Claim 11 In claim 9, the light-emitting display device wherein the at least two light-emitting signal stages are included in at least two of a first light-emitting control signal generating unit, a second light-emitting control signal generating unit, an initialization control signal generating unit, and a bias control signal generating unit. Claim 12 In claim 11, the pixel circuit portion of the display area receives a first light emission control signal generated by the first light emission control signal generating unit, a second light emission control signal generated by the second light emission control signal generating unit, a first initialization control signal and a second initialization control signal generated by the initialization control signal generating unit, a bias control signal generated by the bias control signal generating unit, a first scan signal generated by the first scan signal generating unit, and a second scan signal generated by the second scan signal generating unit. Claim 13 In paragraph 12, the light-emitting signal stage within the initialization control signal generating unit that generates the first initialization control signal is a light-emitting display device located upstream of the light-emitting signal stage within the initialization control signal generating unit that generates the second initialization control signal.

Images