Pam-3 transceiver including multiple equalization methods for multi-voltage levels

Abstract

The present application relates to a PAM-3 transmitter. In some embodiments of the present application, the PAM-3 transmitter comprises: an encoder that maps input data to a transition having first to third voltage levels within two unit intervals and, in response to said transition, encodes said input data into encoding data divided into odd and even orders; and an equalizer that equalizes said first to third voltage levels in response to said encoding data. The equalizer includes a driver that outputs output data for a PAM-3 (Pulse Amplitude Modulation Level-3) signal in response to the equalized voltage level, and the equalizer equalizes the voltage level in a first mode when the first or third voltage level is maintained within two consecutive unit intervals, equalizes the voltage level in a second mode when the first or third voltage level is switched to the second voltage level within at least one unit interval, and equalizes the voltage level in a third mode when the second voltage level is switched to the first or third voltage level within at least one unit interval.

Description

Technology Field

[0001] The present invention relates to a PAM-3 transceiver comprising a plurality of equalization methods corresponding to multiple voltage levels. Background Technology

[0002] With the rapid supply of mobile devices and the rapid increase in internet connectivity, the demand for high-capacity and high-speed data transmission is growing day by day. However, it is difficult to satisfy these demands for high-capacity and high-speed data transmission with signal modulation schemes based on NRZ (Non-Return to Zero) type encoding. Recently, Pulse Amplitude Modulation (PAM) is being actively researched as an alternative signaling scheme for high-capacity and high-speed data transmission.

[0003] Meanwhile, the PAM-3 (PAM 3-Level) data transmission method can transmit about 1.5 bits with three voltage levels in one unit interval, which offers the potential for speed improvement, but signal distortion may occur due to limited bandwidth. This signal distortion can act as a major problem that can significantly degrade transmission quality. Prior art literature

[0004] Republic of Korea Published Patent No. 10-2024-0000229 The problem to be solved

[0005] The present invention is intended to solve the aforementioned problem, and the objective of the present invention is to provide a PAM-3 transceiver comprising a plurality of equalization methods corresponding to multiple voltage levels. means of solving the problem

[0006] The present application comprises: an encoder that maps input data to a transition having first to third voltage levels within two unit intervals and encodes the input data into encoding data divided into odd and even orders in response to the transition; an equalizer that equalizes the first to third voltage levels in response to the encoding data; and a driver that outputs output data for a PAM-3 (Pulse Amplitude Modulation Level-3) signal in response to the equalized voltage levels, wherein the equalizer equalizes the voltage levels in a first mode when the first or third voltage level is maintained within two consecutive unit intervals, equalizes the voltage levels in a second mode when the first or third voltage level is switched to the second voltage level within at least one unit interval, and equalizes the voltage levels in a third mode when the second voltage level is switched to the first or third voltage level within at least one unit interval.

[0007] In some embodiments, the encoder may encode the 3-bit input data into one of the remaining 8 transitions, excluding one of the first to ninth transitions within the 2 unit intervals, and may not use the one transition that maintains the state of the first voltage level during the 2 unit intervals for encoding the input data.

[0008] In some embodiments, the equalizer may use one tap corresponding to one transition that maintains the state of the first voltage level.

[0009] In some embodiments, the equalizer may use two taps corresponding to the transition that maintains the third voltage level.

[0010] In some embodiments, the equalizer may operate in the first mode to adjust the voltage level of the repeating data, operate in the second mode to increase the rate of voltage drop or rise of the voltage level, and operate in the third mode to adjust the data switching time of the voltage level.

[0011] The present application comprises: an encoder that maps input data to a transition having first to third voltage levels within two unit intervals and, in response to said transition, encodes said input data into encoding data classified into odd and even orders; an equalizer that equalizes said voltage levels in a first mode when said first or third voltage levels are maintained within two consecutive unit intervals corresponding to said encoding data, equalizes said voltage levels in a second mode when said first or third voltage levels are switched to said second voltage levels within at least one unit interval corresponding to said encoding data, and equalizes said voltage levels in a third mode when said second voltage levels are switched to said first or third voltage levels within at least one unit interval corresponding to said encoding data; and a driver that outputs output data for a PAM-3 (Pulse Amplitude Modulation Level-3) signal in response to said equalized voltage levels. and may include a receiver that receives the output data and decodes the output data for the PAM-3 signal to generate the input data.

[0012] In some embodiments, the receiver may include: an amplifier that amplifies the output data; and a decoder that decodes the output data amplified from the amplifier to restore the 3-bit input data.

[0013] In some embodiments, the amplifier may classify the output data into odd and even orders and use a single comparator for each order.

[0014] In some embodiments, the receiver may further include a DCDL that controls the time delay of the amplifier.

[0015] In some embodiments, the decoder can recover the input data in response to the adjusted time delay. Effects of the invention

[0016] According to embodiments of the present application, a PAM-3 transceiver can minimize signal distortion by using a plurality of equalization methods for multiple voltage levels. Accordingly, the PAM-3 transceiver can improve quality by attenuating noise in the output signal and ensuring stability. Brief explanation of the drawing

[0017] FIG. 1 is a block diagram illustrating a PAM-3 transmitter according to some embodiments of the present application. FIG. 2 is a diagram showing an example of transition mapping of an encoder according to some embodiments of the present application. FIGS. 3a and 3b are drawings showing an example of an equalizer operating in a first mode according to some embodiments of the present application. FIG. 4 is a drawing showing an example of an equalizer operating in a second mode according to some embodiments of the present application. FIG. 5 is a drawing showing an example of an equalizer operating in a third mode according to some embodiments of the present application. FIG. 6 is a drawing showing an example of a driver according to some embodiments of the present application. FIGS. 7a and 7b illustrate eye diagrams of output data according to some embodiments of the present application. FIG. 8 is a drawing of a PAM-3 transceiver according to some embodiments of the present application. FIG. 9 is a drawing illustrating a terminal circuit according to some embodiments of the present application. FIG. 10 is a drawing illustrating a comparator according to some embodiments of the present application. Specific details for implementing the invention

[0018] In the following, embodiments of the present invention will be described clearly and in detail with reference to the accompanying drawings.

[0019] FIG. 1 is a block diagram illustrating a PAM-3 transmitter according to some embodiments of the present application.

[0020] Referring to FIG. 1, a PAM-3 (Pulse Amplitude Modulation 3-Level) transmitter (10) may include an encoder (100), a mux (200), an equalizer (300), and a driver (400).

[0021] In some embodiments, the PAM-3 transmitter (10) may be implemented in a transmitting device as a device for transmitting a PAM-3 signal. For example, the PAM-3 transmitter (10) may be implemented as a transmitter for various devices such as High Bandwidth Memory (HBM), desktop computers, laptop computers, tablet computers, smartphones, wearable devices, video game consoles, home appliances, medical devices, etc.

[0022] In some embodiments, the encoder (100) is electrically connected to the multiplexer (200) to transmit encoding data (ENC_DATA) to the multiplexer (200). Specifically, the encoder (100) receives at least one input data (IN_DATA) and can map the input data (IN_DATA) to a transition within a unit interval. Additionally, the encoder (100) can output encoding data (ENC_DATA) based on encoding logic corresponding to the transition to which the input data (IN_DATA) is mapped.

[0023] Here, the unit interval may be the minimum bit pulse width of the transmission signal in the PAM-3 transmitter (10). Additionally, the transition may refer to a transition to a specific voltage according to the voltage level of a multi-level signal, and each voltage level may be determined by the input data (IN_DATA). That is, the transition may include a High Level, a Middle Level, and a Low Level. Below, the High Level will be defined as the first voltage level, the Middle Level as the second voltage level, and the Low Level as the third voltage level for explanation.

[0024] For example, transitions may refer to aspects in which multi-level signals are switched in two unit intervals as described in Fig. 2.

[0025] In some embodiments, the encoder (100) may receive 3-bit input data (IN_DATA). Accordingly, the encoder (100) may map the 3-bit input data (IN_DATA) to transitions within two unit intervals and generate encoding data (ENC_DATA) separated into odd (ODD) and even (EVEN) orders, each being 3 bits.

[0026] Here, the encoder (100) can map 3-bit input data (IN_DATA) to 8 transitions within 2 unit intervals. Specifically, the encoder (100) can map the input data (IN_DATA) to the remaining 8 transitions, excluding one of the 1st to 9th transitions. That is, the encoder (100) can generate encoding data (ENC_DATA) of an odd or even order corresponding to the 8 transitions. Subsequently, the encoder (100) can transmit the encoding data (ENC_DATA) generated of odd and even orders to a multiplexer (200).

[0027] The multiplexer (200) receives encoding data (ENC_DATA) from an electrically connected encoder (100) and can serialize the encoding data (ENC_DATA). Specifically, the multiplexer (200) receives encoding data (ENC_DATA) of odd and even order corresponding to eight transitions and can serialize it through an N:1 multiplexer.

[0028] In some embodiments, the multiplexer (200) can serialize the odd and even order encoding data (ENC_DATA) into 6-bit length encoding data (ENC_DATA) through a 2:1 multiplexer.

[0029] The equalizer (300) is electrically connected to the multiplexer (200) and can receive serialized encoding data (ENC_DATA). Specifically, the equalizer (300) receives at least one encoding data (ENC_DATA) and can compensate the voltage level corresponding to the voltage level of the transition of the encoding data (ENC_DATA).

[0030] In some embodiments, the equalizer (300) receives encoding data (ENC_DATA) having a length of 6 bits and can compensate the voltage level in the first to third modes in response to the voltage level of the transition of the encoding data (ENC_DATA). That is, the equalizer (300) can equalize the voltage level in response to the voltage levels of the encoding data (ENC_DATA) of odd and even order.

[0031] For example, if the voltage level of the encoding data (ENC_DATA) is maintained at a first or third voltage level within two consecutive unit intervals, the equalizer (300) can equalize the voltage level of the encoding data (ENC_DATA) in the first mode.

[0032] Additionally, if the first or third voltage level of the encoding data (ENC_DATA) is switched to the second voltage level within at least one unit interval, the equalizer (300) can equalize the voltage level of the encoding data (ENC_DATA) in the second mode. Additionally, if the second voltage level of the encoding data (ENC_DATA) is switched to the first or third voltage level within at least one unit interval, the equalizer (300) can equalize the voltage level of the encoding data (ENC_DATA) in the third mode.

[0033] Here, the first mode is an operating mode for reducing noise that occurs when the same data is repeated within a continuous unit interval, and can operate to improve the quality of the output signal by reducing the voltage level of the remaining repeated data excluding the first data. For example, if the encoding data (ENC_DATA) is continuously maintained at a first voltage level or a third voltage level, the equalizer (300) can adjust the voltage level of the subsequently repeated data while maintaining the voltage level of the first data. Accordingly, the equalizer (300) can attenuate noise caused by voltage fluctuations and ensure the stability of the output signal.

[0034] In some embodiments, the equalizer (300) can adjust the voltage level using iPWM (Integrated Pulse Width Modulation) in a first mode.

[0035] The second mode is an operating mode for performing the switching process quickly and stably when the first voltage level or the third voltage level is switched to the second voltage level within at least one unit interval, and can accelerate the switching to the next voltage level by increasing the speed of voltage drop or rise during the voltage switching. For example, when the current encoding data (ENC_DATA) has the first voltage level and the next data is switched to the second voltage level, the equalizer (300) can increase the strength of the voltage drop during the switching to increase the switching speed and reduce signal distortion that may occur during the switching process.

[0036] In some embodiments, the equalizer (300) can adjust the voltage level using a second mode VM FFE (Voltage Mode Feed-Forward Equalizer).

[0037] The third mode is an operating mode that optimizes the signal crossing point by adjusting the data switching time when the second voltage level is switched to the first voltage level or the third voltage level within at least one unit interval, thereby increasing the timing precision of the output signal and ensuring signal integrity. For example, when the current encoding data (ENC_DATA) has the second voltage level and the next data is switched to the first voltage level, the equalizer (300) can control the length of the unit interval by adjusting the switching time. Accordingly, the equalizer (300) can maintain the accuracy of the data crossing point.

[0038] In some embodiments, the equalizer (300) can adjust the voltage level using a Delay Line Controller (DCL) in a third mode.

[0039] The driver (400) is electrically connected to the equalizer (300) and can receive an equalized voltage level from the equalizer (300). Specifically, the driver (400) can generate output data (DQ) by amplifying or converting a signal through a driver circuit in response to the voltage level received from the equalizer (300). Additionally, the driver (400) can be designed to maintain the quality of the output data (DQ) according to the equalized voltage level.

[0040] As described above, the PAM-3 transmitter (10) according to some embodiments of the present application can reduce power consumption by using a hybrid equalizer that compensates for the signal in response to first to third voltage levels.

[0042] FIG. 2 is a diagram showing an example of transition mapping of an encoder according to some embodiments of the present application. For convenience of explanation, one transition mapping method is described below as an example, but this is merely illustrative and is not limited thereto.

[0043] Referring to FIG. 2, the input data (IN_DATA) is 3-bit data (A, B, C) input to the encoder (100), and the transmitting end output (TX OUTPUT) may represent first to third level differential output voltages (TXN, TXP) output from the driver (200) at 2 unit intervals.

[0044] Specifically, the encoder (100) can map 3-bit (A, B, C) input data (IN_DATA) to a first unit interval (ODD UI) and a second unit interval (EVEN UI). Here, the first to third level differential output voltages (TXN, TXP) may include a total of nine transitions in the consecutive first unit interval (ODD UI) and second unit interval (EVEN UI).

[0045] For example, in the case where the 3-bit (A, B, C) input data (IN_DATA) is 1, 1, 1 respectively, as in the first case (Case 1), the encoder (100) can map the input data (IN_DATA) to a transition that is in the state of the first voltage level in the first unit interval (ODD UI) and to a transition that is in the state of the second voltage level in the second unit interval (EVEN UI).

[0046] In addition, when the 3-bit (A, B, C) input data (IN_DATA) is 1, 1, and 0 respectively, as in the second case (Case 2), the encoder (100) can map the input data (IN_DATA) to a transition that is in the state of the first voltage level in the first unit interval (ODD UI) and to a transition that is in the state of the third voltage level in the second unit interval (EVEN UI).

[0047] In some embodiments, one of the first to ninth transitions excluded may be a transition that maintains the state of the first voltage level of the PAM-3 signal for two unit intervals.

[0048] For example, as in Case 3, the encoder (100) may include an unassigned value in which input data (IN_DATA) is not assigned during a transition in which the state of the first voltage level is maintained during the first unit interval (ODD UI) and the second unit interval (EVEN UI). Accordingly, the encoder (100) can increase the resistance of the signal to noise by not assigning input data (IN_DATA) during a transition in which the state of the first voltage level is maintained during the two unit intervals, and can increase the symmetry of the signal by reducing unnecessary voltage fluctuations.

[0050] FIGS. 3a and 3b are drawings showing an example of an equalizer operating in a first mode according to some embodiments of the present application. Hereinafter, the equalizer (300) is described using iPWM, but this is merely illustrative and is not limited thereto.

[0051] Specifically, FIG. 3a is a drawing for explaining an equalizer (300) that uses iPWM and maintains a first voltage level during two unit intervals, and FIG. 3b is a drawing for explaining an equalizer (300) that uses iPWM and maintains a third voltage level during two or more unit intervals.

[0052] Referring to FIG. 3a, the equalizer (300) can equalize the voltage level in a first mode using iPWM. Specifically, the equalizer (300) can calculate the data of the first voltage level (HIGH_1) of the first unit interval and the first voltage level (HIGH) of the second unit interval through logic gates, and control the voltage level and timing of the signal through switching operations.

[0053] Here, referring to FIG. 2, the case in which the first voltage level is maintained within two consecutive unit intervals is the case of an odd-order unit interval following an even-order unit interval, and the equalizer (300) using iPWM may require only one tap.

[0054] That is, referring to the timing diagram at the bottom, when the encoding data (ENC_DATA) continuously maintains the first voltage level, the equalizer (300) using iPWM can adjust the voltage level of the repeating data while maintaining the voltage level of the first data.

[0055] Referring to FIG. 3b, the equalizer (300) can equalize the voltage level in the first mode using iPWM. Specifically, the equalizer (300) can calculate the data of the third voltage level (LOW_1) of the first unit interval and the third voltage level (LOW) of the second unit interval through logic gates, and control the voltage level and timing of the signal through switching operations.

[0056] Here, referring to FIG. 2, since the input data (IN_DATA) is mapped to a transition that maintains a third voltage level, the equalizer (300) using iPWM may require two taps.

[0057] That is, referring to the timing diagram at the bottom, when the encoding data (ENC_DATA) continuously maintains a third voltage level, the equalizer (300) using iPWM can adjust the voltage level of the repeating data while maintaining the voltage level of the first data.

[0059] FIG. 4 is a drawing showing an example of an equalizer operating in a second mode according to some embodiments of the present application. Below, the equalizer (300) is described using VM FFE, but this is illustrative and is not limited thereto.

[0060] Referring to FIG. 4, the equalizer (300) can equalize the voltage level in a second mode using VM FFE. Specifically, the equalizer (300) can calculate the data of the first voltage level (HIGH_1) or the third voltage level (LOW_1) of the first unit interval and the second voltage level (MID) of the second unit interval through a plurality of logic gates, and control the voltage level and timing of the signal through a switching operation.

[0061] That is, referring to the timing diagram at the bottom, when the encoding data (ENC_DATA) is at the first or third voltage level in the first unit interval and at the second voltage level in the second unit interval, the equalizer (300) using VM FFE can increase the speed of voltage drop or rise to accelerate the transition to the next voltage level.

[0063] FIG. 5 is a drawing showing an example of an equalizer operating in a third mode according to some embodiments of the present application. Below, the equalizer (300) is described using DCL, but this is illustrative and is not limited thereto.

[0064] Referring to FIG. 5, the equalizer (300) can equalize the voltage level in a third mode using DCL. Specifically, the equalizer (300) receives data of the second voltage level (MID_1) of the first unit interval and the first voltage level (HIGH) or third voltage level (LOW) of the second unit interval through a plurality of transistors, and can control the voltage level and timing of the signal through a switching operation.

[0065] That is, referring to the timing diagram on the right, when the encoding data (ENC_DATA) is at the second voltage level in the first unit interval and at the first or third voltage level in the second unit interval, the equalizer (300) using DCL can control the signal crossing point by adjusting the data switching time.

[0067] FIG. 6 is a drawing showing an example of a driver according to some embodiments of the present application.

[0068] Referring to FIG. 6, the driver (400) can receive a voltage level output from the equalizer (300) using a plurality of transistors. Specifically, a plurality of transistors constituting the driver (400) can be turned on or turned off by first to third voltage levels. Based on the first to third voltage levels, the driver (400) can output a multi-level PAM-3 signal by selectively electrically connecting a path between an output terminal and a plurality of voltage nodes. In this specification, the PAM-3 signal and the output data (DQ) corresponding to the PAM-3 signal are used interchangeably with the same meaning.

[0069] That is, the driver (400) can amplify or convert the signal in response to the received voltage level and output output data (DQ) corresponding to the PAM-3 signal.

[0071] FIGS. 7a and 7b illustrate eye diagrams of output data according to some embodiments of the present application.

[0072] Referring to FIG. 7a, FIG. 7a is an eye diagram when no equalizer is applied to the PAM-3 transmitter (10), and it can be seen that the opening and margin of the eye diagram are degraded as attenuation is not compensated.

[0073] On the other hand, referring to FIG. 7b, FIG. 7b is an eye diagram in which an equalizer (300) according to some embodiments described above is applied to a PAM-3 transmitter (10), and it can be seen that the opening and margin of the eye diagram are improved as attenuation is compensated.

[0075] FIG. 8 is a drawing of a PAM-3 transceiver according to some embodiments of the present application. Specifically, the transmitter in FIG. 8 is similar to the PAM-3 transmitter (10) in FIG. 1. Therefore, redundant descriptions of the same PAM-3 transmitter (10) will be omitted below.

[0076] Referring to FIG. 8, the PAM-3 transceiver (1000) may include a transmitter (10) and a receiver (20).

[0077] The transmitter (10) can transmit a signal according to data to the receiver (20) through a channel (CH). The transmitter (10) can transmit signals containing serialized bits of data. For example, the transmitter (10) can transmit signals in a single-ended signaling manner.

[0078] A channel (CH) may be a path that physically or electrically connects a transmitter (10) and a receiver (20). For example, a channel (CH) may be implemented using traces on a PCB (Printed Circuit Board) or a coaxial cable. A channel (CH) may degrade high-frequency components of data transmitted through the channel (CH) due to the skin effect, dielectric loss, etc. When a signal is transmitted through the channel (CH), channel loss may occur at the receiver (1200). Accordingly, each bit of data passing through the channel (CH) may interfere with the next bit(s) due to channel loss or bandwidth limitation, and adjacent symbols may overlap, causing a phenomenon where the bit error rate (BER) increases, i.e., signal interference may occur.

[0079] A receiver (20) is connected to a transmitter (10) via a channel (CH) and can receive output data (DQ) transmitted from the transmitter (10) to restore input data (IN_DATA). To this end, the receiver (20) may include an amplifier (500), a DCDL (Digitally Controlled Delay Line, 600), and a decoder (700).

[0080] The amplifier (500) receives output data (DQ) from the transmitter (10) and can amplify the output data (DQ). Specifically, the amplifier (500) receives the output data (DQ) through a terminal circuit connected to a channel (CH) and can classify the output data (DQ) into odd and even orders. Additionally, the amplifier (500) can use a comparator for each order to compare the voltage of the odd order and the voltage of the even order with a reference voltage. Here, the amplifier (500) can use only a single comparator for each order by classifying the output data (DQ) into odd and even orders.

[0081] Additionally, the amplifier (500) can amplify data of each order through a buffer and store it in a DFF (D Flip-Flop). Furthermore, the data stored in the DFF can be output in response to a clock signal.

[0082] DCDL (600) controls the time delay and can adjust the time difference of the clock signal used at the receiving end. Specifically, DCDL (600) can control the time delay between the comparator of the amplifier (500) and the DFF, and can control the signal transmission between the two circuits to be accurate. For example, DCDL (600) can control the data so that after comparing data at the comparator, it provides a time delay before the data reaches the DFF, thereby ensuring that the data is output from the DFF at the correct timing.

[0083] The decoder (700) can decode the output data amplified from the amplifier (500) to restore 3-bit input data (IN_DATA). Specifically, the decoder (700) can perform decoding based on time. That is, the decoder (700) can restore data by timing the signal using the time delay controlled by the DCDL (600). Accordingly, the decoder (700) can compensate for the signal delay and output 3-bit data that has been accurately restored over time.

[0085] FIG. 9 is a diagram illustrating a termination circuit according to some embodiments of the present application. A termination circuit using TIA is described below, but this is merely illustrative and is not limited thereto.

[0086] Referring to FIG. 9, the termination circuit (510) of the TIA can be implemented in a structure that receives output data (DQ) transmitted from a channel (CH) using a plurality of transistors. Specifically, the termination circuit (510) of the TIA can operate in such a way that a plurality of transistors are selectively turned on or turned off by first to third voltage levels.

[0087] Multiple transistors control the flow of signals in response to different voltage levels, thereby allowing the optimal path to be selectively connected according to the voltage level of the output data (DQ). Consequently, the termination circuit (510) of the TIA selectively connects the path between the transmitting terminal and the output terminal based on the voltage level of the output data (DQ), and through this process, the output data (DQ) can be accurately received.

[0088] In addition, the termination circuit (510) of the TIA can provide a function to analyze the received output data (DQ) and classify it into odd and even orders, thereby ensuring the accuracy and stability of the data signal.

[0090] FIG. 10 is a drawing illustrating a comparator according to some embodiments of the present application.

[0091] Referring to FIG. 10, the comparator (520) can generate a comparison result by comparing output data (DQ) classified into odd and even orders with a reference voltage (VREF) and transfer the comparison result to a buffer to decode it into a digital value. That is, the comparator (520) can generate a digital signal of HIGH or LOW by comparing output data (DQ) having first to third voltage levels with the reference voltage (VREF).

[0092] The above description describes specific embodiments for carrying out the present application. In addition to the embodiments described above, the present application will also include embodiments that are simply modified or can be easily modified. Furthermore, the present application will include technologies that can be easily modified and implemented using the embodiments. Accordingly, the scope of the present application should not be limited to the embodiments described above, but should be defined by the claims set forth below as well as equivalents to the claims of this application. Explanation of the symbols

[0093] 10 : Transmitter 20 : Receiver 100 : Encoder 200 : Multiplexer 300 : Lighting 400 : Driver 500 : Amplifier 600 : DCDL 700 : Decoder

Claims

Claim 1 An encoder that maps input data to a transition having first to third voltage levels within two unit intervals and encodes the input data into encoding data divided into odd and even orders in response to the transition; an equalizer that equalizes the first to third voltage levels in response to the encoding data; and a driver that outputs output data for a PAM-3 (Pulse Amplitude Modulation Level-3) signal in response to the equalized voltage levels, wherein the equalizer equalizes the voltage levels in a first mode when the first or third voltage level is maintained within two consecutive unit intervals, equalizes the voltage levels in a second mode when the first or third voltage level is switched to the second voltage level within at least one unit interval, and equalizes the voltage levels in a third mode when the second voltage level is switched to the first or third voltage level within at least one unit interval. Claim 2 A PAM-3 transmitter according to claim 1, wherein the encoder encodes the input data composed of 3 bits into one of the remaining 8 transitions excluding one of the first to ninth transitions within the 2 unit intervals, and does not use the one transition that maintains the state of the first voltage level during the 2 unit intervals for encoding the input data. Claim 3 In paragraph 2, the equalizer is a PAM-3 transmitter that uses one tap corresponding to one transition maintaining the state of the first voltage level. Claim 4 In paragraph 3, the equalizer is a PAM-3 transmitter using two taps corresponding to the transition maintaining the third voltage level. Claim 5 In claim 1, the equalizer is a PAM-3 transmitter that operates in the first mode to adjust the voltage level of repeating data, operates in the second mode to increase the speed of voltage drop or rise of the voltage level, and operates in the third mode to adjust the data switching time of the voltage level. Claim 6 An encoder that maps input data to a transition having first to third voltage levels within two unit intervals and encodes the input data into encoding data classified into odd and even orders in response to the transition; an equalizer that equalizes the voltage level in a first mode when the first or third voltage level is maintained within two consecutive unit intervals in response to the encoding data, equalizes the voltage level in a second mode when the first or third voltage level is switched to the second voltage level within at least one unit interval in response to the encoding data, and equalizes the voltage level in a third mode when the second voltage level is switched to the first or third voltage level within at least one unit interval in response to the encoding data; and a driver that outputs output data for a PAM-3 (Pulse Amplitude Modulation Level-3) signal in response to the equalized voltage level. A PAM-3 transceiver comprising a receiver that receives the output data and decodes the output data for the PAM-3 signal to generate the input data. Claim 7 In claim 6, the receiver comprises: an amplifier that amplifies the output data; and a decoder that decodes the output data amplified from the amplifier to restore the input data composed of three bits, forming a PAM-3 transceiver. Claim 8 In claim 7, the amplifier is a PAM-3 transceiver that classifies the output data into the odd order and the even order and uses a single comparator for each order. Claim 9 In paragraph 7, the receiver is a PAM-3 transceiver further comprising a DCDL that controls the time delay of the amplifier. Claim 10 In claim 9, the decoder is a PAM-3 transceiver that recovers the input data in response to the adjusted time delay.

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