Gate driving circuit, display device

Abstract

The embodiments of the present disclosure relate to a gate driving circuit and a display device, and more specifically, a gate driving circuit including a sensing unit, a logic unit, and a buffer group can provide a gate driving circuit and a display device that can accurately control a transistor and prevent real-time line-showing phenomena by including a stabilization circuit.

Description

Technology Field

[0001] The embodiments of the present disclosure relate to a gate driving circuit and a display device. Background Technology

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms, and recently, various display devices such as liquid crystal displays and organic light-emitting diodes (OLEDs) are being utilized.

[0003] For image display, the display device may include a display panel having a plurality of data lines and a plurality of gate lines, a data driving circuit that outputs data signals to a plurality of data lines, and a gate driving circuit that outputs scan signals to a plurality of gate lines.

[0004] The gate driving circuit may include a plurality of stage circuits that output a scan signal. The stage circuits include M node, Q node, QH node, and QB node, include a plurality of transistors, and can be supplied with a plurality of high voltages and a plurality of low voltages.

[0005] The source or drain nodes of some transistors included in the stage circuit may be electrically connected to a high-voltage node. If a transistor is electrically connected to a high-voltage node for an extended period, the transistor's threshold voltage may shift. The problem to be solved

[0006] As mentioned above, if the threshold voltage of the transistor is shifted, the transistor may be turned on or turned off for an unintended period.

[0007] If the threshold voltage of a transistor electrically connected to a high-voltage node is shifted, the M node may unintentionally become electrically connected to the high-voltage node. Consequently, the Q node is also charged, and a scan signal may be randomly output from the stage circuit. This may lead to a real-time line visibility phenomenon.

[0008] Accordingly, embodiments of the present disclosure can provide a gate driving circuit and a display device capable of accurately controlling a transistor with a shifted threshold voltage.

[0009] Embodiments of the present disclosure can provide a gate driving circuit and a display device capable of driving at low power by accurately controlling a transistor with a threshold voltage shift.

[0010] In addition, embodiments of the present disclosure may provide a gate driving circuit and a display device in which real-time line visibility is prevented. means of solving the problem

[0011] Embodiments of the present disclosure include a plurality of stage circuits electrically connected to a carry signal output line to which a carry signal is output and a plurality of scan signal output lines to which a scan signal is output, wherein each of the plurality of stage circuits has its operation controlled by the electrical state of each of the Q node and QB node, and includes a buffer group that outputs a scan signal to the plurality of scan signal output lines and outputs the carry signal to the carry signal output line, a logic unit that controls the buffer group during a display driving period for image driving, and a sensing unit that controls the buffer group during a sensing driving period for sensing a characteristic value of a subpixel, wherein the sensing unit includes a Q node charging transistor electrically connected between a first high voltage node to which a first high voltage is supplied and the Q node, a first transistor and a second transistor connected in series between an M node, which is the gate node of the Q node charging transistor, and a node to which a front-end carry signal is input, and a stabilization circuit that controls the connection between a first connection node, which is a node shared by the first transistor and the second transistor connected in series, and the first high voltage node according to the voltage of the M node, wherein the stabilization circuit is the first high voltage A gate driving circuit may be provided comprising a first stabilization transistor and a second stabilization transistor connected in series between a node and the first connection node, a second connection node which is a node shared by the first and second stabilization transistors connected in series, and a third stabilization transistor and a fourth stabilization transistor connected in series between a second connection node and a second high voltage node to which a second high voltage is supplied.

[0012] The first stabilization transistor is electrically connected between the first high-voltage node and the second connection node, and its gate node is electrically connected to the M node; the second stabilization transistor is electrically connected between the second connection node and the first connection node, and its gate node is electrically connected to the M node; and the gate node of the third stabilization transistor and the gate node of the fourth stabilization transistor can be electrically connected to the second high-voltage node.

[0013] The threshold voltage of the first stabilized transistor may have a voltage magnitude smaller than the threshold voltage of the first stabilized transistor stored in memory.

[0014] Embodiments of the present disclosure include a gate driving circuit comprising a plurality of stage circuits electrically connected to a carry signal output line to which a carry signal is output and a plurality of scan signal output lines to which a scan signal is output, and a display panel having a plurality of scan lines to which the scan signal is supplied, wherein each of the plurality of stage circuits has its operation controlled by the electrical state of each of the Q node and QB node, and includes a buffer group that outputs a scan signal to the plurality of scan signal output lines and outputs the carry signal to the carry signal output lines, a logic unit that controls the buffer group during a display driving period for image driving, and a sensing unit that controls the buffer group during a sensing driving period for sensing a characteristic value of a subpixel, wherein the sensing unit includes a Q node charging transistor electrically connected between a first high voltage node to which a first high voltage is supplied and the Q node, a first transistor and a second transistor connected in series between an M node, which is the gate node of the Q node charging transistor, and a node to which a front-end carry signal is input, and a first connection node, which is a node shared by the first transistor and the second transistor connected in series, and the first high voltage according to the voltage of the M node. A display device may be provided that includes a stabilization circuit for controlling the connection of nodes, wherein the stabilization circuit comprises a first stabilization transistor and a second stabilization transistor connected in series between the first high-voltage node and the first connection node, and a third stabilization transistor and a fourth stabilization transistor connected in series between the second connection node, which is a node shared by the first and second stabilization transistors connected in series, and the second high-voltage node to which the second high voltage is supplied. Effects of the invention

[0015] According to embodiments of the present disclosure, a gate driving circuit and a display device capable of accurately controlling a transistor with a shifted threshold voltage can be provided.

[0016] According to embodiments of the present disclosure, a gate driving circuit and a display device capable of driving at low power can be provided by accurately controlling a transistor with a threshold voltage shift.

[0017] According to embodiments of the present disclosure, a gate driving circuit and a display device can be provided in which real-time line visibility is prevented. Brief explanation of the drawing

[0018] FIG. 1 is a configuration diagram of a display device according to embodiments of the present disclosure. FIG. 2 shows a system of a display device according to embodiments of the present disclosure. FIG. 3 shows the connection relationship between a signal line and a stage circuit according to embodiments of the present disclosure. FIG. 4 shows a stage circuit included in a gate driving circuit according to embodiments of the present disclosure. FIG. 5 shows the nth stage circuit according to embodiments of the present disclosure. FIG. 6 is a diagram relating to sensing intervals for sensing characteristic values ​​of driving transistors of a display device according to embodiments of the present disclosure. FIG. 7 is a drawing of the active period and blank period according to embodiments of the present disclosure. FIG. 8 is an output waveform of a stage circuit during an active period and a blank period according to embodiments of the present disclosure. FIG. 9 is a drawing of a stage circuit according to embodiments of the present disclosure. FIG. 10 is a diagram of the circuit configuration of a stabilization circuit according to embodiments of the present disclosure. FIG. 11 is an output waveform of a stage circuit during an active period and a blank period according to embodiments of the present disclosure. Specific details for implementing the invention

[0019] Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the exemplary drawings. In assigning reference numerals to the components of each drawing, the same components may have the same reference numeral as much as possible, even if they are shown in different drawings. Furthermore, in describing the present disclosure, if it is determined that a detailed description of related known components or functions may obscure the essence of the present disclosure, such detailed description may be omitted. Where terms such as "comprising," "having," or "consisting of" are used in this specification, other parts may be added unless "only" is used. Where a component is expressed in the singular, it may include a plural unless there is a special explicit description otherwise.

[0020] Additionally, terms such as first, second, A, B, (a), (b), etc., may be used to describe the components of the present disclosure. These terms are used merely to distinguish the components from other components, and the nature, order, sequence, or number of the components are not limited by such terms.

[0021] In describing the positional relationship of components, where it is stated that two or more components are "connected," "combined," or "joined," it should be understood that while the two or more components may be directly "connected," "combined," or "joined," they may also be "connected," "combined," or "joined" with other components "intervened." Here, the other components may be included in one or more of the two or more components that are "connected," "combined," or "joined" with one another.

[0022] In describing the temporal flow relationship regarding components, methods of operation, or methods of production, for example, when the temporal or sequential relationship is described using "after," "following," "next," or "before," it may include cases where the relationship is not continuous unless "immediately" or "directly" is used.

[0023] Meanwhile, where numerical values ​​or corresponding information regarding a component (e.g., levels, etc.) are mentioned, even without separate explicit notation, the numerical values ​​or corresponding information may be interpreted as including a range of error that may occur due to various factors (e.g., process factors, internal or external shocks, noise, etc.).

[0024] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the attached drawings.

[0025] FIG. 1 is a configuration diagram of a display device (100) according to embodiments of the present disclosure.

[0026] Referring to FIG. 1, a display device (100) according to embodiments of the present disclosure may include a display panel (110) and a driving circuit for driving the display panel (110).

[0027] The driving circuit may include a data driving circuit (120) and a gate driving circuit (130), and may further include a controller (140) that controls the data driving circuit (120) and the gate driving circuit (130).

[0028] A display panel (110) may include a substrate (SUB) and signal wiring such as a plurality of data lines (DL) and a plurality of gate lines (GL) disposed on the substrate (SUB). The display panel (110) may include a plurality of subpixels (SP) connected to a plurality of data lines (DL) and a plurality of gate lines (GL).

[0029] The display panel (110) may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed. In the display panel (110), a plurality of subpixels (SP) for displaying an image are arranged in the display area (DA), and driving circuits (120, 130, 140) may be electrically connected or driving circuits (120, 130, 140) may be mounted in the non-display area (NDA), and a pad portion to which an integrated circuit or printed circuit is connected may be arranged.

[0030] The data driving circuit (120) is a circuit for driving a plurality of data lines (DL) and can supply data signals to a plurality of data lines (DL). The gate driving circuit (130) is a circuit for driving a plurality of gate lines (GL) and can supply scan signals to a plurality of gate lines (GL). The controller (140) can supply a data control signal (DCS) to the data driving circuit (120) to control the operation timing of the data driving circuit (120). The controller (140) can supply a gate control signal (GCS) to the gate driving circuit (130) to control the operation timing of the gate driving circuit (130).

[0031] The controller (140) can start scanning according to the timing implemented in each frame, convert externally input image data to match the data signal format used by the data driving circuit (120), supply the converted image data (Data) to the data driving circuit (120), and control data driving at an appropriate time in accordance with the scan.

[0032] The controller (140) receives various timing signals, including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE: Data Enable), a clock signal (CLK), etc., along with input video data from an external source (e.g., a host system (150)).

[0033] The controller (140) receives timing signals such as a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE), and a clock signal (CLK) to control the data driving circuit (120) and the gate driving circuit (130), generates various control signals (DCS, GCS), and outputs them to the data driving circuit (120) and the gate driving circuit (130).

[0034] For example, the controller (140) can output various gate control signals (GCS: Gate Control Signal), including a gate start pulse (GSP: Gate Start Pulse), a gate shift clock (GSC: Gate Shift Clock), and a gate output enable signal (GOE: Gate Output Enable), in order to control the gate driving circuit (130).

[0035] Additionally, the controller (140) can output various data control signals (DCS), including a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE), in order to control the data driving circuit (120).

[0036] The controller (140) may be implemented as a separate component from the data driving circuit (120), or it may be integrated with the data driving circuit (120) to be implemented as an integrated circuit.

[0037] The data driving circuit (120) receives image data (Data) from the controller (140) and drives the multiple data lines (DL) by supplying data voltage to the multiple data lines (DL). Here, the data driving circuit (120) is also referred to as a source driving circuit.

[0038] This data driving circuit (120) may include one or more source driver integrated circuits (SDIC).

[0039] Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter (DAC), an output buffer, etc. Each source driver integrated circuit (SDIC) may additionally include an analog-to-digital converter (ADC) in some cases.

[0040] For example, each source driver integrated circuit (SDIC) may be connected to the display panel (110) by Tape Automated Bonding (TAB), connected to the bonding pad of the display panel (110) by Chip On Glass (COG) or Chip On Panel (COP), or connected to the display panel (110) by Chip On Film (COF).

[0041] The gate driving circuit (130) can output a scan signal of a turn-on level voltage or a scan signal of a turn-off level voltage according to the control of the controller (140). The gate driving circuit (130) can sequentially drive a plurality of gate lines (GL) by sequentially supplying a scan signal of a turn-on level voltage to a plurality of gate lines (GL).

[0042] The gate driving circuit (130) may be connected to the display panel (110) via tape automatic bonding (TAB), connected to the bonding pad of the display panel (110) via chip-on-glass (COG) or chip-on-panel (COP) methods, or connected to the display panel (110) via chip-on-film (COF) methods. Alternatively, the gate driving circuit (130) may be formed in the non-display area (NDA) of the display panel (110) in the form of a Gate In Panel (GIP) type. The gate driving circuit (130) may be placed on a substrate (SUB) or connected to the substrate (SUB). That is, if the gate driving circuit (130) is of the GIP type, it may be placed in the non-display area (NDA) of the substrate (SUB). If the gate driving circuit (130) is of the chip-on-glass (COG) type, chip-on-film (COF) type, etc., it may be connected to the substrate (SUB). In addition, the gate driving circuit (130) may be placed on the substrate (SUB) and may also be placed in the display area (DA).

[0043] Meanwhile, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed in the display area (DA). For example, at least one of the data driving circuit (120) and the gate driving circuit (130) may be placed so as not to overlap with the subpixels (SP), or may be placed so as to partially or entirely overlap with the subpixels (SP).

[0044] The data driving circuit (120) can convert image data (Data) received from the controller (140) into an analog data voltage and supply it to a plurality of data lines (DL) when a specific gate line (GL) is opened by the gate driving circuit (130).

[0045] The data driving circuit (120) may be connected to one side (e.g., the upper side or the lower side) of the display panel (110). Depending on the driving method, panel design method, etc., the data driving circuit (120) may be connected to both sides (e.g., the upper side and the lower side) of the display panel (110), or to two or more sides of the four sides of the display panel (110).

[0046] The gate driving circuit (130) may be connected to one side (e.g., left or right) of the display panel (110). Depending on the driving method, panel design method, etc., the gate driving circuit (130) may be connected to both sides (e.g., left and right) of the display panel (110), or to two or more of the four sides of the display panel (110).

[0047] The controller (140) may be a timing controller (140) used in conventional display technology, or a control device capable of performing other control functions including the timing controller (140), or a control device different from the timing controller (140), or a circuit within the control device. The controller (140) may be implemented as various circuits or electronic components such as an IC (Integrate Circuit), FPGA (Field Programmable Gate Array), ASIC (Application Specific Integrated Circuit), or processor.

[0048] The controller (140) is mounted on a printed circuit board, a flexible printed circuit, etc., and can be electrically connected to a data driving circuit (120) and a gate driving circuit (130) through the printed circuit board, the flexible printed circuit, etc.

[0049] The controller (140) can transmit and receive signals to and from the data driving circuit (120) according to one or more predetermined interfaces. Here, for example, the interface may include an LVDS (Low Voltage Differential Signaling) interface, an EPI interface, an SPI (Serial Peripheral Interface), etc.

[0050] The controller (140) may include one or more memory media, such as registers.

[0051] The display device (100) according to the embodiments may be a display including a backlight unit such as a liquid crystal display, or a self-emissive display such as an OLED (Organic Light Emitting Diode) display, a Quantum Dot display, or a Micro LED (Micro Light Emitting Diode) display.

[0052] Each of the multiple subpixels (SP) may include a light-emitting element, a driving transistor, a scan transistor, a sensing transistor, and a storage capacitor, etc.

[0053] The driving transistor may be a transistor for driving a light-emitting element. The scan transistor may transmit the image data voltage supplied from the data line (DL) to the gate node of the driving transistor. The sensing transistor may be used in a display driving period for image display or in a sensing driving period for sensing the characteristic value of the driving transistor. The gate node of the scan transistor and the gate node of the sensing transistor may be electrically connected to the gate line (GL).

[0054] In the case where the display device (100) according to the embodiments is an OLED display, each subpixel (SP) may include a self-emitting organic light-emitting diode (OLED) as a light-emitting element. In the case where the display device (100) according to the embodiments is a quantum dot display, each subpixel (SP) may include a light-emitting element made of a quantum dot, which is a semiconductor crystal that emits light. In the case where the display device (100) according to the embodiments is a micro LED display, each subpixel (SP) may include a self-emitting micro LED (Micro Light Emitting Diode) made of an inorganic material as a light-emitting element.

[0055] FIG. 2 shows a system of a display device (100) according to embodiments of the present disclosure.

[0056] Referring to FIG. 2, the display panel (110) may include a display area (DA) where an image is displayed and a non-display area (NDA) where an image is not displayed.

[0057] Referring to FIG. 2, when the data driving circuit (120) includes one or more source driver integrated circuits (SDIC) and is implemented in a chip-on-film (COF) manner, each source driver integrated circuit (SDIC) may be mounted on a circuit film (SF) connected to a non-display area (NDA) of a display panel (110).

[0058] Referring to FIG. 2, the gate driving circuit (130) can be implemented as a gate-in-panel (GIP) type. In this case, the gate driving circuit (130) can be formed in the non-display area (NDA) of the display panel (110). Unlike FIG. 3, the gate driving circuit (130) can also be implemented as a COF (Chip On Film) type.

[0059] A display device (100) may include at least one source printed circuit board (SPCB) for circuit connection between one or more source driver integrated circuits (SDIC) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0060] At least one source printed circuit board (SPCB) may be connected to a circuit film (SF) on which a source driver integrated circuit (SDIC) is mounted. That is, one side of the circuit film (SF) on which the source driver integrated circuit (SDIC) is mounted may be electrically connected to a display panel (110) and the other side may be electrically connected to a source printed circuit board (SPCB).

[0061] A controller (140) and a power management integrated circuit (PMIC: Power Management IC, 210) may be mounted on the control printed circuit board (CPCB). The controller (140) can perform overall control functions related to the driving of the display panel (110) and can control the operation of the data driving circuit (120) and the gate driving circuit (130). The power management integrated circuit (210) can supply various voltages or currents to the data driving circuit (120) and the gate driving circuit (130), or control various voltages or currents to be supplied.

[0062] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be circuitously connected through at least one connecting cable (CBL). Here, the connecting cable (CBL) may be, for example, a flexible printed circuit (FPC), a flexible flat cable (FFC), etc.

[0063] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0064] A display device (100) according to embodiments of the present disclosure may further include a level shifter (200) for adjusting a voltage level. For example, the level shifter (200) may be placed on a control printed circuit board (CPCB) or a source printed circuit board (SPCB).

[0065] In particular, in the display device (100) according to the embodiments of the present disclosure, the level shifter (200) can supply signals required for gate driving to the gate driving circuit (130). For example, the level shifter (200) can supply a plurality of clock signals to the gate driving circuit (130). Accordingly, the gate driving circuit (130) can output a plurality of scan signals to a plurality of gate lines (GL) based on a plurality of clock signals input from the level shifter (200). Here, the plurality of gate lines (GL) can transmit a plurality of scan signals to subpixels (SP) placed in the display area (DA) of the substrate (SUB).

[0066] Multiple clock signals may be voltages that turn on or turn off the transistor.

[0067] “Turn-on level voltage” is a voltage capable of turning on a transistor that receives a scan signal, and “turn-off level voltage” is a voltage capable of turning off a transistor that receives a scan signal.

[0068] If the transistor is an n-type transistor, the turn-on level voltage may be a high level voltage and the turn-off level voltage may be a low level voltage. If the transistor is a p-type transistor, the turn-on level voltage may be a low level voltage and the turn-off level voltage may be a high level voltage. For the sake of convenience of explanation, the following description assumes that the turn-on level voltage is a high level voltage and the turn-off level voltage is a low level voltage.

[0069] FIG. 3 shows the connection relationship between a signal line and a stage circuit (ST) according to embodiments of the present disclosure.

[0070] The gate driving circuit (130) may include a plurality of stage circuits (ST).

[0071] A plurality of stage circuits (ST) are electrically connected to a plurality of signal lines and can be electrically connected to a scan signal output line that outputs a plurality of scan signals (SOUT) and a carry signal output line that outputs a carry signal (C).

[0072] The scan signal (SOUT) output from the stage circuit (ST) can be supplied to a gate line (GL) electrically connected to the scan signal output line. Depending on the control of the Q node, which is the gate node of the transistor electrically connected to the scan clock signal line, the scan clock signal (SCCLK) can be output as the scan signal (SOUT). A Q node charging transistor can be electrically connected between the Q node and the first high voltage node (NHV1). The Q node can be controlled depending on the control of the M node (M), which is the gate node of the Q node charging transistor. The M node (M) can be controlled depending on whether or not a front-end carry signal is input. The detailed configuration of the stage circuit (ST) will be described in detail in the description of FIG. 5 below.

[0073] A plurality of signal lines may include a gate driving voltage line (301), a clock signal line (302), a line selection signal line (303), a reset signal line (304), and a start signal line (305).

[0074] The gate driving voltage line (301) can supply a number of high voltages (GVDD) and a number of low voltages (GVSS) supplied from a power supply circuit (not shown) to a number of stage circuits (ST).

[0075] A plurality of high voltages (GVDD) may include a first high voltage (GVDD1), a second high voltage (GVDD2), and a third high voltage (GVDD3) having different voltage levels. A plurality of low voltages (GVSS) may include a first low voltage (GVSS1), a second low voltage (GVSS2), and a third low voltage (GVSS3) having different voltage levels.

[0076] The clock signal line (302) can supply a number of clock signals (CLKs) input from the controller (140) to a number of stage circuits (ST).

[0077] A plurality of clock signals (CLKs) may include a plurality of carry clock signals (CRCLK) or a plurality of scan clock signals (SCCLK).

[0078] The clock signal line (302) may include a carry clock signal line (not shown) to which a carry clock signal (CRCLK) is supplied, and there may be three carry clock signal lines.

[0079] The clock signal line (302) may include a scan clock signal line (not shown) to which a scan clock signal (SCCLK) is supplied, and there may be 12 scan clock signal lines.

[0080] The line selection signal line (303) can supply a line selection signal (LSP) input from the controller (140) to a number of stage circuits (ST).

[0081] The reset signal line (304) can supply a reset signal (RESET) input from the controller (140) to a number of stage circuits (ST).

[0082] The start signal line (305) can supply a start signal (VST) input from the controller (140) to a number of stage circuits (ST).

[0083] Each of the multiple stage circuits (ST) can output multiple scan signals (SOUT) and one carry signal (C). The multiple scan signals may be four scan signals.

[0084] The scan signal (SOUT) may be a signal supplied to the gate line (GL) during the display driving period for displaying an image. The scan signal (SOUT) may be a signal supplied to the gate line (GL) during the sensing driving period for detecting the characteristic value of the driving transistor.

[0085] A plurality of stage circuits (ST) may further include dummy stage circuits (not shown).

[0086] FIG. 4 shows a stage circuit (ST) included in a gate driving circuit (130) according to embodiments of the present disclosure.

[0087] The stage circuit (ST) can output four scan signals (SOUT) and one carry signal (C).

[0088] The carry signal (C) can be input to the stage circuit (ST) as a setting signal (SET). The carry signal (C) can be input to the stage circuit (ST) as a reset signal (RESET).

[0089] The (n-2)th stage circuit (ST(n-2)) can receive the carry signal (C(n-4)) output from the (n-4)th stage circuit (ST(n-4)) as a setting signal (SET). The (n-2)th stage circuit (ST(n-2)) can receive the carry signal (C(n)) output from the nth stage circuit (STn) as a reset signal (RESET).

[0090] The n-th stage circuit (STn) can receive the carry signal (C(n-2)) output from the (n-2)-th stage circuit (ST(n-2)) as a setting signal (SET). The n-th stage circuit (STn) can receive the carry signal (C(n+2)) output from the (n+2)-th stage circuit (ST(n+2)) as a reset signal (RESET).

[0091] The (n+2)th stage circuit (ST(n+2)) can receive the carry signal (C(n)) output from the nth stage circuit (STn) as a setting signal (SET). The (n+2)th stage circuit (ST(n+2)) can receive the carry signal (C(n+4)) output from the (n+4)th stage circuit (ST(n+4)) as a reset signal (RESET).

[0092] FIG. 5 shows an nth stage circuit (STn) according to embodiments of the present disclosure.

[0093] Each of the plurality of stage circuits (ST) may include a Q node, a QB node (QB), and an M node (M). Each of the plurality of stage circuits (ST) may include a sensing unit (RT), a logic unit (LOG), and a buffer group (BUF).

[0094] The buffer group (BUF) is controlled by the electrical state of each of the Q node and QB node (QB) and can output a scan signal (SOUT) and a carry signal (C). The buffer group (BUF) may include a carry signal output buffer (560) and a scan signal output buffer (570). The scan signal output buffer (570) can output a plurality of scan signals (SOUT). The plurality of scan signals (SOUT) may be four scan signals (SOUT).

[0095] The logic unit (LOG) can control the buffer group (BUF) during the display driving period for video driving. The logic unit (LOG) may include a Q node control unit (520), a first stabilization unit (530), an inverter unit (540), and a second stabilization unit (550).

[0096] The sensing unit (RT) can control the buffer group (BUF) during the sensing driving period for sensing the characteristic value of the driving transistor. The sensing unit (RT) may include a line selection unit (510). The sensing unit (RT) may include a Q node charging transistor connected between the Q node and the first high voltage node (NHV1). The Q node charging transistor may be referred to as the third transistor (T13) below. The M node (M) included in the sensing unit (RT) may be the gate node of the Q node charging transistor.

[0097] Referring to FIG. 5, the nth stage circuit (STn) may include a sensing unit (RT), a logic unit (LOG), and a buffer group (BUF).

[0098] The nth stage circuit (STn) may include a line selection unit (510), a Q node control unit (520), a first stabilization unit (530), an inverter unit (540), a second stabilization unit (550), a carry signal output buffer (560), and a scan signal output buffer (570).

[0099] The first high voltage (GVDD1) can be supplied to the first high voltage node (NHV1). The second high voltage (GVDD2) can be supplied to the second high voltage node (NHV2). The third high voltage (GVDD3) can be supplied to the third high voltage node (NHV3).

[0100] The first low voltage (GVSS1) can be supplied to the first low voltage node (NLV1). The second low voltage (GVSS2) can be supplied to the second low voltage node (NLV2). The third low voltage (GVSS3) can be supplied to the third low voltage node (NLV3).

[0101] The line selection unit (510) can charge the M node (M) with a front-end carry signal (C(n-2)) and charge the Q node with a first high voltage (GVDD1).

[0102] The line selection unit (510) may include first to seventh transistors (T11 to T17) and a pre-charging capacitor (CA).

[0103] The first transistor (T11) can be electrically connected between the node where the front-end carry signal (C(n-2)) is input and the first connection node (NC1).

[0104] Depending on the line select signal (LSP) input to the gate node of the first transistor (T11), the first transistor (T11) is turned on, and the front-end carry signal (C(n-2)) can be supplied to the first connection node (NC1).

[0105] The second transistor (T12) can be electrically connected between the first connection node (NC1) and the M node (M).

[0106] Depending on the line select signal (LSP) input to the gate node of the second transistor (T12), the second transistor (T12) is turned on, and the first connection node (NC1) can be electrically connected to the M node (M).

[0107] When the first transistor (T11) and the second transistor (T12) are turned on, the front-end carry signal (C(n-2)) can be supplied to the M node (M) to be charged.

[0108] The seventh transistor (T17) can be electrically connected between the first high voltage node (NHV1) and the first connection node (NC1).

[0109] The gate node of the seventh transistor (T17) can be electrically connected to the M node (M). Depending on the voltage level of the M node (M), the seventh transistor (T17) can be turned on.

[0110] When the seventh transistor (T17) is turned on, the first high voltage (GVDD1) can be supplied to the first connection node (NC1). When a low-level line select signal (LSP) is supplied to the gate node of the first transistor (T11), the first transistor (T11) can be kept in a completely turned-off state due to the voltage difference between the gate node voltage of the first transistor (T11) and the first connection node (NC1). Accordingly, current leakage of the first transistor (T11) and the resulting voltage drop of the M node (M) are prevented, so that the voltage of the M node (M) can be maintained stably.

[0111] A pre-charging capacitor (CA) can be connected between the first high voltage node (NHV1) and the M node (M).

[0112] When the first transistor (T11), the second transistor (T12), and the seventh transistor (T17) are turned on, the pre-charging capacitor (CA) can store the voltage difference between the first high voltage (GVDD1) and the front-end carry signal (C(n-2)). When the first transistor (T11), the second transistor (T12), and the seventh transistor (T17) are turned off, the voltage of the M node (M) can be maintained for a certain period of time at the voltage stored in the pre-charging capacitor (CA).

[0113] The third transistor (T13) can be electrically connected between the first high voltage node (NHV1) and the first shared node (NS1).

[0114] The gate node of the third transistor (T13) can be electrically connected to the M node (M). Depending on the voltage level of the M node (M), the third transistor (T13) can be turned on, and the first high voltage (GVDD1) can be delivered to the first shared node (NS1).

[0115] The fourth transistor (T14) can be electrically connected between the first shared node (NS1) and the Q node.

[0116] When a reset signal (RESET) is input to the gate node of the fourth transistor (T14), the fourth transistor (T14) is turned on, and the first shared node (NS1) can be electrically connected to the Q node.

[0117] When the third transistor (T13) and the fourth transistor (T14) are turned on, the first high voltage (GVDD1) can be supplied to the Q node to charge it.

[0118] The fifth transistor (T15) can be electrically connected between the Q node and the QH node (QH).

[0119] When a start signal (VST) supplied to the gate node of the fifth transistor (T15) is turned on, the fifth transistor (T15) can be electrically connected to the Q node (QH).

[0120] The sixth transistor (T16) can be electrically connected between the QH node (QH) and the third low voltage node (NLV3).

[0121] When a start signal (VST) supplied to the gate node of the sixth transistor (T16) is turned on, the sixth transistor (T16) can be turned on, and the QH node (QH) can be discharged to the third low voltage (GVSS3).

[0122] The Q node control unit (520) can charge the Q node to a first high voltage (GVDD1) according to the front carry signal (C(n-2)) and discharge the Q node to a third low voltage (GVSS3) according to the rear carry signal (C(n+2)).

[0123] The Q node control unit (520) may include first to eighth transistors (T21 to T28).

[0124] The first transistor (T21) can be electrically connected between the first high voltage node (NHV1) and the second connection node (NC2).

[0125] Depending on the front-end carry signal (C(n-2)) input to the gate node of the first transistor (T21), the first transistor (T21) can be turned on, and the first high voltage (GVDD1) can be supplied to the second connection node (NC2).

[0126] The second transistor (T22) can be electrically connected between the second connection node (NC2) and the Q node.

[0127] Depending on the front-end carry signal (C(n-2)) supplied to the gate node of the second transistor (T22), the second transistor (T22) is turned on, and the second connection node (NC2) can be electrically connected to the Q node.

[0128] When the first transistor (T21) and the second transistor (T22) are turned on, the first high voltage (GVDD1) can be supplied to the Q node to charge it.

[0129] The third transistor (T23) can be electrically connected between the third high-voltage node (NHV3) and the second-first shared node (NS21).

[0130] The fourth transistor (T24) can be electrically connected between the second-1 shared node (NS21) and the second connected node (NC2).

[0131] When the third transistor (T23) and the fourth transistor (T24) are turned on, the third high voltage (GVDD3) can be supplied to the second connection node (NC2).

[0132] The fifth transistor (T25) can be electrically connected between the Q node and the QH node (QH).

[0133] Depending on the rear carry signal (C(n+2)) input to the gate node of the fifth transistor (T25), the fifth transistor (T25) is turned on, and the Q node can be electrically connected to the QH node (QH).

[0134] The sixth transistor (T26) can be connected between the QH node (QH) and the third low voltage node (NLV3).

[0135] Depending on the rear carry signal (C(n+2)) input to the gate node of the sixth transistor (T26), the sixth transistor (T26) is turned on, and the QH node (QH) can be discharged to the voltage level of the third low voltage (GVSS3).

[0136] When the fifth transistor (T25) and the sixth transistor (T26) are turned on, the Q node and the QH node (QH) can be discharged to the third low voltage (GVSS3).

[0137] The seventh transistor (T27) can be electrically connected between the first high voltage node (NHV1) and the second-to-second shared node (NS22).

[0138] The gate node of the seventh transistor (T27) can be electrically connected to the Q node. The seventh transistor (T27) is turned on by the voltage of the Q node, so that the first high voltage node (NHV1) can be electrically connected to the second-2 shared node (NS22).

[0139] The eighth transistor (T28) can be electrically connected between the second-2 shared node (NS22) and the QH node (QH).

[0140] The gate node of the eighth transistor (T28) can be electrically connected to the Q node. The eighth transistor (T28) is turned on by the voltage of the Q node, and the second-2 shared node (NS22) can be electrically connected to the QH node (QH).

[0141] When the 7th transistor (T27) and the 8th transistor (T28) are turned on, the 1st high voltage (GVDD1) can be supplied to the QH node (QH) to charge it.

[0142] The first stabilization unit (530) can discharge the Q node and QH node (QH) to a third low voltage (GVSS3) according to the voltage level of the QB node (QB).

[0143] The first stabilization unit (530) may include a first transistor (T31) and a second transistor (T32).

[0144] The first transistor (T31) can be electrically connected between the Q node and the QH node (QH).

[0145] The gate node of the first transistor (T31) can be electrically connected to the QB node (QB). The first transistor (T31) is turned on by the voltage of the QB node (QB), and the Q node can be electrically connected to the QH node (QH).

[0146] The second transistor (T32) can be electrically connected between the QH node (QH) and the third low voltage node (NLV3).

[0147] The gate node of the second transistor (T32) can be electrically connected to the QB node (QB). The second transistor (T32) is turned on by the voltage of the QB node (QB), and the QH node (QH) can be discharged to the third low voltage (GVSS3).

[0148] When the first transistor (T31) and the second transistor (T32) are turned on, the Q node and the QH node (QH) can be discharged to the third low voltage (GVSS3).

[0149] The inverter unit (540) can change the voltage level of the QB node (QB) according to the voltage level of the Q node.

[0150] The inverter section (540) may include first to fifth transistors (T41 to T45).

[0151] The first transistor (T41) can be electrically connected between the second high voltage node (NHV2) and the QB node (QB).

[0152] The gate node of the first transistor (T41) can be electrically connected to the fourth connection node (NC4). The first transistor (T41) is turned on by the voltage of the fourth connection node (NC4), and the second high voltage (GVDD2) can be supplied to the QB node (QB) to charge it.

[0153] The second transistor (T42) can be electrically connected between the second high voltage node (NHV2) and the fourth shared node (NS4).

[0154] The second transistor (T42) is turned on by the second high voltage (GVDD2) supplied to the gate node of the second transistor (T42), and the second high voltage (GVDD2) can be supplied to the fourth shared node (NS4).

[0155] The third transistor (T43) can be electrically connected between the fourth shared node (NS4) and the fourth connected node (NC4).

[0156] The third transistor (T43) is turned on by the second high voltage (GVDD2) supplied to the gate node of the third transistor (T43), so that the fourth shared node (NS4) can be electrically connected to the fourth connection node (NC4).

[0157] When the second transistor (T42) and the third transistor (T43) are turned on, the second high voltage (GVDD2) can be supplied to the fourth connection node (NC4).

[0158] The fourth transistor (T44) can be electrically connected between the fourth connection node (NC4) and the second low voltage node (NLV2).

[0159] The gate node of the fourth transistor (T44) can be electrically connected to the Q node. The fourth transistor (T44) is turned on by the voltage of the Q node, and the fourth connection node (NC4) can be discharged to the second low voltage (GVSS2).

[0160] The fifth transistor (T45) can be electrically connected between the QB node (QB) and the third low voltage node (NLV3).

[0161] The gate node of the fifth transistor (T45) can be electrically connected to the Q node. The fifth transistor (T45) is turned on by the voltage of the Q node, and the QB node (QB) can be discharged to the third low voltage (GVSS3).

[0162] The second stabilization unit (550) can discharge the QB node (QB) to the third low voltage (GVSS3) according to the input of the front-end carry signal (C(n-2)), the input of the reset signal (RESET), and the voltage level of the M node (M).

[0163] The second stabilization unit (550) may include the first to third transistors (T51 to T53).

[0164] The first transistor (T51) can be electrically connected between the QB node (QB) and the third low voltage node (NLV3).

[0165] The first transistor (T51) is turned on upon input of the front-end carry signal (C(n-2)), and the QB node (QB) can be discharged to the third low voltage (GVSS3).

[0166] The second transistor (T52) can be electrically connected between the QB node (QB) and the fifth shared node (NS5).

[0167] When a reset signal (RESET) is input to the gate node of the second transistor (T52), the second transistor (T52) is turned on, and the QB node (QB) can be electrically connected to the fifth shared node (NS5).

[0168] The third transistor (T53) can be electrically connected between the fifth shared node (NS5) and the third low-voltage node (NLV3).

[0169] The gate node of the third transistor (T53) can be electrically connected to the M node (M). The third transistor (T53) is turned on by the voltage of the M node (M), so that the fifth shared node (NS5) can be electrically connected to the third low voltage node (NLV3).

[0170] When the second transistor (T52) and the third transistor (T53) are turned on, the QB node (QB) can be discharged to the third low voltage (GVSS3).

[0171] The carry signal output buffer (560) can output a carry signal (C(n)) based on a carry clock signal (CRCLK1) or a third low voltage (GVSS3) depending on the voltage level of the Q node or the voltage level of the QB node (QB).

[0172] The carry signal output buffer (560) may include a first transistor (T61), a second transistor (T62), and a boosting capacitor (CC).

[0173] The boosting capacitor (CC) can be electrically connected between the gate node of the first transistor (T61) and the carry output node (NOC).

[0174] The first transistor (T61) can be electrically connected between the carry clock node (NCR), where the carry clock signal (CRCLK1) is input, and the carry output node (NOC).

[0175] The gate node of the first transistor (T61) can be electrically connected to the Q node. Depending on the voltage level of the Q node, the first transistor (T61) is turned on, and the carry clock signal (CRCLK1) can be output as a carry signal (C(n)) to the carry output node (NOC). The carry signal (C(n)) can be output to the carry signal output line via the carry output node (NOC).

[0176] When the carry signal (C(n)) is output, the voltage of the carry output node (NOC) rises, which can increase the voltage charged to the boosting capacitor (CC); consequently, the voltage of the Q node rises and bootstraps. When the voltage of the Q node is bootstrapped, the carry clock signal (CRCLK) can be rapidly output to the carry output node (NOC) without voltage distortion.

[0177] The second transistor (T62) can be electrically connected between the carry output node (NOC) and the third low voltage node (NLV3).

[0178] The gate node of the second transistor (T62) can be electrically connected to the QB node (QB). Depending on the voltage level of the QB node (QB), the second transistor (T62) is turned on, and the third low voltage (GVSS3) can be output as a low-level carry signal (C(n)) to the carry output node (NOC). The carry signal (C(n)) can be output to the carry signal output line via the carry output node (NOC).

[0179] The scan signal output buffer (570) can output a plurality of scan signals (SOUT(i), SOUT(i+1), SOUT(i+2), SOUT(i+3)) based on the first to fourth scan clock signals (SCCLK1, SCCLK2, SCCLK3, SCCLK4) or the first low voltage (GVSS1) depending on the voltage level of the Q node or the voltage level of the QB node (QB). (i is a natural number)

[0180] The scan signal output buffer (570) may include first to eighth transistors (T71 to T78) and first to fourth boosting capacitors (CS1, CS2, CS3, CS4).

[0181] The first boosting capacitor (CS1) can be electrically connected between the gate node of the first transistor (T71) and the first output node (NO1).

[0182] The first transistor (T71) can be electrically connected between the first scan clock node (NSC1), to which the first scan clock signal (SCCLK1) is input, and the first output node (NO1).

[0183] The second boosting capacitor (CS2) can be electrically connected between the gate node of the second transistor (T72) and the second output node (NO2).

[0184] The second transistor (T72) can be electrically connected between the second scan clock node (NSC2), into which the second scan clock signal (SCCLK2) is input, and the second output node (NO2).

[0185] The third boosting capacitor (CS3) can be electrically connected between the gate node of the third transistor (T73) and the third output node (NO3).

[0186] The third transistor (T73) can be electrically connected between the third scan clock node (NSC3), into which the third scan clock signal (SCCLK3) is input, and the third output node (NO3).

[0187] The fourth boosting capacitor (CS4) can be electrically connected between the gate node of the fourth transistor (T74) and the fourth output node (NO4).

[0188] The fourth transistor (T74) can be electrically connected between the fourth scan clock node (NSC4), to which the fourth scan clock signal (SCCLK4) is input, and the fourth output node (NO4).

[0189] The gate nodes of each of the first transistor (T71), second transistor (T72), third transistor (T73), and fourth transistor (T74) can be electrically connected to the Q node. Depending on the voltage level of the Q node, each of the first transistor (T71), second transistor (T72), third transistor (T73), and fourth transistor (T74) can be turned on.

[0190] When the first transistor (T71) is turned on, the first scan clock signal (SCCLK1) can be output as a scan signal (SOUT(i)) to the first output node (NO1).

[0191] When the second transistor (T72) is turned on, the second scan clock signal (SCCLK2) can be output as a scan signal (SOUT(i+1)) to the second output node (NO2).

[0192] When the third transistor (T73) is turned on, the third scan clock signal (SCCLK3) can be output as a scan signal (SOUT(i+2)) to the third output node (NO3).

[0193] When the fourth transistor (T74) is turned on, the fourth scan clock signal (SCCLK4) can be output as a scan signal (SOUT(i+3)) to the fourth output node (NO4).

[0194] When scan signals (SOUT(i), SOUT(i+1), SOUT(i+2), SOUT(i+3)) are output, the voltages of the first to fourth output nodes (NO1, NO2, NO3, NO4) rise, and the voltage charged to the first to fourth boosting capacitors (CS1, CS2, CS3, CS4) can rise, and accordingly, the voltage of the Q node can be bootstrapped by raising it. When the voltage of the Q node is bootstrapped, high voltage level scan clock signals (SCCLK(i), SCCLK(i+1), SCCLK(i+2), SCCLK(i+3)) can be rapidly output to the first to fourth output nodes (NO1, NO2, NO3, NO4) without voltage distortion.

[0195] The fifth transistor (T75) can be electrically connected between the first output node (NO1) and the first low voltage node (NLV1).

[0196] The sixth transistor (T76) can be electrically connected between the second output node (NO2) and the first low voltage node (NLV1).

[0197] The seventh transistor (T77) can be electrically connected between the third output node (NO3) and the first low voltage node (NLV1).

[0198] The eighth transistor (T78) can be electrically connected between the fourth output node (NO4) and the first low voltage node (NLV1).

[0199] The gate nodes of each of the fifth transistor (T75), sixth transistor (T76), seventh transistor (T77), and eighth transistor (T78) can be electrically connected to the QB node (QB). Depending on the voltage level of the QB node (QB), the fifth transistor (T75), sixth transistor (T76), seventh transistor (T77), and eighth transistor (T78) can be turned on.

[0200] When the fifth transistor (T75) is turned on, the first low voltage (GVSS1) can be output as a low-level scan signal (SOUT(i)) to the first output node (NO1).

[0201] When the sixth transistor (T76) is turned on, the first low voltage (GVSS1) can be output to the second output node (NO2) as a low-level scan signal (SOUT(i+1)).

[0202] When the seventh transistor (T77) is turned on, the first low voltage (GVSS1) can be output as a low-level scan signal (SOUT(i+2)) to the third output node (NO3).

[0203] When the eighth transistor (T78) is turned on, the first low voltage (GVSS1) can be output as a low-level scan signal (SOUT(i+3)) to the fourth output node (NO4).

[0204] Scan signals (SOUT(i), SOUT(i+1), SOUT(i+2), SOUT(i+3)) can be output to the gate line (GL) through the scan signal output line.

[0205] FIG. 6 is a diagram relating to sensing intervals for sensing characteristic values ​​of driving transistors of a display device (100) according to embodiments of the present disclosure.

[0206] Referring to FIG. 6, a display device (100) according to embodiments of the present disclosure can sense the characteristic value of a driving transistor in each subpixel (SP) placed in a display panel (110) when a Power On Signal occurs. This sensing process is called an "On-Sensing Process."

[0207] In addition, when a Power Off Signal occurs, the characteristic value of the driving transistor within each subpixel (SP) placed on the display panel (110) may be sensed before an Off-Sequence, such as power cutoff, is performed. This sensing process is called an "Off-Sensing Process."

[0208] In addition, the characteristic values ​​of the driving transistors within each subpixel (SP) can be sensed during display operation, from the time a power-on signal is generated until a power-off signal is generated. This sensing process is called the "Real-time Sensing Process."

[0209] As the aforementioned sensing process proceeds, the characteristic value of the driving transistor can be sensed, and the sensed characteristic value of the driving transistor can be stored in memory.

[0210] The memory may be placed inside the controller (140) or separately placed outside.

[0211] The Vertical Sync (VSYNC) signal is a control signal for defining frames and may repeatedly include signal intervals defining the Active Period (ACT) and signal intervals defining the Blank Period (BLANK). The Active Period (ACT) is the period during which actual display driving for updating the image takes place, and the Blank Period (BLANK) may be a rest period during which actual display driving does not take place.

[0212] For example, the signal interval defining the active period (ACT) may be a high-level voltage interval, and the signal interval defining the blank period (BLANK) may be a low-level voltage interval. As another example, the signal interval defining the active period (ACT) may be a low-level voltage interval, and the signal interval defining the blank period (BLANK) may be a high-level voltage interval.

[0213] A single frame period may include one active period (ACT) and one blank period (BLANK).

[0214] The aforementioned real-time sensing process can be performed during every blank period between active periods based on the vertical synchronization signal (VSYNC).

[0215] FIG. 7 is a drawing of the active period (ACT) and blank period (BLANK) according to embodiments of the present disclosure.

[0216] The Nth frame (Frame N) may include an active period (ACT) and a blank period (BLANK).

[0217] During the active period (ACT), a scan signal (SOUT) can be supplied sequentially to each of the gate lines (GL).

[0218] During the blank period, the real-time sensing process can be carried out. In other words, the blank period and the sensing operation period can overlap.

[0219] During the blank period (BLANK), a scan signal (SOUT) can be supplied to only one gate line (GL_M) among multiple gate lines (GL).

[0220] A single gate line (GL_M) supplied with a scan signal (SOUT) can be selected sequentially or randomly.

[0221] A single gate line (GL_M) supplied with a scan signal (SOUT) can be electrically connected to multiple subpixels (SP). That is, the subpixels (SP) can receive the scan signal (SOUT).

[0222] Sensing of the characteristic value of the driving transistor included in the subpixel (SP) can be performed on the subpixel (SP) that receives the scan signal (SOUT).

[0223] The N+1th frame (Frame N+1) may include an active period (ACT) and a blank period (BLANK).

[0224] During the active period (ACT), a scan signal (SOUT) can be supplied sequentially to each of the gate lines (GL).

[0225] During the blank period, the real-time sensing process can be carried out. In other words, the blank period and the sensing operation period can overlap.

[0226] During the blank period (BLANK), a scan signal (SOUT) can be supplied to only one gate line (GL_L) among multiple gate lines (GL).

[0227] One gate line (GL_L) supplied with a scan signal (SOUT) can be selected sequentially or randomly.

[0228] A single gate line (GL_L) supplied with a scan signal (SOUT) can be electrically connected to multiple subpixels (SP). That is, the subpixels (SP) can receive the scan signal (SOUT).

[0229] Sensing of the characteristic value of the driving transistor included in the subpixel (SP) can be performed on the subpixel (SP) that receives the scan signal (SOUT).

[0230] FIG. 8 is an output waveform of a stage circuit (ST) during an active period (ACT) and a blank period (BLANK) according to embodiments of the present disclosure.

[0231] During the active period (ACT), each of the multiple stage circuits (ST) can output a scan signal (SOUT).

[0232] Referring to FIG. 8, the waveform of the scan signal (SOUT) output from each of the multiple stage circuits (ST) during the active period (ACT) can be observed. However, the waveform of the scan signal (SOUT) is not limited to this.

[0233] During the blank period (BLANK), the scan signal (SOUT) may be output from a second stage circuit (ST2), which is one of the stage circuits among the plurality of stage circuits (ST). The second stage circuit (ST2) may include a plurality of scan signal output lines. The scan signal (SOUT) may be output from one of the plurality of scan signal output lines.

[0234] Referring to FIG. 5, one stage circuit (ST2) that outputs the aforementioned scan signal (SOUT) can output the scan signal (SOUT) depending on whether the M node (M) is charged. That is, if the M node (M) of the second stage circuit (ST2) is charged during the blank period (BLANK), the second stage circuit (ST2) can output the scan signal (SOUT).

[0235] If the M node (M) of the stage circuit (ST) is not charged, the scan signal (SOUT) cannot be output from the stage circuit.

[0236] That is, among the multiple stage circuits (ST), only the second stage circuit (ST2) can output a scan signal (SOUT), and the remaining stage circuits, where the M node (M) is not charged, cannot output a scan signal (SOUT).

[0237] However, a scan signal (SOUT) may be output from all or part of the remaining stage circuit (ST1). For convenience of explanation, all or part of the remaining stage circuit (ST1) is referred to as the first stage circuit (ST1) below.

[0238] Referring to FIG. 8, the waveform of the scan signal (SOUT) output from the first stage circuit (ST1) can be observed. As the first stage circuit (ST1) outputs the scan signal (SOUT), a problem occurs in which a “real-time line visibility phenomenon” takes place. The reason for the aforementioned problem is as follows.

[0239] Referring to FIG. 5, the M node (M) included in the first stage circuit (ST1) during the blank period (BLANK) may be in a voltage level state that does not output a scan signal (SOUT). That is, the voltage state of the M node (M) may be a low level voltage state, which may be a voltage that causes the seventh transistor (T17) to turn off. However, depending on the type of the seventh transistor (T17), it may be a high level voltage.

[0240] Meanwhile, the seventh transistor (T17) can be electrically connected to the first high voltage node (NHV1). When the seventh transistor (T17) is connected to the first high voltage node (NHV1) for a long period, the threshold voltage of the seventh transistor (T17) can be negatively shifted. That the threshold voltage of the driving transistor has been negatively shifted means that the threshold voltage of the driving transistor is smaller than the threshold voltage stored in memory according to the sensing process.

[0241] As the threshold voltage of the seventh transistor (T17) is negatively shifted, the seventh transistor (T17) can be turned on. Accordingly, the first high voltage node (NHV1) and the first connection node (NC1) can be electrically connected. As the first high voltage node (NHV1) and the first connection node (NC1) are connected, the voltage of the M node (M) is not maintained at a low level voltage and the voltage value may fluctuate. That is, even though the voltage of the M node (M) of the first stage circuit (ST1) is designed to be maintained in a low state, the voltage of the M node (M) of the first stage circuit (ST1) may fluctuate, and the scan signal (SOUT) may be output from the first stage circuit (ST1).

[0242] In other words, as the threshold voltage of the seventh transistor (T17) included in the first stage circuit (ST1) is negatively shifted, the scan signal (SOUT) is output from the first stage circuit (ST1), and a real-time line display phenomenon may occur.

[0243] Accordingly, embodiments of the present disclosure can provide a gate driving circuit (130) and a display device (100) capable of accurately controlling a transistor with a shifted threshold voltage.

[0244] Additionally, embodiments of the present disclosure may provide a gate driving circuit (130) and a display device (100) with improved real-time line visibility.

[0245] FIG. 9 is a drawing of a stage circuit (ST) according to embodiments of the present disclosure. FIG. 10 is a drawing of a circuit configuration of a stabilization circuit (911) according to embodiments of the present disclosure.

[0246] Referring to FIG. 9, the nth stage circuit (STn) may include a sensing unit (RT), a logic unit (LOG), and a buffer group (BUF).

[0247] The nth stage circuit (STn) may include a line selection unit (910), a Q node control unit (920), a first stabilization unit (930), an inverter unit (940), a second stabilization unit (950), a carry signal output buffer (960), and a scan signal output buffer (970).

[0248] The sensing unit (RT) may include a line selection unit (910). The logic unit (LOG) may include a Q node control unit (920), a first stabilization unit (930), an inverter unit (940), and a second stabilization unit (950). The buffer group (BUF) may include a carry signal output buffer (960) and a scan signal output buffer (970).

[0249] The sensing unit (RT) may include a first-1 connection node (NC11), which is a node shared by the first transistor (T11) and the second transistor (T12), and a first-1 shared node (NS11), which is a node shared by the third transistor (T13) and the fourth transistor (T14). Among the features of the nth stage circuit (STn) shown in FIG. 9, features identical to the features of the nth stage circuit (STn) described in FIG. 5 may be omitted from the description.

[0250] Referring to FIG. 9, the sensing unit (RT) may include a first transistor (T11), a second transistor (T12), a third transistor (T13), and a stabilization circuit (911).

[0251] The first transistor (T11) can be electrically connected between the node where the front-end carry signal (C(n-2)) is input and the first-1 connection node (NC11).

[0252] The second transistor (T12) can be electrically connected between the first-1 connection node (NC11) and the M node (M).

[0253] The third transistor (T13) can be electrically connected between the first high voltage node (NHV1) and the Q node.

[0254] The stabilization circuit (911) can control the connection between the first-1 connection node (NC11) and the first high voltage node (NHV1) to which the first high voltage (GVDD1) is supplied, depending on the voltage of the M node (M).

[0255] The stabilization circuit (911) may include a first stabilization transistor (Ts1), a second stabilization transistor (Ts2), a third stabilization transistor (Ts3), and a fourth stabilization transistor (Ts4). The first stabilization transistor (Ts1) and the second stabilization transistor (Ts2) may share a first-second connection node (NC12). The third stabilization transistor (Ts3) and the fourth stabilization transistor (Ts4) may be arranged in series between the third high-voltage node (NHV3) and the first-second connection node (NC12).

[0256] Referring to FIG. 10, the first stabilization transistor (Ts1) can be electrically connected between the first high voltage node (NHV1) and the first-second connection node (NC12), and the gate node of the first stabilization transistor (Ts1) can be electrically connected to the M node (M).

[0257] The second stabilization transistor (Ts2) can be electrically connected between the first-2 connection node (NC12) and the first-1 connection node (NC11), and the gate node of the second stabilization transistor (Ts2) can be electrically connected to the M node (M).

[0258] The gate node of the third stabilization transistor (Ts3) and the gate node of the fourth stabilization transistor (Ts4) can be electrically connected to the third high voltage node (NHV3).

[0259] FIG. 11 is an output waveform of a stage circuit (ST) during an active period (ACT) and a blank period (BLANK) according to embodiments of the present disclosure.

[0260] During the active period (ACT), each of the multiple stage circuits (ST) can output a scan signal (SOUT).

[0261] Referring to FIG. 11, the waveform of the scan signal (SOUT) output from each of the multiple stage circuits (ST) during the active period (ACT) can be observed. However, the waveform of the scan signal (SOUT) is not limited to this.

[0262] Sensing operation proceeds during the blank period, so the blank period and the sensing operation period may overlap.

[0263] A plurality of stage circuits (ST) may include a first stage circuit (ST1) that does not output a scan signal during the sensing driving period and a second stage circuit (ST2) that outputs a scan signal during the sensing driving period.

[0264] The first stage circuit (ST1), in which the voltage of the M node (M) is maintained in a low state during the sensing driving period, may not output a scan signal (SOUT).

[0265] Referring to FIG. 10, during the sensing driving period, the voltage difference value between the first-second connection node (NC12) included in the first stage circuit (ST1) and the gate node of the first stabilization transistor (Ts1) may be a voltage value that causes the first stabilization transistor (Ts1) to turn off.

[0266] Accordingly, during the sensing driving period, the first stabilization transistor (Ts1) included in the first stage circuit (ST1) may be in a turned-off state.

[0267] That is, during the sensing driving period, the voltage of the first-second connection node (NC12) included in the first stage circuit (ST1) may be greater than the voltage of the gate node of the first stabilization transistor (Ts1) included in the first stage circuit (ST1). However, depending on the type of the first stabilization transistor (Ts1), the voltage of the first-second connection node (NC12) may be smaller than the voltage of the gate node of the first stabilization transistor (Ts1).

[0268] Referring to FIGS. 9 and 10, as the first stabilization transistor (Ts1) is in a turned-off state, the first high voltage node (NHV1) cannot be electrically connected to the M node (M), so the voltage of the M node (M) can be maintained constant. The voltage of the M node (M) may be a voltage at which a scan signal (SOUT) cannot be output, and the voltage of the M node (M) may be maintained at a low level voltage. However, depending on the type of transistor, it may be maintained at a high level voltage. The voltage of the M node (M) maintained constant may fluctuate slightly, but it does not fluctuate to the extent that the on / off of other transistors connected to the M node (M) is controlled.

[0269] That is, even though the threshold voltage of the first stabilization transistor (Ts1) can be negatively shifted, the first stabilization transistor (Ts1) can be kept in a turned-off state. Accordingly, the real-time line visibility phenomenon may not occur.

[0270] Referring to FIG. 11, a waveform can be observed in which the first stage circuit (ST1), in which the voltage of node M (M) is maintained at a low level voltage, does not output a scan signal (SOUT).

[0271] A second stage circuit (ST2), in which the voltage of node M (M) is maintained at a high level during the sensing driving period, can output a scan signal (SOUT).

[0272] Referring to FIGS. 9 and 10, during the sensing driving period, the first stabilization transistor (Ts1) and the second stabilization transistor (Ts2) may be in a turned-on state depending on the voltage state of the M node (M).

[0273] In a second stage circuit (ST2) in which the voltage of the M node (M) is maintained at a high level voltage, the first stabilization transistor (Ts1) and the second stabilization transistor (Ts2) included in the second stage circuit (ST2) can be turned on. Accordingly, the first-1 connection node (NC11) included in the second stage circuit (Ts2) can be electrically connected to the first high voltage node (NHV1).

[0274] When the M node (M) included in the second stage circuit (ST2) is in a high-level voltage state and a reset signal (RESET) is applied to the gate node of the fourth transistor (T14), the Q node can be charged to the first high voltage (GVDD1).

[0275] And a scan signal (SOUT) can be output to a single scan signal output line included in a plurality of scan signal output lines.

[0276] Referring to FIG. 11, the second stage circuit (ST2), in which the voltage of node M (M) is maintained at a high level voltage state, can output a scan signal (SOUT) and the output waveform can be checked.

[0277] According to the embodiments of the present disclosure described above, a gate driving circuit and a display device capable of accurately controlling a transistor with a shifted threshold voltage can be provided.

[0278] According to embodiments of the present disclosure, a gate driving circuit and a display device capable of driving at low power can be provided by accurately controlling a transistor with a threshold voltage shift.

[0279] According to embodiments of the present disclosure, a gate driving circuit and a display device with improved real-time line visibility can be provided.

[0280] The embodiments of the present disclosure described above are briefly explained as follows.

[0281] According to embodiments of the present disclosure, the apparatus comprises a plurality of stage circuits electrically connected to a carry signal output line to which a carry signal is output and a plurality of scan signal output lines to which a scan signal is output, wherein each of the plurality of stage circuits has its operation controlled by the electrical state of each of the Q node and QB node, and includes a buffer group that outputs a scan signal to the plurality of scan signal output lines and outputs the carry signal to the carry signal output line, a logic unit that controls the buffer group during a display driving period for image driving, and a sensing unit that controls the buffer group during a sensing driving period for sensing a characteristic value of a subpixel, wherein the sensing unit includes a Q node charging transistor electrically connected between a first high voltage node to which a first high voltage is supplied and the Q node, a first transistor and a second transistor connected in series between an M node, which is the gate node of the Q node charging transistor, and a node to which a front-end carry signal is input, and a stabilization circuit that controls the connection between a first connection node, which is a node shared by the first transistor and the second transistor connected in series, and the first high voltage node according to the voltage of the M node, wherein the stabilization circuit comprises the first A gate driving circuit may be provided comprising a first stabilization transistor and a second stabilization transistor connected in series between a high voltage node and the first connection node, a second connection node which is a node shared by the first and second stabilization transistors connected in series, and a third stabilization transistor and a fourth stabilization transistor connected in series between a second connection node to which a second high voltage is supplied.

[0282] The first stabilization transistor is electrically connected between the first high-voltage node and the second connection node, and its gate node is electrically connected to the M node; the second stabilization transistor is electrically connected between the second connection node and the first connection node, and its gate node is electrically connected to the M node; and the gate node of the third stabilization transistor and the gate node of the fourth stabilization transistor can be electrically connected to the second high-voltage node.

[0283] The above sensing driving period overlaps with the blank period, and the plurality of stage circuits may include a first stage circuit that does not output the scan signal during the sensing driving period and a second stage circuit that outputs the scan signal during the sensing driving period.

[0284] During the above sensing driving period, the voltage of the second connection node included in the first stage circuit may be greater than the gate voltage of the first stabilization transistor included in the first stage circuit.

[0285] During the above sensing driving period, the first stabilization transistor included in the first stage circuit may be in a turned-off state.

[0286] During the above sensing driving period, the voltage of the M node included in the first stage circuit may be constant.

[0287] During the above sensing driving period, the first stabilization transistor and the second stabilization transistor included in the second stage circuit may be in a turned-on state.

[0288] During the above sensing driving period, the first connection node included in the second stage circuit can be electrically connected to the first high voltage node.

[0289] The threshold voltage of the first stabilized transistor may have a voltage magnitude smaller than the threshold voltage of the first stabilized transistor stored in memory.

[0290] The gate driving circuit may be placed in a non-display area of ​​the display panel or in the lower part of the display panel.

[0291] According to embodiments of the present disclosure, the gate driving circuit comprises a plurality of stage circuits electrically connected to a carry signal output line to which a carry signal is output and a plurality of scan signal output lines to which a scan signal is output, and a display panel having a plurality of scan lines to which the scan signal is supplied, wherein each of the plurality of stage circuits has its operation controlled by the electrical state of each of the Q node and QB node, and includes a buffer group that outputs a scan signal to the plurality of scan signal output lines and outputs the carry signal to the carry signal output lines, a logic unit that controls the buffer group during a display driving period for image driving, and a sensing unit that controls the buffer group during a sensing driving period for sensing a characteristic value of a subpixel, wherein the sensing unit includes a Q node charging transistor electrically connected between a first high voltage node to which a first high voltage is supplied and the Q node, a first transistor and a second transistor connected in series between an M node, which is the gate node of the Q node charging transistor, and a node to which a front-end carry signal is input, and a first connection node, which is a node shared by the first transistor and the second transistor connected in series according to the voltage of the M node, and the first A display device may be provided that includes a stabilization circuit for controlling the connection of high-voltage nodes, wherein the stabilization circuit comprises a first stabilization transistor and a second stabilization transistor connected in series between the first high-voltage node and the first connection node, and a third stabilization transistor and a fourth stabilization transistor connected in series between the second connection node, which is a node shared by the first and second stabilization transistors connected in series, and the second high-voltage node to which the second high voltage is supplied.

[0292] The first stabilization transistor is electrically connected between the first high-voltage node and the second connection node, and its gate node is electrically connected to the M node; the second stabilization transistor is electrically connected between the second connection node and the first connection node, and its gate node is electrically connected to the M node; and the gate node of the third stabilization transistor and the gate node of the fourth stabilization transistor can be electrically connected to the second high-voltage node.

[0293] The above sensing driving period overlaps with the blank period, and the plurality of stage circuits may include a first stage circuit that does not output the scan signal during the sensing driving period and a second stage circuit that outputs the scan signal during the sensing driving period.

[0294] During the above sensing driving period, the voltage of the second shared node included in the first stage circuit may be greater than the gate voltage of the first stabilization transistor included in the first stage circuit.

[0295] During the above sensing driving period, the first stabilization transistor included in the first stage circuit may be in a turned-off state.

[0296] The threshold voltage of the first stabilized transistor may have a voltage magnitude smaller than the threshold voltage of the first stabilized transistor stored in memory.

[0297] The gate driving circuit may be placed in a non-display area of ​​the display panel or in the lower part of the display panel.

[0298] The foregoing description is merely an illustrative explanation of the technical concept of the present disclosure, and those skilled in the art to which the present disclosure pertains may make various modifications and variations within the scope of the essential characteristics of the present disclosure. Furthermore, the embodiments disclosed in the present disclosure are intended to explain, not limit, the technical concept of the present disclosure, and thus the scope of the technical concept of the present disclosure is not limited by these embodiments. Explanation of the symbols

[0299] 100: Display device 110: Display panel 120: Data driving circuit 130: Gate driver circuit 140: Controller

Claims

Claim 1 It includes a plurality of stage circuits electrically connected to a carry signal output line for outputting a carry signal and a plurality of scan signal output lines for outputting a scan signal, wherein each of the plurality of stage circuits is controlled by the electrical state of each of the Q node and QB node, and outputs a scan signal to the plurality of scan signal output lines and outputs the carry signal to the carry signal output lines; a buffer group that controls the buffer group during a display driving period for image driving; and a sensing unit that controls the buffer group during a sensing driving period for sensing a characteristic value of a subpixel, wherein the sensing unit includes a Q node charging transistor electrically connected between a first high voltage node to which a first high voltage is supplied and the Q node; and a first transistor and a second transistor connected in series between an M node, which is the gate node of the Q node charging transistor, and a node to which a front-end carry signal is input. A gate driving circuit comprising, depending on the voltage of the M node, a first connection node shared by the first and second transistors connected in series and the first high voltage node, wherein the stabilization circuit comprises: a first stabilization transistor and a second stabilization transistor connected in series between the first high voltage node and the first connection node; and a third stabilization transistor and a fourth stabilization transistor connected in series between the second connection node shared by the first and second stabilization transistors connected in series and the second high voltage node to which the second high voltage is supplied, wherein the gate nodes of the first and second stabilization transistors are each electrically connected to the M node, which is the gate node of the Q node charging transistor. Claim 2 A gate driving circuit according to claim 1, wherein the first stabilization transistor is electrically connected between the first high-voltage node and the second connection node, and the gate node is electrically connected to the M node, the second stabilization transistor is electrically connected between the second connection node and the first connection node, and the gate node is electrically connected to the M node, and the gate node of the third stabilization transistor and the gate node of the fourth stabilization transistor are electrically connected to the second high-voltage node. Claim 3 In paragraph 2, the sensing driving period overlaps with the blank period, and the plurality of stage circuits is a gate driving circuit comprising a first stage circuit that does not output the scan signal during the sensing driving period and a second stage circuit that outputs the scan signal during the sensing driving period. Claim 4 In paragraph 3, during the sensing driving period, the voltage of the second connection node included in the first stage circuit is greater than the gate voltage of the first stabilization transistor included in the first stage circuit. Claim 5 In paragraph 4, during the sensing driving period, the first stabilization transistor included in the first stage circuit is a gate driving circuit in a turn-off state. Claim 6 In claim 5, a gate driving circuit in which the voltage of the M node included in the first stage circuit is maintained constant during the sensing driving period. Claim 7 In paragraph 3, during the sensing driving period, the first stabilization transistor and the second stabilization transistor included in the second stage circuit are a gate driving circuit in a turn-on state. Claim 8 In claim 7, during the sensing driving period, the first connection node included in the second stage circuit is a gate driving circuit electrically connected to the first high voltage node. Claim 9 In paragraph 3, the threshold voltage of the first stabilized transistor is a gate driving circuit with a voltage magnitude smaller than the threshold voltage of the first stabilized transistor stored in memory. Claim 10 A gate driving circuit according to claim 1, which is placed in a non-display area of ​​a display panel or placed at the bottom of the display panel. Claim 11 A gate driving circuit comprising a plurality of stage circuits electrically connected to a carry signal output line for outputting a carry signal and a plurality of scan signal output lines for outputting a scan signal; and a display panel having a plurality of scan lines to which the scan signal is supplied, wherein each of the plurality of stage circuits has its operation controlled by the electrical state of each of the Q node and QB node, and outputs a scan signal to the plurality of scan signal output lines and outputs the carry signal to the carry signal output lines; a logic unit for controlling the buffer group during a display driving period for image driving; and a sensing unit for controlling the buffer group during a sensing driving period for sensing a characteristic value of a subpixel, wherein the sensing unit comprises: a Q node charging transistor electrically connected between a first high voltage node to which a first high voltage is supplied and the Q node; and a first transistor and a second transistor connected in series between an M node, which is the gate node of the Q node charging transistor, and a node to which a front-end carry signal is input. A display device comprising a stabilization circuit that controls the connection between a first connection node, which is a node shared by a first transistor and a second transistor connected in series, and a first high voltage node according to the voltage of the M node, wherein the stabilization circuit comprises: a first stabilization transistor and a second stabilization transistor connected in series between the first high voltage node and the first connection node; and a third stabilization transistor and a fourth stabilization transistor connected in series between a second connection node, which is a node shared by the first stabilization transistor and the second stabilization transistor connected in series, and a second high voltage node to which a second high voltage is supplied, wherein the gate nodes of each of the first stabilization transistor and the second stabilization transistor are electrically connected to the M node, which is the gate node of the Q node charging transistor. Claim 12 A display device according to claim 11, wherein the first stabilization transistor is electrically connected between the first high-voltage node and the second connection node, and the gate node is electrically connected to the M node, the second stabilization transistor is electrically connected between the second connection node and the first connection node, and the gate node is electrically connected to the M node, and the gate node of the third stabilization transistor and the gate node of the fourth stabilization transistor are electrically connected to the second high-voltage node. Claim 13 A display device according to claim 12, wherein the sensing driving period overlaps with the blank period, and the plurality of stage circuits include a first stage circuit that does not output the scan signal during the sensing driving period and a second stage circuit that outputs the scan signal during the sensing driving period. Claim 14 In paragraph 13, the voltage of the second shared node included in the first stage circuit during the sensing driving period is greater than the gate voltage of the first stabilization transistor included in the first stage circuit. Claim 15 In claim 14, the first stabilization transistor included in the first stage circuit is in a turn-off state during the sensing driving period of the display device. Claim 16 In paragraph 13, the threshold voltage of the first stabilized transistor is a display device in which the voltage magnitude is smaller than the threshold voltage of the first stabilized transistor stored in memory. Claim 17 In claim 11, the gate driving circuit is a display device that is placed in a non-display area of ​​a display panel or is placed at the bottom of the display panel.

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