Semiconductor package test apparatus, and semiconductor package test method using the same
The semiconductor package test device facilitates easy testing of core chips and external connection bumps in stacked semiconductor packages by using a controlled test socket and probe system, ensuring effective quality assessment.
KR102991087B1Active Publication Date: 2026-07-21SAMSUNG ELECTRONICS CO LTD
Patent Information
- Application Number
- KR1020220020400
- Authority / Receiving Office
- KR · KR
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2022-02-16
- Publication Date
- 2026-07-21
- Estimated Expiration
- 2042-02-16
AI Technical Summary
Technical Problem
Existing semiconductor package test devices struggle to easily test both the pass/fail status of external connection bumps and core chips in stacked semiconductor packages.
Method used
A semiconductor package test device and method utilizing a test socket with a conductive sheet and test probe, controlled by a test control unit, to separately contact and non-contact the external connection bumps and test pads, allowing for independent testing of core chips and external connection bumps.
Benefits of technology
Enables efficient testing of both the quality of core chips and external connection bumps in stacked semiconductor packages, ensuring reliable functionality and connectivity.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure 112022017592518-PAT00006_ABST
Abstract
The semiconductor package test device of the present invention includes a test socket capable of mounting a semiconductor package; and a test control unit for controlling the test socket. The test socket includes a conductive sheet and a test probe, and the semiconductor package includes a stacked semiconductor chip having a buffer chip and a plurality of core chips located on the buffer chip. The buffer chip includes an internal wiring layer, an internal via layer connecting the internal wiring layers, a plurality of external connection bumps electrically connected to the internal wiring layer and the internal via layer, and a test pad located apart from the external connection bumps. The test control unit controls the contact and miscontact between the conductive sheet and the external connection bumps, and the test control unit controls the contact and miscontact between the test probe and the test pad.
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Citation Information
Patent Citations
Test socket having conductive wire
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Stacked semiconductor package
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Device and method for testing semiconductor device and test handler
KR1020200047813A
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KR1020210051535A