Neuromorphic circuit unit

Abstract

A neuromorphic circuit unit according to one embodiment of the present invention includes an input terminal, a volatile memory element, a non-volatile memory element, and an output terminal. The input terminal provides an input signal. The volatile memory element is electrically connected to the input terminal. The non-volatile memory element is connected in series with the volatile memory element. The output terminal is electrically connected to the non-volatile memory element. The output terminal provides an output signal to the outside. The volatile memory element and the non-volatile memory element are disposed between the input terminal and the output terminal. The frequency of the output signal changes according to the voltage of the input signal.

Description

Technology Field

[0001] The present invention relates to a circuit unit that generates an output signal with a spike-shaped vibrating form by mimicking a neuron. Background Technology

[0002] Neurons exchange signals that vibrate in a spike-like shape. Recently, the development of circuits to generate the aforementioned neuronal signals has been underway in the fields of artificial intelligence and neuromorphic computing. However, there is a problem in that using conventionally proposed technologies requires excessively complex circuits to generate the aforementioned signals. Prior art literature

[65535] M Shahsavari, P Falez, P Boulet "Combining a volatile and nonvolatile memristor in artificial synapse to improve learning in spiking neural networks", IEEE / ACM, 2016, pp. 67-72 The problem to be solved

[0003] The present invention aims to solve the aforementioned problems, and the objective of the present invention is to provide a neuromorphic circuit unit that mimics a neuron with a simpler structure than the prior art by utilizing one volatile memory element and one non-volatile memory element. means of solving the problem

[0004] A neuromorphic circuit unit according to one embodiment of the present invention may include an input terminal, a volatile memory element, a non-volatile memory element, and an output terminal. The input terminal may provide an input signal. The volatile memory element may be electrically connected to the input terminal. The non-volatile memory element may be connected in series with the volatile memory element. The output terminal may be electrically connected to the non-volatile memory element. The output terminal may provide an output signal to the outside. The volatile memory element and the non-volatile memory element may be disposed between the input terminal and the output terminal. The frequency of the output signal may be changed according to the voltage of the input signal.

[0005] In one embodiment of the present invention, at a first time point, the input signal may have a first voltage value and the output signal may have a first frequency. At a second time point after the first time point, the input signal may be changed to have a second voltage value greater than the first voltage value, and the output signal may be changed to have a second frequency greater than the first frequency. Each of the first voltage value and the second voltage value may be a positive number.

[0006] In one embodiment of the present invention, at a third time point after a second time point, the input signal may be changed to have a first voltage value, and the output signal may be changed to have a third frequency that is greater than the first frequency and less than the second frequency.

[0007] In one embodiment of the present invention, at a fourth time point, the input signal may have a fourth voltage value and the output signal may have a fourth frequency. At a fifth time point, which is after the fourth time point, the input signal may be modified to have a fifth voltage value smaller than the fourth voltage value, and the output signal may be modified to have a fifth frequency smaller than the fourth frequency. Each of the fourth voltage value and the fifth voltage value may be negative. The absolute value of the fourth voltage value may be smaller than the absolute value of the fifth voltage value.

[0008] In one embodiment of the present invention, at a sixth time point after a fifth time point, the input signal may be changed to have a sixth voltage value equal to a fourth voltage value, and the output signal may be changed to have a sixth frequency smaller than a fourth frequency and larger than a fifth frequency.

[0009] In one embodiment of the present invention, the first voltage value and the third voltage value may each be +1.6V, the second voltage value may be +1.9V, the fourth voltage value and the sixth voltage value may each be -1.9V, and the fifth voltage value may be -2.5V.

[0010] In one embodiment of the present invention, the volatile memory device may be a Mott Transition Device.

[0011] In one embodiment of the present invention, the volatile memory device may include titanium nitride (TiN) and niobium oxide (NbOx).

[0012] In one embodiment of the present invention, the non-volatile memory device may be a VCM memristor (Valence Change Mechanism Memristor).

[0013] In one embodiment of the present invention, the non-volatile memory device may include titanium nitride (TiN), hafnium oxide (HfO2), niobium pentoxide (Nb2O5), and platinum (Pt). Effects of the invention

[0014] According to one embodiment of the present invention, a neuromorphic circuit unit simulating a neuron with a simpler structure than the prior art can be provided by using one volatile memory element and one non-volatile memory element. Brief explanation of the drawing

[0015] FIG. 1 illustrates an exemplary view of a neuromorphic circuit unit according to one embodiment of the present invention. FIGS. 2a to 2d illustrate graphs of an input signal, a signal applied to a volatile memory element, a signal applied to a non-volatile memory element, and an output signal over time. Figure 3a may be a current-voltage graph of a volatile memory device. Figure 3b may be a current-voltage graph of a non-volatile memory device. Figure 3c may be a graph of the output signal for the input signal. Figure 4a illustrates an exemplary graph of the input signal and output signal with respect to time when the voltage value of the input signal is positive. FIG. 4b illustrates, exemplarily, a graph of the input signal, output signal, and frequency of the output signal over time when the voltage value of the input signal is positive. Figure 5a illustrates an exemplary graph of the input signal and output signal over time when the voltage value of the input signal is negative. FIG. 5b illustrates, exemplarily, a graph of the input signal, output signal, and frequency of the output signal over time when the voltage value of the input signal is negative. Specific details for implementing the invention

[0016] Preferred embodiments of the present invention will be described in more detail below with reference to the attached drawings. In the drawings, the proportions and dimensions of the components may be exaggerated for the effective explanation of the technical content.

[0017] Terms such as "include" are intended to indicate the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not precluding the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0018] In addition, when a component is described as "above," it refers to the area above or below the component, and does not necessarily mean that it is located on the upper side relative to the direction of gravity.

[0019] In addition, where it is stated that a component is "connected" or "combined" to another component, this may include not only cases where the component is directly connected or combined to the other component, but also cases where the component is indirectly connected or combined through another component.

[0020] In addition, terms such as "first," "second," etc., may be used to describe a component; however, these terms are intended merely to distinguish the component from other components and are not intended to limit the essence, order, or sequence of the component.

[0021] Preferred embodiments of the present invention will be described in more detail below with reference to the attached drawings. In the drawings, the proportions and dimensions of the components may be exaggerated for the effective explanation of the technical content.

[0022] FIG. 1 illustrates an exemplary view of a neuromorphic circuit unit (NCU) according to one embodiment of the present invention.

[0023] FIGS. 2a to 2d are input signals ( ), a signal applied to a volatile memory device (VMM), a signal applied to a nonvolatile memory device (NMM), and an output signal ( This is a graph plotting ) against time.

[0024] Referring to FIG. 1, the neuromorphic circuit unit (NCU) may include an input terminal (TM1), a volatile memory element (VMM), a non-volatile memory element (NMM), and an output terminal (TMO).

[0025] The input terminal (TM1) is an input signal ( Can provide ). Input signal ( Output signal ( depending on the voltage of ) The frequency of ) can be changed. For example, the input terminal (TM1) can be electrically connected to an external power source. Part of the input signal ( ) is applied to the volatile memory device (VMM) and the rest ( ) can be applied to a non-volatile memory device (NMM).

[0026] A volatile memory device (VMM) can be electrically connected to an input terminal (TM1). The volatile memory device (VMM) can be placed between the input terminal (TM1) and the output terminal (TMO).

[0027] In one embodiment of the present invention, the volatile memory device (VMM) may include titanium nitride (TiN) and niobium oxide (NbOx). For example, the volatile memory device (VMM) may be a Mott Transition Device.

[0028] A non-volatile memory device (NMM) can be connected in series with a volatile memory device (VMM). The non-volatile memory device (NMM) can be placed between an input terminal (TM1) and an output terminal (TMO). In one embodiment of the present invention, the non-volatile memory device (NMM) may include titanium nitride (TiN), hafnium oxide (HfO2), niobium pentoxide (Nb2O5), and platinum (Pt). For example, the non-volatile memory device (NMM) may be a VCM memristor (Valence Change Mechanism Memristor).

[0029] The output terminal (TMO) can be electrically connected to a non-volatile memory device (NMM). The output terminal (TMO) can externally output a signal ( It can provide ).

[0030] The input terminal (TMI) is the input signal of FIG. 2a ( It can provide ). Input signal applied to a volatile memory device (VMM) ( The waveform of ) and the input signal applied to the non-volatile memory device (NMM) Each waveform of ) may have a spike-shaped vibrating form as illustrated in FIGS. 2b and 2c. Accordingly, the output signal provided by the output terminal (TMO) ( ) may have a shape that vibrates in the shape of a spike as in FIG. 2d. That is, since the neuromorphic circuit unit (NCU) of the present invention has the intrinsic plasticity and adaptive characteristics of a neuron, it can be utilized in artificial neural networks and neuromorphic computing systems.

[0031] Figure 3a may be a current-voltage graph of a volatile memory device (VMM).

[0032] Figure 3b may be a current-voltage graph of a non-volatile memory device (NMM).

[0033] Fig. 3c is an input signal ( Output signal for ) It can be a graph of ).

[0034] Referring to FIG. 3a, the resistance of the volatile memory device (VMM) can be changed according to the voltage applied to the volatile memory device (VMM). Referring to FIG. 3b, the resistance of the non-volatile memory device (NMM) can be changed according to the voltage applied to the non-volatile memory device (NMM). Accordingly, the same input signal ( Output signal for ) The current values ​​of ) can be different from each other.

[0035] Fig. 4a is an input signal ( When the voltage value of ) is positive, the input signal with respect to time ( ) and output signal( This is an exemplary graph of ).

[0036] Figure 4b shows the input signal ( When the voltage value of ) is positive, the input signal with respect to time ( ), output signal( This is an exemplary graph showing the frequency (Freq) of the output signal, and the ), and the output signal.

[0037] Hereinafter, with reference to FIGS. 4a and FIGS. 4b, an input signal ( Output signal according to the voltage value of ) Explains the change in frequency of ).

[0038] At the first time point (T1), the input signal ( ) has a first voltage value (V1) and outputs a signal ( ) can have a first frequency (F1). The first voltage value (V1) can be positive.

[0039] At the second time point (T2) after the first time point (T1), an input signal ( ) is modified to have a second voltage value (V2) greater than the first voltage value (V1) and the output signal ( ) can be changed to have a second frequency (F2) greater than the first frequency (F1). Each of the second voltage values ​​(V2) can be positive.

[0040] At the third time point (T3) after the second time point (T2), the input signal ( ) is changed to have a third voltage value (V3) equal to the first voltage value (V1) and the output signal ( ) can be modified to have a third frequency (F3) that is greater than the first frequency (F1) and smaller than the second frequency (F2).

[0041] For example, the first frequency (F1) may be 2.23 MHz and the third frequency (F3) may be 3.12 MHz, the first voltage value (V1) and the third voltage value (V3) may each be +1.6 V and the second voltage value (V2) may be +1.9 V. However, this is merely an example and the first frequency (F1), the second frequency (F2), the first voltage value (V1), and the second voltage value (V2) of the present invention are not limited thereto.

[0042] Fig. 5a shows the input signal ( When the voltage value of ) is negative, the input signal (with respect to time) ) and output signal( This is an exemplary graph of ).

[0043] Figure 5b shows the input signal ( When the voltage value of ) is negative, the input signal (with respect to time) ), output signal( This is an exemplary graph showing the frequency (Freq) of the output signal, and the ), and the output signal.

[0044] Hereinafter, with reference to FIGS. 5a and FIGS. 5b, an input signal ( Output signal according to the voltage value of ) Explains the change in frequency of ).

[0045] At the fourth time point (T4), the input signal ( ) has the fourth voltage value (V4) and outputs the signal ( ) can have a fourth frequency (F4). The fourth voltage value (V4) can be negative.

[0046] At the fifth time point (T5), which is after the fourth time point (T4), the input signal ( ) is modified to have a fifth voltage value (V5) smaller than the fourth voltage value (V4) and the output signal ( ) can be changed to have a fifth frequency (F5) smaller than the fourth frequency (F4). The fifth voltage value (V5) can be negative.

[0047] At the 6th time point (T6), which is after the 5th time point (T5), the input signal ( ) is changed to have a sixth voltage value (V6) equal to the fourth voltage value (V4) and the output signal ( ) can be changed to have a 6th frequency (F6) that is smaller than the 4th frequency (F4) and larger than the 5th frequency (F5).

[0048] For example, the fourth frequency (F4) may be 3.01 MHz and the sixth frequency (F6) may be 2.24 MHz, and the fourth voltage value (V4) and the sixth voltage value (V6) may each be -1.9 V and the fifth voltage value (V5) may be -2.5 V. However, this is merely an example and the fourth frequency (F4), the fifth frequency (F5), the sixth frequency (F6), the fourth voltage value (V4), the fifth voltage value (V5), and the sixth voltage value (V6) of the present invention are not limited thereto.

[0049] Although the invention has been described with reference to exemplary embodiments, those skilled in the art will understand that various modifications and changes can be made to the invention without departing from the spirit and scope of the invention as set forth in the following claims. Furthermore, the exemplary embodiments disclosed in the invention are not intended to limit the technical spirit of the invention, and all technical spirits within the scope of the following claims and their equivalents should be interpreted as being included within the scope of the rights of the invention. Explanation of the symbols

[0050] NCU: Neuromorphic Circuit Unit TMI: Input Terminal TMO: Output terminal VMM: Volatile memory device NMM: Non-volatile memory device

Claims

Claim 1 A neuromorphic circuit unit comprising: an input terminal providing an input signal; a volatile memory element electrically connected to the input terminal; a non-volatile memory element connected in series to the volatile memory element; and an output terminal electrically connected to the non-volatile memory element and providing an output signal to the outside, wherein the volatile memory element and the non-volatile memory element are disposed between the input terminal and the output terminal, the frequency of the output signal is changed according to the voltage of the input signal, and the volatile memory element is a Mott Transition Device. Claim 2 A neuromorphic circuit unit according to claim 1, wherein at a first time point, the input signal has a first voltage value and the output signal has a first frequency, and at a second time point after the first time point, the input signal is changed to have a second voltage value greater than the first voltage value and the output signal is changed to have a second frequency greater than the first frequency, and each of the first voltage value and the second voltage value is a positive number. Claim 3 A neuromorphic circuit unit according to claim 2, wherein at a third time point after the second time point, the input signal is changed to have a third voltage value equal to the first voltage value, and the output signal is changed to have a third frequency greater than the first frequency and smaller than the second frequency. Claim 4 A neuromorphic circuit unit according to claim 3, wherein at a fourth time point, the input signal has a fourth voltage value and the output signal has a fourth frequency, and at a fifth time point after the fourth time point, the input signal is changed to have a fifth voltage value smaller than the fourth voltage value and the output signal is changed to have a fifth frequency smaller than the fourth frequency, and each of the fourth voltage value and the fifth voltage value is negative. Claim 5 A neuromorphic circuit unit according to claim 4, wherein at the 6th time point after the 5th time point, the input signal is changed to have a 6th voltage value equal to the 4th voltage value, and the output signal is changed to have a 6th frequency smaller than the 4th frequency and larger than the 5th frequency. Claim 6 A neuromorphic circuit unit according to claim 5, wherein the first voltage value and the third voltage value are each +1.6V, the second voltage value is +1.9V, the fourth voltage value and the sixth voltage value are each -1.9V, and the fifth voltage value is -2.5V. Claim 7 delete Claim 8 In claim 1, the volatile memory element is a neuromorphic circuit unit comprising titanium nitride (TiN) and niobium oxide (NbOx). Claim 9 In claim 1, the non-volatile memory element is a neuromorphic circuit unit that is a VCM memristor (Valence Change Mechanism Memristor). Claim 10 In claim 1, the non-volatile memory element is a neuromorphic circuit unit comprising titanium nitride (TiN), hafnium oxide (HfO2), niobium pentoxide (Nb2O5), and platinum (Pt).

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