Antifuse Array Structure and Memory

Abstract

The present application provides an antifuse array structure and a memory, wherein the antifuse array structure comprises a plurality of antifuse integrated structures arranged in an antifuse matrix in the extension direction of a bit line and the extension direction of a word line; each antifuse integrated structure is installed within the same active area, and the extension direction of the active area is the same as the extension direction of the bit line; the antifuse integrated structure comprises a first antifuse memory MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse memory MOS transistor; the first switch transistor and the second switch transistor are each controlled through two adjacent word lines, and the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are each controlled through two adjacent programming wires, and the programming wires are also intended to control adjacent antifuse integrated structures.

Description

Technology Field

[0001] Cross-reference of related applications

[0002] This application is based on a Chinese patent application with application number 202111095281.X, filing date September 17, 2021, and application title "Antifuse array structure and memory", and claims priority to said Chinese patent application, all contents of said Chinese patent application are incorporated into this application by reference.

[0003] This application relates to an antifuse array structure and memory, but is not limited thereto. Background Technology

[0004] Semiconductor devices are indispensable in many modern applications. In semiconductor devices, memory devices for storing data play a crucial role. As technology advances, the capacity of memory devices continuously increases; in other words, the density of memory arrays placed on a base increases.

[0005] In the case of antifuse memory, as the density of the memory array increases and the spacing between antifuse memory units decreases, it is difficult to guarantee the electrical isolation effect of electrical elements between antifuse memory units.

[0006] Therefore, in order to ensure the electrical isolation effect of electrical elements between antifuse memory units, the layout method of the antifuse array structure must be urgently improved. The problem to be solved

[0007] The following is a brief description of the subject matter described in detail in this application. This brief description is not intended to limit the scope of protection of the claims.

[0008] The present application provides an antifuse array structure and a memory. means of solving the problem

[0009] In the first aspect of the present application, an antifuse array structure is provided, wherein the antifuse array structure comprises a plurality of antifuse integrated structures arranged in an antifuse matrix in the extension direction of a bit line and the extension direction of a word line, wherein the extension direction of the bit line and the extension direction of the word line are perpendicular to each other; each antifuse integrated structure is installed within the same active area, wherein the extension direction of the active area is the same as the extension direction of the bit line; and each antifuse integrated structure comprises a first antifuse memory MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse memory MOS transistor installed sequentially along the extension direction of the bit line; wherein the first switch transistor and the second switch transistor are each controlled through two adjacent word lines, and the common end of the first switch transistor and the second switch transistor is connected to the bit line, and the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are each controlled through two adjacent programming wires, and above the extension direction of the bit line, the programming wires are also intended to control adjacent antifuse integrated structures.

[0010] When combining the first aspect, in a partial implementation of the first aspect, the active area includes an active area body, the longitudinal direction of the active area body is the extension direction of the active area, and the width of each part of the active area body is the same along the extension direction of the active area.

[0011] When combining the first aspect, in a partial implementation of the first aspect, the active area further includes a protrusion, the protrusion is installed on at least one side of the active area body, and in the extension direction of the active area, the length of the protrusion is smaller than the length of the active area body; and in the extension direction of the word line, the width of the middle part of the active area is larger than the width of both ends of the active area.

[0012] When the first side is combined, in a partial implementation method of the first side, a protrusion is installed on one side of the active area body, and on the extension direction of the bit line, two adjacent active area protrusions are installed facing each other.

[0013] When combining the first aspect, in a partial implementation of the first aspect, the gate of the second antifuse memory MOS transistor of each antifuse integrated structure is connected to the same programming wire as the gate of the first antifuse memory MOS transistor of the adjacent antifuse integrated structure in the direction of the extension of the bit line.

[0014] When combining the first aspect, in a partial implementation of the first aspect, the gate of the first antifuse memory MOS transistor is connected to the first programming wire; the gate of the first switch transistor is connected to the first word line, the source is connected to the first antifuse memory MOS transistor, and the drain is connected to the bit line; the gate of the second switch transistor is connected to the second word line, the source is connected to the second antifuse memory MOS transistor, and the drain is connected to the bit line; and the gate of the second antifuse memory MOS transistor is connected to the second programming wire.

[0015] When combining the first aspect, in a partial implementation of the first aspect, the active region includes a first doping region, a second doping region, a third doping region, a fourth doping region, and a fifth doping region sequentially distributed along the extension direction of the active region; the first doping region is the idle end of the first antifuse MOS transistor, the second doping region is the common end of the first antifuse memory MOS transistor and the first switch transistor, the third doping region is the common end of the first switch transistor and the second switch transistor, the fourth doping region is the common end of the second switch transistor and the second antifuse memory MOS transistor, and the fifth doping region is the idle end of the second antifuse MOS transistor; and the bit line is electrically connected to the third doping region.

[0016] When combining the first aspect, in a partial implementation of the first aspect, the antifuse array structure further comprises: an insulating layer covering an active region—whereby a bit line is installed on the insulating layer, and the insulating layer is also provided with conductive holes, which expose the top surface of a third doping region—; and a conductive layer filling the conductive holes—one end of which is in contact with the third doping region and the other end of which is in contact with the bit line, so that the bit line is electrically connected to the third doping region. By connecting the bit line and the conductive layer through an extension layer of the bit line, the stability of the electrical contact between the bit line and the conductive layer is ensured, and the formed antifuse matrix is ​​prevented from having a conductive defect.

[0017] When combining the first aspect, in a partial implementation of the first aspect, a conductive through-hole is installed on one side of a connected bit line, and on the extension direction of the bit line, conductive through-holes of two adjacent antifuse integrated structures are installed on both sides of the connected bit line, and the connected bit line comes into contact with the conductive layer through the extension layer of the bit line.

[0018] When combining the first aspect, in a partial implementation of the first aspect, the gate of the first antifuse memory MOS transistor is installed on the top surface of the active region between the first doping region and the second doping region, the gate of the first switch transistor is installed on the top surface of the active region between the second doping region and the third doping region, the gate of the second switch transistor is installed on the top surface of the active region between the third doping region and the fourth doping region, and the gate of the second antifuse memory MOS transistor is installed on the top surface of the active region between the fourth doping region and the fifth doping region.

[0019] When combining the first aspect, in a partial implementation of the first aspect, the gate of the first antifuse memory MOS transistor is installed embeddedly in the active region between the first doping region and the second doping region, the gate of the first switch transistor is installed embeddedly in the active region between the second doping region and the third doping region, the gate of the second switch transistor is installed embeddedly in the active region between the third doping region and the fourth doping region, and the gate of the second antifuse memory MOS transistor is installed embeddedly in the active region between the fourth doping region and the fifth doping region.

[0020] When combining the first aspect, in a partial implementation method of the first aspect, the antifuse matrix includes a plurality of columns of antifuse integrated structures arranged along the extension direction of the word lines, the bit line connected to the antifuse integrated structure of the first column is a first virtual bit line, and the bit line connected to the antifuse integrated structure of the last column is a second virtual bit line.

[0021] When combining the first aspect, in a partial implementation of the first aspect, the antifuse matrix includes multiple rows of antifuse integrated structures arranged along the extension direction of the bit line, the gate of a first antifuse MOS transistor in the first row of antifuse integrated structures is connected to a first virtual programming wire, and the gate of a second antifuse MOS transistor in the last row of antifuse integrated structures is connected to a second virtual programming wire.

[0022] When combining the first aspect, in a partial implementation of the first aspect, the gate of the first switch transistor in the first row of the antifuse integrated structure is connected to the first virtual word line, and the gate of the second switch transistor in the last row of the antifuse integrated structure is connected to the second virtual word line; the first virtual programming wire and the second virtual programming wire are located at the outermost part of the antifuse matrix, and the first virtual word line and the second virtual word line are located at the second outer part of the antifuse matrix.

[0023] In a second aspect of the present application, a memory is provided, said memory includes a memory array, and the memory array adopts an antifuse array structure of any one of the first aspects. Effects of the invention

[0024] In the antifuse array structure and memory provided in the embodiment of the present application, the domain length of the antifuse memory array is reduced in the direction of the bit line extension, thereby increasing the spacing between the switch unit and the antifuse memory unit located in the same active area on the basis of laying out a memory array of the same capacity and the original layout area, thereby ensuring the electrical isolation effect of the electrical elements in the memory array formed in the antifuse integrated structure.

[0025] By reading and understanding the drawings and detailed descriptions, you can understand other aspects. Brief explanation of the drawing

[0026] The drawings incorporated into and constituting part of this specification are intended to illustrate embodiments of the present application and to interpret the principles of the embodiments of the present application together with the description. In these drawings, similar drawing notations are intended to indicate similar elements. The drawings in the description below are only some embodiments of the present application, not all. A person skilled in the art can obtain other drawings based on these drawings without creative work. FIG. 1 is a circuit example of an antifuse integrated structure provided in one embodiment of the present application. FIG. 2 is a circuit example diagram of an antifuse matrix provided in one embodiment of the present application. FIG. 3 is a diagram illustrating the principle that one antifuse memory unit of an adjacent antifuse integrated structure provided in one embodiment of the present application is connected to the same programming wire. FIGS. 4 and FIGS. 5 are planar examples of the domain structure of an antifuse integrated structure provided in one embodiment of the present application. FIG. 6 is an example cross-sectional view of the domain structure of an antifuse integrated structure provided in one embodiment of the present application. FIG. 7 is a cross-sectional example of a domain structure of another antifuse integrated structure provided in one embodiment of the present application. FIGS. 8 and FIGS. 9 are example diagrams of the domain structure of an antifuse matrix provided in one embodiment of the present application. FIGS. 10 and FIGS. 11 are example diagrams of the domain structure of a bit line in an antifuse matrix provided in one embodiment of the present application. FIG. 12 is an example diagram of a virtual structure of a memory provided in another embodiment of the present application. FIG. 13 is an example of the time sequence of the programming and reading steps of a memory provided in another embodiment of the present application. Specific details for implementing the invention

[0027] The technical methods in the embodiments of this application are described below in conjunction with the attached drawings, clearly and completely. It is evident that the described embodiments are only some of the embodiments of this application and not all of them. All other embodiments obtained by a person skilled in the art without creative labor based on the embodiments of this application should fall within the scope of protection of this application. It should be noted that, unless there is a conflict, the embodiments and features of this application may be combined arbitrarily.

[0028] In the case of antifuse memory, as the density of the memory array increases and the spacing between antifuse memory units decreases, it is difficult to guarantee the electrical isolation effect of electrical elements between antifuse memory units.

[0029] In one embodiment of the present application, an antifuse array structure is provided and a new antifuse array layout method is provided so that a memory array of the same capacity occupies only a smaller layout area, thereby increasing the spacing between antifuse memory units based on the original layout area and ensuring the electrical isolation effect of electrical elements between antifuse memory units.

[0030] FIG. 1 is a circuit example diagram of an antifuse integrated structure provided in the present embodiment, FIG. 2 is a circuit example diagram of an antifuse matrix provided in the present embodiment, FIG. 3 is a principle diagram in which one antifuse memory unit of an adjacent antifuse integrated structure provided in the present embodiment is connected to the same programming wire, FIG. 4 and FIG. 5 are planar example diagrams of a domain structure of an antifuse integrated structure provided in the present embodiment, FIG. 6 is a cross-sectional example diagram of a domain structure of an antifuse integrated structure provided in the present embodiment, FIG. 7 is a cross-sectional example diagram of a domain structure of another antifuse integrated structure provided in the present embodiment, FIG. 8 and FIG. 9 are example diagrams of a domain structure of an antifuse matrix provided in the present embodiment, FIG. 10 and FIG. 11 are example diagrams of a domain structure of a bit line in an antifuse matrix provided in the present embodiment, and the antifuse array structure provided in the present embodiment is further described in detail below by combining the drawings, and specifically as follows.

[0031] Referring to FIGS. 1 and FIGS. 2, the antifuse array structure is,

[0032] It includes a plurality of antifuse integrated structures (100) (see FIG. 1) arranged in an antifuse matrix (see FIG. 2) in the bit line (BL) extension direction and the word line (WL) extension direction, and the bit line (BL) extension direction and the word line (WL) extension direction are perpendicular to each other.

[0033] Each antifuse integrated structure (100) includes a first antifuse memory MOS transistor (101), a first switch transistor (111), a second switch transistor (112), and a second antifuse memory MOS transistor (102) installed sequentially along the bit line (BL) extension direction. Here, the first switch transistor (111) and the second switch transistor (112) are each controlled through two adjacent word lines (WL), and the common end of the first switch transistor (111) and the second switch transistor (112) is connected to the bit line (BL), and the first antifuse memory MOS transistor (101) and the second antifuse memory MOS transistor (102) are each controlled through one programming wire PGM, and along the bit line (BL) extension direction, the programming wire PGM is also intended to control adjacent antifuse integrated structures (100).

[0034] Additionally, each antifuse integrated structure (100) is installed within the same active area, and the extension direction of the active area is the same as the extension direction of the bit line (BL).

[0035] Figure 2 is merely an example of a formed antifuse matrix and is intended to show the distribution method of the antifuse matrix in the embodiment of the present application, and is not intended to limit the number of bit lines (BL), word lines (WL), and programming wire PGMs, and in specific use, the number of corresponding bit lines (BL), word lines (WL), and programming wire PGMs can be selected according to the capacity of the memory array required; furthermore, the numbers in "<>" are merely for distinguishing different bit lines (BL), word lines (WL), or programming wire PGMs and are not a limitation to the present embodiment.

[0036] As illustrated in FIG. 1, the antifuse integrated structure (100) includes a first antifuse memory MOS transistor (101), a second antifuse memory MOS transistor (102), a first switch transistor (111), and a second switch transistor (112), i.e., the antifuse integrated structure (100) includes two antifuse memory units and two switch units, wherein the first antifuse memory MOS transistor (101) and the second antifuse memory MOS transistor (102) are controlled via adjacent programming wires PGM, i.e., the two antifuse memory units are controlled via adjacent programming wires, and the first switch transistor (111) and the second switch transistor (112) are switch transistors of the antifuse memory units and are controlled via adjacent word lines (WL); In the antifuse array, the extension direction of the programming wire PGM and the extension direction of the word line (WL) are the same, that is, the extension direction of the programming wire PGM and the extension direction of the bit line (BL) are perpendicular; where, on the extension direction of the bit line (BL), the programming wire PGM is also intended to control two adjacent antifuse integrated structures (100) arranged along the extension direction of the bit line (BL), and the same programming wire PGM is intended to control one antifuse memory unit among two adjacent antifuse integrated structures (100) connected on the same bit line (BL), that is, the same programming wire PGM is intended to control two antifuse memory units located in different antifuse integrated structures (100), thereby reducing the domain length of the antifuse memory array on the extension direction of the bit line (BL); and, on the basis of laying out a memory array of the same capacity as the original layout area, increasing the spacing between the switch unit and the antifuse memory unit located in the same active area, thereby ensuring the electrical isolation effect of the electrical elements of the antifuse memory array.

[0037] As shown in FIG. 1, the gate of the first antifuse memory MOS transistor (101) is the first programming wire PGM <1> It is connected to, and the gate of the first switch transistor (111) is the first word line (WL) <1> It is connected to, and one end of the source or drain is connected to the first antifuse memory MOS transistor (101), and the other end is connected to the bit line (BL), and the gate of the second switch transistor (112) is connected to the second word line (WL) <2> It is connected to, and one end of the source or drain is connected to the second antifuse memory MOS transistor (102), and the other end is connected to the bit line (BL), and the gate of the second antifuse memory MOS transistor (102) is connected to the second programming wire PGM <2> It connects to.

[0038] In some exemplary embodiments, referring to FIG. 3, in the case of any two adjacent antifuse integrated structures (100) on the bit line (BL) extension direction, the gate of the second switch transistor (112) of one of the antifuse integrated structures (100) is a word line (WL) <n-2>Connected to, and the gate of the second antifuse memory MOS transistor (102) is the programming wire PGM <m>It is connected to; and the gate of the first antifuse memory MOS transistor (101) of another antifuse integrated structure (100) is connected to the programming wire PGM <m>It is connected to, and the gate of the first switch transistor (111) is the word line (WL) <n-1>Connected to; in the case of the first switch transistor (111) and the second switch transistor (112) of any two adjacent antifuse integrated structures (100) on the bit line (BL) extension direction, both bit line (BL) <n>It is connected to. That is, on the bit line (BL) extension direction, the gate of the second antifuse memory MOS transistor (102) of each antifuse integrated structure (100) is connected to the same programming wire PGM as the gate of the first antifuse memory MOS transistor (101) of the adjacent antifuse integrated structure (100). <m>It is connected to, where, n, m, are positive integers greater than or equal to 1.

[0039] It should be explained that, in another embodiment, the gate of the first antifuse memory MOS transistor of each antifuse integrated structure may be installed to be connected to the same programming wire as the gate of the second antifuse memory MOS transistor of the adjacent antifuse integrated structure, in the direction of the extension of the bit line.

[0040] Referring to FIGS. 4 and 5, in the case of a first antifuse memory MOS transistor (101), a first switch transistor (111), a second switch transistor (112), and a second antifuse memory MOS transistor (102) installed in the same active region, in one example, the active region (200) includes an active region body, and the length direction of the active region body is the extension direction of the active region (200), and the width of each part of the active region body is the same on the extension direction of the active region (200), thereby ensuring that the spacing between each active element in the antifuse matrix is ​​the same, and additionally ensuring the electrical isolation effect of each active element in the antifuse matrix.

[0041] In some embodiments, with reference to FIG. 4, the active region further comprises a protrusion, the protrusion being installed on at least one side of the active region body, for example, on at least one side in the length direction of the active region. In the extension direction of the active region (200), the length of the protrusion is shorter than the length of the active region body; and in the extension direction of the word line (WL), the width of the middle portion of the active region (200) is greater than the width of both ends of the active region (200). The protrusion and the active region body are for forming the first switch transistor (111) and the second switch transistor (112), and the trench region width of the first switch transistor (111) and the second switch transistor (112) is the sum of the widths of the protrusion and the active region body, and the first antifuse memory MOS transistor (101) and the second antifuse memory MOS transistor (102) are installed in the active region body, and the trench region width of the first antifuse memory MOS transistor (101) and the second antifuse memory MOS transistor (102) is the active region width. By installing a protrusion, the aspect ratio of the active region where the first switch transistor (111) and the second switch transistor (112) are located is increased, and the conductivity of the first switch transistor (111) and the second switch transistor (112) is improved, ensuring that a sufficient melting voltage flows through the first antifuse memory MOS transistor (101) and the second antifuse memory MOS transistor (102), thereby preventing the degradation of the conductivity of the first switch transistor (111) and the second switch transistor (112) and preventing errors in the data reading of the antifuse memory unit, and also increasing the width of the middle part of the active region (200) while making it easier to manufacture the first switch transistor (111) and the second switch transistor (112).

[0042] In one example, the active area consists only of an active area body; in one example, referring to FIG. 4, a protrusion is installed on one side of the active area body, and two adjacent active area protrusions are installed facing each other in the direction of the bit line (BL) extension, that is, in the case of two adjacent rows of active areas (200), the protrusion of one row of active areas (200) is located on one side of the active area body, and the protrusion of the other row of active areas (200) is located on the other side of the active area protrusion; thereby increasing the active area area and simultaneously ensuring that the two adjacent rows of active areas are closely aligned, the area of ​​the antifuse array structure can be reduced.

[0043] In another example, referring to FIG. 5, the protrusions are installed on opposite sides of the active area body, and the protrusions are installed symmetrically based on the active area body.

[0044] In some embodiments, the area of ​​the antifuse array structure can be further reduced by at least partially overlapping the projection of the active area body of two adjacent antifuse integrated structures (100) on a preset plane along the extended direction of the bit line (BL). Here, the preset plane is parallel to the extended direction of the bit line (BL) and perpendicular to the extended direction of the word line.

[0045] In some embodiments, referring to FIGS. 6 and FIGS. 7, the active region (200) is,

[0046] It includes a first doping area (212), a second doping area (222), a third doping area (232), a fourth doping area (242), and a fifth doping area (252) sequentially distributed along the extension direction of the active area (200).

[0047] Here, an isolation region (201) surrounds the active region (200), and the first doping region (212) is the idle end of the first antifuse memory MOS transistor (101); the second doping region (222) is the common end of the first antifuse memory MOS transistor (101) and the first switch transistor (111); the third doping region (232) is the common end of the first switch transistor (111) and the second switch transistor (112); the fourth doping region (242) is the common end of the second switch transistor (112) and the second antifuse memory MOS transistor (102); and the fifth doping region (252) is the idle end of the second antifuse memory MOS transistor (102).

[0048] That is, the source of the first antifuse memory MOS transistor (101) is idle, and the drain is connected to the drain of the first switch transistor (111), and the source of the first switch transistor (111) is connected to the bit line (BL), so that electrical conduction between the first antifuse memory MOS transistor (101) and the bit line (BL) is achieved after conduction through the first switch transistor (111). The source of the second antifuse memory MOS transistor (102) is idle, and the drain is connected to the drain of the second switch transistor (112), and the source of the second switch transistor (112) is connected to the bit line (BL), so that electrical conduction between the second antifuse memory MOS transistor (102) and the bit line (BL) is achieved after conduction through the second switch transistor (112).

[0049] Since the source connection relationship of the first switch transistor (111) and the second switch transistor (112) is the same, the domain area of ​​the antifuse integrated structure (100) is reduced by sharing the source, that is, by sharing the same doping region between the first switch transistor (111) and the second switch transistor (112).

[0050] In the case of an antifuse memory unit, the conduction of the antifuse MOS transistor is controlled via a programming wire PGM to form a memory unit, and a word line (WL) switch control transistor allows the bit line (BL) to easily write storage data. After the corresponding word line (WL) is gated, the antifuse memory unit is electrically connected to the bit line (BL). The antifuse memory unit can determine whether the antifuse memory unit has broken down by the discharge rate of the bit line (BL) charge (by comparing the bit line (BL) voltage with a standard voltage after a preset time), thereby obtaining 1 bit of binary data stored by the antifuse memory unit.

[0051] In one example, referring to FIG. 6, the gate of the first antifuse memory MOS transistor (101) is installed on the top surface of the active region (200) between the first doping region (212) and the second doping region (222), the gate of the first switch transistor (111) is installed on the top surface of the active region (200) between the second doping region (222) and the third doping region (232), the gate of the second switch transistor (112) is installed on the top surface of the active region (200) between the third doping region (232) and the fourth doping region (242), and the gate of the second antifuse memory MOS transistor (102) is installed on the top surface of the active region (200) between the fourth doping region (242) and the fifth doping region (252). That is, the active regions of the first antifuse memory MOS transistor (101), the first switch transistor (111), the second switch transistor (112), and the second antifuse memory MOS transistor (102) are installed through the top gate method.

[0052] In one example, referring to FIG. 7, the gate of the first antifuse memory MOS transistor (101) is installed embedded in the active region (200) between the first doping region (212) and the second doping region (222), the gate of the first switch transistor (111) is installed embedded in the active region (200) between the second doping region (222) and the third doping region (232), the gate of the second switch transistor (112) is installed embedded in the active region (200) between the third doping region (232) and the fourth doping region (242), and the gate of the second antifuse memory MOS transistor (102) is installed embedded in the active region (200) between the fourth doping region (242) and the fifth doping region (252). That is, the active regions of the first antifuse memory MOS transistor (101), the first switch transistor (111), the second switch transistor (112), and the second antifuse memory MOS transistor (102) are installed through a gate purchase method.

[0053] Combining FIG. 6 and FIG. 7, the antifuse integrated structure further includes an insulating layer (203) covering an active region (200), and a bit line (BL) (205) is installed on the insulating layer (203) and is electrically connected to a third doping region (232).

[0054] In some embodiments, the insulating layer (203) is provided with a conductive hole (not shown) and a conductive layer (204), the conductive hole (not shown) exposes the top surface of the third doping region (232); the conductive layer (204) fills the conductive hole (not shown), one end of which is in contact with the third doping region (232) and the other end of which is in contact with the BL (205), so that the bit line is electrically connected to the third doping region (232).

[0055] For a domain layout drawing of an antifuse matrix, refer to FIGS. 1, 8, and 10. The antifuse matrix comprises a plurality of rows of antifuse integrated structures (100) arranged along the word line (WL) extension direction, and a plurality of columns of antifuse integrated structures (100) arranged along the bit line (BL) extension direction. A plurality of antifuse integrated structures (100) in each row are spaced apart along the WL extension direction, and a plurality of antifuse integrated structures (100) in each column are spaced apart along the BL extension direction. Along the extended direction of the bit line (BL), two adjacent antifuse integrated structures (100) are spaced apart and located in two adjacent columns.

[0056] Referring to FIG. 9, FIG. 9 corresponds to the bit line distribution of FIG. 8, and the conductive holes of the antifuse integrated structure (100) (as shown in FIG. 1) of the same column are located on the same straight line, and the bit line (BL) (205) is distributed along the straight line, and the bit line (BL) (205) covers the conductive holes located on the same straight line, so that the process of forming the bit line (BL) (205) can be simplified.

[0057] Referring to FIG. 11, FIG. 11 corresponds to the bit line distribution of FIG. 10, wherein a conductive through-hole is installed on one side of a connected bit line (BL) (205), and on the extension direction of the bit line (BL) (205), a conductive through-hole of an adjacent antifuse integrated structure (100) is installed on both sides of the connected bit line (BL) (205), and the bit line (BL) comes into contact with a conductive layer (204) (see FIG. 6 and FIG. 7) through an extension layer (300) of the bit line. By connecting the bit line (BL) and the conductive layer through the extension layer (300) of the bit line, the stability of the electrical contact between the bit line and the conductive layer is ensured, and the formed antifuse matrix is ​​prevented from having a conductive defect.

[0058] In one example, referring to FIGS. 1 and FIGS. 2, antifuse integrated structures (100) connected through the same word line (WL) are installed at equal intervals. That is, in the direction of extension of the word line (WL), the spacing between adjacent antifuse integrated structures (100) is equal, so that the distance between adjacent antifuse integrated structures (100) is relatively small, thereby avoiding the destruction of the electrical isolation effect of the entire antifuse memory array.

[0059] In one example, referring to FIGS. 1 and FIGS. 2, antifuse integrated structures (100) connected through the same bit line (BL) are installed at equal intervals. That is, in the direction of extension of the bit line (BL), the spacing between adjacent antifuse integrated structures (100) is equal, so that the distance between adjacent antifuse integrated structures (100) is relatively small, thereby avoiding the destruction of the electrical isolation effect of the entire antifuse memory array.

[0060] In one example, referring to FIGS. 1 and 2, the bit line (BL) connected to the antifuse integrated structure (100) in the first column is the first virtual bit line Dummy1, and the bit line (BL) connected to the antifuse integrated structure (100) in the last column is the second virtual bit line Dummy2. By installing virtual bit lines at the edges of the antifuse matrix, it is ensured that the domain environment of the antifuse integrated structure (100) located at the edge of the antifuse matrix matches the domain environment of the antifuse integrated structure inside the matrix, and it prevents normal operation from being impossible due to a defect appearing in the edge antifuse memory unit.

[0061] In one example, referring to FIGS. 1 and FIG. 2, the gate of the first memory MOS transistor (101) in the first row of the antifuse integrated structure (100) is connected to the first virtual programming wire Dummy3, and the gate of the second memory MOS transistor (102) in the last row of the antifuse integrated structure (100) is connected to the second virtual programming wire Dummy4. By installing virtual programming wires at the edges of the antifuse matrix, it is ensured that the domain environment of the antifuse integrated structure (100) located at the edge of the antifuse matrix matches that of the antifuse integrated structure inside the matrix, and it prevents normal operation from being impossible due to a defect appearing in the edge antifuse memory unit.

[0062] In some embodiments, referring to FIGS. 1 and 2, the gate of the first switch transistor (111) in the first row of the antifuse integrated structure (100) is connected to the first virtual word line Dummy5, ​​and the gate of the second switch transistor (112) in the last row of the antifuse integrated structure (100) is connected to the second virtual word line Dummy6. Here, the first virtual programming wire Dummy3 and the second virtual programming wire Dummy4 are located at the outermost edge of the antifuse matrix, and the first virtual word line Dummy5 and the second virtual word line Dummy6 are located at the second outer edge of the antifuse matrix. By installing virtual word lines at the edges of the antifuse matrix, it is ensured that the domain environment of the antifuse integrated structure (100) located at the edge of the antifuse matrix matches that of the antifuse integrated structure inside the matrix, and it prevents normal operation from being impossible due to a defect appearing in the edge antifuse memory unit.

[0063] The embodiment of the present application reduces the domain length of the antifuse memory array along the extension direction of the bit line, thereby increasing the spacing between the switch unit and the antifuse memory unit located in the same active area on the basis of laying out a memory array of the same capacity and the original layout area, and ensures the electrical isolation effect of the electrical elements in the memory array formed in the antifuse integrated structure.

[0064] It should be noted that the specific connection method of the "source" and "drain" defined above is not a limitation to the embodiments of this application, and in other embodiments, a connection method in which "drain" is replaced with "source" and "source" is replaced with "drain" may be adopted. Furthermore, to emphasize the creative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problem raised in this application, but this does not mean that other units do not exist in this embodiment.

[0065] Another embodiment of the present application further provides a memory, wherein the memory array of the memory utilizes the antifuse array structure provided in the above embodiment and is used as a memory array by utilizing the antifuse array structure provided in the above embodiment, and, based on laying out a memory array of the same capacity and original layout area, the spacing between a switch unit and an antifuse memory unit located in the same active area is increased to ensure an electrical isolation effect of the electrical elements in the memory array formed by the antifuse integrated structure.

[0066] FIG. 12 is an example diagram of the virtual structure of the memory provided in this embodiment, and FIG. 13 is an example diagram of the time sequence of the programming step and the reading step of the memory provided in this embodiment. The memory provided in this embodiment is described in more detail below by combining the drawings, and specifically as follows.

[0067] Referring to FIG. 12, the memory comprises: a memory array (403) adopting an antifuse array structure provided in any one embodiment; a control unit (401) for receiving a row address signal Row_ADD, a programming enable signal PGM_En, and a word line enable signal WL_En; and a programming gating signal PGM connected to the memory array (403) and the control unit (401), and according to the row address signal Row_ADD and the programming enable signal PGM_En. <n 2:0>It generates, and the word line gating signal WL according to the row address signal Row_ADD and the word line enable signal WL_En. <n:0>It includes a row selection control unit (402) for generating a row; and a column selection control unit (404) connected to a memory array (403) and for conducting a corresponding bit line WL of the memory array (403) according to a bit line gating signal (not shown).

[0068] Here, the programming enable signal PGM_En is intended to indicate programming wire conduction, and the word line enable signal WL_En is intended to indicate bit line conduction; and the programming gating signal PGM <n 2:0>is for conducting the programming wire PGM in the corresponding memory array (403); and the word line gating signal WL <n:0>It is intended to conduct the word line (WL) in the corresponding memory array (403).

[0069] Referring to FIG. 13, in the programming step, a programming enable signal PGM_En and a row address signal Row_ADD are provided, and a programming gating signal PGM <n 2:0>Generates, selects and melts a corresponding antifuse MOS transistor to form an antifuse memory unit, and a word line gating signal WL <n:0>It controls the opening of the switch transistor through, and performs data writing to the antifuse memory unit through the corresponding bit line (BL). In the read step, the word line enable signal WL_En and the row address signal Row_ADD are provided, and the word line gating signal WL <n:0>A corresponding antifuse memory unit is selected and electrically connected to the bit line (BL) by generating a corresponding antifuse memory unit.

[0070] By jointly controlling the bit line (BL) and the word line (WL), after the corresponding word line (WL) is gated, the antifuse memory unit is electrically connected to the bit line (BL), and the antifuse memory unit can determine whether the antifuse memory unit has broken down by the discharge rate of the bit line (BL) charge (by comparing the bit line (BL) voltage with the standard voltage VREF after a preset time), thereby obtaining 1 bit of binary data stored by the antifuse memory unit.

[0071] It needs to be explained that, in this embodiment, the programming wire PGM is connected to two antifuse memory units controlled by different word lines (WL), that is, to complete the programming of data, the programming gating signal PGM <n 2:0>The high level of duration required is two word line gating signals WL <n:0>This high level of time must be covered.

[0072] In this embodiment, each related unit is a logic unit, and in actual application, a logic unit may be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to emphasize the creative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problem raised in this application, but this does not mean that other units do not exist in this embodiment.

[0073] In this specification, each embodiment or form is described in a progressive manner, with each embodiment focusing on the differences from other embodiments, and identical or similar parts between embodiments may be referenced to one another.

[0074] In the description of this specification, the description of reference terms such as "example," "exemplary example," "some embodiment," "exemplary embodiment," "example," etc., means that specific features, structures, materials, or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of this application.

[0075] In this specification, exemplary expressions of the terms may not imply the same embodiment or example. Additionally, the specific features, structures, materials, or characteristics described may be combined in a suitable manner among any one or more embodiments or examples.

[0076] It should be understood from the description of this application that the indicated orientations or positional relationships, such as the terms "center," "top," "bottom," "left," "right," "vertical," "horizontal," "inside," and "outside," are based on the orientations or positional relationships shown in the accompanying drawings and are intended merely to facilitate the description and simplification of the explanation of this application; they do not imply or suggest that the device or element is necessarily equipped with a specific orientation or configured and operated in a specific orientation, and should not be understood as a limitation to this application.

[0077] It should be understood that terms such as "first," "second," etc., used in this application may be used to describe each structure in this application, but such structures are not limited to these terms. These terms are merely used to distinguish the first structure from the other.

[0078] In one or more drawings, the same element is indicated by similar notation. For clarity, multiple parts in the drawings are not drawn in proportion. Additionally, some known parts may not be depicted. For brevity, a structure obtained after multiple steps may be described in a single drawing. Many specific details of the present application, such as the structure, material, size, processing steps, and technology of the element, are described below to facilitate a clearer understanding of the present application. However, as will be understood by those skilled in the art, the present application may be implemented without adhering to these specific details.

[0079] Finally, it should be noted that each of the above embodiments is merely for the purpose of illustrating the technical solution of the present invention and is not intended to be limiting. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art may still make modifications to the technical solution described in each of the aforementioned embodiments, or make equivalent substitutions for some or all technical features, and it should be understood that such modifications or substitutions do not deviate from the scope of the technical solution of each embodiment of the present invention in the essence of the corresponding technical solution.

[0080] [Industrial Applicability]

[0081] In the antifuse array structure and memory provided in the embodiment of the present application, the antifuse array structure comprises a plurality of antifuse integrated structures, and the antifuse integrated structures comprise a first antifuse memory MOS transistor, a second antifuse memory MOS transistor, a first switch transistor, and a second switch transistor, wherein the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are controlled through adjacent programming wires, i.e., two antifuse memory units are controlled through adjacent programming wires, and the first switch transistor and the second switch transistor are switch transistors of the antifuse memory units and are controlled through adjacent word lines; in the antifuse array, the extension direction of the programming wire and the extension direction of the word line are the same, i.e., the extended direction of the programming wire and the extension direction of the bit line are perpendicular; Here, in the direction of the bit line extension, the programming wire is also intended to control two adjacent antifuse integrated structures arranged along the direction of the bit line extension, and the same programming wire is intended to control one of the antifuse memory units among the two adjacent antifuse integrated structures connected on the same bit line, and since the two antifuse memory units each belong to two adjacent antifuse integrated structures, the domain length of the antifuse memory array is reduced in the direction of the bit line extension; and on the basis of laying out a memory array of the same capacity and the original layout area, the spacing between the switch unit and the antifuse memory unit located in the same active area is increased, thereby ensuring the electrical isolation effect of the electrical elements of the antifuse memory array. < / n> < / n> < / n> < / n> < / m> < / n> < / m> < / m>

Claims

Claim 1 An antifuse array structure comprises a plurality of antifuse integrated structures arranged in an antifuse matrix in the extension direction of a bit line and the extension direction of a word line, wherein the extension direction of the bit line and the extension direction of the word line are perpendicular to each other; each antifuse integrated structure is installed within the same active region, and the extension direction of the active region is the same as the extension direction of the bit line; and each antifuse integrated structure comprises a first antifuse memory MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse memory MOS transistor installed sequentially along the extension direction of the bit line; The first switch transistor and the second switch transistor are each controlled through two adjacent word lines, the common end of the first switch transistor and the second switch transistor is connected to a bit line, the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are each controlled through two adjacent programming wires, and in the direction of the extension of the bit line, the programming wire is also intended to control an adjacent antifuse integrated structure, and in the direction of the extension of the bit line, the gate of the second antifuse memory MOS transistor of each antifuse integrated structure is connected to the same programming wire as the gate of the first antifuse memory MOS transistor of the adjacent antifuse integrated structure. Claim 2 An antifuse array structure according to claim 1, wherein the active region comprises an active region body, the longitudinal direction of the active region body is the extension direction of the active region, and the width of each part of the active region body is the same in the extension direction of the active region. Claim 3 An antifuse array structure according to paragraph 2, wherein the active region further includes a protrusion, the protrusion is installed on at least one side of the active region body, and in the extension direction of the active region, the length of the protrusion is smaller than the length of the active region body; in the extension direction of the word line, the width of the middle part of the active region is larger than the width of both ends of the active region, the protrusion is installed on one side of the active region body, and in the extension direction of the bit line, two adjacent protrusions of the active region are installed facing each other. Claim 4 delete Claim 5 An antifuse array structure according to claim 1, wherein the gate of the first antifuse memory MOS transistor is connected to a first programming wire; the gate of the first switch transistor is connected to a first word line, the source is connected to the first antifuse memory MOS transistor, and the drain is connected to the bit line; the gate of the second switch transistor is connected to a second word line, the source is connected to the second antifuse memory MOS transistor, and the drain is connected to the bit line; and the gate of the second antifuse memory MOS transistor is connected to a second programming wire. Claim 6 The antifuse array structure according to claim 1, wherein the active region comprises a first doping region, a second doping region, a third doping region, a fourth doping region and a fifth doping region sequentially distributed along the extension direction of the active region; wherein the first doping region is the idle end of the first antifuse memory MOS transistor, the second doping region is the common end of the first antifuse memory MOS transistor and the first switch transistor, the third doping region is the common end of the first switch transistor and the second switch transistor, the fourth doping region is the common end of the second switch transistor and the second antifuse memory MOS transistor, and the fifth doping region is the idle end of the second antifuse memory MOS transistor; and wherein the bit line is electrically connected to the third doping region. Claim 7 An antifuse array structure according to claim 6, further comprising: an insulating layer covering the active region—wherein the bit line is installed on the insulating layer, and the insulating layer is also provided with a conductive through-hole, wherein the conductive through-hole exposes the top surface of the third doping region—; and a conductive layer filling the conductive through-hole—one end of which is in contact with the third doping region and the other end of which is in contact with the bit line, so that the bit line is electrically connected to the third doping region. Claim 8 An antifuse array structure according to claim 7, wherein the conductive through-hole is installed on one side of the connected bit line, and in the extension direction of the bit line, the conductive through-holes of two adjacent antifuse integrated structures are installed on both sides of the connected bit line, and the connected bit line comes into contact with the conductive layer through the extension layer of the bit line. Claim 9 In claim 6, the gate of the first antifuse memory MOS transistor is installed on the top surface of the active region between the first doping region and the second doping region, the gate of the first switch transistor is installed on the top surface of the active region between the second doping region and the third doping region, the gate of the second switch transistor is installed on the top surface of the active region between the third doping region and the fourth doping region, and the gate of the second antifuse memory MOS transistor is installed on the top surface of the active region between the fourth doping region and the fifth doping region, or the gate of the first antifuse memory MOS transistor is installed embeddedly in the active region between the first doping region and the second doping region, the gate of the first switch transistor is installed embeddedly in the active region between the second doping region and the third doping region, the gate of the second switch transistor is installed embeddedly in the active region between the third doping region and the fourth doping region, and the second antifuse memory An antifuse array structure characterized in that the gate of the MOS transistor is embedded in the active region between the fourth doping region and the fifth doping region. Claim 10 An antifuse array structure according to claim 1, wherein the antifuse matrix comprises a plurality of columns of the antifuse integrated structure arranged along the extension direction of the word line, and the bit line connected to the antifuse integrated structure of the first column is a first virtual bit line, and the bit line connected to the antifuse integrated structure of the last column is a second virtual bit line. Claim 11 An antifuse array structure according to claim 1, wherein the antifuse matrix comprises a plurality of rows of the antifuse integrated structure arranged along the extension direction of the bit line, the gate of the first antifuse memory MOS transistor in the first row of the antifuse integrated structure is connected to a first virtual programming wire, the gate of the second antifuse memory MOS transistor in the last row of the antifuse integrated structure is connected to a second virtual programming wire, the gate of the first switch transistor in the first row of the antifuse integrated structure is connected to a first virtual word line, and the gate of the second switch transistor in the last row of the antifuse integrated structure is connected to a second virtual word line; wherein the first virtual programming wire and the second virtual programming wire are located at the outermost part of the antifuse matrix, and the first virtual word line and the second virtual word line are located at the second outer part of the antifuse matrix. Claim 12 A memory comprising a memory array, wherein the memory array adopts an antifuse array structure according to any one of claims 1 to 3 and claims 5 to 11. Claim 13 delete Claim 14 delete Claim 15 delete

Images