Electronic device performing a power gating operation

Abstract

The electronic device includes a drive control signal generation circuit that generates first and second drive control signals and a drive switching control signal. The electronic device includes a switching control signal driving circuit that drives a switching control signal to a first voltage based on the first drive control signal and the drive switching control signal, or drives a switching control signal to a second voltage based on the second drive control signal, depending on whether a power-down mode is performed.

Description

Technology Field

[0001] The present disclosure relates to an electronic device that performs a power gating operation. Background Technology

[0002] A semiconductor device can perform power gating to control whether power is supplied to an internal circuit in order to reduce unnecessary power consumption. In order for a semiconductor device to perform power gating, it must be equipped with a plurality of transistors that drive a signal to control the power gating operation.

[0003] Transistors can experience worsening degradation over time, including phenomena such as Time Dependent Dielectric Breakdown (TDDB) and Bias Temperature Instability (BTI). The problem to be solved

[0004] The present disclosure provides an electronic device that performs a power gating operation. means of solving the problem

[0005] To this end, the present disclosure provides an electronic device comprising: a drive control signal generating circuit that generates a first and second drive control signal and a drive switching control signal; and a switching control signal driving circuit that drives a switching control signal to a first voltage based on the first drive control signal and the drive switching control signal or drives the switching control signal to a second voltage based on the second drive control signal, depending on whether a power-down mode is performed, wherein the first drive control signal and the drive switching control signal are driven at different levels when the power-down mode is performed.

[0006] Additionally, the present disclosure provides an electronic device comprising: a drive control signal generating circuit that generates a first and second drive control signal and a drive switching control signal; and a switching control signal driving circuit that drives a switching control signal to a first voltage based on the first drive control signal and the drive switching control signal, or drives the switching control signal to a second voltage based on the second drive control signal and the drive switching control signal, depending on whether a power-down mode is performed, wherein the first drive control signal and the drive switching control signal are driven at different levels when the power-down mode is performed.

[0007] Additionally, the present disclosure provides an electronic device comprising: a first drive control signal generating circuit for generating a first drive control signal and a first drive switching control signal; a second drive control signal generating circuit for generating a second drive control signal; and a switching control signal driving circuit for driving a switching control signal to a first voltage based on the first drive control signal and the first drive switching control signal, or driving the switching control signal to a ground voltage based on the second drive control signal and the first drive switching control signal, depending on whether a power-down mode is entered, wherein the first drive control signal and the first drive switching control signal are driven at different levels when the power-down mode is performed. Effects of the invention

[0008] According to the present disclosure, in pulling down a switching control signal for power gating operation, the degradation of the pull-up driving element and the pull-up switching element can be mitigated by setting different levels of control signals that control whether the pull-up driving element and the pull-up switching element are turned on.

[0009] In addition, according to the present disclosure, when driving a switching control signal for power gating operation in a pull-up manner, the levels of control signals controlling whether the pull-down driving element and the pull-down switching element are turned on are set differently, thereby mitigating the degradation of the pull-down driving element and the pull-down switching element. Brief explanation of the drawing

[0010] FIG. 1 is a block diagram illustrating the configuration of an electronic device according to one example of the present disclosure. FIG. 2 is a table for explaining the levels of voltages applied to the switching control signal generation circuit illustrated in FIG. 1. Figure 3 is a diagram according to an example of a switching control signal generation circuit illustrated in Figure 1. Figure 4 is a diagram according to an example of an internal operation circuit shown in Figure 1. FIGS. 5 and 6 are drawings for explaining the operation of the switching control signal generation circuit illustrated in FIG. 3. Figure 7 is a diagram according to another example of the switching control signal generation circuit shown in Figure 1. FIGS. 8 and 9 are drawings for explaining the operation of the switching control signal generation circuit illustrated in FIG. 7. FIG. 10 is a block diagram illustrating the configuration of an electronic device according to another example of the present disclosure. FIG. 11 is a diagram for explaining the operation of the power-down signal generation circuit illustrated in FIG. 10. FIG. 12 is a diagram according to an example of a switching control signal generation circuit illustrated in FIG. 10. Specific details for implementing the invention

[0011] In describing the following examples, the term "pre-set" means that the numerical value of a parameter is predetermined when the parameter is used in a process or algorithm. Depending on the example, the numerical value of the parameter may be set when the process or algorithm starts or during the execution period of the process or algorithm.

[0012] Terms such as "first" and "second," used to distinguish various components, are not limited by the components. For example, the first component may be named the second component, and conversely, the second component may be named the first component.

[0013] When it is stated that one component is "connected" or "connected" to another component, it should be understood that they are connected directly or through an intermediate component. On the other hand, the descriptions "directly connected" and "directly connected" should be understood as meaning that one component is directly connected to another component without any intermediary component.

[0014] "Logic high level" and "logic low level" are used to describe the logic levels of signals. A signal having a "logic high level" is distinguished from a signal having a "logic low level." For example, when a signal having a first voltage corresponds to a signal having a "logic high level," a signal having a second voltage may correspond to a signal having a "logic low level." According to one embodiment, the "logic high level" may be set to a voltage greater than the "logic low level." Meanwhile, the logic levels of the signals may be set to different logic levels or opposite logic levels according to an embodiment. For example, a signal having a logic high level may be set to have a logic low level according to an embodiment, and a signal having a logic low level may be set to have a logic high level according to an embodiment.

[0015] The present disclosure will be explained in more detail below through examples. These examples are merely for illustrating the present disclosure and do not limit the scope of protection of the rights of the present disclosure.

[0016] FIG. 1 is a block diagram illustrating the configuration of an electronic device (100) according to an example of the present disclosure. As shown in FIG. 1, the electronic device (100) may include an internal voltage generating circuit (VINT GEN) (101), a bias voltage generating circuit (VNG GEN) (103), a power down signal generating circuit (POWER DOWN SIGNAL GEN) (105), a switching control signal generating circuit (CTR_SW GEN) (107), and an internal operation circuit (OPERATION CIRCUIT) (109). The electronic device (100) may be implemented as a semiconductor device. The electronic device (100) may receive a power supply voltage (VDD) and a ground voltage (VSS) from a power pad (not shown). The electronic device (100) may receive a command (CMD) from the outside and perform various internal operations, including a power down mode. The number of bits of the command (CMD) can be set differently depending on the embodiment.

[0017] The internal voltage generation circuit (101) can generate an internal voltage (VINT) by receiving a power supply voltage (VDD). The power supply voltage (VDD) and the internal voltage (VINT) can be set to positive voltages. The internal voltage generation circuit (101) can generate the internal voltage (VINT) by adjusting the level of the power supply voltage (VDD). More specifically, the internal voltage generation circuit (101) can set the level of the internal voltage (VINT) by lowering the level of the power supply voltage (VDD). That is, the internal voltage (VINT) can be set to a level lower than the level of the power supply voltage (VDD). For example, the internal voltage generation circuit (101) can generate an internal voltage (VINT) having a level of 0.8 (V) from a power supply voltage (VDD) having a level of 1.05 (V).

[0018] The bias voltage generating circuit (103) can generate a bias voltage (VNG) by receiving a ground voltage (VSS). The level of the ground voltage (VSS) can be set to 0 (V). The bias voltage (VNG) can be set to a negative voltage. The bias voltage generating circuit (103) can set the level of the bias voltage (VNG) by adjusting the level of the ground voltage (VSS). For example, the bias voltage generating circuit (105) can generate a bias voltage (VNG) having a level of -0.2 (V) from a ground voltage (VSS) having a level of 0 (V).

[0019] The power down signal generation circuit (105) can generate a power down section signal (PWDD) based on a command (CMD). The power down signal generation circuit (105) can activate the power down section signal (PWDD) by decoding a command (CMD) that has a combination for performing a power down mode. The power down signal generation circuit (105) can deactivate the power down section signal (PWDD) by decoding a command (CMD) that has a combination for terminating the power down mode. The power down section signal (PWDD) can be activated during the period in which the power down mode is performed. The power down mode can be set as a mode for cutting off the power supplied to the internal operation circuit (109). The power down section signal (PWDD) can be deactivated during the period in which the normal mode is performed. The normal mode can be set as a mode for supplying power to the internal operation circuit (109).

[0020] The switching control signal generation circuit (107) can generate a switching control signal (CTR_SW) by receiving a power supply voltage (VDD), an internal voltage (VINT), a ground voltage (VSS), and a bias voltage (VNG) based on a power down section signal (PWDD). The switching control signal generation circuit (107) can drive the switching control signal (CTR_SW) with the bias voltage (VNG) during the period when the power down section signal (PWDD) is active. The switching control signal generation circuit (107) can drive the switching control signal (CTR_SW) with the power supply voltage (VDD) during the period when the power down section signal (PWDD) is inactive. A detailed description of the specific configuration and operation of the switching control signal generation circuit (107) will be provided later with reference to FIG. 3.

[0021] The internal operation circuit (109) can perform various internal operations based on the switching control signal (CTR_SW). When the switching control signal (CTR_SW) is driven by the bias voltage (VNG), the internal operation circuit (109) can enter a power-down mode and cut off the power supply. When the switching control signal (CTR_SW) is driven by the power supply voltage (VDD), the internal operation circuit (109) can enter a normal mode to receive power and perform various internal operations. A detailed description of the specific configuration and operation of the internal operation circuit (109) will be provided later with reference to FIG. 4.

[0022] FIG. 2 is a table for explaining the levels of voltages applied to the switching control signal generation circuit (107) illustrated in FIG. 1. Referring to FIG. 2, the level of the power supply voltage (VDD) can be set to 1.05 (V). The level of the internal voltage (VINT) can be set to 0.8 (V), which is lower than the level of the power supply voltage (VDD). The level of the ground voltage (VSS) can be set to 0 (V). The level of the bias voltage (VNG) can be set to a negative voltage of -0.2 (V).

[0023] FIG. 3 is a drawing according to an example of a switching control signal generating circuit (107) illustrated in FIG. 1. As illustrated in FIG. 3, the switching control signal generating circuit (107) may include a driving control signal generating circuit (121) and a switching control signal driving circuit (123a).

[0024] The drive control signal generation circuit (121) may include first, second, third, and fourth drive circuits (121_1, 121_2, 121_3, 121_4) and a level shifter (122_1). The drive control signal generation circuit (121) may generate a first drive control signal (CTR_DRV1), a drive switching control signal (CTR_DSW), and a second drive control signal (CTR_DRV2) by receiving a power supply voltage (VDD), an internal voltage (VINT), a ground voltage (VSS), and a bias voltage (VNG) based on a power down section signal (PWDD).

[0025] The drive control signal generation circuit (121) can drive the first drive control signal (CTR_DRV1) to the power supply voltage (VDD) and drive the drive switching control signal (CTR_DSW) and the second drive control signal (CTR_DRV2) to the internal voltage (VINT) when performing the power down mode. That is, the drive control signal generation circuit (121) can drive the first drive control signal (CTR_DRV1) and the drive switching control signal (CTR_DSW) to different levels when performing the power down mode.

[0026] The drive control signal generation circuit (121) can drive the first drive control signal (CTR_DRV1) and the drive switching control signal (CTR_DSW) to the ground voltage (VSS) and the second drive control signal (CTR_DRV2) to the bias voltage (VNG) when the power-down mode ends. That is, the drive control signal generation circuit (121) can drive the second drive control signal (CTR_DRV2) and the drive switching control signal (CTR_DSW) to different levels when the power-down mode ends.

[0027] The first driving circuit (121_1) receives a power down section signal (PWDD) and can drive the inverted power down section signal (PWDDB) to either the power supply voltage (VDD) or the ground voltage (VSS). When performing a power down mode, the first driving circuit (121_1) can drive the inverted power down section signal (PWDDB) to the ground voltage (VSS) based on the activated power down section signal (PWDD). When the power down mode ends, the first driving circuit (121_1) can drive the inverted power down section signal (PWDDB) to the power supply voltage (VDD) based on the deactivated power down section signal (PWDD). The first driving circuit (121_1) can be implemented as an inverter.

[0028] The second driving circuit (121_2) receives an inverted power-down section signal (PWDDB) and can drive the first driving control signal (CTR_DRV1) to either the power supply voltage (VDD) or the ground voltage (VSS). The second driving circuit (121_2) can drive the first driving control signal (CTR_DRV1) to the power supply voltage (VDD) when performing the power-down mode. The second driving circuit (121_2) can drive the first driving control signal (CTR_DRV1) to the ground voltage (VSS) when the power-down mode ends. The second driving circuit (121_2) can be implemented as an inverter.

[0029] The third driving circuit (121_3) receives the inverted power-down section signal (PWDDB) and can drive the driving switching control signal (CTR_DSW) to either the internal voltage (VINT) or the ground voltage (VSS). The third driving circuit (121_3) can drive the driving switching control signal (CTR_DSW) to the internal voltage (VINT) when performing the power-down mode. The third driving circuit (121_3) can drive the driving switching control signal (CTR_DSW) to the ground voltage (VSS) when the power-down mode ends. The third driving circuit (121_3) can be implemented as an inverter.

[0030] The level shifter (122_1) can shift the level of the inverted power down section signal (PWDDB). For example, the level shifter (122_1) can lower the level of the inverted power down section signal (PWDDB) by 0.2 (V) and output it to the input terminal of the fourth driving circuit (121_4).

[0031] The fourth driving circuit (121_4) receives the output signal of the level shifter (122_1) and can drive the second driving control signal (CTR_DRV2) to either an internal voltage (VINT) or a bias voltage (VNG). The fourth driving circuit (121_4) can drive the second driving control signal (CTR_DRV2) to the internal voltage (VINT) when performing a power-down mode. The fourth driving circuit (121_4) can drive the second driving control signal (CTR_DRV2) to the bias voltage (VNG) when the power-down mode ends. The fourth driving circuit (121_4) can be implemented as an inverter.

[0032] The switching control signal driving circuit (123a) can drive the switching control signal (CTR_SW) by receiving the power supply voltage (VDD) and bias voltage (VNG) based on the first driving control signal (CTR_DRV1), the second driving control signal (CTR_DRV2), and the driving switching control signal (CTR_DSW). The switching control signal driving circuit (123a) may include a first driving element (123_1a), a driving switching element (123_2a), and a second driving element (123_3a). The first driving element (123_1a) and the driving switching element (123_2a) may be implemented as P-MOS transistors with a thin gate oxide thickness to quickly enter normal mode when the power-down mode ends. The second driving element (123_3a) can be implemented as an n-MOS transistor with a thicker gate oxide layer to mitigate transistor degradation. Transistor degradation can be more severe as the voltage difference between the gate and drain terminals of the transistor increases. According to an embodiment, the second driving element (123_3a) may have a thicker gate oxide layer than the first driving element (123_1a) and the driving switching element (123_2a). When the first driving element (123_1a) is turned on based on the first driving control signal (CTR_DRV1), it can drive an internal node (nd11) by receiving a power supply voltage (VDD). When the driving switching element (123_2a) is turned on based on the driving switching control signal (CTR_DSW), it can electrically connect the internal node (nd11) and the output node (nd12) that outputs the switching control signal (CTR_SW). When the second driving element (123_3a) is turned on based on the second driving control signal (CTR_DRV2), it can drive the output node (nd12) by receiving a bias voltage (VNG). The body of the second driving element (123_3a) can have the bias voltage (VNG) applied to it.

[0033] The switching control signal driving circuit (123a) can turn on the first driving element (123_1a) and the driving switching element (123_2a) to drive the switching control signal (CTR_SW) to the power supply voltage (VDD) or turn on the second driving element (123_3a) to drive the switching control signal (CTR_SW) to the bias voltage (VNG) depending on whether the power down mode is performed. When the power down mode is performed, the switching control signal driving circuit (123a) can turn on the second driving element (123_3a) based on the second driving control signal (CTR_DRV2) to drive the switching control signal (CTR_SW) to the bias voltage (VNG). The switching control signal driving circuit (123a) can turn off the first driving element (123_1a) and the driving switching element (123_2a) based on the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) when performing a power-down mode. When the power-down mode ends, the switching control signal driving circuit (123a) can turn on the first driving element (123_1a) and the driving switching element (123_2a) based on the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) to drive the switching control signal (CTR_SW) to the power supply voltage (VDD). The switching control signal driving circuit (123a) can turn off the second driving element (123_3a) based on the second driving control signal (CTR_DRV2) when the power-down mode ends.

[0034] FIG. 4 is a drawing according to an example of an internal operation circuit (111) illustrated in FIG. 1. As illustrated in FIG. 4, the internal operation circuit (111) may include a logic circuit (LOGIC) (131) and a switching element (133).

[0035] The logic circuit (131) may be implemented with elements to perform various internal operations according to the embodiment. The logic circuit (131) may be connected between a power line (135_1) and a virtual ground line (135_2). The power line (135_1) may supply a positive voltage. For example, the power line (135_1) may be connected to a terminal of the power voltage (VDD in FIG. 1). For another example, the power line (135_1) may supply an internal voltage (VINT in FIG. 1).

[0036] The switching element (133) can be implemented as an n-MOS transistor. The switching element (133) can be connected between a virtual ground line (135_2) and a ground line (135_3). The ground line (135_3) can be connected to a terminal of the ground voltage (VSS in FIG. 1). The switching element (133) can control the supply of the ground voltage (VSS) to the logic circuit (131) based on a switching control signal (CTR_SW). When performing a power-down mode, the switching element (133) can cut off the supply of the ground voltage (VSS) to the logic circuit (131) based on a switching control signal (CTR_SW) driven by a bias voltage (VNG in FIG. 1). In this embodiment, the switching element (133) can reduce the leakage current of the logic circuit (131) during the period of performing the power-down mode by receiving a switching control signal (CTR_SW) driven by a bias voltage (VNG) having a level lower than the level of the ground voltage (VSS in FIG. 1) when performing the power-down mode. When the power-down mode ends, the switching element (133) can supply the ground voltage (VSS) to the logic circuit (131) based on the switching control signal (CTR_SW) driven by the power supply voltage (VDD in FIG. 1). In this embodiment, the switching element (133) can smoothly supply power to the logic circuit (131) during the period of performing the normal mode by receiving a switching control signal (CTR_SW) driven by a power supply voltage (VDD) having a level higher than the level of the internal voltage (VINT) when performing the power-down mode.

[0037] FIG. 5 is a diagram illustrating the operation performed in the switching control signal generation circuit (107) shown in FIG. 3 when performing a power-down mode. Referring to FIG. 2, the power supply voltage (VDD), internal voltage (VINT), and bias voltage (VNG) shown in FIG. 5 can be set to levels of 1.05 (V), 0.8 (V), and -0.2 (V), respectively.

[0038] The drive control signal generation circuit (121) can drive the first drive control signal (CTR_DRV1), the drive switching control signal (CTR_DSW), and the second drive control signal (CTR_DRV2) to 1.05 (V), 0.8 (V), and 0.8 (V), respectively, based on the power down section signal (PWDD) having a logic high level ('H') when performing the power down mode.

[0039] The second driving element (123_3a) can be turned on based on the second driving control signal (CTR_DRV2) driven to 0.8 (V) when performing a power-down mode, and can drive the output node (nd12) to -0.2 (V).

[0040] The first driving element (123_1a) can be turned off based on the first driving control signal (CTR_DRV1) driven at 1.05 (V) when performing a power-down mode. Degradation can be mitigated by isolating the first driving element (123_1a) from the output node (nd12) driven at -0.2 (V) by the driving switching element (123_2a). (Transistor degradation may become more severe as the voltage difference between the gate and drain terminals of the transistor increases.)

[0041] When performing a power-down mode, the driving switching element (123_2a) is turned off based on a driving switching control signal (CTR_DSW) that is driven to 0.8 (V), which is lower than 1.05 (V), even if the output node (nd12) is driven to -0.2 (V), which is lower than 0 (V), thereby mitigating degradation.

[0042] Accordingly, when the switching control signal driving circuit (123a) pulls down the switching control signal (CTR_SW) for power gating operation when performing a power down mode, it receives the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) driven at different levels, thereby mitigating the degradation of the first driving element (123_1a) and the driving switching element (123_2a).

[0043] FIG. 6 is a diagram illustrating the operation performed in the switching control signal generation circuit (107) shown in FIG. 3 when the power-down mode is terminated. Referring to FIG. 2, the power supply voltage (VDD), ground voltage (VSS), and bias voltage (VNG) shown in FIG. 6 can be set to 1.05 (V), 0 (V), and -0.2 (V), respectively.

[0044] The drive control signal generation circuit (121) can drive the first drive control signal (CTR_DRV1), the drive switching control signal (CTR_DSW), and the second drive control signal (CTR_DRV2) to 0(V), 0(V), and -0.2(V), respectively, based on the power down section signal (PWDD) having a logic low level ('L') when the power down mode ends.

[0045] The first driving element (123_1a) and the driving switching element (123_2a) are turned on based on the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) which are driven to 0 (V) when the power down mode ends, and can drive the output node (nd12) to 1.05 (V).

[0046] The second driving element (123_3a) can be turned off based on the second driving control signal (CTR_DRV2) driven at -0.2 (V) when the power-down mode ends. Even if the output node (nd12) of the second driving element (123_3a) is driven at 1.05 (V), which is higher than 0.8 (V), the gate oxide film can be formed thickly so that degradation can be mitigated.

[0047] FIG. 7 is a drawing according to another example of the switching control signal generation circuit (107) illustrated in FIG. 1. As illustrated in FIG. 7, the switching control signal generation circuit (107) may include a driving control signal generation circuit (121) and a switching control signal driving circuit (123b). A detailed description of the driving control signal generation circuit (121) was previously provided in the description of FIG. 3.

[0048] The switching control signal driving circuit (123b) can drive the switching control signal (CTR_SW) by receiving the power supply voltage (VDD) and bias voltage (VNG) based on the first driving control signal (CTR_DRV1), the second driving control signal (CTR_DRV2), and the driving switching control signal (CTR_DSW). The switching control signal driving circuit (123b) may include a first driving element (123_1b), a first driving switching element (123_2b), a second driving element (123_3b), and a second driving switching element (123_4b). The first driving element (123_1b) and the first driving switching element (123_2b) may be implemented as P-MOS transistors with a thin gate oxide thickness to quickly enter normal mode when the power-down mode ends. The second driving element (123_3b) and the second driving switching element (123_4b) can be implemented as n-MOS transistors with a thin gate oxide thickness to quickly enter power-down mode when the normal mode ends. When the first driving element (123_1b) is turned on based on the first driving control signal (CTR_DRV1), it can drive the internal node (nd21) by receiving the power supply voltage (VDD). When the first driving switching element (123_2b) is turned on based on the driving switching control signal (CTR_DSW), it can electrically connect the internal node (nd21) and the output node (nd22) that outputs the switching control signal (CTR_SW). When the second driving element (123_3b) is turned on based on the second driving control signal (CTR_DRV2), it can drive the internal node (nd23) by receiving a bias voltage (VNG). When the second driving switching element (123_4b) is turned on based on the second driving control signal (CTR_DRV2), it can electrically connect the internal node (nd23) and the output node (nd22). The body of the second driving element (123_3b) and the second driving switching element (123_4b) can have the bias voltage (VNG) applied.

[0049] The switching control signal driving circuit (123b) can turn on the first driving element (123_1b) and the first driving switching element (123_2b) to drive the switching control signal (CTR_SW) to the power supply voltage (VDD) depending on whether the power down mode is performed, or turn on the second driving element (123_3b) and the second driving switching element (123_4b) to drive the switching control signal (CTR_SW) to the bias voltage (VNG). When the power down mode is performed, the switching control signal driving circuit (123b) can turn on the second driving element (123_3b) and the second driving switching element (123_4b) based on the second driving control signal (CTR_DRV2) and the driving switching control signal (CTR_DSW) to drive the switching control signal (CTR_SW) to the bias voltage (VNG). The switching control signal driving circuit (123b) can turn off the first driving element (123_1b) and the first driving switching element (123_2b) based on the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) when performing a power-down mode. The switching control signal driving circuit (123a) can turn on the first driving element (123_1b) and the first driving switching element (123_2b) based on the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) when the power-down mode ends, thereby driving the switching control signal (CTR_SW) to the power supply voltage (VDD). The switching control signal driving circuit (123a) can turn off the second driving element (123_3b) and the second driving switching element (123_4b) based on the second driving control signal (CTR_DRV2) and the driving switching control signal (CTR_DSW) when the power down mode ends.

[0050] FIG. 8 is a diagram illustrating the operation performed in the switching control signal generation circuit (107) shown in FIG. 7 when performing a power-down mode. Referring to FIG. 2, the power supply voltage (VDD), internal voltage (VINT), and bias voltage (VNG) shown in FIG. 7 can be set to levels of 1.05 (V), 0.8 (V), and -0.2 (V), respectively.

[0051] The drive control signal generation circuit (121) can drive the first drive control signal (CTR_DRV1), the drive switching control signal (CTR_DSW), and the second drive control signal (CTR_DRV2) to 1.05 (V), 0.8 (V), and 0.8 (V), respectively, based on the power down section signal (PWDD) having a logic high level ('H') when performing the power down mode.

[0052] The second driving element (123_3b) and the second driving switching element (123_4b) can be turned on based on the second driving control signal (CTR_DRV2) and the driving switching control signal (CTR_DSW) driven to 0.8 (V) when performing a power-down mode, and can drive the output node (nd22) to -0.2 (V).

[0053] The first driving element (123_1b) can be turned off based on the first driving control signal (CTR_DRV1) driven at 1.05 (V) when performing a power-down mode. Degradation can be mitigated by isolating the first driving element (123_1b) from the output node (nd22) driven at -0.2 (V) by the driving switching element (123_2b). (Transistor degradation may become more severe as the voltage difference between the gate and drain terminals of the transistor increases.)

[0054] When performing a power-down mode, the first driving switching element (123_2b) is turned off based on a driving switching control signal (CTR_DSW) that is driven to 0.8 (V), which is lower than 1.05 (V), even if the output node (nd22) is driven to -0.2 (V), which is lower than 0 (V), thereby mitigating degradation.

[0055] Accordingly, when the switching control signal driving circuit (123b) pulls down the switching control signal (CTR_SW) for power gating operation when performing a power down mode, it receives the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) driven at different levels, thereby mitigating the degradation of the first driving element (123_1b) and the first driving switching element (123_2b).

[0056] FIG. 9 is a diagram illustrating the operation performed in the switching control signal generation circuit (107) shown in FIG. 7 when the power-down mode is terminated. Referring to FIG. 2, the power supply voltage (VDD), ground voltage (VSS), and bias voltage (VNG) shown in FIG. 9 can be set to 1.05 (V), 0 (V), and -0.2 (V), respectively.

[0057] The drive control signal generation circuit (121) can drive the first drive control signal (CTR_DRV1), the drive switching control signal (CTR_DSW), and the second drive control signal (CTR_DRV2) to 0(V), 0(V), and -0.2(V), respectively, based on the power down section signal (PWDD) having a logic low level ('L') when the power down mode ends.

[0058] The first driving element (123_1b) and the first driving switching element (123_2b) can drive the output node (nd22) to 1.05 (V) based on the first driving control signal (CTR_DRV1) and the driving switching control signal (CTR_DSW) which are driven to 0 (V) when the power down mode ends.

[0059] The second driving element (123_3b) can be turned off based on the first driving control signal (CTR_DRV1) driven at -0.2 (V) when the power-down mode ends. The second driving element (123_3b) can be isolated from the output node (nd22) driven at 1.05 (V) by the second driving switching element (123_4b), thereby mitigating degradation.

[0060] The second driving switching element (123_4b) can be turned off based on the driving switching control signal (CTR_DSW) which is driven to 0 (V) which is higher than -0.2 (V), even if the output node (nd22) is driven to 1.05 (V) which is higher than 0.8 (V) when the power down mode ends, so that degradation can be mitigated.

[0061] Accordingly, when the power down mode ends, the switching control signal driving circuit (123b) pulls up the switching control signal (CTR_SW) for power gating operation, by receiving the second driving control signal (CTR_DRV2) and the driving switching control signal (CTR_DSW) driven at different levels, thereby mitigating the degradation of the second driving element (123_3b) and the second driving switching element (123_4b).

[0062] FIG. 10 is a block diagram illustrating the configuration of an electronic device (100c) according to another example of the present disclosure. As shown in FIG. 10, the electronic device (100c) may include an internal voltage generating circuit (VINT GEN) (101), a bias voltage generating circuit (VNG GEN) (103), a power down signal generating circuit (POWER DOWN SIGNAL GEN) (105c), a switching control signal generating circuit (CTR_SW GEN) (107c), and an internal operation circuit (OPERATION CIRCUIT) (109). The description of the internal voltage generating circuit (101), the bias voltage generating circuit (103), and the internal operation circuit (109) is omitted as they were previously described in the description of FIG. 1.

[0063] The power down signal generation circuit (105c) can generate a power down interval signal (PWDD), a power down pulse (PWDD_P), and a power down delay interval signal (PWDD_D) based on a command (CMD). The power down interval signal generation circuit (105c) can activate the power down interval signal (PWDD) by decoding a command (CMD) that has a combination for performing a power down mode. The power down signal generation circuit (105c) can deactivate the power down interval signal (PWDD) by decoding a command (CMD) that has a combination for terminating the power down mode. The power down interval signal generation circuit (105c) can be activated during the interval in which the power down mode is performed. The power down interval signal (PWDD) can be deactivated during the interval in which the normal mode is performed. The power down signal generation circuit (105c) can activate a power down pulse (PWDD_P) during a set interval when entering a power down mode. The set interval can be set in various ways depending on the embodiment. The power down signal generation circuit (105c) can activate a power down delay interval signal (PWDD_D) from the time the set interval has elapsed until the power down mode ends. A detailed description of the operation of the power down signal generation circuit (105c) will be provided later with reference to FIG. 11.

[0064] The switching control signal generation circuit (107c) can generate a switching control signal (CTR_SW) by receiving a power supply voltage (VDD), an internal voltage (VINT), a ground voltage (VSS), and a bias voltage (VNG) based on a power down interval signal (PWDD), a power down pulse (PWDD_P), and a power down interval signal (PWDD_D). The switching control signal generation circuit (107c) can drive the switching control signal (CTR_SW) to the ground voltage (VSS) during the interval when both the power down interval signal (PWDD) and the power down pulse (PWDD_P) are active. That is, the switching control signal generation circuit (107c) can drive the switching control signal (CTR_SW) to the ground voltage (VSS) during a set interval when entering a power down mode. The switching control signal generation circuit (107c) can drive the switching control signal (CTR_SW) to the bias voltage (VNG) during the period when the power down interval signal (PWDD_D) is active. That is, the switching control signal generation circuit (107c) can drive the switching control signal (CTR_SW) to the bias voltage (VNG) from the time when the set interval has elapsed until the power down mode ends. The switching control signal generation circuit (107c) can drive the switching control signal (CTR_SW) to the power supply voltage (VDD) during the period when the power down interval signal (PWDD) is deactivated. The switching control signal generation circuit (107c) drives the switching control signal (CTR_SW) from the power supply voltage (VDD) to the ground voltage (VSS) and then to the bias voltage (VNG) when entering the power-down mode, thereby reducing power consumption compared to driving the switching control signal (CTR_SW) directly from the power supply voltage (VDD) to the bias voltage (VNG). The specific configuration and operation of the switching control signal generation circuit (107c) will be described later with reference to FIG. 12.

[0065] FIG. 11 is a diagram for explaining the operation of the power down section signal generation circuit (105c) illustrated in FIG. 10. Referring to FIG. 11, the power down section signal generation circuit (105c) can activate the power down section signal (PWDD) during the section (td11) in which the power down mode is performed. The power down section signal generation circuit (105c) can activate the power down pulse (PWDD_P) during the set section (td12) when entering the power down mode. The power down section signal generation circuit (105c) can activate the power down duration section signal (PWDD_D) during the section (td13) from the time the set section (td12) has elapsed until the power down mode ends.

[0066] FIG. 12 is a drawing according to an example of a switching control signal generation circuit (107c) illustrated in FIG. 10. As illustrated in FIG. 12, the switching control signal generation circuit (107c) may include a first driving control signal generation circuit (121_1c), a second driving control signal generation circuit (121_2c), a third driving control signal generation circuit (121_3c), and a switching control signal driving circuit (123c).

[0067] The first drive control signal generation circuit (121_1c) can generate a first drive control signal (CTR_DRV1) and a first drive switching control signal (CTR_DSW1) by receiving the power supply voltage (VDD), internal voltage (VINT), and ground voltage (VSS) based on the power down section signal (PWDD). When performing a power down mode, the first drive control signal generation circuit (121_1c) can drive the first drive control signal (CTR_DRV1) with the power supply voltage (VDD) and drive the first drive switching control signal (CTR_DSW1) with the internal voltage (VINT). That is, when performing a power down mode, the first drive control signal generation circuit (121_1c) can drive the first drive control signal (CTR_DRV1) and the first drive switching control signal (CTR_DSW1) at different levels. The first drive control signal generation circuit (121_1c) can drive the first drive control signal (CTR_DRV1) and the first drive switching control signal (CTR_DSW1) to ground voltage (VSS) when the power down mode ends. The first drive control signal generation circuit (121_1c) may include first, second, and third drive circuits (121_11c, 121_12c, 121_13c). The first, second, and third drive circuits (121_11c, 121_12c, 121_13c) may each be implemented as an inverter.

[0068] The second drive control signal generation circuit (121_2c) can generate a second drive control signal (CTR_DRV2) by receiving the power supply voltage (VDD), internal voltage (VINT), ground voltage (VSS), and bias voltage (VNG) based on the power down pulse (PWDD_P). The second drive control signal generation circuit (121_2c) can drive the second drive switching control signal (CTR_DSW2) with the internal voltage (VINT) during a set interval when entering the power down mode. The second drive control signal generation circuit (121_2c) can drive the second drive switching control signal (CTR_DSW2) with the bias voltage (VNG) after the set interval when entering the power down mode. The second drive control signal generation circuit (121_2c) may include fourth and fifth drive circuits (121_21c, 121_23c) and a level shifter (121_22c). The fourth and fifth drive circuits (121_21c, 121_23c) may each be implemented as an inverter. The level shifter (121_22c) may shift the level of the signal output from the fourth drive circuit (121_21c) and output it to the input terminal of the fifth drive circuit (121_23c). For example, the level shifter (121_22c) may lower the level of the signal output from the fourth drive circuit (121_21c) by 0.2 (V) and output it to the input terminal of the fifth drive circuit (121_23c).

[0069] The third drive control signal generation circuit (121_3c) can generate the third drive control signal (CTR_DRV2) and the second drive switching control signal (CTR_DSW2) by receiving the power supply voltage (VDD), internal voltage (VINT), ground voltage (VSS), and bias voltage (VNG) based on the power down interval signal (PWDD_D). The third drive control signal generation circuit (121_3c) can drive the third drive control signal (CTR_DRV2) and the second drive switching control signal (CTR_DSW2) with the internal voltage (VINT) after the set interval in the power down mode. When the power down mode ends, the third drive control signal generation circuit (121_3c) can drive the third drive control signal (CTR_DRV2) with the bias voltage (VNG) and drive the second drive switching control signal (CTR_DSW2) with the ground voltage (VSS). That is, the third drive control signal generation circuit (121_3c) can drive the third drive control signal (CTR_DRV3) and the second drive switching control signal (CTR_DSW2) to different levels when the power-down mode ends. The third drive control signal generation circuit (121_3c) may include the sixth, seventh, and eighth drive circuits (121_31c, 121_32c, 121_34c) and a level shifter (121_33c). The sixth, seventh, and eighth drive circuits (121_31c, 121_32c, 121_34c) may each be implemented as an inverter. The level shifter (121_33c) can shift the level of the signal output from the sixth driving circuit (121_31c) and output it to the input terminal of the eighth driving circuit (121_34c). For example, the level shifter (121_33c) can lower the level of the signal output from the sixth driving circuit (121_31c) by 0.2 (V) and output it to the input terminal of the eighth driving circuit (121_34c).

[0070] The switching control signal driving circuit (123c) can drive the switching control signal (CTR_SW) by receiving the power supply voltage (VDD), ground voltage (VSS), and bias voltage (VNG) based on the first driving control signal (CTR_DRV1), the second driving control signal (CTR_DRV2), the third driving control signal (CTR_DRV3), the first driving switching control signal (CTR_DSW1), and the second driving switching control signal (CTR_DSW2). The switching control signal driving circuit (123c) may include a first driving element (123_1c), a first driving switching element (123_2c), a second driving element (123_3c), a second driving switching element (123_4c), a third driving element (123_5c), and a third driving switching element (123_6c). The first driving element (123_1c) and the first driving switching element (123_2c) can be implemented as P-MOS transistors with a thin gate oxide thickness to quickly enter normal mode when the power-down mode ends. The second driving element (123_3c), the second driving switching element (123_4c), the third driving element (123_5c), and the third driving switching element (123_6c) can be implemented as N-MOS transistors with a thin gate oxide thickness to quickly enter power-down mode when the normal mode ends. When the first driving element (123_1c) is turned on based on the first driving control signal (CTR_DRV1), it can drive the internal node (nd31) by receiving the power supply voltage (VDD). When the first driving switching element (123_2c) is turned on based on the first driving switching control signal (CTR_DSW1), it can electrically connect the internal node (nd31) and the output node (nd32) that outputs the switching control signal (CTR_SW). When the second driving element (123_3c) is turned on based on the second driving control signal (CTR_DRV2), it can drive the internal node (nd33) by receiving the ground voltage (VSS). When the second driving switching element (123_4c) is turned on based on the second driving control signal (CTR_DRV2), it can electrically connect the internal node (nd33) and the output node (nd32).When the third driving element (123_5c) is turned on based on the third driving control signal (CTR_DRV3), it can drive the internal node (nd34) by receiving a bias voltage (VNG). When the third driving switching element (123_6c) is turned on based on the second driving switching control signal (CTR_DSW2), it can electrically connect the internal node (nd34) and the output node (nd32). The bodies of the second driving element (123_3c), the second driving switching element (123_4c), the third driving element (123_5c), and the third driving switching element (123_6c) can each have a bias voltage (VNG) applied.

[0071] The switching control signal driving circuit (123c) can turn on the first driving element (123_1c) and the first driving switching element (123_2c) to drive the switching control signal (CTR_SW) to the power supply voltage (VDD) depending on whether the power down mode is entered, or turn on the second driving element (123_3c) and the second driving switching element (123_4c) to drive the switching control signal (CTR_SW) to the ground voltage (VSS). The switching control signal driving circuit (123c) can turn on the second driving element (123_3c) and the second driving switching element (123_4c) during a set interval when entering a power-down mode to drive the switching control signal (CTR_SW) to ground voltage (VSS), and after the set interval, turn on the third driving element (123_5c) and the third driving switching element (123_6c) to drive the switching control signal (CTR_SW) to bias voltage (VNG).

[0072] The switching control signal driving circuit (123c) can turn on the second driving element (123_3c) and the second driving switching element (123_4c) based on the second driving control signal (CTR_DRV2) and the first driving switching control signal (CTR_DSW1) during the setting period when entering the power down mode, thereby driving the switching control signal (CTR_SW) to the ground voltage (VSS). The switching control signal driving circuit (123c) can turn on the third driving element (123_5c) and the third driving switching element (123_6c) based on the third driving control signal (CTR_DRV3) and the second driving switching control signal (CTR_DSW2) after the setting period in the power down mode, thereby driving the switching control signal (CTR_SW) to the bias voltage (VNG). The switching control signal driving circuit (123c) can turn off the first driving element (123_1c) and the first driving switching element (123_2c) based on the first driving control signal (CTR_DRV1) and the first driving switching control signal (CTR_DSW1) during the period of performing the power down mode.

[0073] The switching control signal driving circuit (123c) can turn on the first driving element (123_1c) and the first driving switching element (123_2c) based on the first driving control signal (CTR_DRV1) and the first driving switching control signal (CTR_DSW1) when the power down mode ends, and drive the switching control signal (CTR_SW) to the power supply voltage (VDD). The switching control signal driving circuit (123a) can turn off the second driving element (123_3c) and the second driving switching element (123_4c) based on the second driving control signal (CTR_DRV2) and the first driving switching control signal (CTR_DSW1) when the power down mode ends. The switching control signal driving circuit (123a) can turn off the third driving element (123_5c) and the third driving switching element (123_6c) based on the third driving control signal (CTR_DRV3) and the second driving switching control signal (CTR_DSW2) when the power down mode ends.

[0074] Accordingly, the switching control signal driving circuit (123c) drives the switching control signal (CTR_SW) from the power supply voltage (VDD) to the ground voltage (VSS) and then drives it to the bias voltage (VNG) when entering the power down mode, thereby reducing power consumption compared to when the switching control signal (CTR_SW) is driven directly from the power supply voltage (VDD) to the bias voltage (VNG).

[0075] In addition, the switching control signal driving circuit (123c) can mitigate the degradation of the pull-up driving element and the pull-up switching element by setting different levels of control signals that control whether the pull-up driving element and the pull-up switching element turn on when driving the switching control signal for power gating operation. Likewise, the switching control signal driving circuit (123c) can mitigate the degradation of the pull-down driving element and the pull-down switching element by setting different levels of control signals that control whether the pull-down driving element and the pull-down switching element turn on when driving the switching control signal for power gating operation. Explanation of the symbols

[0076] 100: Electronic device 101: Internal voltage generation circuit 103: Bias voltage generation circuit 105: Power-down signal generation circuit 107: Switching control signal generation circuit 109: Internal operation circuit

Claims

Claim 1 An electronic device comprising: a drive control signal generating circuit that generates a first and second drive control signal and a drive switching control signal; and a switching control signal driving circuit that drives a switching control signal to a first voltage based on the first drive control signal and the drive switching control signal or drives the switching control signal to a second voltage based on the second drive control signal, depending on whether a power down mode is performed, wherein the first drive control signal and the drive switching control signal are driven at different levels when the power down mode is performed. Claim 2 An electronic device according to claim 1, wherein the switching control signal driving circuit drives the switching control signal to the second voltage when performing the power-down mode, and the second voltage is set to a negative voltage. Claim 3 An electronic device according to claim 1, wherein the switching control signal driving circuit drives the switching control signal to the first voltage when the power-down mode is terminated, and the first voltage is set to a positive voltage. Claim 4 An electronic device according to claim 1, wherein the drive control signal generating circuit drives the first drive control signal to the first voltage and drives the drive switching control signal to the third voltage when performing the power down mode, wherein the level of the third voltage is set to a positive voltage lower than the level of the first voltage. Claim 5 In claim 4, the drive control signal generating circuit is an electronic device that drives the second drive control signal to the third voltage when performing the power down mode. Claim 6 An electronic device according to claim 1, wherein the switching control signal driving circuit comprises: a first driving element that drives an internal node by receiving the first voltage based on the first driving control signal; a driving switching element that electrically connects the internal node and an output node that outputs the switching control signal based on the driving switching control signal; and a second driving element that drives the output node by receiving the second voltage based on the second driving control signal. Claim 7 An electronic device according to claim 6, wherein the first driving element and the driving switching element are implemented as P-MOS transistors, and the second driving element is implemented as an N-MOS transistor. Claim 8 In claim 6, the switching control signal driving circuit is an electronic device that, when performing the power-down mode, turns on the second driving element based on the second driving control signal to drive the output node to the second voltage, and turns off the first driving element and the driving switching element based on the first driving control signal and the driving switching control signal. Claim 9 In claim 6, the switching control signal driving circuit is an electronic device that, when the power-down mode ends, turns on the first driving element and the driving switching element based on the first driving control signal and the driving switching control signal to drive the output node to the first voltage, and turns off the second driving element based on the second driving control signal. Claim 10 In claim 6, the second driving element is an electronic device in which the gate oxide film is formed thicker than that of the first driving element and the driving switching element. Claim 11 An electronic device according to claim 1, further comprising an internal operation circuit in which the power supply is cut off based on the switching control signal when performing the power down mode. Claim 12 In claim 11, the internal operating circuit comprises a logic circuit connected between a power line and a virtual ground line; and a switching element implemented by an n-MOS transistor connected to the virtual ground line and a ground line, wherein the switching element controls the supply of a ground voltage to the logic circuit based on the switching control signal. Claim 13 An electronic device comprising: a drive control signal generating circuit that generates a first and second drive control signal and a drive switching control signal; and a switching control signal driving circuit that drives a switching control signal to a first voltage based on the first drive control signal and the drive switching control signal, or drives the switching control signal to a second voltage based on the second drive control signal and the drive switching control signal, depending on whether a power down mode is performed, wherein the first drive control signal and the drive switching control signal are driven at different levels when the power down mode is performed. Claim 14 In claim 13, the drive control signal generating circuit is an electronic device that drives the second drive control signal and the drive switching control signal to different levels when the power-down mode is terminated. Claim 15 In claim 13, the switching control signal driving circuit comprises: a first driving element that drives a first internal node by receiving a first voltage based on the first driving control signal; a first driving switching element that electrically connects the first internal node and an output node that outputs the switching control signal based on the driving switching control signal; a second driving element that drives a second internal node by receiving a second voltage based on the second driving control signal; and a second driving switching element that electrically connects the second internal node and the output node based on the driving switching control signal. Claim 16 An electronic device according to claim 15, wherein the first driving element and the first driving switching element are implemented as P-MOS transistors, and the second driving element and the second driving switching element are implemented as N-MOS transistors. Claim 17 An electronic device comprising: a first drive control signal generating circuit that generates a first drive control signal and a first drive switching control signal; a second drive control signal generating circuit that generates a second drive control signal; and a switching control signal driving circuit that drives a switching control signal to a first voltage based on the first drive control signal and the first drive switching control signal, or drives the switching control signal to a ground voltage based on the second drive control signal and the first drive switching control signal, depending on whether a power down mode is entered, wherein the first drive control signal and the first drive switching control signal are driven at different levels when the power down mode is performed. Claim 18 An electronic device according to claim 17, wherein the switching control signal driving circuit drives the switching control signal to the ground voltage based on the second driving control signal and the first driving switching control signal during a set interval when entering the power down mode, and drives the switching control signal to the second voltage based on the third driving control signal and the second driving switching control signal after the set interval, wherein the second voltage is set to a negative voltage. Claim 19 In claim 18, the switching control signal driving circuit comprises: a first driving element that drives a first internal node by receiving a first voltage based on the first driving control signal; a first driving switching element that electrically connects the first internal node and an output node that outputs the switching control signal based on the first driving switching control signal; a second driving element that drives a second internal node by receiving a ground voltage based on the second driving control signal; a second driving switching element that electrically connects the second internal node and the output node based on the first driving switching control signal; a third driving element that drives a third internal node by receiving a second voltage based on the third driving control signal; and a third driving switching element that electrically connects the third internal node and the output node based on the second driving switching control signal. Claim 20 An electronic device according to claim 19, wherein the first driving element and the first driving switching element are implemented as P-MOS transistors, and the second driving element, the second driving switching element, the third driving element, and the third driving switching element are implemented as N-MOS transistors.

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