Memory package, semiconductor device, and storage device

Abstract

A memory package according to one embodiment of the present invention includes a plurality of memory chips and an interface chip that mediates communication between a controller and the plurality of memory chips and receives a data signal and a RAW clock signal from the plurality of memory chips. The interface chip includes a delay circuit that outputs a delayed clock signal by applying an offset delay corresponding to half of a unit interval of the data signal and an additional delay to the RAW clock signal, and a sampler that samples the data signal synchronized with the output of the delay circuit. When the delayed clock signal and the data signal have a phase difference of the unit interval, the delay circuit outputs a clock signal to the sampler in which the offset delay is removed from the delayed clock signal.

Description

Technology Field

[0001] The present invention relates to a memory package, a semiconductor device, and a storage device. Background Technology

[0003] A memory package provides the function of writing and erasing data or reading written data in response to control signals received from an external host or controller, and may include one or more memory chips. To improve the communication speed of data exchange between the memory package and the external host or controller, a structure has been proposed that includes an interface chip implemented as a separate semiconductor chip from the memory chip. When an interface chip is connected between the host or controller and the memory chip, a method is required to eliminate skew between signals transmitted between the interface chip and the memory chip.

[0004] delete Prior art literature

[65535] Republic of Korea Published Patent Application No. 10-2018-0093648 (August 22, 2018) The problem to be solved

[0005] One of the objectives of the technical concept of the present invention is to provide a memory package, a semiconductor device, and a storage device capable of optimizing the phase difference between a data signal and a clock signal by effectively eliminating the skew of the data signal and clock signal exchanged between a semiconductor device, such as an interface chip, and a memory chip. means of solving the problem

[0007] A memory package according to one embodiment of the present invention comprises a plurality of memory chips and an interface chip that mediates communication between a controller and the plurality of memory chips and receives a data signal and a RAW clock signal from the plurality of memory chips, wherein the interface chip comprises a delay circuit that outputs a delayed clock signal by applying an offset delay corresponding to half of a unit interval of the data signal and an additional delay to the RAW clock signal, and a sampler that samples the data signal synchronized with the output of the delay circuit; wherein the delay circuit outputs a clock signal to the sampler in which the offset delay is removed from the delayed clock signal when the delayed clock signal and the data signal have a phase difference of the unit interval.

[0009] A semiconductor device according to one embodiment of the present invention comprises a plurality of receivers that output a data signal and a low clock signal received from at least one of a plurality of memory chips during a predetermined training interval to a first sampler, a delay fixed loop circuit that outputs a first delay code, a counter circuit that outputs a second delay code generated based on a signal detected at at least one of an input terminal and an output terminal of the first sampler, and a delay cell that outputs a delay clock signal to the first sampler by a delay amount determined according to the first delay code and the second delay code, wherein if the phase difference between the data signal and the delay clock signal corresponds to a unit interval of the data signal, the delay cell outputs a clock signal with the delay according to the first delay code removed to the first sampler.

[0011] A storage device according to one embodiment of the present invention comprises a controller that executes a predetermined training, a memory chip that outputs signals having the same phase through a DQ pad and a DQS pad respectively while the training is executed, a sampler connected between the controller and the memory chip that samples a first signal received through the DQ pad, and an interface chip including a delay circuit that delays a second signal received through the DQS pad and inputs it to the sampler, wherein the memory chip and the interface chip are included in a single package, and the delay circuit generates a first delay code corresponding to a first delay determined regardless of the phase difference between the first signal and the second signal detected at the input terminal of the sampler, and a second delay code corresponding to a second delay determined according to the phase difference between the first signal and the second signal detected at the input terminal of the sampler. Effects of the invention

[0013] According to one embodiment of the present invention, in order to eliminate skew between a data signal and a clock signal that a memory chip exchanges with another semiconductor device, an offset delay corresponding to half of a unit interval of the data signal and an additional delay set separately from the offset delay can be applied to the clock signal. If the clock signal to which the offset delay and the additional delay are applied has a phase difference of a unit interval with the data signal, the offset delay can be removed from the clock signal to minimize the skew between the data signal and the clock signal.

[0014] The various and beneficial advantages and effects of the present invention are not limited to those described above and will be more easily understood in the process of explaining specific embodiments of the present invention. Brief explanation of the drawing

[0016] FIG. 1 is a simplified block diagram of a storage device according to one embodiment of the present invention. FIG. 2 is a simplified block diagram of a memory device according to one embodiment of the present invention. FIGS. 3a, FIGS. 3b, FIGS. 4a, and FIGS. 4b are block diagrams simply illustrating an interface chip according to embodiments of the present invention. FIGS. 5 and 6 are flowcharts provided to explain the operation of a memory system according to embodiments of the present invention. FIG. 7 is a simple block diagram showing an interface chip according to one embodiment of the present invention. FIGS. 8 to 13 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention. FIGS. 14 to 19 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention. FIG. 20 is a simplified block diagram of an interface chip according to one embodiment of the present invention. FIGS. 21 to 25 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention. FIGS. 26 to 28 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention. FIG. 29 is a simplified drawing of a storage device according to one embodiment of the present invention. Specific details for implementing the invention

[0017] Hereinafter, preferred embodiments of the present invention are described as follows with reference to the attached drawings.

[0019] FIG. 1 is a simplified block diagram of a storage device according to one embodiment of the present invention.

[0020] Referring to FIG. 1, a storage device (1) according to one embodiment of the present invention may include a controller (10) and a memory package (20), etc. According to the embodiment, the storage device (1) may include two or more memory packages (20), and one controller (10) may control two or more memory packages (20).

[0021] The controller (10) can communicate with an external host to which the storage device (1) is connected, and in response to a command signal received from the host, read data stored in the memory package (20) and output it to the host, or store data received from the host within the memory package (20). According to an embodiment, the controller (10) may be mounted on a processor of the host, etc., rather than the storage device (1).

[0022] A memory package (20) may include an interface chip (21) and a plurality of memory chips (NVM, 22). The plurality of memory chips (22) are connected to the interface chip (21) through internal channels of the memory package (20), and, for example, two or more memory chips may be connected to a single internal channel. In one embodiment, each of the plurality of memory chips (22) may be a non-volatile memory device in which stored data is retained even when the power is cut off.

[0023] The interface chip (21) can mediate communication between the controller (10) and the plurality of memory chips (22). For example, the interface chip (21) can transmit a command signal, an address signal, etc. received from the controller (10) to at least one of the plurality of memory chips (22).

[0024] A program operation to store data in the controller (10) and the memory package (20), and / or a read operation to read data stored in the memory package (20), can be executed in synchronization with a predetermined clock signal. As the data rate between the controller (10) and the memory package (20) increases, the phases of the data signal and the clock signal exchanged between the controller (10) and the memory package (20) may need to be accurately aligned.

[0025] For example, if skew occurs in the phase difference between the data signal and the clock signal between the controller (10) and the interface chip (21), and / or between the interface chip (21) and the plurality of memory chips (22), the reliability of the storage device (1) may be reduced. Additionally, if the controller (10) side cannot determine whether the interface chip (21) is present inside the memory package (20), only the skew between the controller (10) and the interface chip (21) can be minimized during the training operation executed after power is supplied to the storage device (1). In this case, the skew between the interface chip (21) and the plurality of memory chips (22) increases, which may cause problems in the operation inside the memory package (20).

[0026] In one embodiment of the present invention, after power is supplied to the storage device (1), the phases of the data signal and the clock signal in the internal channels between the interface chip (21) and the plurality of memory chips (22) can be aligned to reduce skew. Alternatively, during a training operation performed by the controller (10) on the memory package (20), the phases of the data signal and the clock signal in the internal channels of the memory package (20) can be aligned to minimize skew occurring in the internal channels of the memory package (20) without a separate training time.

[0027] According to an embodiment, the memory package (20) may not include an interface chip (21). In this case, an operation to align the phases of the data signal and the clock signal and minimize skew may be performed within the controller (10).

[0029] FIG. 2 is a simplified block diagram of a memory device according to one embodiment of the present invention.

[0030] Referring to FIG. 2, the semiconductor device (30) may include a control logic circuit (32), a cell area (33), a page buffer section (34), a voltage generator (35), and a row decoder (36). The semiconductor device (30) may further include an interface circuit (31) and may also further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, a source driver, etc. The semiconductor device (30) may be a memory device for storing data, and, for example, may be a non-volatile memory device in which stored data is retained even when the power is cut off.

[0031] The control logic circuit (32) can control various operations within the semiconductor device (30) overall. The control logic circuit (32) can output various control signals in response to a command (CMD) and / or address (ADDR) received by the interface circuit (31). For example, the control logic circuit (32) can output a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR).

[0032] The cell region (33) may include a plurality of memory blocks (BLK1-BLKz) (where z is a positive integer), and each of the plurality of memory blocks (BLK1-BLKz) may include a plurality of memory cells. In one embodiment, the plurality of memory blocks (BLK1-BLKz) may be separated from one another by first separation regions comprising an insulating material, and second separation regions different from the first separation regions may be disposed inside each of the plurality of memory blocks (BLK1-BLKz). For example, each of the second separation regions may have a structure different from the first separation regions.

[0033] For example, a plurality of memory blocks (BLK1-BLKz) may include main blocks for storing data and at least one spare block for storing data necessary for the operation of the semiconductor device (30). The cell area (33) may be connected to the page buffer section (34) via bit lines (BL) and may be connected to the row decoder (36) via word lines (WL), string select lines (SSL), and ground select lines (GSL).

[0034] In an exemplary embodiment, the cell region (33) may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines stacked vertically on a substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference. In an exemplary embodiment, the cell region (33) may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0035] The page buffer unit (34) may include a plurality of page buffers (PB1-PBn) (where n is an integer greater than or equal to 3), and the plurality of page buffers (PB1-PBn) may each be connected to memory cells through a plurality of bit lines (BL). The page buffer unit (34) may select at least one bit line among the bit lines (BL) in response to a column address (Y-ADDR). The page buffer unit (34) may operate as a write driver or a sense amplifier depending on the operation mode. For example, during a program operation, the page buffer unit (34) may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer unit (34) may detect the current or voltage of the selected bit line to detect the data stored in the memory cell. Data to be programmed to the cell area (33) during a program operation and data read from the cell area (33) during a read operation may be input / output through the interface circuit (31).

[0036] The voltage generator (35) can generate various types of voltages for performing program, read, and erase operations based on the voltage control signal (CTRL_vol). For example, the voltage generator (35) can generate a program voltage, a read voltage, a pass voltage, a program verification voltage, an erase voltage, etc. In one embodiment, the control logic circuit (32) can control the voltage generator (35) to generate voltages for executing program, read, and erase operations using data stored in a spare block. Some of the voltages generated by the voltage generator (35) may be input to the word lines (WL) as word line voltages (VWL) by the row decoder (36), and some may be input to the common source line by the source driver.

[0037] The row decoder (36) can select one of a plurality of word lines (WL) and one of a plurality of string selection lines (SSL) in response to a row address (X-ADDR). For example, during a program operation, the row decoder (36) can apply a program voltage and a program verification voltage to the selected word line, and during a read operation, it can apply a read voltage to the selected word line.

[0039] FIGS. 3a, FIGS. 3b, FIGS. 4a, and FIGS. 4b are block diagrams simply illustrating an interface chip according to embodiments of the present invention.

[0040] First, referring to FIG. 3a, an interface chip (100) according to one embodiment of the present invention may include a delay circuit (110) and a sampler (120), etc. Additionally, the interface chip (100) may be connected to other external semiconductor devices through a plurality of pads (101-104). In one embodiment illustrated in FIG. 3, a first receiver (RX1) and a second receiver (RX2) may receive a signal from a memory chip through the first pad (101) and the second pad (102). Meanwhile, a third receiver (RX3) may receive a signal from a controller or host, etc., through the third pad (103), and a transmitter (TX) may transmit a signal to the memory chip through the fourth pad (104).

[0041] A controller or host connected to a memory package including an interface chip (100) may execute a predetermined training operation after power is supplied to the memory package. For example, the training operation may include ZQ training, DCC (Duty Cycle Correction) training, read training, and write training. To execute a DCC training operation that adjusts the duty ratio of a clock signal, the controller or external host may transmit a read enable signal (nRE) to the memory package.

[0042] The third receiver (RX3) of the interface chip (100) can receive a read enable signal through the third pad (103) and transmit the read enable signal to the memory chip through the fourth pad (104). The memory chip that receives the read enable signal can output a data signal and a raw clock signal to the interface chip (100) for DCC training. For example, the read enable signal may be a square wave signal having a predetermined frequency and duty ratio, and the interface chip (100) can receive the data signal through the first pad (101) and receive the raw clock signal through the second pad (102).

[0043] The sampler (120) of the interface chip (100) can output data by sampling the data signal at every rising edge and / or falling edge of the low clock signal. Thus, if the rising edge and / or falling edge of the low clock signal in the sampler (120) are accurately aligned within a unit interval of the data signal, the sampler (120) can accurately sample the data contained in the data signal without error.

[0044] In one embodiment, the data signal and the low clock signal output by the memory chip may have the same phase. Therefore, assuming there is no skew between the data signal and the low clock signal, the rising edge and / or falling edge of the low clock signal can be aligned within the unit interval of the data signal by applying a delay of half a unit interval to the low clock signal. However, even when receiving a data signal and a low clock signal having the same phase, skew may occur between the data signal and the low clock signal within the interface chip (100) due to differences in the transmission paths through which the data signal and the low clock signal are respectively transmitted within the interface chip (100). Therefore, if a delay of half a unit interval is applied to the low clock signal without considering the skew, the data signal and the low clock signal may be misaligned in the sampler (120), and consequently, an error may be included in the output of the sampler (120). As the data rate supported by the interface chip (100) increases, problems caused by misalignment of the data signal and the low clock signal may occur with a higher probability.

[0045] In order to solve the above problem, the delay circuit (110) can generate a clock signal that is accurately aligned with the data signal using a low clock signal. Accordingly, the skew between the data signal and the clock signal input to the sampler (120) can be minimized, and the sampler (120) can accurately sample and output the data included in the data signal.

[0046] The delay circuit (110) may include a delay fixed loop circuit (111), a delay cell (112), a counter circuit (113), a phase detector (114), etc. The delay fixed loop circuit (111) may output a first delay code to generate an offset delay of a fixed value by referring to a signal received by the third receiver (RX3), for example, a read enable signal. The phase detector (114) detects the phase difference between the data signal and the clock signal input to the sampler (110), and the counter circuit (113) may output a second delay code to generate an additional delay corresponding to the phase difference between the data signal and the clock signal by referring to the output of the phase detector (114). The delay cell (112) may apply at least one of the offset delay and the additional delay to the low clock signal and output a delayed clock signal to the sampler (120).

[0047] When a DCC training operation is initiated by a controller or host, the delay fixed loop circuit (111) may output a first delay code corresponding to an offset delay by referring to a read enable signal. For example, the read enable signal may be a square wave signal having a predetermined period and duty ratio, and the period of the read enable signal may be equal to the period of the data signal. The offset delay may correspond to half of a unit interval of the data signal.

[0048] The delay cell (112) can input the low clock signal to the sampler (110) by applying an offset delay to it. The phase detector (114) detects the phase difference between the data signal input to the sampler (110) and the delay clock signal output by the delay cell (112), and the counter circuit (113) can output a second delay code by referring to the phase difference detected by the phase detector (114). The delay cell (112) can apply an additional delay determined by the second delay code to the low clock signal.

[0049] Unlike an offset delay having a fixed value corresponding to half of a unit interval of a data signal, an additional delay may vary depending on the phase difference between the data signal input to the sampler (110) and the delay clock signal. For example, the counter circuit (113) and the phase detector (114) can determine the additional delay such that the delay clock signal, to which both the offset delay and the additional delay are applied, has a phase difference of one unit interval from the data signal.

[0050] When an additional delay is determined such that the data signal and the delayed clock signal have a phase difference equal to a unit interval of the data signal, the delay cell (112) can output a clock signal with the offset delay removed from the delayed clock signal to the sampler (110). For example, the delay fixed loop circuit (111) may stop the output of the first delay code, or the delay cell (112) may ignore the first delay code. Since the offset delay corresponding to half of the unit interval is removed at a phase difference equal to one unit interval of the data signal, the rising edge and / or falling edge of the clock signal output by the delay cell (112) can be accurately aligned within the unit interval of the data signal.

[0051] An interface chip (100A) according to one embodiment illustrated in FIG. 3b may further include a second delay cell (115) in the delay circuit (110A). Referring to FIG. 3b, the first delay cell (112) can adjust the phase of a clock signal input to a sampler (120), and the second delay cell (115) can adjust the phase of a data signal input to a sampler (120). For example, the delay circuit (110A) may operate similarly to a vernier type circuit.

[0052] For example, the delay circuit (110A) can adjust both the delay code output by the counter circuit (113) to the first delay cell (112) and the delay code output by the second delay cell (115) to adjust the phase difference between the data signal and the clock signal input to the sampler (120). For example, if the minimum delay adjustable in the first delay cell (112) is A and the minimum delay adjustable in the second delay cell (115) is B, which is different from A, the phase difference between the data signal and the clock signal input to the sampler (120) can be adjusted by the difference between A and B by individually adjusting the delay codes output by the counter circuit (113) to the first delay cell (112) and the second delay cell (115), respectively.

[0053] As previously explained with reference to FIG. 3a, the delay circuit (110A) can adjust the phase of the clock signal input to the sampler (120) and simultaneously adjust the phase of the data signal input to the sampler (120) so that the phases of the data signal and the clock signal in the sampler (120) can be accurately aligned.

[0054] For example, the phase difference between the data signal input to the first pad (101) and the low clock signal input to the second pad (102) may vary depending on the phase difference that is fundamentally present between the data signal output by the memory chip and the low clock signal, and the difference between the amount of delay present between the first pad (101) and the second delay cell (115) and the amount of delay present between the second pad (102) and the first delay cell (112) within the interface chip (100A). Depending on the phase difference between the data signal and the low clock signal, the phase difference between the data signal and the first delay clock signal, to which an offset delay is applied to the low clock signal, may be greater than 1UI.

[0055] In the above case, the first delay cell (112) may generate a negative additional delay so that the second delay clock signal, to which both the offset delay and the additional delay are applied to the low clock signal, has a phase difference of 1UI with the data signal. In one embodiment illustrated in FIG. 3b, in such a case, the second delay cell (115) can reduce the phase difference between the data signal and the low clock signal by reflecting a predetermined delay to the data signal. When the second delay cell (115) reflects a predetermined delay to the data signal, the operation to determine the additional delay may be restarted. For example, the phase difference existing in the output of the memory chip and the difference in the amount of delay due to the mismatch of signal paths inside the interface chip (100A) may be applied as a default delay. The default delay reflected in the data signal and the default delay reflected in the low clock signal each do not have a fixed value and may vary depending on the memory chip and the interface chip (100A), etc.

[0056] Next, referring to FIG. 4a, an interface chip (200) according to one embodiment of the present invention may include a delay circuit (210) and a sampler (220), etc. In addition, the configuration of a plurality of pads (201-204) and a transmit / receive circuit (RX1-RX3, TX) included in the interface chip (200) may be similar to one embodiment described above with reference to FIG. 3.

[0057] However, in one embodiment illustrated in FIG. 4a, the delay circuit (210) may include a delay fixed loop circuit (211), a delay cell (212), and a counter circuit (213). The delay fixed loop circuit (211) may output a first delay code by referencing a square wave signal input to the third pad (203), for example, a read enable signal. The delay cell (212) may generate an offset delay corresponding to half of a unit interval of the data signal by referencing the first delay code, and output a delay clock signal by applying the offset delay to a low clock signal received from the second pad (202).

[0058] The counter circuit (213) can detect the output of the sampler (220). The data signal may be a toggle signal that repeatedly transitions between a low level and a high level. Accordingly, depending on the phase difference between the data signal input to the sampler (220) and the delayed clock signal, a dithering phenomenon may occur in which the output of the sampler (220) does not stabilize at a single level. In one embodiment illustrated in FIG. 4a, it can be determined that the phases of the data signal and the delayed clock signal are aligned at the time when the output of the sampler (220) is dithering.

[0059] The counter circuit (213) outputs a second delay code, and the delay cell (212) can apply an additional delay to the low clock signal by referring to the second delay code. The phase difference between the data signal and the delay clock signal in the sampler (220) can be different due to the additional delay determined according to the second delay code. The delay circuit (210) can select an additional delay under conditions where dithering occurs in the signal output by the sampler (220). The delay clock signal, in which the selected additional delay is applied to the low clock signal along with the offset delay, can have a phase difference equal to a unit interval of the data signal compared to the data signal.

[0060] The delay circuit (210) can output a clock signal to the sampler (220) by applying only the selected additional delay to the low clock signal, excluding the offset delay. By removing the offset delay corresponding to half of the unit interval and applying only the selected additional delay to the low clock signal, the rising edge and / or falling edge of the clock signal can be accurately aligned within the unit interval of the data signal in the sampler (220).

[0061] An interface chip (200A) according to one embodiment illustrated in FIG. 4b may further include a second delay cell (214) in the delay circuit (210A). Referring to FIG. 4b, the first delay cell (212) can adjust the phase of a clock signal input to a sampler (220), and the second delay cell (214) can adjust the phase of a data signal.

[0062] As previously explained, the phase difference between the data signal input to the first pad (201) and the low clock signal input to the second pad (202) may vary depending on the phase difference present in the output of the memory chip, and the difference between the amount of delay between the first pad (201) and the second delay cell (214) and the amount of delay between the second pad (202) and the first delay cell (212). For example, depending on the phase difference between the data signal and the low clock signal, the phase difference between the first delay clock signal and the data signal, to which an offset delay is applied to the low clock signal, may be greater than 1UI.

[0063] Similar to the embodiment described with reference to FIG. 3b, the second delay cell (214) can reduce the phase difference between the data signal input to the delay circuit (210A) and the low clock signal by reflecting a predetermined delay in the data signal. After the second delay cell (214) reflects a predetermined delay in the data signal, an operation to determine an additional delay can be started again.

[0064] In one embodiment illustrated in FIG. 4b, the delay circuit (210A) can operate like a vernier type circuit. For example, in the delay circuit (210A), the counter circuit (213) can individually adjust the delay code input to each of the first delay cell (212) and the second delay cell (214). Accordingly, the phase difference between the data signal and the clock signal input to the sampler (220) can be finely adjusted by the difference between the minimum delay adjustable by the first delay cell (212) and the minimum delay adjustable by the second delay cell (214), and the phase difference between the data signal and the clock signal can be precisely matched.

[0066] According to an embodiment, the memory chip may be directly connected to an external host or controller without passing through an interface chip (100, 200). In this case, as described with reference to FIGS. 3 and 4, an operation to align the phases of the data signal and the clock signal may be executed within the host or controller. For example, the data signal and the low clock signal may be input to a sampler within the controller by a training command transmitted by the controller to the memory chip. The controller includes a delay circuit, and the delay circuit may apply an offset delay of half the unit interval of the data signal and an additional delay to the low clock signal.

[0067] As previously explained, the length of the additional delay can be determined so that the delayed clock signal, to which the additional delay and offset delay have been applied, has a phase difference equal to a unit interval of the data signal when compared to the data signal. Once the additional delay is determined, the delay circuit inside the controller inputs the clock signal, to which the offset delay has been removed from the delayed clock signal, into the sampler, thereby accurately positioning the rising edge and / or falling edge of the clock signal within a unit interval of the data signal.

[0069] FIGS. 5 and 6 are flowcharts provided to explain the operation of a memory system according to embodiments of the present invention.

[0070] FIG. 5 may be a flowchart for explaining the operation of a memory package including an interface chip according to an embodiment illustrated in FIG. 3. Referring to FIG. 3 and FIG. 5 together, a controller or host connected to a memory package according to an embodiment of the present invention may start DCC training (S10). DCC training is training for determining the duty ratio of a clock signal, and in one embodiment, it may be performed between ZQ training and lead training.

[0071] When DCC training begins, the interface chip (100) may execute an operation to eliminate skew between the data signal and the clock signal input to the sampler (120) independently of the DCC training. The controller or external host does not know whether the interface chip (100) is included in the memory package, and the interface chip (100) may execute an operation to eliminate skew between the data signal and the clock signal received from the memory chip during DCC training so that the data signal and the clock signal can be accurately aligned in the sampler (110) without separate training time. According to an embodiment, if the operation to eliminate skew between the data signal and the clock signal is not completed during the DCC training operation, the interface chip (100) may complete the operation to eliminate skew between the data signal and the clock signal while lead training is executed after the DCC training.

[0072] The sampler (120) of the interface chip (100) can receive a data signal and a low clock signal from at least one of the memory chips (S11). In step S11, the data signal and the low clock signal output by the memory chip may have the same phase. However, due to a delay occurring inside the interface chip (100), skew may occur between the data signal and the low clock signal input to the sampler (120).

[0073] The delay circuit (110) can generate a delayed clock signal by applying an offset delay to a low clock signal (S12). The offset delay is a delay determined by a delay fixed loop circuit (111) included in the delay circuit (110), and can correspond, for example, to half the time of a unit interval of a data signal. For example, the delay fixed loop circuit (111) of the delay circuit (110) can generate an offset delay using a read enable signal received from a controller or host while executing DCC training, and apply this to the low clock signal to generate a delayed clock signal.

[0074] When a delay clock signal is generated, the delay circuit (110) can determine whether the phase difference between the data signal and the delay clock signal is the same as the unit interval of the data signal (S13). If, as a result of the determination in step S13, the phase difference between the data signal and the delay clock signal is different from the unit interval of the data signal, an additional delay can be determined based on the phase difference between the data signal and the delay clock signal detected by the phase detector (113) (S14). For example, the additional delay may be a delay that must be additionally applied to the delay clock signal so that the phase difference between the data signal and the delay clock signal matches the unit interval of the data signal. The counter circuit (114) of the delay circuit (110) outputs a delay code corresponding to the additional delay to the delay cell (112), and the delay cell (112) can apply the additional delay to the delay clock signal (S15).

[0075] While the delayed clock signal with the offset delay and additional delay applied is input to the sampler (120), the delay circuit (110) can determine again whether the phase difference between the data signal and the delayed clock signal is the same as the unit interval of the data signal (S13). If the result of the determination in step S13 is that the phase difference between the data signal and the delayed clock signal is still different from the unit interval of the data signal, the additional delay can be determined again (S14) and applied to the delayed clock signal (S15).

[0076] On the other hand, if the phase difference between the data signal and the delayed clock signal is equal to the unit interval of the data signal as a result of the judgment in step S13, the delay circuit (110) can generate a clock signal by removing the offset delay from the delayed clock signal input to the sampler (120) (S16). The clock signal generated in step S16 may be a signal in which the delay existing inside the interface chip (100) and the additional delay generated by the delay cell (112) are applied to the low clock signal.

[0077] Under the condition that the phase difference between the delayed clock signal and the data signal is the unit interval of the data signal, the clock signal is generated by removing the offset delay from the delayed clock signal, so that the data signal and the clock signal can have a phase difference of half the unit interval of the data signal. Therefore, the rising edge and / or falling edge of the clock signal are accurately aligned within the unit interval of the data signal, and the skew between the data signal and the clock signal can be effectively eliminated. The clock signal is input to the sampler (120) (S17), and the sampler (120) can sample the data contained in the data signal by synchronizing with the clock signal.

[0079] FIG. 6 may be a flowchart for explaining the operation of a memory package including an interface chip according to an embodiment illustrated in FIG. 4. Referring to FIG. 4 and FIG. 6 together, a controller or host connected to a memory package according to an embodiment of the present invention may start DCC training (S20). When DCC training starts, the interface chip (200) may perform an operation to eliminate skew between a data signal input to a sampler (220) and a clock signal.

[0080] The sampler (220) of the interface chip (200) can receive a data signal and a low clock signal from at least one of the memory chips included in the memory package (S21). In step S21, the data signal and the low clock signal output by the memory chip may have the same phase. Due to a delay existing within the interface chip (200), skew may occur between the data signal and the low clock signal input to the sampler (220).

[0081] The delay circuit (210) can generate a delayed clock signal by applying an offset delay to the low clock signal (S22). Similar to what was previously explained with reference to FIG. 5, the offset delay is a fixed delay and can correspond to half the time of a unit interval of the data signal.

[0082] The delay circuit (210) applies an additional delay to the delay clock signal (S23), and the sampler (220) can sample the data signal by synchronizing with the delay clock signal output by the delay circuit (210). The delay circuit (210) can detect the output of the sampler (220). For example, the counter circuit (213) determines whether dithering occurs at the output of the sampler (220) after applying an additional delay to the delay clock signal (S24), and can determine whether to change the delay code that determines the additional delay based on the result of the determination.

[0083] If dithering does not occur at the output of the sampler (220) after applying an additional delay, the counter circuit (213) can change the delay code and output it to the delay cell (212). For example, in response to the delay code changed by the counter circuit (213), the delay cell (212) can increase the additional delay applied to the delay clock signal (S25). The delay cell (212) applies the changed additional delay to the delay clock signal (S23) and can determine again whether dithering occurs at the output of the sampler (220) (S25).

[0084] If dithering is detected in the output of the sampler as a result of the judgment in step S25, the delay circuit (210) can determine that the delayed clock signal with an additional delay applied has a phase difference of a unit interval with the data signal. Accordingly, the delay circuit (210) can generate a clock signal by removing the offset delay from the delayed clock signal (S27) and input the clock signal to the sampler (S28).

[0085] As described with reference to FIG. 5, under the condition that the delayed clock signal with additional delay and offset delay applied has a phase difference of a unit interval of the data signal and the data signal, the offset delay is removed from the delayed clock signal, so that the data signal and the clock signal can have a phase difference of half of the unit interval of the data signal. Therefore, the rising edge and / or falling edge of the clock signal are accurately aligned within the unit interval of the data signal, and the skew between the data signal and the clock signal can be effectively eliminated.

[0087] FIG. 7 is a simple block diagram showing an interface chip according to one embodiment of the present invention.

[0088] Referring to FIG. 7, the interface chip (300) may include a delay circuit (310) and a sampler (320), etc. The interface chip (300) is connected to other external semiconductor devices through a plurality of pads (301-304), and the plurality of pads (301-304) may be connected to a transmit / receive circuit (RX1-RX3, TX).

[0089] As previously explained, while a controller or host connected to the third pad (303) is executing a predetermined training operation, the interface chip (300) can eliminate the phase difference between the data signal (DIN) and the clock signal (CK) input to the sampler (320). The DQ signal received by the first receiver (RX1) from the memory chip may have a different phase from the data signal (DIN) input to the sampler (320). This may be due to a delay in the transmission path between the first pad (301) and the sampler (320) within the interface chip (300). Similarly, due to a delay in the transmission path between the second pad (302) and the sampler (320), the DQS signal input to the second pad (302) may have a different phase from the low clock signal (CKIN) input to the delay circuit (310).

[0090] A controller or host may transmit a predetermined control signal, for example, a read enable signal (nRE), to an interface chip (300) to execute a training operation. The interface chip (300) may output the read enable signal (nRE) to a memory chip and receive a DQ signal and a DQS signal.

[0091] The delay circuit (310) can generate a first delay (DL1) having a fixed value while the training operation is in progress by referencing the read enable signal (nRE). Additionally, the delay circuit (310) can generate a second delay (DL2) whose value varies depending on the condition, unlike the first delay (DL1). For example, the second delay (DL2) can be determined to a value optimized for eliminating skew between the data signal (DIN) and the clock signal (CK) input to the sampler (320). Hereinafter, the operation of the interface chip (300) will be described in more detail with reference to FIGS. 8 to 13.

[0093] FIGS. 8 to 13 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention.

[0094] First, referring to FIG. 8, the DQ signal may be a signal having a predetermined unit interval (UI), and the DQS signal may be a signal having the same phase as the DQ signal. In one embodiment, the duty ratio of the DQS signal may be 50%. The memory chip may generate and output the DQ signal and the DQS signal so that they have the same phase at the first pad (301) and the second pad (302).

[0095] As previously explained, the delay generated in the transmission path between the first pad (301) and the sampler (320) may differ from the delay generated in the transmission path between the second pad (302) and the sampler (320). Referring to FIG. 9, the first default delay (TDL1) existing in the transmission path between the first pad (301) and the sampler (320) may differ from the second default delay (TDL2) existing in the transmission path between the second pad (302) and the sampler (320). As previously explained, the first default delay (TDL1) and the second default delay (TDL2) may each differ depending on the mismatch existing in the transmission path within the interface chip (300), as well as the memory chip that outputs the DQ signal and DQS signal to the interface chip (300).

[0096] In one embodiment illustrated in FIG. 9, the second default delay (TDL2) may be greater than the first default delay (TDL1). The data signal (DIN) input to the sampler (320) may have a phase difference of the first default delay (TDL1) with the DQ signal, and the low clock signal (CKIN) input to the delay circuit (310) may have a phase difference of the second default delay (TDL2) with the DQS signal.

[0097] Next, referring to FIG. 10, the delay circuit (310) can generate a first delayed clock signal (CKDL1) by applying a first delay (DL1) to a low clock signal (CKIN). The first delay (DL1) can correspond to half of a unit interval (UI) of the data signal (DIN). For example, the delay fixed loop circuit (311) outputs a first delay code corresponding to the first delay (DL1) to the delay cell (312), and the delay cell (312) can apply the first delay (DL1) to the low clock signal (CKIN) by referring to the first delay code. Since the first delay (DL1) is additionally applied to the low clock signal (CKIN), the phase difference between the data signal (DIN) and the first delayed clock signal (CKDL1) can be greater than the phase difference between the data signal (DIN) and the low clock signal (CKIN).

[0098] The sampler (320) can sample the data signal (DIN) by synchronizing with the first delay clock signal (CKDL1). The phase detector (314) of the delay circuit (310) can detect the phase difference between the first delay clock signal (CKDL1) and the data signal (DIN) output by the delay cell (312). The counter circuit (313) can output a second delay code to the delay cell (312) by referring to the phase difference between the first delay clock signal (CKDL1) and the data signal (DIN). The delay cell (312) can generate a second delay (DL2) by referring to the second delay code and apply the second delay (DL2) to the first delay clock signal (CKDL1).

[0099] Referring to FIG. 11, the delay cell (312) can generate a second delay clock signal (CKDL2) by additionally applying a second delay (DL2) to the first delay clock signal (CKDL1). While the delay cell (312) outputs the second delay clock signal (CKDL2), the phase detector (314) can compare the phase difference between the data signal (DIN) and the second delay clock signal (CKDL2). If the phase difference between the data signal (DIN) and the second delay clock signal (CKDL2) is smaller than the unit interval (UI) of the data signal (DIN), the counter circuit (313) can change the second delay code to increase the second delay (DL2) and output it to the delay cell (312).

[0100] The second delay (DL2) can be adjusted until the phase difference between the second delay clock signal (CKDL2) and the data signal (DIN) becomes equal to the unit interval of the data signal (DIN), as illustrated in FIG. 12. Referring to FIG. 12, the second delay clock signal (CKDL2), to which the first delay (DL1) and the second delay (DL2) are applied to the low clock signal (CKIN), can have a phase difference with the data signal (DIN) equal to the unit interval of the data signal (DIN).

[0101] As illustrated in FIG. 12, when the second delay (DL2) is determined, the delay circuit (310) can output a clock signal (CK) to the sampler (320) by removing the first delay (DL1) from the second delay clock signal (CKDL2). Referring to FIG. 13, the delay cell (312) can generate a clock signal (CK) by removing the first delay (DL1) from the second delay clock signal (CKDL2). The clock signal (CK) can have a phase difference equal to the sum of the second default delay (TDL2) and the second delay (DL2) when compared with the DQS signal.

[0102] By removing the first delay (DL1) corresponding to half the time of the unit interval of the data signal (DIN) from the second delayed clock signal (CKDL2), which has a phase difference equal to the unit interval of the data signal (DIN) compared to the data signal (DIN), the rising edge or falling edge of the clock signal (CK) can be accurately aligned within the unit interval of the data signal (DIN). Accordingly, the skew of the data signal (DIN) and the clock signal (CK) input to the sampler (320) can be minimized, and the reliability of the interface chip (300) can be improved even in high-speed operation.

[0104] FIGS. 14 to 19 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention.

[0105] An interface chip according to an embodiment described with reference to FIGS. 14 to 19 can eliminate skew between a data signal input to a sampler and a clock signal by utilizing the output of a sampler. First, referring to FIG. 14, the DQ signal may be a signal having a predetermined unit interval (UI), and may be a toggle signal that transitions between a high level and a low level for each unit interval (UI). The memory chip can generate and output a DQ signal and a DQS signal so that they have the same phase at the first pad and the second pad.

[0106] As previously explained, the first default delay (TDL1) existing in the transmission path between the first pad and the sampler may be different from the second default delay (TDL2) existing in the transmission path between the second pad and the sampler. In one embodiment illustrated in FIG. 15, the first default delay (TDL1) may be greater than the second default delay (TDL2). When the first default delay (TDL1) is shorter than the second default delay (TDL2), the code determining the delay of the clock signal input to the sampler is updated, and the operation of comparing the phase difference between the data signal input to the sampler and the clock signal is repeated to match the phase of the data signal input to the sampler and the clock signal input to the sampler.

[0107] Next, referring to FIG. 16, the delay circuit can generate a first delay clock signal (CKDL1) by applying a first delay (DL1) to a low clock signal (CKIN). The first delay (DL1) can correspond to half of the unit interval (UI) of the data signal (DIN). The delay fixed loop circuit can output a first delay code to a delay cell that is necessary to generate a first delay (DL1) corresponding to half of the unit interval (UI) of the data signal (DIN) by using a read enable signal (nRE).

[0108] The delay circuit outputs a second delayed clock signal (CKDL2) to a sampler by applying a second delay (DL2) to a first delayed clock signal (CKDL1), while detecting the output of the sampler while the sampler is synchronized with the second delayed clock signal (CKDL2) and samples a data signal (DIN). For example, when a second delay (DL2) as shown in FIG. 17 is applied to the first delayed clock signal (CKDL1), the sampler can sample and output a data signal (DIN) on the rising edge of the second delayed clock signal (CKDL2).

[0109] In one embodiment, the delay circuit can detect the output of a sampler synchronized with the second delay clock signal (CKDL2) while gradually increasing the second delay (DL2). As the second delay (DL2) increases, and the rising edge of the second delay clock signal (CKDL2) aligns with the falling edge of the data signal (DIN) as illustrated in FIG. 18, the output of the sampler can be changed from a high logic value to a low logic value. In this way, the delay circuit can determine the second delay (DL2) under conditions where the second delay clock signal (CKDL2) and the data signal (DIN) have a phase difference equal to a unit interval (UI) of the data signal (DIN).

[0110] As illustrated in FIG. 18, when the second delayed clock signal (CKDL2), to which the second delay (DL2) is additionally applied, has a phase difference equal to the unit interval (UI) of the data signal (DIN), the delay circuit can generate a clock signal (CK) by removing the first delay (DL1) from the second delayed clock signal (CKDL2). The clock signal (CK) can have a phase difference equal to the sum of the second default delay (TDL2) and the second delay (DL2) when compared with the DQS signal.

[0111] Referring to FIG. 19, the first delay (DL1) corresponding to half the time of the unit interval of the data signal (DIN) is removed from the second delayed clock signal (CKDL2), which has a phase difference equal to the unit interval of the data signal (DIN) when compared with the data signal (DIN), so that the rising edge or falling edge of the clock signal (CK) can be accurately aligned within the unit interval of the data signal (DIN). Accordingly, the skew of the data signal (DIN) and the clock signal (CK) input to the sampler is minimized, and the reliability of the interface chip can be improved even at high speeds.

[0113] FIG. 20 is a simplified block diagram of an interface chip according to one embodiment of the present invention.

[0114] Referring to FIG. 20, an interface chip (400) according to one embodiment of the present invention may include a delay circuit (410), a first sampler (420), a second sampler (430), etc. The interface chip (400) may be connected to other external semiconductor devices through a plurality of pads (401-405). In one embodiment illustrated in FIG. 20, a first receiver (RX1) may receive a DQ signal from a memory chip through a first pad (401). A second receiver (RX2) may receive a DQS signal through a second pad (402), and a third receiver (RX3) may receive a DQSB signal through a third pad (403). A fourth receiver (RX4) may receive a signal from a controller or host, etc., through a fourth pad (404), and a transmitter (TX) may transmit a signal to a memory chip through a fifth pad (405).

[0115] The DQS signal and the DQSB signal may have a phase difference of 180 degrees. In other words, the DQSB signal may be a complementary signal of the DQS signal. The first sampler (420) may sample the data signal (DIN) by synchronizing with the clock signal (CK) generated by the DQS signal, and the second sampler (430) may sample the data signal (DIN) by synchronizing with the complementary clock signal (CKB) generated by the DQSB signal.

[0116] The delay circuit (410) may include a delay fixed loop circuit (411), a delay cell (412), a counter circuit (413), a phase detector (414), an operation circuit (415), etc. The delay fixed loop circuit (411) may output a first delay code for generating a first delay (DL1) by referring to a signal received by the fourth receiver (RX4) from a controller or host, for example, a read enable signal. The first delay (DL1) may be determined regardless of the phase difference between the DQ signal and the DQS signal.

[0117] The phase detector (414) can detect the phase difference between the data signal (DIN) and the clock signal (CK) and the phase difference between the data signal (DIN) and the complementary clock signal (CKB). The counter circuit (413) can output a second delay code necessary to generate a second delay (DL2) by referring to the output of the phase detector (414).

[0118] In one embodiment illustrated in FIG. 20, skew control between the data signal (DIN) and the clock signal (CK) and skew control between the data signal (DIN) and the complementary clock signal (CKB) can be performed sequentially. For example, skew control between the data signal (DIN) and the clock signal (CK) can be performed first, and then skew between the data signal (DIN) and the complementary clock signal (CKB) can be controlled. Alternatively, skew between the data signal (DIN) and the complementary clock signal (CKB) can be controlled first, and then skew between the data signal (DIN) and the clock signal (CK) can be controlled.

[0119] When a training operation is initiated by a controller or host, the delay fixed loop circuit (411) may output a first delay code corresponding to a first delay (DL1) by referring to a read enable signal (nRE). For example, the first delay (DL1) may correspond to half of a unit interval of a data signal.

[0120] The delay circuit (410) can first adjust the skew of the clock signal (CK) generated by the DQS signal and the data signal (DIN). As previously described, the delay circuit (410) generates a delayed clock signal by applying a first delay (DL1) and a second delay (DL2) to the low clock signal (CKIN), and can set the second delay (DL2) so that the delayed clock signal has a phase difference equal to the unit interval between the data signal (DIN) and the data signal (DIN). When the second delay (DL2) is set, the delay circuit (410) can determine the phase of the clock signal (CK) by removing the first delay (DL1) from the delayed clock signal.

[0121] In one embodiment illustrated in FIG. 20, when the phase of the clock signal (CK) is determined, the interface chip (400) can adjust the phase of the complementary clock signal (CKB) to minimize the skew between the complementary clock signal (CKB) and the data signal (DIN). Hereinafter, with reference to FIGS. 21 to 25, the operation of adjusting the phase of the complementary clock signal (CKB) to minimize the skew between the complementary clock signal (CKB) and the data signal (DIN) will be described.

[0123] FIGS. 21 to 25 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention.

[0124] Referring to FIG. 21, the DQ signal may be a signal having a predetermined unit interval (UI), and the DQSB signal may be a signal having an opposite phase to the DQ signal. The memory chip may output a DQS signal having the same phase as the DQ signal and output a DQSB signal having an opposite phase to the DQ signal.

[0125] The first default delay (TDL1) generated in the transmission path between the first pad (401) and the second sampler (430) may be different from the second default delay (TDL2) generated in the transmission path between the third pad (403) receiving the DQSB signal and the second sampler (430). In one embodiment illustrated in FIG. 22, the first default delay (TDL1) may be smaller than the second default delay (TDL2).

[0126] Referring to FIG. 23, the delay circuit (410) can generate a first complementary delayed clock signal (CKBDL1) by applying a first delay (DL1) to a complementary low clock signal (CKBIN). The first delay (DL1) may correspond to half of a unit interval (UI) of a data signal (DIN). For example, the delay fixed loop circuit (411) outputs a first delay code corresponding to the first delay (DL1) to a delay cell (412), and the delay cell (412) may apply the first delay (DL1) to the complementary low clock signal (CKBIN) by referring to the first delay code. As the first delay (DL1) is applied, the phase difference between the data signal (DIN) and the first complementary delayed clock signal (CKBDL1) may become greater than the phase difference between the data signal (DIN) and the complementary low clock signal (CKBIN).

[0127] The second sampler (430) can sample the data signal (DIN) while the delay cell (412) outputs the first complementary delay clock signal (CKBDL1) and synchronizes with the first complementary delay clock signal (CKBDL1). The phase detector (414) can detect the phase difference between the first complementary delay clock signal (CKBDL1) output by the delay cell (412) and the data signal (DIN). The counter circuit (413) can output a second delay code to the delay cell (412) by referencing the phase difference between the first complementary delay clock signal (CKBDL1) and the data signal (DIN). The delay cell (412) can generate a second delay (DL2) by referencing the second delay code and apply the second delay (DL2) to the first complementary delay clock signal (CKBDL1).

[0128] Referring to FIG. 24, the delay cell (412) can generate a second complementary delay clock signal (CKBDL2) by additionally applying a second delay (DL2) to the first complementary delay clock signal (CKBDL1). The delay circuit (410) can adjust the value of the second delay (DL2) so that the falling edge of the second complementary delay clock signal (CKBDL2) matches the rising edge of the data signal (DIN).

[0129] As illustrated in FIG. 24, when the phase difference between the second complementary delay clock signal (CKBDL2) and the data signal (DIN) becomes equal to the unit interval of the data signal (DIN), the delay circuit can remove the first delay (DL1) from the second complementary delay clock signal (CKBDL2). Referring to FIG. 25, the delay cell (412) can generate a complementary clock signal (CKB) by removing the first delay (DL1) from the second complementary delay clock signal (CKBDL2). The complementary clock signal (CKB) can have a phase difference equal to the sum of the second default delay (TDL2) and the second delay (DL2) when compared with the DQSB signal received by the third pad (403).

[0130] By removing the first delay (DL1) corresponding to half the time of the unit interval of the data signal (DIN) from the second complementary delay clock signal (CKBDL2), which has a phase difference equal to the unit interval of the data signal (DIN) compared to the data signal (DIN), the rising edge or falling edge of the complementary clock signal (CKB) can be accurately aligned within the unit interval of the data signal (DIN). Accordingly, the skew of the data signal (DIN) and the complementary clock signal (CKB) input to the second sampler (430) can be minimized, and the reliability of the interface chip (400) can be improved even in high-speed operation.

[0131] In one embodiment of the present invention, the phases of the DQS signal and the DQSB signal received by the interface chip (400) can be individually adjusted. In an actual operating environment, the duty ratio of the DQS signal and the DQSB signal input to the interface chip (400) may not be set to exactly 50%. For example, the duty ratio of the DQS signal may be set to a value greater than 50%, and the duty ratio of the DQSB signal may be set to a value less than 50%.

[0132] In this case, the second delay (DL2) for the DQS signal and the second delay (DL2) for the DQSB signal may have different values. In an interface chip (400) according to one embodiment of the present invention, considering the difference in duty ratio between the DQS signal and the DQSB signal, the average value of the second delay (DL2) for the DQS signal and the second delay (DL2) for the DQSB signal may be calculated and the average value may be applied to the DQS signal and the DQSB signal. Hereinafter, the explanation will be described with reference to FIGS. 26 to 28.

[0134] FIGS. 26 to 28 are drawings for explaining the operation of an interface chip according to an embodiment of the present invention.

[0135] Referring to FIG. 26, the DQ signal may be a signal having a predetermined unit interval (UI), and the DQS signal and the DQSB signal may have opposite phases to each other. The DQ signal and the DQS signal may have the same phase. The duty ratio of the DQ signal may be 50%, the duty ratio of the DQS signal may be less than 50%, and the duty ratio of the DQSB signal may be greater than 50%.

[0136] The DQ signal can be delayed by a first default delay (TDL1) existing in the transmission path within the interface chip and input as a data signal (DIN) to the first sampler and the second sampler. Meanwhile, the DQS signal can be delayed by a first clock delay (CDL1) by a delay cell of the interface chip and input as a delayed clock signal (CKIN) to the first sampler. The DQSB signal can be delayed by a second clock delay (CDL2) by a delay cell and input as a complementary delayed clock signal (CKBIN) to the second sampler.

[0137] A method for determining each of the first clock delay (CDL1) and the second clock delay (CDL2) can be understood by referring to one of the embodiments described above. For example, by applying an offset delay equal to half of the unit interval (UI) of the DQ signal and an additional delay to the DQS signal, a signal having a phase difference of the unit interval (UI) with the data signal (DIN) can be generated. A delay cell included in the interface chip can generate a signal having a phase difference of the unit interval (UI) with the data signal (DIN) by referring to a first delay code corresponding to the offset delay and a second delay code corresponding to the additional delay, and by removing the offset delay from the generated signal, generate a delayed clock signal (CKIN) with minimized skew with the data signal (DIN). The first clock delay (CDL1) can correspond to the sum of the additional delay corresponding to the second delay code and the delay existing in the transmission path through which the DQS signal is transmitted within the interface chip.

[0138] The second clock delay (CDL2) can also be determined in a manner similar to the first clock delay (CDL1). A delay cell included in the interface chip can generate a signal having a phase difference of a unit interval (UI) with respect to the data signal (DIN) by referencing a first delay code corresponding to the offset delay and a third delay code corresponding to the additional delay, and can generate a complementary delayed clock signal (CKBIN) with minimized skew with the data signal (DIN) by removing the offset delay from the generated signal. The third delay code may be the same as or different from the second delay code. For example, the second clock delay (CDL2) may correspond to the sum of the additional delay corresponding to the third delay code and the delay existing in the transmission path through which the DQS signal is transmitted within the interface chip.

[0139] However, since the duty ratios of the DQS signal and the DQSB signal are different, the first clock delay (CDL1) and the second clock delay (CDL2) may also be different. In one embodiment of the present invention, an arithmetic circuit included in the interface chip may calculate the average code of the second delay code and the third delay code, and generate a clock signal (CK) and a complementary clock signal (CKB) using a delay (ADL) corresponding to the average code. Referring to FIG. 28, a delay (ADL) corresponding to the average code may be applied to both the clock signal (CK) and the complementary clock signal (CKB). The delay (ADL) corresponding to the average code may be smaller than the first clock delay (CDL1) and larger than the second clock delay (CDL2).

[0141] FIG. 29 is a simplified drawing of a storage device according to one embodiment of the present invention.

[0142] FIG. 29 is a diagram illustrating an exemplary storage device (500) according to an embodiment of the present invention, wherein the storage device (500) may include a memory package (510) and a controller (520), etc. The memory package (510) includes an interface chip (511) and a plurality of memory chips (NVM1-NVM8), and the plurality of memory chips (NVM1-NVM8) may be stacked together.

[0143] Referring to FIG. 29, a memory package (510) and a controller (520) can be mounted on a circuit board (501). The controller (520) can be connected to an interface chip (511) included in the memory package (510) through wiring inside the board (501). The interface chip (511) and the controller (520) can exchange signals with each other through a channel (CH) provided by the wiring of the board (501).

[0144] In a memory package (510), multiple memory chips (NVM1-NVM8) connected to an interface chip (511) can be divided into multiple groups. For example, first to fourth memory chips (NVM1-NVM4) connected to the interface chip (511) through a first internal channel (ICH1) can be divided into a first group, and fifth to eighth memory chips (NVM5-NVM8) connected to the interface chip (511) through a second internal channel (ICH2) can be divided into a second group.

[0145] In one embodiment illustrated in FIG. 29, the 5th to 8th memory chips (NVM5-NVM8) included in the second group are shown being placed on top of the 1st to 4th memory chips (NVM1-NVM4) included in the first group, but this is not necessarily limited to this form. Also, in FIG. 29, the interface chip (511) is shown being placed on one side of the memory chips (NVM1-NVM8), but alternatively, the interface chip (511) may be stacked together with the memory chips (NVM1-NVM8).

[0146] Referring to FIG. 29, memory chips (NVM1-NVM8) and interface chip (511) can be connected to each other through internal channels (ICH1, ICH2) provided by wires. However, this is only one embodiment, and memory chips (NVM1-NVM8) and interface chip (511) may also be connected to each other by via structures penetrating memory chips (NVM1-NVM8) and interface chip (511).

[0147] When power is supplied to the storage device (500) and operation begins, the controller (520) can execute a training operation for the memory package (510). The training operation may include ZQ training, DCC training, read training, and write training. While the memory package (510) executes the DCC training operation under the control of the controller (520), the interface chip (511) can eliminate skew of data signals and clock signals received from memory chips (NVM1-NVM8) through internal channels (ICH1, ICH2).

[0148] According to the embodiment, if the skew of the data signal and clock signal is not removed and the phase is not optimized while executing the DCC training operation, an additional operation to remove the skew of the data signal and clock signal may be executed while executing the lead training operation. As previously described, while removing the skew of the data signal and clock signal within the interface chip (511), the memory chips (NVM1-NVM8) may output a DQ signal that transitions between high and low levels in unit intervals through internal channels (ICH1, ICH2).

[0149] The interface chip (511) includes a sampler that samples a data signal synchronized with a clock signal, and can adjust the phase of the clock signal so that the skew between the data signal and the clock signal is minimized in the sampler. For example, an offset delay and an additional delay can be applied to the clock signal to generate a delayed clock signal, and the additional delay can be adjusted so that the delayed clock signal has a phase difference of a unit interval between the data signal and the data signal. When the additional delay is adjusted so that the delayed clock signal has a phase difference of a unit interval between the data signal and the data signal, the signal obtained by removing the offset delay from the delayed clock signal can be determined as the clock signal and output to the sampler. The offset delay can correspond to half of the unit interval of the data signal. Thus, in the above manner, the rising edge and / or falling edge of the clock signal can be accurately positioned near the center of the unit interval of the data signal.

[0151] The present invention is not limited by the embodiments described above and the attached drawings, but is intended to be limited by the appended claims. Accordingly, various substitutions, modifications, and changes may be made by those skilled in the art within the scope of the technical concept of the present invention as described in the claims, and such are also to be considered to fall within the scope of the present invention. Explanation of the symbols

[0153] 1: Storage device 10: Controller 20: Memory Package 21, 100, 200, 300, 400: Interface chips 22: Memory chip 110, 210, 310, 410: Delay circuit 120, 220, 320: Sampler 420: 1st Sampler 430: 2nd Sampler 111, 211, 311, 411: Delay-locked loop circuits 112, 212, 312, 412: Delayed cells 113, 213, 313, 413: Counter circuit 114, 314, 414: Phase detector

Claims

Claim 1 A memory package comprising: a plurality of memory chips; and an interface chip that mediates communication between a controller and the plurality of memory chips and receives a data signal and a RAW clock signal from the plurality of memory chips; wherein the interface chip includes: a delay circuit that outputs a delayed clock signal by applying an offset delay corresponding to half of a unit interval of the data signal and an additional delay to the RAW clock signal; and a sampler that samples the data signal synchronized with the output of the delay circuit; wherein the delay circuit outputs a clock signal obtained by removing the offset delay from the delayed clock signal to the sampler when the delayed clock signal and the data signal have a phase difference of the unit interval. Claim 2 A memory package according to claim 1, wherein the delay circuit comprises: a delay fixed loop circuit that outputs a first delay code corresponding to the offset delay; a counter circuit that outputs a second delay code corresponding to the additional delay; and a delay cell that applies the offset delay and the additional delay to the low clock signal based on the first delay code and the second delay code, and outputs the clock signal by applying only the additional delay to the low clock signal when the delay clock signal and the data signal have a phase difference of the unit interval. Claim 3 In paragraph 2, the delay circuit further comprises a phase detector that detects the phase difference between the data signal input to the input terminal of the sampler and the delay clock signal; and the counter circuit determines the additional delay based on the output of the phase detector, a memory package. Claim 4 In paragraph 2, the counter circuit determines the additional delay based on the output of the sampler while the data signal and the delay clock signal are input to the sampler, in a memory package. Claim 5 In claim 1, the additional delay is smaller than the offset delay, in a memory package. Claim 6 A memory package according to claim 1, wherein the data signal and the row clock signal have a default delay, and the sum of the default delay and the additional delay corresponds to 1 / 2 of the unit interval. Claim 7 A memory package according to claim 1, wherein the low clock signal is a data strobe signal. Claim 8 A memory package according to claim 1, wherein the data signal is a toggle signal that repeatedly transitions between a high level and a low level in each unit interval. Claim 9 In claim 8, during the DCC (Duty Cycle Correction) training interval, the plurality of memory chips output the data signal as the toggle signal, a memory package. Claim 10 A memory package according to claim 9, wherein, during at least a portion of the Read training section following the DCC training section, the plurality of memory chips output the data signal as the toggle signal. Claim 11 A semiconductor device comprising: a plurality of receivers that output a data signal and a low clock signal received from at least one of a plurality of memory chips to a first sampler during a predetermined training interval; a delay-locked loop circuit that outputs a first delay code; a counter circuit that outputs a second delay code generated based on a signal detected at at least one of the input terminal and output terminal of the first sampler; and a delay cell that outputs a delayed clock signal to the first sampler by a delay amount determined according to the first delay code and the second delay code; wherein the delay cell outputs a clock signal with the delay according to the first delay code removed to the first sampler when the phase difference between the data signal and the delayed clock signal corresponds to a unit interval of the data signal. Claim 12 A semiconductor device according to claim 11, further comprising: a phase detector that detects the phases of the data signal and the delay clock signal, respectively, at the input terminal of the first sampler and transmits them to the counter circuit. Claim 13 A semiconductor device according to claim 11, wherein the counter circuit is connected to the output terminal of the first sampler, and the second delay code is determined by referring to the signal output by the first sampler while the first sampler is synchronized with the delay clock signal and samples the data signal. Claim 14 A semiconductor device according to claim 13, wherein while the first sampler is synchronized with the delay clock signal and samples the data signal, the signal output by the first sampler is a toggle signal that repeatedly transitions between a high level and a low level. Claim 15 A semiconductor device according to claim 11, wherein the delay determined according to the first delay code corresponds to 1 / 2 of the unit interval of the data signal. Claim 16 A semiconductor device according to claim 11, wherein the delay determined according to the second delay code is smaller than half of the unit interval of the data signal. Claim 17 A semiconductor device according to claim 11, wherein the plurality of receivers output the data signal and a complementary low clock signal having a phase difference of 180 degrees with respect to the low clock signal to a second sampler different from the first sampler, and the delay cell outputs a complementary delayed clock signal to the second sampler by delaying the complementary low clock signal by a delay determined according to the first delay code and the third delay code, and when the data signal and the complementary delayed clock signal have the same phase, outputs a complementary clock signal with the delay according to the first delay code removed to the second sampler. Claim 18 A semiconductor device according to claim 17, wherein the second delay code and the third delay code are different from each other, and the delay cell outputs the clock signal and the complementary clock signal using a delay according to an average code corresponding to the average of the second delay code and the third delay code. Claim 19 A storage device comprising: a controller that sequentially executes a plurality of training operations; a memory chip that outputs signals having the same phase through a DQ pad and a DQS pad, respectively, while at least one of the training operations is executed; an interface chip connected between the controller and the memory chip, comprising a sampler that samples a first signal received through the DQ pad, and a delay circuit that delays a second signal received through the DQS pad and inputs it to the sampler; wherein the memory chip and the interface chip are included in a single package, and the delay circuit generates a first delay code corresponding to a first delay determined regardless of the phase difference between the first signal and the second signal detected at the input terminal of the sampler, and a second delay code corresponding to a second delay determined according to the phase difference between the first signal and the second signal detected at the input terminal of the sampler. Claim 20 In claim 19, the storage device wherein the first delay is determined according to the period of the read enable signal transmitted by the controller to the interface chip during the execution of the training.

Images