Semiconductor module and method of manufacturing the same, electronic device, electronic module, and method of manufacturing the electronic device

Abstract

A method for manufacturing a semiconductor module involves sealing a first die having a first die electrode, a second die having a second die electrode, a first connection part connected to the first die electrode, and a second connection part connected to the second die electrode by means of a sealant, and then mounting a bridge having a first bridge electrode and a second bridge electrode on a structure sealed by the sealant. The first die and the second die (42) are electrically connected through the bridge.

Description

Technology Field

[0001] The present invention relates to a semiconductor module and a method for manufacturing the same. Background Technology

[0002] There is a technology for connecting multiple IC (Integrated Circuit) chips. For example, Patent Document 1 describes a semiconductor package in which two IC chips are connected by a bridge (nested component) molded together with an interposer. Patent Document 2 describes a semiconductor package in which two IC chips are electrically connected through a bridge formed integrally with the interposer through an underfill material. Prior art literature

[0003] Specification of U.S. Patent Application Publication No. 2021 / 0005542 Specification of U.S. Patent Application Publication No. 2020 / 0395313 The problem to be solved

[0004] As a result of examining a semiconductor package having multiple IC chips connected via a bridge, or a semiconductor module using the same, the inventors of the present invention found that there is room for improvement in said semiconductor package or semiconductor module. For example, when two IC chips are electrically connected via a bridge integrated with an interposer, it is difficult to align the positions of the respective terminals of the two IC chips and the bridge terminals with high precision. In this case, the high-density of the terminal portion electrically connecting the IC chips and the bridge is constrained.

[0005] The present invention was made in this context, and one of its exemplary objectives is to provide a technology that enables the coupling of IC chips and bridges at a higher density. means of solving the problem

[0006] A method for manufacturing a semiconductor module according to one embodiment comprises: (a) forming a first connection portion including a first pillar-shaped connection portion extending outwardly from the first surface and a second connection portion including a second pillar-shaped connection portion extending outwardly from the first surface on a first surface of a first support; (b) preparing a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip and a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, and mounting each of the first semiconductor die and the second semiconductor die on the first support such that the first die electrode is disposed on the first connection portion and the second die electrode is disposed on the second connection portion; (c) after the process of (b), sealing the first semiconductor die, the second semiconductor die, the first connection portion and the second connection portion by a first sealing body; (d) after the process of (c), removing the first support, and also a part of the first pillar-shaped connection portion and The method comprises: a process of exposing a portion of each of the second pillar-shaped connection portions from the first seal; (e) preparing a bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, and, after the process (d), mounting the bridge on a structure sealed with the first seal, such that the first bridge electrode is placed on the first pillar-shaped connection portion and the second bridge electrode is placed on the second pillar-shaped connection portion.

[0007] A method for manufacturing a semiconductor module in another embodiment comprises: (a) forming a first insulating layer on a first surface of a first support, and then forming a first opening and a second opening in the first insulating layer; (b) forming a first connection portion including a first pillar-shaped connection portion formed within the first opening and a second connection portion including a second pillar-shaped connection portion formed within the second opening; (c) preparing a first semiconductor die having a first IC chip, a first die electrode connected to the first IC chip, and a second insulating layer sealing the first die electrode, and a second semiconductor die having a second IC chip, a second die electrode connected to the second IC chip, and a third insulating layer sealing the second die electrode, wherein the first die electrode is disposed on the first connection portion and the second die electrode is disposed on the second connection portion, and each of the first semiconductor die and the second semiconductor die is mounted on the first support; and (d) after the process of (c), the first semiconductor die and the second semiconductor The method comprises: (e) a process of sealing a die by a first sealing body; (e) after the process of (d), removing the first support and exposing a portion of the first pillar-shaped connection part and a portion of the second pillar-shaped connection part, respectively, from the first insulating layer; (f) a process of preparing a bridge including a first bridge electrode connected to the first connection part and a second bridge electrode connected to the second connection part, and after the process of (e), mounting the bridge on a structure sealed by the first sealing body such that the first bridge electrode is disposed on the first pillar-shaped connection part and the second bridge electrode is disposed on the second pillar-shaped connection part. In the process of (c), the first insulating layer and the second insulating layer are bonded to each other, and the first die electrode is sealed by the first insulating layer and the second insulating layer.In the above process (c), the first insulating layer and the third insulating layer are joined together, and the second die electrode is sealed by the first insulating layer and the third insulating layer.

[0008] A semiconductor module of another embodiment comprises a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, a first connection part electrically connected to the first die electrode, a second connection part electrically connected to the second die electrode, a bridge having a first bridge electrode connected to the first connection part and a second bridge electrode connected to the second connection part, and a first sealing body that seals the first semiconductor die and the second semiconductor die. The first connection part includes a first pillar-shaped connection part disposed between the first semiconductor die and the bridge and extending in a direction from one side of the first semiconductor die and the bridge to the other side. The first connection part includes a second pillar-shaped connection part disposed between the first semiconductor die and the bridge and extending in a direction from one side of the first semiconductor die and the bridge to the other side. The first bridge electrode and the second bridge electrode are exposed from the first sealing body. Each of the first column-shaped connecting part and the second column-shaped connecting part is sealed in the first seal.

[0009] Another embodiment of the present invention relates to an electronic device. The electronic device comprises a first die having a first electrode, a second die having a second electrode, a first connection part electrically connected to the first electrode, a second connection part electrically connected to the second electrode, and a bridge electrically connected to the first connection part and the second connection part. The first connection part has a pillar-shaped connection part extending from the bridge to the first die.

[0010] Another embodiment of the present invention relates to an electronic module. The electronic module comprises a wiring layer in which the electronic device and wiring are installed internally, and a pillar-shaped connection portion that electrically connects the wiring and the electronic device.

[0011] Another embodiment of the present invention relates to a method for manufacturing an electronic device. The method for manufacturing an electronic device comprises a forming process in which a first connection part and a second connection part are formed on a support, the first connection part having a columnar shape protruding from the support; a die joining process in which a first electrode having a first die is joined to the first connection part and a second electrode having a second die is joined to the second connection part; a sealing process in which the first die, the second die, and the first connection part are sealed with a resin; and a bridge joining process in which a bridge is joined to the lower part of the first connection part and the lower part of the second connection part.

[0012] In addition, any combination of the above components and a conversion of the expression of the present invention among methods, devices, systems, recording media, computer programs, etc., are also valid as forms of the present invention. Effects of the invention

[0013] According to the above embodiment, the IC chip and the bridge can be combined at a higher density. Brief explanation of the drawing

[0014] Figure 1 is a schematic diagram of a chip integrated system according to one embodiment. FIG. 2 is a perspective view showing an example of the configuration of the chip integrated circuit shown in FIG. 1. Figure 3 is an explanatory diagram showing an example of the configuration of the chip integrated circuit shown in Figure 2. FIG. 4 is an enlarged cross-sectional view showing an example of the configuration of a part of the chip integrated module shown in FIG. 3. Figure 5 is an explanatory diagram schematically illustrating an example of the configuration of the optical module shown in Figure 3. FIG. 6 is an explanatory diagram showing an overview of a method for manufacturing a chip integrated module, which is a review example of one embodiment. Figure 7 is an explanatory diagram showing an overview of the manufacturing process of the chip integrated module shown in Figure 4. FIG. 8 is an enlarged cross-sectional view showing the details of the connection part formation process shown in FIG. 7. FIG. 9 is an enlarged cross-sectional view showing the details of the connection part formation process following FIG. 8. FIG. 10 is an enlarged cross-sectional view showing the details of the connection part formation process following FIG. 9. FIG. 11 is an enlarged cross-sectional view showing details of the connection part formation process following FIG. 10. FIG. 12 is an enlarged cross-sectional view showing the details of the connection part formation process following FIG. 11. FIG. 13 is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in FIG. 7. FIG. 14 is an enlarged cross-sectional view showing details of the semiconductor die mounting process following FIG. 13. FIG. 15 is an enlarged cross-sectional view showing details of the semiconductor die mounting process following FIG. 14. FIG. 16 is an enlarged cross-sectional view showing the details of the first sealing process shown in FIG. 7. FIG. 17 is an enlarged cross-sectional view showing the details of the support removal process shown in FIG. 7. FIG. 18 is an enlarged cross-sectional view showing the details of the connection part exposure process shown in FIG. 7. FIG. 19 is an enlarged cross-sectional view showing details of the connection part exposure process following FIG. 18. FIG. 20 is an enlarged cross-sectional view showing details of the bridge mounting process shown in FIG. 7. FIG. 21 is an enlarged cross-sectional view showing details of the bridge mounting process following FIG. 20. FIG. 22 is an enlarged cross-sectional view showing details of the bridge mounting process following FIG. 21. FIG. 23 is an enlarged cross-sectional view showing the details of the second sealing process shown in FIG. 7. FIG. 24 is an enlarged cross-sectional view showing a modified example of FIG. 23. FIG. 25 is an enlarged cross-sectional view showing a modified example of the seal shown in FIG. 4. FIG. 26 is an enlarged cross-sectional view showing another variation of the seal shown in FIG. 4. FIG. 27 is an enlarged cross-sectional view showing another variation of the seal shown in FIG. 4. FIG. 28 is an enlarged cross-sectional view of a chip integrated module that is a modified example of FIG. 4. FIG. 29 is an explanatory diagram showing an overview of the manufacturing process of the chip integrated module shown in FIG. 28. FIG. 30 is an enlarged cross-sectional view showing the details of the insulating layer formation process shown in FIG. 29. FIG. 31 is an enlarged cross-sectional view showing details of the insulating layer formation process following FIG. 30. FIG. 32 is an enlarged cross-sectional view showing the details of the connection part formation process shown in FIG. 29. FIG. 33 is an enlarged cross-sectional view showing details of the semiconductor die mounting process shown in FIG. 29. FIG. 34 is an enlarged cross-sectional view showing details of the semiconductor die mounting process following FIG. 33. FIG. 35 is an enlarged cross-sectional view showing details of the semiconductor die mounting process following FIG. 34. FIG. 36 is an enlarged cross-sectional view showing details of the sealing process shown in FIG. 29. FIG. 37 is an enlarged cross-sectional view showing the details of the connection part exposure process shown in FIG. 29. FIG. 38 is an enlarged cross-sectional view showing details of the connection part exposure process following FIG. 37. FIG. 39 is an enlarged cross-sectional view showing the details of the bridge mounting process shown in FIG. 29. FIG. 40 is an enlarged cross-sectional view showing details of the bridge mounting process following FIG. 39. FIG. 41 is an enlarged cross-sectional view showing details of the bridge mounting process following FIG. 40. FIG. 42 is an explanatory diagram showing a modified example of the chip integrated circuit shown in FIG. 3. FIG. 43 is an explanatory diagram showing another variation of the chip integrated circuit shown in FIG. 3. FIG. 44 is a cross-sectional view showing a modified example of the bridge shown in FIG. 4. FIG. 45 is a cross-sectional view showing an overview of the wiring layer formation process during the manufacturing process of the bridge shown in FIG. 44. FIG. 46 is a cross-sectional view showing an overview of the wiring layer transfer process during the manufacturing process of the bridge shown in FIG. 44. FIG. 47 is a cross-sectional view showing an overview of the support removal process during the manufacturing process of the bridge shown in FIG. 44. FIG. 48 is an explanatory diagram showing another variation of the bridge shown in FIG. 4. FIG. 49 is a drawing showing a partial configuration of a chip integrated module that is a variation of FIG. 4. FIG. 50 is a diagram showing the configuration of a chip integrated module according to a first variation of the chip integrated module shown in FIG. 49. FIG. 51 is a diagram showing the configuration of a chip integrated module according to a second variation of the chip integrated module shown in FIG. 49. FIG. 52 is a diagram showing the configuration of a chip integrated module according to a third variation of the chip integrated module shown in FIG. 49. FIG. 53 is a diagram showing the configuration of a chip integrated module according to a fourth variation of the chip integrated module shown in FIG. 49. FIG. 54 is a diagram showing the configuration of a chip integrated module according to a fifth variation of the chip integrated module shown in FIG. 49. FIG. 55 is a drawing for explaining a method of manufacturing a chip integrated module according to another embodiment. FIG. 56 is a drawing for explaining a method of manufacturing a chip integrated module according to the above embodiment. FIG. 57 is a drawing for explaining a method of manufacturing a chip integrated module according to the above embodiment. FIG. 58 is a drawing for explaining a method of manufacturing a chip integrated module according to the above embodiment. FIG. 59 is a drawing for explaining a method of manufacturing a chip integrated module according to the above embodiment. FIG. 60 is a drawing for explaining a method of manufacturing a chip integrated module according to the above embodiment. FIG. 61 is a drawing for explaining a method for manufacturing a chip integrated module according to a sixth variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 62 is a drawing for explaining a method for manufacturing a chip integrated module according to a sixth variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 63 is a drawing for explaining a method for manufacturing a chip integrated module according to a sixth variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 64 is a drawing for explaining a method for manufacturing a chip integrated module according to a sixth variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 65 is a drawing for explaining a method for manufacturing a chip integrated module according to a seventh variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 66 is a drawing for explaining a method for manufacturing a chip integrated module according to a seventh variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 67 is a drawing for explaining a method for manufacturing a chip integrated module according to an eighth variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 68 is a drawing for explaining a method for manufacturing a chip integrated module according to an eighth variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 69 is a drawing for explaining a method for manufacturing a chip integrated module according to an eighth variation of the method for manufacturing a chip integrated module shown in FIG. 55 to 60. FIG. 70 is a drawing for explaining a method of manufacturing an optical module according to one embodiment. FIG. 71 is a drawing for explaining a method of manufacturing a light module according to the above embodiment. FIG. 72 is a drawing for explaining a method of manufacturing a light module according to the above embodiment. FIG. 73 is a drawing for explaining a method of manufacturing a light module according to the above embodiment. FIG. 74 is a drawing for explaining a method of manufacturing a light module according to the above embodiment. FIG. 75 is a drawing for explaining a method of manufacturing a chip integrated circuit according to another embodiment. FIG. 76 is a drawing for explaining a method for manufacturing a chip integrated circuit according to the above embodiment. FIG. 77 is a drawing for explaining a method for manufacturing a chip integrated circuit according to the above embodiment. FIG. 78 is a drawing for explaining a method for manufacturing a chip integrated circuit according to the above embodiment. FIG. 79 is a drawing for explaining a method for manufacturing a chip integrated circuit according to the above embodiment. FIG. 80 is a drawing showing an example of the configuration of an integrated circuit chip that is an embodiment. Specific details for implementing the invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, a structure in which circuit elements such as transistors or wiring are formed on a semiconductor substrate is referred to as an IC chip. The IC chip includes superconducting integrated circuits (quantum computers), etc. A structure having a wiring layer stacked on the main surface of the IC chip is referred to as a semiconductor die. There may also be cases where a rewiring layer is further formed on the IC chip, and in such cases, the rewiring layer is included in the wiring layer. A structure in which a plurality of semiconductor dies are sealed by a sealing body and integrated is referred to as a chip integrated module. A chip integrated module also includes a bridge that electrically connects a plurality of semiconductor dies to each other. A structure in which a plurality of modules including a chip integrated module are integrated is referred to as a chip integrated body. A chip integrated body may include modules such as optical modules in addition to the chip integrated module. A chip integrated body may include a plurality of chip integrated modules. Furthermore, a chip integrated body may include a wide-area wiring layer that electrically connects a plurality of modules, or a heat dissipation mechanism or heat dissipation member having a function of dissipating heat generated from each module to the outside. Among chip integrations, the part excluding heat dissipation components is called an integrated layer. In the following description, a chip integrated module is used as an example of a semiconductor module. Additionally, an integrated layer is used as an example of a semiconductor package.

[0016] However, the scope of the semiconductor module and the scope of the semiconductor package are not limited to the above definitions. For example, as illustrated in FIG. 1 described below, the chip integrated body (10) is an electronic component (module) embedded within the chip integrated system (1). In this case, the chip integrated body (10) can be considered as a semiconductor module embedded in the chip integrated system (1). Furthermore, each of the chip integrated module, integrated layer, and chip integrated body described below includes an IC chip and may also be distributed as a packaged semiconductor package. Therefore, each form of the chip integrated module, integrated layer, and chip integrated body can be considered as a semiconductor package.

[0017] Chip Integrated Systems

[0018] FIG. 1 is a schematic diagram of a chip integrated system according to one embodiment of the present invention. The chip integrated system (1) according to this embodiment comprises a plurality of chip integrated bodies (10). These chip integrated bodies (10) are connected to each other by optical wiring (110). Optical wiring may, for example, be used to connect between other chip integrated bodies, but in cases where the size of the chip integrated body is large, it may also be used to connect other parts within the chip integrated body. The chip integrated system (1) can be used, for example, in an artificial intelligence system that highly integrates various processors and memory. Additionally, although two chip integrated bodies (10a, 10b) are shown in FIG. 1, the chip integrated system (1) may comprise three or more chip integrated bodies (10), or the chip integrated system (1) may consist of only one chip integrated body (10).

[0019] The chip integrated body (10) is an integrated body that has multiple chip integrated modules inside. The size of the chip integrated module is not particularly limited, but for example, it can be exemplified as having a size of about 50mm × 50mm, or larger than about 300mm × 300mm. Here, the chip integrated module is a semiconductor module equipped with multiple IC chips. In FIG. 1, the area where the chip integrated modules are arranged in the chip integrated body (10) is shown by a dashed line. In the example shown in FIG. 1, eight chip integrated modules are arranged vertically and eight horizontally, and the chip integrated body (10) has a total of 64 chip integrated modules. However, the number of chip modules equipped by the chip integrated body (10) is not limited to this, and there may be cases where there are 63 or fewer, or 65 or more.

[0020] Additionally, the chip integrated body (10) according to the present embodiment is equipped with an optical transceiver module (hereinafter referred to as an "optical module"). The chip integrated body (10) according to the present embodiment is equipped with, for example, six optical modules. In the example shown in FIG. 1, the chip integrated body (10a) is equipped with optical modules (11a, 12a, 13a, 14a, 15a, and 16a). The chip integrated body (10b) is equipped with optical modules (11b, 12b, 13b, 14b, 15b, and 16b). Each of the optical modules (11a to 16a) and optical modules (11b to 16b) shown in FIG. 1 corresponds to the optical modules (11 to 16) shown in FIG. 2, which will be described later. These optical modules are connected by optical wiring (110) to an optical module installed in the same chip integrated body (10) or to an optical module installed in a different chip integrated body (10). Representative examples of optical wiring include optical fibers, but are not limited thereto; for example, a flat panel or sheet equipped with an optical waveguide, or optical wiring using free space, may also be used. In the chip integrated system (1) according to the present embodiment, since the signal in the chip integrated body (10) is transmitted by light, the signal is transmitted at a higher speed than when the signal is transmitted only by electrical signals.

[0021] Chip Integration

[0022] FIG. 2 is a perspective view showing an example configuration of a chip integrated structure shown in FIG. 1. The chip integrated structure (10) according to the present embodiment comprises an integrated layer (also referred to as a semiconductor package or electronic module) (100), optical modules (11 to 16) disposed on the upper surface of the integrated layer (100), a heat dissipation mechanism (20) disposed on the upper surface of the integrated layer (100), and an external terminal (30) disposed on the lower surface of the integrated layer (100).

[0023] The integrated layer (100) has a stacked structure and is a layer having a plurality of chip integrated modules (also called semiconductor modules or electronic devices). The detailed configuration of the integrated layer (100) will be described later with reference to FIG. 3.

[0024] The heat dissipation mechanism (20) is a mechanism for dissipating heat generated in the chip integrated body (10). The heat dissipation mechanism (20) is equipped with a function to dissipate heat generated when the IC chips of each of the plurality of IC chips and optical modules (11 to 16) embedded in the integrated layer (100), for example, are operated. In other words, the heat dissipation mechanism (20) can dissipate heat generated when the integrated circuit chips of the integrated layer (100) and optical modules (11 to 16) (see FIG. 2) are operated, for example.

[0025] The external terminal (30) is a terminal that is electrically connected to any one of the optical modules (11 to 16) or the chip integrated module (40) (see FIG. 3 described later). In the example shown in FIG. 2, the external terminal (30) is a solder ball and forms a part of the transmission path of an electrical signal. In this embodiment, the external terminal (30) can be used to supply power to the optical module or the chip integrated module, or to be used for input and output of electrical signals to the outside. The shape of the external terminal may be spherical as shown in FIG. 2, or may be various shapes such as a pin shape or a pad shape.

[0026] FIG. 3 is an explanatory diagram showing an example of the configuration of the chip integrated circuit shown in FIG. 2. FIG. 3 is a diagram showing the cross-sectional structure of the chip integrated circuit, but hatching has been omitted for ease of viewing. In addition, FIG. 3 shows two of the 64 chip integrated circuit modules shown in FIG. 1.

[0027] Each of the plurality of optical modules (11 to 16) shown in FIG. 2 is equipped with an optical transceiver, a connector, and a heat dissipation member. For example, the optical module (13) shown in FIG. 3 is equipped with an optical transceiver (130), a connector (132), and a heat dissipation member (136). The heat dissipation member (136) is equipped with a support plate (heat spreader) fixed on the optical transceiver (130) and a plurality of heat dissipation fins fixed on the support plate and protruding in a direction spaced apart from the optical transceiver (130).

[0028] The optical transceiver (130) is an optical-electrical conversion component equipped with the function of converting an optical signal received through an optical wiring (110) (see FIG. 1) into an electrical signal, and the function of converting an electrical signal into an optical signal and transmitting the optical signal to the outside through the optical wiring (110). A connector (132) is connected to the lower surface of the optical transceiver (130). Additionally, the connector (132) is connected to an electrode (140) formed on the surface of the integrated layer (100) through solder (138). The optical transceiver (130) can transmit and receive electrical signals with the integrated layer (100) through the connector (132). By using the connector, the optical transceiver can be easily attached and detached, and rapid replacement is possible, for example, in the event of a failure of the optical transceiver.

[0029] Additionally, a heat dissipation member (136) is disposed on the upper surface of the optical transceiver (130). The heat dissipation member (136) can dissipate heat from, for example, the optical transceiver (130). The heat dissipation member (136) is equipped with a heat spreader having heat dissipation fins installed on its upper surface to realize a large surface area with a small volume. The heat dissipation fins can dissipate heat from, for example, the optical transceiver (130).

[0030] The heat dissipation mechanism (20) is supported by a support member (210) disposed on the surface of the integrated layer (100). The heat dissipation mechanism (20) is provided with a support plate fixed to the support member (210) and a plurality of heat dissipation fins fixed on the support plate and protruding in a direction spaced apart from the chip integrated module (40). The heat dissipation mechanism (20) is thermally connected to the chip integrated module (40) (in other words, each of the plurality of IC chips) disposed inside the integrated layer (100) (specifically, inside the chip layer (104)) through the support member (210). The support member (210) is, for example, a Thermal Interface Material (TIM) and is thermally connected to the IC chip disposed inside the integrated layer (100).

[0031] The integrated layer (100) shown in FIG. 3 comprises a wide-area wiring layer (102), a chip layer (104), and a connection layer (106).

[0032] The wide-area wiring layer (102) is a layer having a laminated structure composed of multiple layers. Each of the multiple layers of the wide-area wiring layer (102) has a conductor pattern such as wiring and an insulating layer covering the conductor pattern. The insulating layer is made of, for example, an insulating resin. The conductor pattern such as wiring is formed on the base insulating layer. Two wirings installed on layers adjacent to each other in the thickness direction are electrically connected by conductor vias. In the example shown in FIG. 3, the wide-area wiring layer (102) has four layers, and an external terminal (30) is formed on the wiring installed on the bottommost layer (the layer furthest from the chip layer (104)). Additionally, the wiring installed on the topmost layer of the wide-area wiring layer (102) (the layer closest to the chip layer (104)) is electrically connected to an electrode installed on the chip layer (104).

[0033] The chip layer (104) is a layer having an insulating seal (105) and various conductors and functional devices embedded in the seal (105). For example, a conductor post (146) and a plurality of chip integrated modules (40) are embedded in the seal (105). In the example shown in FIG. 3, an electrode (148) is installed on the lower surface of the conductor post (146), and the conductor post (146) is electrically connected to the wiring placed on the uppermost layer of the wide-area wiring layer (102) through the electrode (148).

[0034] In the example shown in FIG. 3, the chip integrated module (40) is electrically connected to the wiring located at the top layer of the wide-area wiring layer (102) through the conductor tall filler (401) and electrode (403). Details of the configuration of the chip integrated module (40) will be described later with reference to FIG. 4.

[0035] The connection layer (106) is a layer that connects a component disposed on the surface of the integrated layer (100) with the chip layer (104). For example, the connection layer (106) has a conductor via (142) and an electrode (144) that connect an optical transceiver (130) to a conductor post (146) of the chip layer (104) and an electrode (140) electrically connected to the optical transceiver (130).

[0036] Additionally, the connection layer (106) has a metal contact portion (222) that is thermally connected to each of the plurality of chip integrated modules (40), and the contact portion (222) is connected to a coupling portion (220) installed inside the support member (210) of the heat dissipation mechanism (20). In this way, the chip integrated module (40) according to the present embodiment is thermally connected to the heat dissipation mechanism (20) through the contact portion (222) and the coupling portion (220).

[0037] Chip Integrated Module

[0038] FIG. 4 is an enlarged cross-sectional view showing an example of the configuration of a part of the chip integrated module shown in FIG. 3. As shown in FIG. 4, the chip integrated module (40) according to the present embodiment has a semiconductor die (41), a semiconductor die (42), and a sealing body (45) that seals the semiconductor die (41) and the semiconductor die (42). In addition, the chip integrated module (40) has a bridge (43) that electrically connects the semiconductor die (41) and the semiconductor die (42). In addition, the chip integrated module (40) has a connection part (47) that electrically connects the semiconductor die (41) and the bridge (43), and a connection part (48) that electrically connects the semiconductor die (42) and the bridge (43). Each of the connection part (47) and the connection part (48) is sealed in the sealing body (45). Additionally, the semiconductor die (41) is electrically connected to the outside of the chip integrated module (40) (e.g., the external terminal (30) shown in FIG. 3) through the connection part (49).

[0039] The semiconductor die (41) has an IC chip (411) having a main surface (411t) and an insulating layer (412) and an insulating layer (413) stacked on the main surface (411t) of the IC chip (411). The semiconductor die (41) has wiring (414) and wiring (415) electrically connected to the IC chip (411). Additionally, the semiconductor die (41) has a die electrode (416) connected to the wiring (414) and a die electrode (417) connected to the wiring (415). In the example shown in FIG. 4, the semiconductor die (41) has two insulating layers (412, 413). However, the total number of insulating layers of the semiconductor die (41) is not limited to two layers, and may have, for example, three or more insulating layers.

[0040] The IC chip (411) includes, for example, a semiconductor substrate such as silicon and circuit elements such as transistors or diodes. Various forms of integration of circuit elements within the IC chip (411) can be taken, for example, circuit elements formed two-dimensionally or three-dimensionally on the surface of the IC chip (411t), or furthermore, circuit elements formed on each layer after the semiconductor substrate itself is stacked in multiple layers and connected through through silicon vias (TSV) penetrating the semiconductor substrate.

[0041] The semiconductor die (42) has an IC chip (421) having a main surface (421t) and an insulating layer (422) and an insulating layer (423) stacked on the main surface (421t) of the IC chip (421). The semiconductor die (42) has wiring (425) electrically connected to the IC chip (421). Additionally, the semiconductor die (42) has a die electrode (427) connected to the wiring (425). In the example shown in FIG. 4, the semiconductor die (42) has two insulating layers (422, 423). However, the total number of insulating layers in the semiconductor die (42) is not limited to two layers, and may, for example, have three or more insulating layers and two or more wiring layers. Also, the structure of the semiconductor die (42) is, for example, the same as the structure of the semiconductor die (41) described above.

[0042] The bridge (43) has a chip (431) having a main surface (431t), and an insulating layer (432) and an insulating layer (433) laminated on the main surface (431t) of the chip (431). The bridge (43) has wiring (434) formed on the insulating layer (432). The chip (431) is formed from a semiconductor substrate, for example, a silicon wafer, but as a variation, it may be formed from an inorganic material such as glass. However, the total number of insulating layers of the bridge (43) is not limited to two layers, and there may be, for example, three or more insulating layers and two or more wiring layers. Also, if the chip (431) has a circuit, it may be electrically connected to the wiring (434). The bridge (43) has a bridge electrode (436) connected to a connection part (47) and a bridge electrode (437) connected to a connection part (48). The bridge electrode (436) and the bridge electrode (437) are electrically connected to each other through wiring (434).

[0043] The bridge (43) according to the present embodiment is a pillar suspended bridge. The wiring (434) according to the present embodiment is electrically connected to the chip (431), and the wiring (434) and the chip (431) are integrated to function as a bridge. However, as described below, the bridge (43) can achieve the function of a bridge circuit if it has the function of electrically connecting the semiconductor die (41) and the semiconductor die (42). For this reason, as a variation, there may be cases where the chip (431) is not present, or where the chip (431) and the wiring (434) are not electrically connected. Also, in the example shown in FIG. 4, the bridge (43) has two insulating layers (432, 433). However, the total number of insulating layers of the bridge (43) is not limited to two layers, and there may be cases where it has, for example, three or more insulating layers.

[0044] The connection portion (47) includes a pillar-shaped connection portion (472). In the example shown in FIG. 4, the connection portion (47) has a solder layer (473) connecting the pillar-shaped connection portion (472) and the die electrode (417), and a solder layer (474) connecting the pillar-shaped connection portion (472) and the bridge electrode (436).

[0045] The connection portion (48) includes a columnar connection portion (482). In the example shown in FIG. 4, the connection portion (48) has a solder layer (483) connecting the columnar connection portion (482) and the die electrode (427), and a solder layer (484) connecting the columnar connection portion (482) and the bridge electrode (437).

[0046] In this embodiment, the columnar connecting portion (472) and the columnar connecting portion (482) are each a columnar conductor of μm size (also referred to as a "micro filler"). The main body portion of each columnar connecting portion (472) and the columnar connecting portion (482) is made of a metal material, for example, copper as the main component. At the bonding interface between the columnar connecting portion (472) and the solder layer (473) and at the bonding interface between the columnar connecting portion (472) and the solder layer (474), an alloy layer is formed between a metal material, for example gold, which has higher oxidation resistance than the main body portion—in other words, has a large free energy for the formation of metal oxides—and a solder, for example tin as the main component. The alloy layer is a layer formed by the process reaction between the metal film formed at the bonding interface between the columnar connecting portion (472) and the solder layer (473, 474) and the solder layer when the columnar connecting portion (472) is bonded to the solder layer (473, 474). Details of the alloy layer will be described later.

[0047] Likewise, at the bonding interface between the pillar-shaped connection part (482) and the solder layer (483) and at the bonding interface between the pillar-shaped connection part (482) and the solder layer (484), a bonding film made of a metal material, such as gold, which has higher oxidation resistance than the main body part, is formed. However, when the pillar-shaped connection part (482) is bonded to the solder layer (483, 484), an alloy layer with the solder layer (483, 484) is formed near the bonding film, and the original constituent component of the bonding film itself is in a state where it is diffused into the solder layer.

[0048] In the example shown in FIG. 4, the connection portion (49) has an electrode (492) connected to the tall filler (401) and a solder layer (493) connecting the electrode (492) and the die electrode (426). In the example shown in FIG. 4, the tall filler (401) connected to the electrode (492) is not included in the chip integrated module (40), so it is indicated by a dotted line. However, as a variation, the tall filler (401) may be considered as part of the chip integrated module (40).

[0049] In the case of this embodiment, in the example shown in FIG. 4, each of the bridge electrode (436) and the bridge electrode (437) is sealed in a seal (44) formed separately from the seal (45). The seal (44) is, for example, an underfill resin. However, as a variation, a seal that seals the chip (431) and the bridge electrodes (436, 437) together may be used. Alternatively, as a separate variation, the seal (44) portion may be replaced with the seal (105) shown in FIG. 3. As shown in FIG. 4, the structure in which the connection portion (47) and the connection portion (48) are sealed in the seal (45) and the bridge (43) is exposed from the seal (45) is a structure obtained by the manufacturing method of the chip integrated module (40) described below. The details of the reason for obtaining the structure shown in FIG. 4 will be described later.

[0050] Additionally, in this embodiment, an example in which the bridge (43) is a semiconductor die including a chip (431) has been described, but there are cases in which the bridge does not include a chip (431) and is mainly composed of wiring (434), an insulating layer (432, 433) in which the wiring is embedded, and bridge electrodes (436, 437). Also, in this embodiment, each of the connection part (47) and the connection part (48) has a single pillar-shaped connection part (472, 482). However, depending on the distance between the semiconductor die (41) and the bridge (43), each of the connection part (47) and the connection part (48) may have two or more stacked pillar-shaped connection parts. The cross-sectional shape and cross-sectional area of ​​the stacked pillar-shaped connection parts may also differ.

[0051] Optical Module

[0052] FIG. 5 is an explanatory diagram schematically illustrating an example of the configuration of the optical module shown in FIG. 3. The optical module (13) according to the present embodiment mainly comprises an optical system mechanism (131), an optical transceiver (130), and a connector (132). In addition, the optical module (13) has a mechanism for transmitting an optical signal to the outside (hereinafter also referred to as a "transmitting mechanism (13T)") and a mechanism for receiving an optical signal from the outside (hereinafter also referred to as a "receiving mechanism (13R)"). In FIG. 5, the transmitting mechanism (13T) is shown on the left side with respect to the ground and the receiving mechanism (13R) is shown on the right side, but there are various variations of the positional relationship between the transmitting mechanism (13T) and the receiving mechanism (13R) other than the form shown in FIG. 5. Furthermore, the structure of the transmitting mechanism (13T) is described below, and the description of parts of the structure of the receiving mechanism (13R) that are common to the structure of the transmitting mechanism (13T) may be omitted.

[0053] The optical system mechanism (131) of the transmitting mechanism (13T) is equipped with an optical fiber (600), a lens (601), a reflecting mechanism (a mirror in FIG. 5) (602), and a lens (603). Light incident on the lens (603) from the optical transceiver (130) passes through the lens (603) and is reflected by the reflecting mechanism (602). The reflected light passes through the lens (601) and is incident on the optical fiber (600). By this, an optical signal is transmitted to the outside through the optical fiber (600).

[0054] The optical system mechanism (131) of the receiving mechanism (13R) is equipped with an optical fiber (610), a lens (611), a reflecting mechanism (a mirror in FIG. 5) (612) and a lens (613). Light emitted from the optical fiber (610) passes through the lens (611) and is reflected by the reflecting mechanism (612). The reflected light passes through the lens (613) and enters the optical transceiver (130). By doing so, the optical signal received by the optical fiber (610) is converted into an electrical signal, and various processing is performed. The lenses and reflecting mechanisms constituting the optical system mechanism (131) can be appropriately added or removed based on design requirements, and, for example, there may be a configuration in which the optical fiber is directly connected to the optical element chip of the optical transceiver, or in some cases, to a light-emitting element or a light-receiving element, without passing through the lenses or reflecting mechanisms.

[0055] The optical transceiver (130) mainly comprises a chip layer (620), a wiring layer (630), two optical element chips (605, 615), a light-emitting element (606), and a light-receiving element (616) disposed on the wiring layer (630). In this embodiment, the two optical element chips (605, 615), the light-emitting element (606), and the light-receiving element (616) are electrically connected to the wiring layer (630), and the connection portion is sealed by an underfill resin (607), etc. In other words, in this embodiment, the two optical element chips (605, 615), the light-emitting element (606), and the light-receiving element (616) are fixed by a fixing member (underfill resin (607)) composed of a resin, etc.

[0056] The wiring layer (630) according to the present embodiment is configured, for example, by a two-layer structure. A conductor pattern, such as wiring and electrodes, is formed in each layer of the wiring layer (630). Additionally, the chip layer (620) is provided with an optical device driving chip (621) and an optical device driving chip (622). The optical device driving chips (621 and 622) are chips that control the driving of the optical device chip (605) and the optical device chip (615), respectively. The optical device driving chips (621 and 622) may include functions such as converting the electrical signal level (voltage, current) required for the optical device to properly convert light / electricity and the electrical signal level input / output from outside the optical transceiver.

[0057] The light-emitting element (606) of the transmitting mechanism is installed on the surface of the optical element chip (605) and is a device that emits an optical signal according to an electrical signal transmitted from the optical element chip (605). The optical signal emitted by the light-emitting element (606) is incident on the lens (603) of the optical system mechanism (131).

[0058] The optical device chip (605) is connected to an electrode (631) formed on the upper layer of the wiring layer (630) through an electrode terminal (608) and a solder layer (609), and the optical device driving chip (621) is connected to an electrode (633) formed on the lower layer of the wiring layer (630) through an electrode terminal (623) and a solder layer (634). Accordingly, the optical device chip (605) and the optical device driving chip (621) are electrically connected through the wiring layer (630). This structure enables multiple parallel and short-distance connections through approximately vertical electrical connections within the wiring layer (630) between the optical device chip and the optical device driving chip. This enables broadband signal transmission between the optical device group arranged in a two-dimensional array and the optical device driving chip. In addition, depending on the manufacturing method of the optical transceiver, the solder layer (634) is not necessarily required. Also, by arranging the electrode terminal (608), conductor via (632), and electrode terminal (623) in a roughly straight line, it is possible to minimize the length of the electrical connection path between the optical device chip and the optical driving device chip, thereby making it possible to have an excellent electrical connection with low parasitic impedance.

[0059] A metal layer (629) made of metal is formed on the lower surface of the optical device driving chip (621). The metal layer (629) is thermally connected to a conductor via (641) installed in the connector (132) through a coupling member (640). Accordingly, heat generated when the optical device driving chip (621) is driven is dissipated through the coupling member (640) in the direction of the arrow schematically shown in FIG. 5 (the direction from the metal layer (629) toward the connector (132). Additionally, while it is desirable for the metal layer (629) to exist for heat dissipation, the effect is obtained even if it is not necessarily present.

[0060] The conductor via (641) of the connector (132) is connected to an electrode (140) formed on the surface of the connection layer (106) through a solder layer (642). Additionally, as shown in FIG. 3, the electrode (140) is connected to an electrode (148) connected to a conductor post (146) formed on the chip layer (104) through a conductor via (142). As a result, heat radiated from the connector (132) is radiated through the conductor post (146).

[0061] An electrode terminal (624) is formed on the upper surface of the optical device driving chip (621), and this electrode terminal (624) is connected to an electrode (626) formed on the lower side of the wiring layer (630) through a solder layer or a conductor connection part (625). Additionally, wiring (635) is formed in the wiring layer (630). The wiring (635) is connected to an electrode (626) electrically connected to the optical device driving chip (621) through a conductor via (636). Additionally, the wiring (635) is connected to an electrode (627) coupled to a conductor post (628) formed on the chip layer (620) through a conductor via (637).

[0062] The conductor post (628) is electrically connected to the conductor via (644) of the connector (132) through the coupling member (643). In the example shown in FIG. 5, electrical signals between, for example, the optical transceiver (130) and the connector (132) are transmitted to each other through the coupling member (643). However, as a variation, the direction of transmission of electrical signals between the optical transceiver (130) and the connector (132) may be one direction. That is, in the case of the transmitting mechanism (13T), an electrical signal is transmitted from the connector (132) toward the optical transceiver (130), and in the case of the receiving mechanism (13R), an electrical signal is transmitted from the optical transceiver (130) toward the connector (132).

[0063] Method for manufacturing a chip integrated module

[0064] Next, a method for manufacturing a chip integrated module (40) shown in FIGS. 3 and FIGS. 4 will be described. Before describing the method for manufacturing a chip integrated module according to the present embodiment, a brief overview of the manufacturing method reviewed by the inventors of the present invention will be described. FIG. 6 is an explanatory diagram showing an overview of the method for manufacturing a chip integrated module, which is a review example for the present embodiment.

[0065] In the method for manufacturing a chip integrated module shown in FIG. 6, first, as shown at the top of FIG. 6, a plurality of semiconductor dies (51) and a bridge structure (52) are prepared. The bridge structure (52) is a structure in which each of a plurality of bridges (520) and a plurality of connection parts (521) is sealed by a sealing body (523). In the example shown in FIG. 6, a plurality of tall fillers (401) are sealed in the sealing body (523) together with a plurality of bridges (520).

[0066] Next, as shown in the middle section of FIG. 6, a plurality of semiconductor dies (51) are mounted on a bridge structure (52). At this time, the plurality of die electrodes (511) of the semiconductor dies (51) and the plurality of connection parts (521) of the bridge structure (52) are each joined.

[0067] Next, as shown at the bottom of FIG. 6, a plurality of semiconductor dies (51) are sealed by a sealing body (512) to integrate the plurality of semiconductor dies (51) and the bridge structure (52) to obtain a chip integrated module (50).

[0068] In the case of the example shown in FIG. 6, by integrating a plurality of bridge structures (52) in advance, the process of electrically connecting a plurality of semiconductor dies (51) and a plurality of bridges (520) can be made more efficient.

[0069] However, regarding the manufacturing method shown in FIG. 6, it was found that there is a concern as follows. That is, it was found that it is difficult to improve the positional accuracy of each of the multiple connection parts (521) due to the shrinkage or expansion of the sealing body (523) constituting the bridge structure (52). As a countermeasure for this problem, a method can be devised to increase the area of ​​the bonding interface of each of the multiple connection parts (521) to increase the allowable margin for positional misalignment. However, in this case, since the placement pitch of adjacent connection parts (521) also needs to be increased, the high-density of the connection parts (521) is hindered. That is, the high-density of the terminal portion that electrically connects the semiconductor die (51) and the bridge (520) is restricted.

[0070] As mentioned above, the reason it is difficult to improve the positional precision of each of the multiple connection parts (521) is thought to be due to the large volume of the seal (523). Although a measure to reduce the linear expansion coefficient of the seal (523) by mixing inorganic filler particles, as described later, into the seal (523) can be considered, there are limitations to such a measure.

[0071] Based on the results of the above review, the inventors of the present invention have discovered a method for manufacturing a chip integrated module according to the present embodiment. Although the details of the manufacturing method will be described later, the method for manufacturing a chip integrated module according to the present embodiment involves preparing a structure in which a plurality of semiconductor dies and a plurality of connection parts are integrated by a sealing body, and mounting a plurality of bridges on the structure. The volume of the sealing body in the structure in which a plurality of semiconductor dies and a plurality of connection parts are integrated can be smaller than the volume of the sealing body (523) in the bridge structure (52) shown in FIG. 6. In particular, by reducing the gap between adjacent IC chips, the effects of thermal shrinkage and thermal expansion can be reduced. As a result, according to the method for manufacturing a chip integrated module according to the present embodiment, the positional precision of each of the plurality of connection parts can be improved, thereby enabling high-density operation of the terminal portion that electrically connects the semiconductor dies and the bridges.

[0072] Hereinafter, details of a method for manufacturing a chip integrated module according to the present embodiment will be described. FIG. 7 is an explanatory diagram showing an overview of the manufacturing process of the chip integrated module shown in FIG. 4. As shown in FIG. 7, the method for manufacturing a chip integrated module according to the present embodiment includes a connection portion forming process, a semiconductor die mounting process, a first sealing process, a support removal process, a connection portion exposure process, a bridge mounting process, and a second sealing process.

[0073] The connection part forming process shown in FIG. 7 includes each process shown in FIG. 8 to FIG. 12. FIG. 8 to FIG. 12 are each enlarged cross-sectional views showing details of the connection part forming process shown in FIG. 7. In the connection part forming process, as shown in FIG. 11, a connection part (47) including a column-shaped connection part (472) extending outwardly from the upper surface (70t) of a support body (70) and a connection part (48) including a column-shaped connection part (482) extending outwardly from the upper surface (70t) are formed on the upper surface (70t) of a support body (70).

[0074] In detail, first, as shown in FIG. 8, a support (70) having an upper surface (70t) is prepared. A peeling layer (71) and a seed layer (72) are pre-formed on the upper surface (70t) of the support (70). The material of the support (70) is not particularly limited, as long as it is a plate having sufficient rigidity to not impair workability in each process up to the support removal process shown in FIG. 7. Examples include a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as glass or a sapphire substrate, or a resin plate. However, considering the expansion caused by heating during connection, it is preferable that the linear expansion coefficient of the support be close to the linear expansion coefficient of the semiconductor die.

[0075] The peeling layer (71) is a functional layer that enables peeling of the support (70) in the support removal process shown in FIG. 7, and various materials are selected according to various methods, such as peeling by an energy beam like a laser or peeling by mechanically. The seed layer (72) is a seed film serving as a base for forming a conductor member, such as a connection part (47, 48, 49), by a plating method. The seed layer (72) can be formed, for example, by depositing copper on the peeling layer (71) by a sputtering method.

[0076] Next, as illustrated in FIG. 9, a resist mask (73) is formed on the upper surface (70t) of the support (70), specifically on the seed layer (72). A plurality of openings (73H) are formed in the resist mask (73), for example, using photolithography technology.

[0077] Next, as illustrated in FIG. 10, a metal film is deposited within the opening (73H) of the resist mask (73) by a plating method or the like to form a connection part (47), a connection part (48), and a connection part (49). Since a seed layer (72) is formed in advance on the upper surface (70t) of the support (70), a columnar connection part (472) which is a part of the connection part (47), a columnar connection part (482) which is a part of the connection part (48), and an electrode (492) which is a part of the connection part (49) can be formed, for example, by a plating method. In the example shown in FIG. 10, the columnar connection part (472) has a main body part (472A) and a metal film (472B). The columnar connection part (482) has a main body part (482A) and a metal film (482B). The electrode (492) comprises a main body (492A) and a metal film (492B). Each of the main body (472A, 482A, 492A) is made of, for example, copper, and each of the metal films (472B, 482B, 492B) is made of, for example, a metal material with higher oxidation resistance than copper, such as gold. Each of the metal films (472B, 482B, 492B) has the function of preventing oxidation of the bonding surface of each of the main body (472A, 482A, 492A) made of copper, and enabling flux-free soldering in the semiconductor die mounting process described later.

[0078] Next, as shown in FIG. 11, the resist mask (73) (see FIG. 10) is removed. When the resist mask (73) is removed, the side of each of the connection portions (47, 48, 49) and a portion of the upper surface of the seed layer (72) are exposed. Although the process may proceed to the semiconductor die mounting process shown in FIG. 7 from the state of FIG. 11, it is preferable to include a process of forming an oxide film (72A) on the exposed surface of each of the connection portions (47, 48, 49) and the seed layer (72), as shown in FIG. 12. By forming the oxide film (72A) before the semiconductor die mounting process, it is possible to prevent the solder from spreading to the side of the connection portion during the semiconductor die mounting process, thereby preventing the bonding shape from becoming unstable. When the process includes forming an oxide film (72A) on the side of each of the connection portions (47, 48, 49) and on the exposed surface of the seed layer (72), as shown in FIG. 4, each of the side of the connection portions (47, 48, 49) is covered with an oxide film (72A). In this process, if the oxide film (72A) is not formed, for example, as shown in FIG. 24 which will be described later, the oxide film (72A) shown in FIG. 4 may not be formed.

[0079] Methods for forming the oxide film (72A) may include the following methods. For example, there is a method of exposing the resist mask (73) shown in FIG. 10 to an oxygen-containing atmosphere until the oxide film (72A) shown in FIG. 12 is formed. Additionally, as a method for forming the oxide film (72A) in a shorter time, there is a method of heating the side of each connection part (47, 48, 49) and the exposed surface of the seed layer (72) in an oxygen-containing atmosphere. Also, in FIG. 12, the oxide film (72A) is shown as thick for ease of viewing, but it is sufficient for the oxide film (72A) to be formed thinly on the side of each connection part (47, 48, 49) and the exposed surface of the seed layer (72).

[0080] The semiconductor die mounting process shown in FIG. 7 includes each process shown in FIG. 13 to FIG. 15. FIG. 13 to FIG. 15 are each enlarged cross-sectional views showing details of the semiconductor die mounting process shown in FIG. 7. In the semiconductor die mounting process, as shown in FIG. 15, a semiconductor die (41) having an IC chip (411) and a die electrode (417) connected to the IC chip (411), and a semiconductor die (42) having an IC chip (421) and a die electrode (427) connected to the IC chip (421) are prepared. In addition, in the semiconductor die mounting process, the semiconductor die (41) and the semiconductor die (42) are each mounted on a support (70) such that the die electrode (417) is placed on the connection part (47) and the die electrode (427) is placed on the connection part (48).

[0081] In detail, first, as shown in FIG. 13, a semiconductor die (41) and a semiconductor die (42) are prepared. Since the detailed structure of the semiconductor die (41) and the semiconductor die (42) has already been explained using FIG. 4, a redundant description is omitted. Next, as shown in FIG. 13, a die electrode (417) is placed on the connection part (47), and a die electrode (427) is placed on the connection part (48), so that the positions of each of the semiconductor die (41) and the semiconductor die (42) are aligned with the support (70). A solder layer (473) is formed on the die electrode (417) of the semiconductor die (41). A solder layer (493) is formed on the die electrode (416) of the semiconductor die (41). A solder layer (483) is formed on the die electrode (427) of the semiconductor die (42).

[0082] Next, as illustrated in FIG. 14, the die electrode (417) of the semiconductor die (41) is pressed against the connection portion (47) through the solder layer (473). At this time, the die electrode (416) of the semiconductor die (41) is pressed against the connection portion (49) through the solder layer (493). Likewise, the die electrode (427) of the semiconductor die (42) is pressed against the connection portion (48) through the solder layer (483). In this process, the solder layer (473) and the pillar-shaped connection portion (472) of the connection portion (47) are temporarily joined by solid-state diffusion bonding. Likewise, the solder layer (493) and the electrode (492) of the connection portion (49) are temporarily joined by solid-state diffusion bonding. Likewise, the solder layer (483) and the pillar-shaped connection part (482) of the connection part (48) are temporarily joined by solid-state diffusion bonding.

[0083] Next, the bonding interface between the solder layer (473) and the metal film (472B) of the pillar-shaped connection part (472) shown in FIG. 14, the bonding interface between the solder layer (493) and the metal film (492B) of the electrode (492), and the bonding interface between the solder layer (483) and the metal film (482B) of the pillar-shaped connection part (482) are each heated to the melting temperature of the solder and maintained. By doing so, a liquid phase can be generated at each bonding interface. As shown in FIG. 15, an alloy layer (472D), an alloy layer (482D), and an alloy layer (492D) are formed at each bonding interface. When the temperature at which the liquid phase is generated is maintained, elements in the liquid phase diffuse toward the alloy layer, thereby raising the melting point of the liquid phase. As a result, the liquid phase portion solidifies. This bonding method is called liquid phase diffusion bonding. As in the present embodiment, when combining a tack bond by solid-state diffusion bonding with a bond by liquid-state diffusion bonding, a robust and thermally stable bonding state can be realized without using flux in a solder bonding process. In the case of a reflow bonding method using flux, there is a high possibility that flux residue will remain around the bonding area in fine bonding such as in the present embodiment. On the other hand, in the present embodiment, since no flux residue remains, the cleaning process can be omitted. Furthermore, the process of cleaning and removing flux residue becomes difficult as the connection area becomes finer and denser. In the present embodiment, since there is no need to clean flux residue, the fineness and density of the connection area can be realized. Additionally, depending on the size and arrangement of the bonding area, as an option for the bonding process, in addition to the above, conventional soldering (hard soldering), flux-based soldering, or solid-state diffusion bonding between metals may also be used.

[0084] When performing solder jointing, it is desirable to suppress the spread of the solder component of each solder layer to the side of the pillar-shaped joint. This is because if the solder component spreads to the side of the pillar-shaped joint or to the upper surface of the seed layer (72), the shape of the joint will not be stable, or there is a high possibility that the solder will have an adverse effect on the seed layer or the peeling layer. In the case of this embodiment, as described above, an oxide film (72A) is formed on the side of the pillar-shaped joint and the exposed surface of the seed layer (72). In this case, since the spreading of the solder component can be suppressed, the die electrode and the joint can be joined with a small amount of solder.

[0085] In the first sealing process shown in FIG. 7, after the semiconductor die mounting process, the semiconductor die (41), semiconductor die (42), connection part (47), and connection part (48) are sealed by a sealing body (45) as shown in FIG. 16. FIG. 16 is an enlarged cross-sectional view showing the details of the first sealing process shown in FIG. 7. In this process, the semiconductor die (41), semiconductor die (42), connection part (47), and connection part (48) are integrated by the sealing body (45). In addition, in the example shown in FIG. 16, the connection part (49) is also sealed by the sealing body (45). The sealing body (45) may be exemplified by a resin material including, for example, a thermosetting resin. As a variation of the sealing body (45), as described later, there may be a case in which a plurality of inorganic filler particles are contained in the resin.

[0086] In the chip integrated module (40) shown in FIG. 4, the distance between the semiconductor die (41) and the semiconductor die (42) is narrow. For example, in the example shown in FIG. 16, the distance (G1) between the semiconductor die (41) and the semiconductor die (42) is shorter than the shortest distance (G2) from the upper surface (70t) of the support (70) to the portion excluding the die electrodes (416, 417) of the semiconductor die (41). Furthermore, the IC chip, which occupies most of the semiconductor die (41) and the semiconductor die (42), is made of a semiconductor material with a very low coefficient of linear expansion compared to the seal (45). As a result, even if the seal (45) undergoes thermal expansion or thermal contraction, the position of each of the die electrodes (416, 417, 427) is unlikely to be affected. Additionally, each of the connection portions (47, 48, 49) is already fixed to the semiconductor die (41) or semiconductor die (42) before the first sealing process. As a result, each of the connection portions (47, 48, 49) can maintain high positional accuracy even when sealed by the sealing body (45). Therefore, the problem of difficulty in improving the positional accuracy of each of the multiple connection portions (521) of the bridge structure (52), as described using FIG. 6, is unlikely to occur in the present embodiment.

[0087] In the support removal process shown in FIG. 7, after the first sealing process, the support (70) (see FIG. 16) is removed as shown in FIG. 17. FIG. 17 is an enlarged cross-sectional view showing the details of the support removal process shown in FIG. 7. In this process, by applying energy to the peeling layer (71) with a laser or the like, the peeling layer (71) is decomposed (ablated), thereby significantly reducing the adhesion of the peeling layer (71) to the support, the support (70) can be easily peeled off. In addition to this, in the support removal process, it is also possible to perform peeling on the peeling layer by mechanical stress.

[0088] In the connection part exposure process shown in FIG. 7, after the support removal process, a part (bottom surface) of the column-shaped connection part (472) and a part (bottom surface) of the column-shaped connection part (482) are each exposed from the seal (45), as shown in FIG. 18. FIG. 18 is an enlarged cross-sectional view showing the details of the connection part exposure process shown in FIG. 7. In this process, the peeling layer (71) and seed layer (72) shown in FIG. 17 are removed, for example, by etching. In addition, in this process, the portion formed on the upper surface of the seed layer (72) among the oxide film (72A) shown in FIG. 17 is removed. In the example shown in FIG. 18, a part (bottom surface) of the electrode (492) is also exposed from the seal (45) in this process.

[0089] In this process, as illustrated in FIG. 19, it is preferable to expose the connection portion from the seal (45) and then form a metal film (472C, 482C, 492C) on the exposed surface of each connection portion. FIG. 19 is an enlarged cross-sectional view showing details of the connection portion exposure process following FIG. 18. As illustrated in FIG. 19, in this process, a metal film (472C) is formed on the exposed surface of the columnar connection portion (472) from the seal (45). Likewise, a metal film (482C) is formed on the exposed surface of the columnar connection portion (482) from the seal (45). A metal film (492C) is formed on the exposed surface of the electrode (492) from the seal (45). Each of the metal films (472C, 482C, 492C) is equipped with a function to prevent oxidation of the bonding surface of each main body part (472A, 482A, 492A) made of copper, and a function to enable bonding in a low-temperature process by reacting with a solder mainly composed of tin during the semiconductor die mounting process described later. For example, each of the metal films (472C, 482C, 492C) is made of a metal material (e.g., gold, etc.) that has higher oxidation resistance than the material of the main body part (472A, 482A, 492A), just like each of the metal films (472B, 482B, 492B). Gold can be exemplified as a metal material having the above function. By installing the metal films (472C, 482C, 492C), the solder bonding can be performed in the bridge mounting process shown in FIG. 7.

[0090] The bridge mounting process shown in FIG. 7 includes each process shown in FIG. 20 to FIG. 22. Each of FIG. 20 to FIG. 22 is an enlarged cross-sectional view showing the details of the bridge mounting process shown in FIG. 7. In the bridge mounting process, as shown in FIG. 22, a bridge (43) is prepared that includes a bridge electrode (436) connected to a connection part (47) and a bridge electrode (437) connected to a connection part (48). In addition, in the bridge mounting process, after the connection part exposure process, the bridge electrode (436) is placed on a pillar-shaped connection part (472), and the bridge electrode (437) is placed on a pillar-shaped connection part (482), so that the bridge (43) is mounted on a structure sealed with a sealant (45).

[0091] In detail, first, as shown in FIG. 20, a bridge (43) is prepared. Since the detailed structure of the bridge (43) has already been explained using FIG. 4, a redundant description is omitted. Next, as shown in FIG. 20, a bridge electrode (436) is placed on the pillar-shaped connection part (472), and a bridge electrode (437) is placed on the pillar-shaped connection part (482). Positional alignment is performed between the bridge (43) and the structure sealed with a sealant (45). A solder layer (474) is formed on the bridge electrode (436). A solder layer (484) is formed on the bridge electrode (437).

[0092] Next, as illustrated in FIG. 21, the bridge electrode (436) of the bridge (43) is pressed against the pillar-shaped connection part (472) of the connection part (47) through the solder layer (474). At this time, the bridge electrode (437) of the bridge (43) is pressed against the pillar-shaped connection part (482) of the connection part (48) through the solder layer (484). In this process, the solder layer (474) and the pillar-shaped connection part (472) of the connection part (47) (specifically, the metal film (472C) of the pillar-shaped connection part (472)) are temporarily joined by solid-state diffusion bonding. Likewise, the solder layer (484) and the pillar-shaped connection part (482) of the connection part (48) (specifically, the metal film (482C) of the pillar-shaped connection part (482)) are temporarily joined by solid-state diffusion bonding.

[0093] Next, the bonding interface between the solder layer (474) shown in FIG. 21 and the metal film (472C) of the pillar-shaped connection part (472), and the bonding interface between the solder layer (484) and the metal film (482C) of the pillar-shaped connection part (482) are bonded by liquid phase diffusion bonding. Since the liquid phase diffusion bonding method is as described above, a redundant description is omitted. By performing liquid phase diffusion bonding, each of the metal films (472C, 482C) shown in FIG. 21 becomes an alloy layer (472E, 482E) formed by a process reaction between tin, which is the main component of the solder layer, and the material of the metal film (e.g., gold), as shown in FIG. 22. Additionally, if the above-described semiconductor die mounting process is included and it is possible to clean flux residue, solder reflow treatment using flux may be performed instead of the combination of solid phase diffusion bonding and liquid phase diffusion bonding described above.

[0094] However, as in the present embodiment, in the bridge mounting process, if the solder layer (473, 483) that joins the pillar-shaped connecting part (472, 782) and the die electrode (417, 427) is already sealed with a sealant (45), it is particularly desirable to apply liquid diffusion bonding in order to prevent melting of the sealed solder layer (473, 483). With liquid diffusion bonding, the interface between the solder layer (474) and the pillar-shaped connecting part (472) and the interface between the solder layer (484) and the pillar-shaped connecting part (482), respectively, can be bonded at a temperature lower than the melting point of the solder layer (473, 483).

[0095] In the second sealing process shown in FIG. 7, after the bridge mounting process, the bridge electrode (436) and the bridge electrode (437) are sealed with a sealing body (44) as shown in FIG. 23. FIG. 23 is an enlarged cross-sectional view showing the details of the second sealing process shown in FIG. 7. In the example shown in FIG. 23, the sealing body (44) is an underfill resin embedded between the bridge (43) and the sealing body (45). By sealing the bridge electrode (436) and the bridge electrode (437) with the sealing body (44), a portion of the pillar-shaped connection portions (472, 482) exposed from the sealing body (45) can be protected.

[0096] However, there are various variations of the form shown in FIG. 23. For example, the second sealing process shown in FIG. 7 may be omitted, and the semiconductor module in the state shown in FIG. 22 may be shipped as a product. Alternatively, as shown as a variation in FIG. 24, the bridge electrode (436) and the bridge electrode (437) together with the conductor tall filler (401) may be sealed by a sealing body (105). This sealing process is generally referred to as mold under fill (MUF). In this variation, a process of forming the tall filler (401) is required before the second sealing process. For example, it is preferable to perform the process of forming the tall filler after the connection part exposure process and also before the bridge mounting process. The method of forming the tall filler (401) can be performed in the same way as the connection part formation process described using FIGs. 8 to 12. That is, a resist mask is formed on the lower surface (45b) of the seal (45) shown in FIG. 24. An opening is formed in the resist mask at a position that overlaps with a part of the connection portion (49). A tall filler (401) is formed by depositing a metal film within the opening of the mask by a plating method or the like. In this case, the tall filler (401) is formed directly on the electrode (492).

[0097] In the case of the variation shown in FIG. 24, the entire chip layer (104) shown in FIG. 3, the entire integrated layer (100), or the entire chip integrated body (10) may be considered as a semiconductor module.

[0098] As illustrated in FIG. 7, in the case of a manufacturing method in which a plurality of semiconductor dies are integrated by a first sealing process and then a bridge mounting process is performed, each of the plurality of die electrodes and the plurality of connection parts can be arranged with high positional precision, so that the IC chip and the bridge can be combined more densely. In addition, as described using FIG. 4, the structure in which each of the connection part (47), the connection part (48), the semiconductor die (41), and the semiconductor die (42) is sealed by a single sealing body (45) is a structure obtained by manufacturing using the manufacturing method described using FIG. 7 to FIG. 24.

[0099] <Example of a modified seal>

[0100] Next, a modified example according to the seal (45) and seal (44) shown in FIG. 4 will be described. FIGS. 25 to 27 are each enlarged cross-sectional views showing a modified example of the seal shown in FIG. 4.

[0101] The chip integrated module (40A) shown in FIG. 25 is different from the chip integrated module (40) shown in FIG. 4 in that the seal (45A) and the seal (44A) are different. The seal (45A) contains a plurality of filler particles (451), and the seal (44A) contains a plurality of filler particles (441). The average particle size of the plurality of filler particles (451) is larger than the average particle size of the plurality of filler particles (441). As in this modified example, by having the seal (45A) contain a plurality of filler particles (451) with a large average particle size, the coefficient of linear expansion of the seal (45A) as a whole can be reduced. As a result, in the bridge mounting process described using FIG. 7 and FIG. 20 to FIG. 22, the positional accuracy of the connection part (47) and the connection part (48) can be further improved. Additionally, a plurality of filler particles (451) are pre-mixed in the sealing resin used in the first sealing process shown in FIG. 7. Likewise, a plurality of filler particles (441) are pre-mixed in the sealing resin used in the second sealing process shown in FIG. 7.

[0102] The chip integrated module (40B) shown in FIG. 26 is different from the chip integrated module (40) shown in FIG. 4 in that the seal (45B) and the seal (44B) are different. The seal (45B) contains a plurality of filler particles (452), and the seal (44) contains a plurality of filler particles (442). The filling rate of the plurality of filler particles (452) in the seal (45B) is greater than the filling rate of the plurality of filler particles (442) in the seal (44B). The "filling rate of filler particles (452)" is defined as the total volume of the plurality of filler particles (452) included in the total volume of the seal (45B) containing the resin (453) and the plurality of filler particles (452). The "filling rate of the filler particles (442)" is defined as the total volume of the plurality of filler particles (442) included in the total volume of the sealant (44B) comprising the insulating resin (443) and the plurality of filler particles (442).

[0103] However, when calculating the filling rate, for example, cross-sections of two or more randomly determined areas within the seal (45A) may be captured, and in each captured area, the ratio of the cross-sectional area of ​​the filler particles (452) to the cross-sectional area of ​​the seal (45A) may be measured, and the average value of each area may be considered as the "filling rate of the filler particles (452)." The same applies to the "filling rate of the filler particles (442)." As in this modified example, by increasing the filling rate of the multiple filler particles (452) in the seal (45B), the coefficient of linear expansion of the seal (45B) as a whole can be reduced. As a result, in the bridge mounting process described using FIG. 7 and FIG. 20 to FIG. 22, the positional accuracy of the connection part (47) and the connection part (48) can be further improved. Additionally, the multiple filler particles (452) are pre-mixed in the sealing resin used in the first sealing process used in FIG. 7. Likewise, a plurality of filler particles (442) are pre-mixed in the sealing resin used in the second sealing process shown in FIG. 7.

[0104] The chip integrated module (40C) shown in FIG. 27 is different from the chip integrated module (40) shown in FIG. 4 in that the seal (45B) is different. The seal (45B) contains a plurality of filler particles (452), and the seal (44) is an insulating resin (443) that does not contain filler particles. As in this modified example, regardless of whether filler particles are present in the seal (44), if filler particles are included in the seal (45B), the coefficient of linear expansion of the seal (45B) as a whole can be reduced. As a result, in the bridge mounting process described using FIG. 7 and FIG. 20 to FIG. 22, the positional accuracy of the connection part (47) and the connection part (48) can be further improved.

[0105] <Examples of variations in manufacturing methods>

[0106] Next, a modified example of the manufacturing method of the chip integrated module (40) described using FIGS. 7 to 23 will be described. FIG. 28 is an enlarged cross-sectional view of a chip integrated module that is another modified example of FIG. 4. The chip integrated module (40D) shown in FIG. 28 is different from the chip integrated module (40) shown in FIG. 4 in that the connection portion (47) and the connection portion (48) are sealed in an insulating layer (81), and the die electrodes (416, 417) of the semiconductor die (41) and the die electrode (427) of the semiconductor die (42) are each sealed in an insulating layer (82) that is in close contact with the insulating layer (81). In addition, the chip integrated module (40D) is different from the chip integrated module (40) shown in FIG. 4 in that each of the bridge electrodes (436) and (437) of the bridge (43) is sealed in an insulating layer (84) that is in close contact with the insulating layer (81).

[0107] Below, a method for manufacturing a chip integrated module (40D) shown in FIG. 28 will be described. In the following description, the differences from the method for manufacturing a chip integrated module (40) described using FIG. 7 to FIG. 23 will be explained, and common processes may be omitted. FIG. 29 is an explanatory diagram showing an overview of the manufacturing process of the chip integrated module shown in FIG. 28. As shown in FIG. 29, the method for manufacturing a chip integrated module of the present variation includes an insulating layer forming process, a connection part forming process, a semiconductor die mounting process, a sealing process, a support removal process, a connection part exposure process, and a bridge mounting process.

[0108] The insulating layer formation process shown in FIG. 29 includes each process shown in FIG. 30 and FIG. 31. FIG. 30 and FIG. 31 are enlarged cross-sectional views showing details of the insulating layer formation process shown in FIG. 29. In the insulating layer formation process, an insulating layer (81) is formed on the upper surface (70t) of a support (70) as shown in FIG. 30, and then, as shown in FIG. 31, an opening (81H1) and an opening (81H2) are formed in the insulating layer (81). In the example shown in FIG. 31, an opening (81H3) for forming a connection part (49) shown in FIG. 28 is also formed. The insulating layer (81) is bonded to the insulating layer (82) shown in FIG. 28 in the semiconductor die mounting process described later. For this reason, it is preferable to use a material with high heat resistance in addition to electrical insulation properties for the insulating material used in the insulating layer (82). Examples of such materials include organic insulating materials such as polyimide or PBO (polybenzoxazole). Since the support (70), peel layer (71), and seed layer (72) shown in FIGS. 30 and FIGS. 31 have already been described using FIG. 8, a redundant description is omitted.

[0109] In the connection part formation process shown in FIG. 29, as shown in FIG. 32, a connection part (47) including a column-shaped connection part (472) formed within an opening (81H1) and a connection part (48) including a column-shaped connection part (482) formed within an opening (81H2) are formed. FIG. 32 is an enlarged cross-sectional view showing the details of the connection part formation process shown in FIG. 29. In the example shown in FIG. 32, an electrode (492) constituting the connection part (49) is formed within the opening (81H3). This modified example differs from the manufacturing method described using FIG. 10 in that an insulating layer (81) is used as a mask instead of the resist mask (73) described using FIG. 10. Since the structure of each of the column-shaped connection part (472, 482) and the electrode (492) is the same as described using FIG. 10, redundant descriptions are omitted.

[0110] As described above, in the case of the present variation, the insulating layer (81) is used as a mask to form the connection portions (47, 48, 49). Therefore, the process of removing the resist mask (73) described using FIG. 11 and the process of forming the oxide film (72A) described using FIG. 12 are not applied in the case of the present variation.

[0111] The semiconductor die mounting process shown in FIG. 29 includes each process shown in FIG. 33 to FIG. 35. FIG. 33 to FIG. 35 are each enlarged cross-sectional views showing details of the semiconductor die mounting process shown in FIG. 29. In the semiconductor die mounting process, as shown in FIG. 35, a semiconductor die (41) having an IC chip (411) and a die electrode (417) connected to the IC chip (411), and a semiconductor die (42) having an IC chip (421) and a die electrode (427) connected to the IC chip (421) are prepared. In addition, in the semiconductor die mounting process, the semiconductor die (41) and the semiconductor die (42) are each mounted on a support (70) such that the die electrode (417) is placed on the connection part (47) and the die electrode (427) is placed on the connection part (48).

[0112] In detail, first, as shown in FIG. 33, a semiconductor die (41) and a semiconductor die (42) are prepared. In this modified example, the semiconductor die mounting process described using FIG. 13 to 15 is different in that an insulating layer (82) is formed on the upper surface (die electrode forming surface) of the semiconductor die (41) and an insulating layer (83) is formed on the upper surface (die electrode forming surface) of the semiconductor die (42). The insulating layer (82) is an insulating layer that is bonded to the insulating layer (81) in this process. Considering the bonding properties with the insulating layer (81), it is particularly preferable that the materials of the insulating layers (82, 83) be made of the same material as the insulating layer (81). Since the detailed structure of the semiconductor die (41) and the semiconductor die (42), other than the above differences, has already been described using FIG. 4, a redundant description is omitted.

[0113] Next, as illustrated in FIG. 33, a die electrode (417) is placed on the connection portion (47), and a die electrode (427) is placed on the connection portion (48). Positional alignment is performed between the semiconductor die (41) and the semiconductor die (42), respectively, and the support (70). A solder layer (473) is formed on the die electrode (417) of the semiconductor die (41). A solder layer (483) is formed on the die electrode (427) of the semiconductor die (42). Furthermore, in the case of the present variation, the sealing body (45) does not come into contact with each of the connection portion (47), the connection portion (48), and the connection portion (49) during the sealing process described in FIG. 29. As a result, it is preferable that a solder layer (493) be formed on the bonding surface of the electrode (492), which has a relatively larger area compared to the die electrode (416). Accordingly, the volume of the void around the solder layer (493) can be reduced after the semiconductor die mounting process. Meanwhile, from the perspective of preventing oxidation of the bonding surface of the die electrode (416), it is preferable that a solder layer be formed on the die electrode (416) as well.

[0114] Next, as illustrated in FIG. 34, the die electrode (417) of the semiconductor die (41) is pressed against the connection portion (47) through the solder layer (473). At this time, the die electrode (416) of the semiconductor die (41) is pressed against the solder layer (493). Likewise, the die electrode (427) of the semiconductor die (42) is pressed against the connection portion (48) through the solder layer (483). In this process, the solder layer (473) and the pillar-shaped connection portion (472) of the connection portion (47) are temporarily joined by solid-state diffusion bonding. Likewise, the solder layer (493) and the electrode (492) of the connection portion (49) are temporarily joined by solid-state diffusion bonding. Likewise, the solder layer (483) and the pillar-shaped connection portion (482) of the connection portion (48) are temporarily joined by solid-state diffusion bonding. At this point, the insulating layer (81) is in contact with the insulating layer (82) and the insulating layer (83), respectively, but they are not yet joined.

[0115] Next, the bonding interface between the solder layer (473) shown in FIG. 34 and the metal film (472B) of the pillar-shaped connection part (472), the bonding interface between the solder layer (493) and the metal film (492B) of the electrode (492), and the bonding interface between the solder layer (483) and the metal film (482B) of the pillar-shaped connection part (482) are each bonded by the liquid phase diffusion bonding described above. In this case, as shown in FIG. 35, an alloy layer (472D), an alloy layer (482D), and an alloy layer (492D) are formed at each bonding interface by a process reaction. Since the details of the liquid phase diffusion bonding have already been explained, a redundant explanation is omitted.

[0116] In addition, in the case of the present variation, during the semiconductor die mounting process, the insulating layer (81) and the insulating layer (82) are bonded together, and the die electrode (417) is sealed by the insulating layer (81) and the insulating layer (82). In addition, during the semiconductor die mounting process, the insulating layer (81) and the insulating layer (83) are bonded together, and the die electrode (427) is sealed by the insulating layer (81) and the insulating layer (83). The timing at which the insulating layer (81) is bonded to each of the insulating layer (82) and the insulating layer (83) may be approximately the same as the timing at which liquid phase diffusion bonding is performed. That is, when the solder layer (473) and the metal film (472B) shown in FIG. 34 are heated to a temperature at which a process reaction occurs, each of the insulating layers (81, 82, 83) is also heated together. As a result, the material constituting the insulating layers (81, 82, 83) is softened, and the contact interfaces are bonded. As a principle for bonding insulating layers, bonding by dehydration polymerization of hydroxyl groups on the surface of insulating layers (fusion bonding) can be used, and depending on the material, bonding by softening or melting can also be used. When using the fusion bonding method, it is desirable to activate the surface of the insulating layers with plasma before bonding the insulating layers.

[0117] In the case of this modified example, the periphery of the connection portion (47), connection portion (48), and connection portion (49) is surrounded by an insulating layer (81). As a result, when performing liquid phase diffusion bonding, the spreading of solder components can be suppressed. Therefore, even in the case of this modified example, the die electrode and the connection portion can be bonded with a small amount of solder.

[0118] In the sealing process shown in FIG. 29, after the semiconductor die mounting process, the semiconductor die (41) and the semiconductor die (42) are sealed by a sealing body (45) as shown in FIG. 36. FIG. 36 is an enlarged cross-sectional view showing the details of the sealing process shown in FIG. 29. In this process, the semiconductor die (41) and the semiconductor die (42) are integrated by the sealing body (45). In the case of this modified example, since the connection part (47), the connection part (48), and the connection part (49) are each already sealed, strictly speaking, the semiconductor die (41) and the semiconductor die (42) are each integrated through the insulating layer (81). In this process, by sealing by the sealing body (45), the rigidity of the structure in which the semiconductor die (41) and the semiconductor die (42) are integrated is improved.

[0119] In the case of this modified example, the volume of the seal (45) is smaller compared to the volume of the seal (45) shown in FIG. 4. As a result, even when the seal (45) undergoes thermal expansion or contraction, each of the connecting parts (47, 48, 49) can maintain high positional accuracy even when sealed by the seal (45).

[0120] In the support removal process shown in FIG. 29, the support (70) shown in FIG. 36 is removed after the sealing process. Since the method of removing the support (70) is the same as the support removal process described using FIG. 17, a redundant description is omitted.

[0121] In the connection part exposure process shown in FIG. 29, after the support removal process, a part (bottom surface) of the column-shaped connection part (472) and a part (bottom surface) of the column-shaped connection part (482) are each exposed from the insulating layer (81), as shown in FIG. 37. FIG. 37 is an enlarged cross-sectional view showing the details of the connection part exposure process shown in FIG. 29. In this process, the peeling layer (71) and seed layer (72) shown in FIG. 36 are removed, for example, by etching. In the example shown in FIG. 37, a part (bottom surface) of the electrode (492) is also exposed from the insulating layer (81) in this process.

[0122] In this process, as illustrated in FIG. 38, it is preferable to expose the connection portion from the insulating layer (81) and then form a metal film (472C, 482C, 492C) on the exposed surface of each connection portion. FIG. 38 is an enlarged cross-sectional view showing the details of the connection portion exposure process following FIG. 37. As illustrated in FIG. 38, in this process, a metal film (472C) is formed on the exposed surface from the seal (45) of the columnar connection portion (472). Likewise, a metal film (482C) is formed on the exposed surface from the seal (45) of the columnar connection portion (482). A metal film (492C) is formed on the exposed surface from the seal (45) of the electrode (492). Since the details of the metal films (472C, 482C, 492C) have already been explained using FIG. 19, a redundant description is omitted.

[0123] The bridge mounting process shown in FIG. 29 includes each process shown in FIG. 39 to FIG. 41. FIG. 39 to FIG. 41 are each enlarged cross-sectional views showing details of the bridge mounting process shown in FIG. 29. In the bridge mounting process, as shown in FIG. 41, a bridge (43) is prepared that includes a bridge electrode (436) connected to a connection part (47) and a bridge electrode (437) connected to a connection part (48). In addition, in the bridge mounting process, after the connection part exposure process, the bridge electrode (436) is placed on a pillar-shaped connection part (472), and the bridge electrode (437) is placed on a pillar-shaped connection part (482), so that the bridge (43) is mounted on a structure sealed with a sealant (45).

[0124] In detail, first, as shown in FIG. 39, a bridge (43) is prepared. In this modified example, an insulating layer (84) is formed on the upper surface (bridge electrode forming surface) of the bridge (43), and each of the bridge electrode (436) and the bridge electrode (437) is sealed by the insulating layer (84), which is different from the semiconductor die mounting process described using FIG. 13 to 15. The detailed structure of the bridge (43), excluding the above differences, is the same as that already described using FIG. 4, so a redundant description is omitted.

[0125] Next, as illustrated in FIG. 39, a bridge electrode (436) is placed on the pillar-shaped connection part (472), and a bridge electrode (437) is placed on the pillar-shaped connection part (482). Positional alignment is performed with the structure sealed by the bridge (43) and the sealant (45). A solder layer (474) is formed on the bridge electrode (436). A solder layer (484) is formed on the bridge electrode (437).

[0126] Next, as illustrated in FIG. 40, the bridge electrode (436) of the bridge (43) is pressed against the pillar-shaped connection part (472) of the connection part (47) through the solder layer (474). At this time, the bridge electrode (437) of the bridge (43) is pressed against the pillar-shaped connection part (482) of the connection part (48) through the solder layer (484). In this process, the solder layer (474) and the pillar-shaped connection part (472) of the connection part (47) (specifically, the metal film (472C) of the pillar-shaped connection part (472)) are temporarily joined by solid-state diffusion bonding. Likewise, the solder layer (484) and the pillar-shaped connection part (482) of the connection part (48) (specifically, the metal film (482C) of the pillar-shaped connection part (482)) are temporarily joined by solid-state diffusion bonding.

[0127] In the case of this modified example, the insulating layer (81) and the insulating layer (84) come into contact with each other. However, at this point, the insulating layer (81) and the insulating layer (84) are not yet joined.

[0128] Next, the bonding interface between the solder layer (474) shown in FIG. 40 and the metal film (472C) of the pillar-shaped connection part (472), and the bonding interface between the solder layer (484) and the metal film (482C) of the pillar-shaped connection part (482) are bonded by liquid diffusion bonding. Since the liquid diffusion bonding method is as described above, a redundant explanation is omitted. By performing liquid diffusion bonding, each of the metal films (472C, 482C) shown in FIG. 40 becomes an alloy layer (472E, 482E) (see FIG. 41) formed by a process reaction between tin, which is the main component of the solder layer, and the material of the metal film (e.g., gold).

[0129] In addition, in the case of the present variation, during the bridge mounting process, the insulating layer (81) and the insulating layer (84) are bonded together. The timing at which the insulating layer (81) and the insulating layer (84) are bonded together is the timing for performing liquid phase diffusion bonding. That is, when the solder layer (474) and the metal film (472C) shown in FIG. 40 are heated to a temperature at which a process reaction occurs, the insulating layer (81) and the insulating layer (84) are each heated together. As a result, the materials constituting the insulating layer (81) and the insulating layer (84) are softened, and their contact interfaces are bonded. As a principle for bonding the insulating layers together, the bonding method (fusion bonding) by dehydration polymerization of hydroxyl groups on the surface of the insulating layer, as described above, may be used.

[0130] Additionally, although the present variation is described as an example using the insulating layer (81) to the insulating layer (84) shown in FIG. 28, there are cases where the configuration of the example shown in FIG. 4 or the variation described using FIG. 24 is partially applied. For example, instead of the insulating layer (84) shown in FIG. 28, the bridge electrode (436) and the bridge electrode (437) are each sealed by the seal (44) shown in FIG. 4 or the seal (105) shown in FIG. 24.

[0131] In addition, in this modified example, the upper surface of the bridge (43) is covered by an insulating layer (84), but there are cases where the insulating layer (84) is not formed. For example, if a functional insulating film called NCF (Non Conductive Film) is used instead of the insulating layer (84), the NCF is positioned to cover the insulating layer (81), the connection part (47), and the connection part (48) after the process shown in FIG. 38. In this case, during the bridge mounting process, the bridge (43) with the structure shown in FIG. 20 is pressed toward the NCF, and the bridge electrode (436) and the bridge electrode (437) each penetrate the NCF and come into contact with the connection part (47) or the connection part (48). Then, the solid-phase diffusion bonding and liquid-phase diffusion bonding described above are performed in this state, thereby obtaining a structure similar to the chip integrated module (40D) shown in FIG. 28.

[0132] Method for manufacturing a chip integrated circuit

[0133] Next, a method for manufacturing a chip integrated circuit is described using FIG. 3. First, a wide-area wiring layer (102) is formed on a support not shown. The method of forming the wide-area wiring layer (102) is not particularly limited, and, for example, a build-up method may be used. Next, a plurality of electrodes (403) and tall fillers (401) are formed on the wide-area wiring layer (102). The method of forming the electrodes (403) and tall fillers (401) can be applied by applying the connection part formation process described using FIG. 8 to FIG. 12. In addition, electrodes (148) and conductor posts (146) are also formed in this process. If the thickness of the electrodes (148) and the electrodes (403) is the same, they can be formed collectively at the same timing. On the other hand, since the conductor posts (146) and the tall fillers (401) have different thicknesses, they are formed separately.

[0134] Next, a chip integrated module (40) is mounted on the tall filler (401). The tall filler (401) is connected to the connection portion (49) shown in FIG. 4. The method of connecting the tall filler (401) and the connection portion (49) is not particularly limited, but, for example, it can be connected through a solder layer not shown. At this time, it is preferable to use liquid diffusion bonding to prevent the solder layer within the chip integrated module (40) from remelting.

[0135] Next, various components formed on the chip layer (104) are sealed with a seal (105). In the example shown in FIG. 3, each of the conductor post (146), electrode (148), chip integration module (40), tall filler (401), and electrode (403) is sealed by the seal (105). Then, a support (not shown) is removed from the wide-area wiring layer (102). Additionally, the upper part of the seal (105) is ground so that the conductor post (146) and the chip integration module (40) are exposed.

[0136] Next, a connection layer (106) is formed on the seal (105). More specifically, the connection layer (106) is formed on the seal (105) such that the wiring included in the connection layer (106) is connected to the exposed portion of the conductor post (146) or the exposed portion of the chip integrated module (40). For example, an electrode (140) formed on the connection layer (106) is connected to the conductor post (146) through a conductor via (142).

[0137] Next, a heat dissipation mechanism (20) is mounted on the contact portion (222). Additionally, an optical module (13) to which an optical fiber (600) (see FIG. 5) or an optical fiber (610) (see FIG. 5) is connected is connected to the electrode (140). The heat dissipation member (136) is already connected to the optical module (13). Subsequently, when a plurality of external terminals (30) are mounted on the wide-area wiring layer (102), a chip integrated body (10) as shown in FIG. 3 is obtained.

[0138] <Examples of variations of chip integrated circuits>

[0139] Next, a modified example of the chip integrated structure shown in FIG. 3 will be described. FIG. 42 and FIG. 43 are explanatory diagrams showing a modified example of the chip integrated structure shown in FIG. 3. The chip integrated structure (10A) shown in FIG. 42 differs from the chip integrated structure (10) shown in FIG. 3 in that a part of the optical module (13) is embedded within the chip layer (104) of the integrated layer (100). Specifically, the connector (132) portion of the optical module (13) is sealed by a sealing body (105). The connector (132) and the electrode (148) are connected through a conductor via (142). When the connector (132) portion is embedded in the chip layer (104), the height of the entire chip integrated structure (10A) can be reduced, and at the same time, compared to the case of FIG. 3, the signal transmission characteristics can be improved by shortening the distance from the chip integrated module to the optical transceiver. Additionally, since the optical transceiver (130) is exposed from the chip layer (104) and the connection layer (106), the optical transceiver (130) can be easily attached or detached.

[0140] The chip integrated body (10B) shown in FIG. 43 differs from the chip integrated body (10) shown in FIG. 3 in that the optical module (13) is positioned on the back side (100b) of the integrated layer (100). The integrated layer (100) has a front side (100f) on which a heat dissipation mechanism (20) is mounted and a back side (100b) opposite to the front side (100f). The optical module (13) is mounted on the back side (100b). By positioning the optical module (13) on the back side (100b), the distance between the heat dissipation mechanism (20) and the optical module (13) increases, thereby reducing the thermal influence from the heat dissipation mechanism (20). Additionally, in the example shown in FIG. 43, the optical module (13) is positioned in a location that overlaps with the chip integrated module (40) in the thickness direction of the integrated layer (100). In this case, the distance between the chip integrated module (40) and the optical module (13) is reduced, so the transmission efficiency of the electrical signal can be improved.

[0141]

[0142] In the signal transmission path through the bridge (43) shown in FIG. 4, the signal is transmitted at ultra-high speed. In the case of a high-speed signal transmission path, it is desirable to reduce the electrical parasitic capacitance applied to the transmission path. Below, a technique for reducing the parasitic capacitance occurring between the chip (431) and the wiring (434) shown in FIG. 4 is described as a modified example. FIG. 44 is a cross-sectional view showing a modified example of the bridge shown in FIG. 4.

[0143] The bridge (43A) shown in FIG. 44 is different from the bridge (43) shown in FIG. 4 in that it further comprises an insulating layer (438) between the insulating layer (432) and the chip (431). The differences are similar to those of the bridge (43) shown in FIG. 4. The bridge (43A) has a chip (431), an insulating layer (438), an insulating layer (432), and an insulating layer (433) stacked sequentially on the chip (431), and wiring (434) sandwiched between the insulating layer (432) and the insulating layer (438), and connected to the bridge electrode (436) and the bridge electrode (437), respectively. The insulating layer (438) is a thick insulating layer. The thickness of the insulating layer (438) is thicker than the thickness of the insulating layer (432) and the insulating layer (433). The insulating layer (438) has a surface (438t) that is adhered to the insulating layer (432) and a surface (438b) that is adhered to the chip (431). Each of the surfaces (438t) and (438b) is equipped with an adhesive function, and the insulating layer (438) is adhered and fixed to the insulating layer (432) and the chip (431) through the adhesive functions of the surfaces (438t) and (438b). The entire insulating layer (438) may be an adhesive layer.

[0144] As in the bridge (43A), when an insulating layer (438) is interposed between the insulating layer (432) and the chip (431), the distance between the wiring (434) and the chip (431) can be increased. As a result, compared to the bridge (43) shown in FIG. 4, the parasitic capacitance occurring between the chip (431) and the wiring (434) can be reduced.

[0145] In the case of a bridge (43A) with an insulating layer (438) installed, bending deformation of the bridge is more likely to occur compared to the bridge (43) shown in FIG. 4. Bending deformation of the bridge is caused by film formation stress (curing shrinkage or thermal shrinkage of the resin) that occurs when forming the insulating layer (438). In terms of reducing this bending deformation, it is desirable to use a material with a low elastic modulus for the insulating layer (438). In addition, in the same regard, it is desirable to use a resin material with a lower curing temperature and thermal decomposition temperature compared to the insulating layer (432) and the insulating layer (433). For example, if the insulating layer (432) and the insulating layer (433) are made of polyimide resin and the insulating layer (438) is made of epoxy resin, the insulating layer (438) is made of a resin material with a lower curing temperature and thermal decomposition temperature compared to the insulating layer (432) and the insulating layer (433), thus suppressing bending deformation of the bridge (43A).

[0146] The bridge (43A) shown in FIG. 44 is manufactured as follows, for example. FIGS. 45 to 47 are cross-sectional views showing an overview of the manufacturing process of the bridge shown in FIG. 44. The manufacturing method of the bridge (43A) includes a wiring layer forming process shown in FIG. 45, a wiring layer transfer process shown in FIG. 46, a support removal process shown in FIG. 47, and a bridge electrode forming process shown in FIG. 44.

[0147] First, in the wiring layer formation process, an insulating layer (433), wiring (434), and an insulating layer (432) are formed in sequence to be laminated on a support (80) shown in FIG. 45. Specifically, in the wiring layer formation process, a support (80) shown in FIG. 45 is prepared. A peeling layer (81A) and a seed layer (82A) are pre-formed on the upper surface (80t) of the support (80). The material of the support (80) is not particularly limited as long as it is a plate having sufficient rigidity to not impair workability in each process up to the support removal process described later. For example, examples include a semiconductor substrate such as a silicon wafer, a plate made of an inorganic material such as glass or a sapphire substrate, or a plate made of resin. The peeling layer (81A) is the same as the peeling layer (71) described using FIG. 8, and the seed layer (82A) is the same as the seed layer (72) described using FIG. 8, so redundant descriptions are omitted.

[0148] Additionally, in the wiring layer formation process, after preparing a support (80), an insulating layer (433) is deposited on a seed layer (82A). Subsequently, an opening is formed in a part of the insulating layer (433), and wiring (434) is formed within the opening. Although redundant descriptions are omitted, the method of forming the opening and the method of forming the wiring (434) within the opening can be formed by using the photolithography technique described using FIG. 9 and FIG. 10. Subsequently, by forming an insulating layer (432) to cover the insulating layer (433) and the wiring (434), a structure shown in FIG. 45 is obtained.

[0149] Next, in the wiring layer transfer process, as shown in FIG. 46, the insulating layer (432) on the support (80) and the chip (431) are bonded through the insulating layer (438). FIG. 46 also illustrates an example of attaching the reorganized chip (431). However, as a variation, in this process, instead of the chip (431), a silicon wafer before reorganization, a glass substrate before reorganization, or a sapphire substrate before reorganization may be attached. In this process, when a substrate in a state before reorganization is attached, after the bridge electrode formation process, a reorganization process is performed to obtain a plurality of bridges (43A) (see FIG. 44) by dicing the substrate. In this variation, a plurality of bridges (43A) can be manufactured in a batch, which is desirable from the perspective of improving manufacturing efficiency. Including this variation, this process can be described as follows. That is, in the wiring layer transfer process, the insulating layer (432) on the support (80) and the substrate are bonded through the insulating layer (438). The "substrate" referred to here includes, in addition to the chip shown in FIG. 46, semiconductor substrates such as silicon wafers before reorganization, glass substrates before reorganization, or sapphire substrates before reorganization. As explained using FIG. 44, since the surface (438t) and surface (438b) of the insulating layer (438) each have an adhesive function, the insulating layer (432) on the support (80) and the chip (431) are bonded and fixed through the insulating layer (438). Furthermore, in the case of this modified example, the chip (431) and the wiring (434) are not electrically connected. In cases where the chip (431) portion is not connected to another circuit, the chip (431) portion shown in FIG. 44 may be replaced with a substrate (e.g., a semiconductor substrate or a glass substrate) on which an integrated circuit is not formed. Alternatively, as described later, the chip (431) portion may be removed to form a bridge.

[0150] Next, in the support removal process, as shown in FIG. 47, the peeling layer (81A) is decomposed by applying energy to the peeling layer (81A) (see FIG. 46). After the support removal process, the conductor portions connected to the bridge electrode (437) and the bridge electrode (436) (conductor portion (437A) connected to the bridge electrode (437) and conductor portion (436A) connected to the bridge electrode (436)) are exposed. Each of the conductor portions (436A) and the conductor portion (437A) functions as a contactor for electrically connecting the wiring board and the bridge electrode. In this process, the peeling layer (81A) and the seed layer (82A) shown in FIG. 46 are removed, for example, by etching.

[0151] Next, in the bridge electrode formation process, as shown in FIG. 44, a bridge electrode (437) is formed on a conductor portion (437A) connected to the wiring (434), and a bridge electrode (436) is formed on a conductor portion (436A) connected to the wiring (434). In addition, in this process, a solder layer (474) is formed on the leading edge of the bridge electrode (436), and a solder layer (484) is formed on the leading edge of the bridge electrode (437).

[0152] After performing the above process on a large size such as a wafer or panel, the bridge (43A) shown in FIG. 44 can be formed by dividing it into bridges of a predetermined size. The bridge (43A) can be used as a substitute for, for example, the bridge (43) shown in FIG. 4. When the bridge (43) is substituted with the bridge (43A), the parasitic capacitance between the chip (431) and the wiring (434) is reduced, making it particularly suitable for transmitting high-speed signals. Furthermore, in this modified example, the bridge (43A) shown in FIG. 44 and the bridge (43B) shown in FIG. 48, which will be described later, are described as modified examples of the bridge (43) shown in FIG. 4. However, bridge (43A) and bridge (43B) can be substituted with a bridge (43) shown in any one of the chip integrated module (40A) shown in FIG. 25, chip integrated module (40B) shown in FIG. 26, chip integrated module (40C) shown in FIG. 27, and chip integrated module (40D) shown in FIG. 28.

[0153] FIG. 48 is a cross-sectional view showing another variation of the bridge shown in FIG. 4. The bridge (43B) shown in FIG. 48 differs from the bridge (43) shown in FIG. 4 in that a portion corresponding to the chip (431) is removed. In the case of the bridge (43B), the chip (431) is not placed near the wiring (434), so the effect of parasitic capacitance on the wiring (434) can be further reduced.

[0154] However, in the case of the bridge (43B), the rigidity is lower compared to the bridge (43) shown in FIG. 4 or the bridge (43A) shown in FIG. 44. For this reason, in the manufacturing process of the chip integrated module (40E), it is preferable to perform each process in the same manner as described in FIG. 20 to FIG. 23, while maintaining the insulating layer (433) on the chip (431) until the semiconductor die (41) and the semiconductor die (42) are each bonded with the bridge (43B) and the area around the bridge electrode (436) and the bridge electrode (437) is sealed. After that, it is preferable to perform the manufacturing method of removing the chip (431) in the state shown in FIG. 23. As a method for removing the chip (431), for example, if the chip (431) is formed of silicon, it can be removed by dry etching, etc., and if it is formed of an inorganic material such as glass, a method can be used in which a stripping layer is interposed between the chip (431) and the insulating layer (433), and the chip (431) is removed by decomposing (ablating) the stripping layer with an energy beam such as a laser. In addition, as a variation of the method for manufacturing the bridge (43B), the manufacturing method described using FIGS. 44 to 47 may be used.

[0155] Other variations of chip integrated modules

[0156] FIG. 49 is a drawing showing a partial configuration of a chip integrated module that is a variation of FIG. 4. As illustrated in FIG. 49, the chip integrated module (40E) according to the present embodiment includes a first die (41E), a second die (42E), a bridge (43E), and sealing members (45E, 46E) that seal them. The first die (41E) is connected to the bridge (43E) through a first connection part (47E). Additionally, the bridge (43E) is connected to the second die (42E) through a second connection part (48E). Additionally, the first die (41E) is connected to the outside of the chip integrated module (40E) through a third connection part (49E).

[0157] The first die (41E) is provided with a first integrated circuit chip (402E), die electrodes (408E, 410E), wiring (404E, 406E) connected to the first integrated circuit chip (402E), and an insulating layer (412E, 414E) in which the wiring (404E, 406E) is embedded. The wiring (404E, 406E) is different from the wiring layer included in the first integrated circuit chip (402E). More specifically, the wiring (404E, 406E) may be a thick-film wiring using an insulating film of organic (or inorganic, depending on the case) resin, and is called a so-called redistribution layer (RDL). Additionally, the wiring provided by the second die and the bridge is also called a redistribution layer. In addition, the second integrated circuit chip (420) and the third integrated circuit chip (442E) described later may also have the same configuration as the first integrated circuit chip (402E).

[0158] The second die (42E) has a second integrated circuit chip (420E), a die electrode (424E), wiring (422E) connected to the second integrated circuit chip (420E), and an insulating layer (426E, 428E) in which the wiring (422E) is embedded.

[0159] The bridge (43E) comprises a third integrated circuit chip (442E), bridge electrodes (446E, 448E), wiring (444E) connected to the third integrated circuit chip (442E), and an insulating layer (450E, 452E) in which the wiring (444E) is embedded. In this embodiment, the wiring (444E) forms part of the bridge that is electrically connected to the first connection part (47E) and the second connection part (48E). The bridge according to this embodiment is a Pillar Suspended Bridge. The wiring (444E) according to this embodiment is electrically connected to the third integrated circuit chip (442E), and the wiring (444E) and the third integrated circuit chip (442E) are integrated to function as a bridge.

[0160] The first connection part (47E) is provided with a columnar connection part (474E, 472E). In this embodiment, the columnar connection part is a columnar conductor of μm size (also called a “micro-filler”). The columnar connection part (472E, 474E) is a columnar conductor formed to extend from the bridge (43E) toward the first die (41E). In this embodiment, the cross-sectional area of ​​the portion of the columnar connection part (472E) connected to the columnar connection part (474E) is larger than the cross-sectional area of ​​the portion of the columnar connection part (474E) connected to the columnar connection part (472E). In this modified example, the columnar connection part (474E) is connected to the die electrode (408E) through solder (478E). Additionally, the pillar-shaped connecting part (472E) is connected to the bridge electrode (446E) through solder (476E).

[0161] The second connecting portion (48E) is provided with a columnar connecting portion (480E, 482E). The columnar connecting portion (480E, 482E) is a columnar conductor formed to extend from the bridge (43E) toward the second die (42E). In this modified example, the cross-sectional area of ​​the portion of the columnar connecting portion (480E) connected to the columnar connecting portion (482E) is larger than the cross-sectional area of ​​the portion of the columnar connecting portion (482E) connected to the columnar connecting portion (480E). In this modified example, the columnar connecting portion (482E) is connected to the die electrode (424E) through solder (486E). Additionally, the columnar connecting portion (480E) is connected to the bridge electrode (448E) through solder (484E).

[0162] The third connection part (49E) is provided with a columnar connection part (492E). The columnar connection part (492E) is a columnar conductor formed to face outward from the first die (41E). The columnar connection part (492E) is connected to the die electrode (410E) through solder (490E). Additionally, the columnar connection part (492E) is connected to an electrode pad (494E) that is connected to the outside (e.g., a wide-area wiring layer (102), etc.). Furthermore, the third connection part (49E) may be provided with various structures in addition to (or instead of) the configuration shown in FIG. 49. For example, the third connection part (49E) may include various structures that can be connected to the wide-area wiring layer (102) (see FIG. 3), such as a deep via, a tall filler, or a columnar connection part, installed below the electrode pad (494E).

[0163] In addition, in the present embodiment, an example in which the bridge is a die including an integrated circuit chip was described, but the bridge may not include an integrated circuit chip and may be composed mainly of wiring and an insulating layer in which the wiring is embedded. In addition, in the present embodiment, an example in which the die and the bridge are connected by two pillar-shaped connecting parts having different diameters was described. Not limited thereto, the die and the bridge may be connected by one pillar-shaped connecting part or by three or more pillar-shaped connecting parts.

[0164] (1st variation)

[0165] FIG. 50 is a diagram showing the configuration of a chip integrated module according to a first variation of the chip integrated module shown in FIG. 49. Among the configurations of the chip integrated module (40F) shown in FIG. 50, the same reference numerals are assigned to configurations that are substantially identical to the chip integrated module (40E) shown in FIG. 50, and descriptions are appropriately omitted.

[0166] The chip integrated module (40F) according to the first variant has a different configuration of the first connection part, the second connection part, and the third connection part compared to the chip integrated module (40E) described above (see FIG. 49). Specifically, in the first variant, the pillar-shaped connection part or electrode pad is directly connected to another electrode or wiring without using solder. More specifically, in the first connection part according to the first variant, the pillar-shaped connection part (502F) is connected to the die electrode (408E) and the bridge electrode (446E). Also, in the second connection part, the pillar-shaped connection part (504) is connected to the die electrode (424E) and the bridge electrode (448E). Also, in the third connection part, the electrode pad (494E) is connected to the die electrode (410E). Here, the pillar-shaped connection part and the die electrode or bridge electrode, or the die electrode and the electrode pad, may be connected by various known techniques regarding hybrid bonding.

[0167] In the first variant, various conductors are embedded in an insulator. Specifically, the die electrodes (408E, 410E, 424E) are embedded in an insulating film (510F). Additionally, the electrode pad (494E) and the pillar-shaped connecting portion (502F, 504F) are embedded in an insulating layer (512F). Additionally, the bridge electrodes (446E, 448E) are embedded in an insulating film (514F). Furthermore, the first die (41E) and the second die (42E) are sealed by an insulating resin (506F). By selecting appropriate material systems and process conditions in various known technologies regarding hybrid bonding, the die electrode (408E), the pillar-shaped connecting portion (502F), the insulating film (510F), and the insulating layer (512F) can be connected and bonded. Likewise, for the bridge, the bridge electrodes (446E, 448E) and the insulating layer (512F) and the insulating film (514F) and the insulating layer (512F) can be connected and bonded.

[0168] In addition, although the first variant described an example in which the bridge includes an integrated circuit chip, it is not limited thereto, and the bridge may not include an integrated circuit chip. For example, the bridge may include a solid chip composed of various materials such as silicon and glass instead of an integrated circuit chip.

[0169] (2nd variation)

[0170] FIG. 51 is a diagram showing the configuration of a chip integrated module according to a second variation of the chip integrated module shown in FIG. 49. In the chip integrated module (40G) according to the second variation, a deep via (520G) is formed in an insulating resin (524G) that seals a bridge (43E), and through this deep via (520G), a first die (41E) is electrically connected to an external conductor. More specifically, the deep via (520G) may be connected to an electrode pad (494E) connected to the bridge (43E), and a solder (522G) connected to an external conductor may be formed at the end of the deep via (520G). Here, the deep via (520G) may be formed such that its diameter increases as it extends from the electrode pad (494E) toward the solder (522G). Additionally, in the second variation, the lower surface of the third integrated circuit chip (442E) may be formed to be exposed.

[0171] In the second variant, the bridge including the bridge (43E) is sealed by an insulating resin (524G). As a result, in the second variant, the bridge is protected by the insulating resin (524G). Additionally, it is possible to seal the bridge and, at the same time, seal (underfill) the connection portion between the bridge and other members. Furthermore, by flattening the portion where the terminals of the die are formed, it is possible to make the pitch of the connection portion with the wide-area wiring layer narrower.

[0172] (Third Variation Example)

[0173] FIG. 52 is a drawing for explaining a chip integrated module according to a third variation of the chip integrated module shown in FIG. 49. FIG. 52 shows the vicinity of a deep via (520G) and a part of a third integrated circuit chip (442E) of a chip integrated module (H), which is a variation of the chip integrated module (40G) shown in FIG. 51. In the third variation, the differences from the chip integrated module (40G) according to the second variation are mainly explained. In addition, the chip integrated module according to the third variation may have the configuration of the chip integrated module (40G) according to the second variation. That is, configurations not shown in FIG. 52 may be substantially the same as the configuration shown in FIG. 51. In the chip integrated module (40H) according to the third variation, unlike the second variation, the lower surface of the third integrated circuit chip (442E) is not exposed. More specifically, the lower side of the third integrated circuit chip (442E) is covered by an insulating resin (525G).

[0174] (Fourth variant)

[0175] FIG. 53 is a drawing showing a chip integrated module according to a fourth variation of the chip integrated module shown in FIG. 49. In the chip integrated module (40K) according to the fourth variation, a wiring layer (570) is formed on the lower part of an insulating resin (524) in which a bridge (43E) is embedded. A first die (41E) and a bridge (43E) are connected to the wiring formed in this wiring layer (570K).

[0176] The wiring layer (570K) according to the fourth variation has various conductors embedded in the insulating layer, specifically, wiring (578K) and electrodes (576) embedded in the insulating layers (572K, 574K). These wiring (578K) and electrodes (576K) may be electrically connected to an external conductor. According to the fourth variation, it becomes possible to place terminals on the bridge, for example. In addition, direct power supply to the bridge from the outside is possible, for example.

[0177] According to the fourth variant, the third integrated circuit chip (564K) is provided with a functional element (566K) having various functions in the area enclosed by the dashed line. This functional element (566K) is connected to an electrode (576K) formed in the wiring layer (570K) through a via (568K) formed inside the third integrated circuit chip (564K). In addition, in this embodiment, the bridge electrode (446E) is connected to the wiring (443K), and the bridge electrode (448E) is connected to the wiring (444E). Thus, in the fourth variant, the first die (41E) and the second die (42E) are connected through the functional element (566K).

[0178] Additionally, the electrode pad (494E) electrically connected to the first die (41E) is connected to the wiring (578K) of the wiring layer (570K) through the tall filler (560K). Unlike the deep via (520G) described in the second variant (see FIG. 51), the cross-sectional area of ​​the tall filler (560K) from the electrode pad (494E) to the wiring (578K) may be approximately constant.

[0179] (5th Variation Example)

[0180] FIG. 54 is a drawing showing a chip integrated module according to a fifth variation of the chip integrated module shown in FIG. 49. In the chip integrated module (40M) according to the fifth variation, the bridge mainly includes wiring. Specifically, the bridge (580M) according to the fifth variation has various wiring and an insulating layer in which the wiring is embedded, but does not have an integrated circuit chip.

[0181] The bridge (580M) has wiring (588M) embedded in the insulating layer (582M), and this wiring (588M) is connected to the bridge electrodes (446E, 448E). Additionally, wiring (589M, 590) is embedded in the insulating layers (582M, 584M, 586M). This wiring (589M, 590M) is connected to the electrode (576) of the wiring layer (570K) through a contact via (592M).

[0182] <Other Variations of Manufacturing Methods for Chip Integrated Modules>

[0183] Referring to FIGS. 55 to 60, other variations of the method for manufacturing a chip integrated module will be described.

[0184] First, a flat support (800) having a film (802) formed on its surface as shown in FIG. 55 is prepared. Various conductors are formed on this film (802) (forming process). Various materials, including glass, silicon, and metal, can be appropriately used as the support. For example, a column-shaped connecting portion (806, 808) protruding from the surface of the support (800) is formed on the film (802). Additionally, electrode pads (804, 809) may be formed on the film (802).

[0185] Next, as illustrated in FIG. 56, a plurality of dies including a first die (81E) and a second die (82E) are bonded to various conductors formed on a thin film (802). The first die (81E) has various electrodes including a first integrated circuit chip (810), a wiring layer (812) formed on its surface, and die electrodes (814, 816) formed on its surface. Additionally, the second die (82E) has various electrodes including a second integrated circuit chip (820), a wiring layer (822) formed on its surface, and die electrodes (824, 826) formed on its surface.

[0186] In this embodiment, the die electrode formed on the die is bonded to various conductors (die bonding process). For example, the die electrode (814) and the die electrode (816) of the first die (81E) are bonded to the electrode pad (804) and the pillar-shaped connection part (806), respectively. Additionally, the die electrode (824) and the die electrode (826) of the second die (82E) are bonded to the electrode pad (809) and the pillar-shaped connection part (808), respectively. The die electrode may be connected to the electrode pad or the pillar-shaped connection part through solder, or may be bonded by hybrid bonding without solder.

[0187] Next, as illustrated in FIG. 57, various conductors and a plurality of dies formed on the peel film (802) are sealed by a resin (818) (sealing member) (sealing process). The space between the first die (81E) and the second die (82E) and the peel layer may be sealed in advance before the sealing process by the resin (818), for example, by injection and curing using capillary action with a liquid underfill resin (Capillary Underfill) or by an insulating resin such as NCF (Non Conductive Film), or simultaneously sealed by the sealing process by the resin (818) (Mold Underfill). By doing so, a plurality of dies are fixed in a state joined to a column-shaped connection part and a metal pad.

[0188] Next, as illustrated in FIG. 58, the peel film (802) and the support (800) are removed, and a process is performed to remove the peel film remaining on the electrode pad, etc. Various methods can be used to remove the support, such as a method of mechanically peeling off the support, a method of peeling off by irradiating the peel film with a laser light, and, in some cases, a method of removing the support by grinding or etching. In the case of the grinding or etching method, the peel film may be unnecessary. Additionally, the resin (818) on the surface side of the die is ground. By doing so, the die can be exposed. Below, by the method described with reference to FIG. 55 to FIG. 58, various conductors and a plurality of dies are embedded as illustrated in FIG. 58, and the ground resin is also referred to as an intermediate body (84E).

[0189] Next, as illustrated in FIG. 59, a bridge is coupled to a plurality of pillar-shaped connection parts (bridge coupling process). In this embodiment, each of a plurality of dies including a bridge (83E) is made into a bridge, and a bridge is coupled to the lower part of each of the plurality of pillar-shaped connection parts. In this embodiment, the bridge (83E) has a third integrated circuit chip (830), a wiring layer (832) formed on its surface, and a bridge electrode (including bridge electrodes (834, 836)) formed thereon.

[0190] The bridge electrode (834) of the bridge (83E) is coupled to the pillar-shaped connection part (806) connected to the first die (81E). Additionally, the bridge electrode (836) of the bridge (83E) is joined to the pillar-shaped connection part (808) connected to the second die (82E). By doing so, the bridge (83E) functions as a bridge electrically connected to the first die (81E) and the second die (82E), and a structure is formed that characterizes a suspended bridge by a filler. Additionally, the bridge electrode may be coupled to the pillar-shaped connection part through solder, or may be coupled by hybrid bonding without solder.

[0191] Next, as illustrated in FIG. 60, the resin (818) is cut so as to divide it into chip integration modules (80). By doing so, each chip integration module is formed individually.

[0192] According to the method for manufacturing a chip integrated module according to the present embodiment, as described with reference to FIG. 57, the first die, the second die, and the pillar-shaped connecting portion are fixed by resin, and then subsequent processes are carried out. As a result, in subsequent processes, the positional relationship of multiple dies is not misaligned, and it becomes possible to connect integrated circuit chips with higher precision. Furthermore, simpler processes and handling are possible. In addition, it becomes possible to form external terminals directly below the integrated circuit chip, and excellent characteristics in terms of Power Integrity (PI) and Signal Integrity (SI) can be expected. Moreover, since stable relative positional precision of the dies can be secured regardless of the module size, according to the present embodiment, it becomes easy to expand to large-scale chip integration on a panel scale.

[0193] (6th Variation Example)

[0194] FIGS. 61 to 64 are drawings for explaining a method for manufacturing a chip integrated module according to a sixth variation of the method for manufacturing a chip integrated module shown in FIGS. 55 to 60. In the sixth variation, a method for manufacturing a chip integrated module having the same configuration as the chip integrated module (40F) according to the second variation described with reference to FIG. 50 is explained.

[0195] First, a plurality of intermediate bodies (84E) embedded in a resin (818) are prepared in the same manner as described above with reference to FIGS. 55 to 58.

[0196] Referring to FIG. 61, the following process is described. First, a bridge is connected to a pillar-shaped connection. The bridge according to the sixth variant has a wiring layer (946) and an integrated circuit chip (948). The wiring layer (946) has wiring (not shown in FIG. 61), and this wiring is connected to a plurality of bridge electrodes. These bridge electrodes are connected to the pillar-shaped connection. For example, a bridge electrode (942) is connected to the pillar-shaped connection (806), and a bridge electrode (944) is connected to the pillar-shaped connection (808). Accordingly, the bridge electrodes (942, 944), the wiring layer (946), and the integrated circuit chip function as a bridge.

[0197] In addition, resin sealing is performed to cover the die electrode, wiring layer, and integrated circuit chip (Fig. 61). In addition, the integrated circuit chip is exposed by grinding or the like (Fig. 62).

[0198] Referring to FIG. 62, the following process is described. In FIG. 61, the lower surface of the integrated circuit chip is covered with resin (940). The lower surface of the integrated circuit chip and the resin (940) on the lower surface are ground. By doing so, the lower surface of the integrated circuit chip is exposed as shown in FIG. 62.

[0199] Referring to FIG. 63, the following process is described. In this process, a via opening (950) is formed in a resin (940) in which an integrated circuit chip is embedded. For example, the opening (950) may be formed in the resin by irradiating the resin (940) with a laser. The opening (950) may be formed so that, for example, an electrode pad (809) connected to the integrated circuit chip is exposed. Additionally, the via opening (950) may be formed such that its diameter increases as it extends downward from the electrode pad (809).

[0200] Referring to FIG. 64, the following process is described. In this process, metal is formed in the opening formed in the resin (940) by, for example, plating, and solder is installed at the end thereof. As a result, as shown in FIG. 64, a deep via (952) with solder (954) installed at the end is formed in the resin (940). Additionally, by cutting the resin (818, 940), it can be individualized into a chip integrated module of a desired size.

[0201] In addition, although the sixth variant describes an example in which the lower surface of the integrated circuit chip and the resin (940) on the lower surface are ground, it is not limited thereto, and an opening (950) may be formed without grinding the resin (940), and a deep via with solder installed at the end may be formed therein. By doing so, the chip integrated module described in the third variant may be manufactured.

[0202] (7th Variation Example)

[0203] Referring to FIGS. 65 to 66, a method for manufacturing a chip integrated module according to the seventh variant is described. In the seventh variant, first, an intermediate (84E) is manufactured as described with reference to FIGS. 55 to 58.

[0204] Referring to FIG. 65, the following process is described. In this process, a tall filler (962) is formed on an electrode pad (809) embedded in a resin (818), or a bridge is joined to a connection part. A bridge according to the seventh variant has a wiring layer (964) and an integrated circuit chip (966). The wiring layer (964) has wiring, and a bridge electrode installed on the surface of this wiring functions as a bridge by being connected, for example, to a pillar-shaped connection part (806, 808).

[0205] Additionally, a resin seal is applied to cover the bridge joined to the formed tall filler and the column-shaped connection part (Fig. 64). Additionally, the tall filler and the bridge are exposed by grinding or the like (Fig. 65).

[0206] Referring to FIG. 66, the following process is described. In this process, the resin (960) sealing the tall filler and bridge, the tall filler, and the integrated circuit chip are ground. As a result, as shown in FIG. 66, the surface of the tall filler and the integrated circuit chip is exposed on the surface of the resin (960). Additionally, by cutting the resin (818, 960), a chip integrated module of a desired size can be manufactured.

[0207] (8th Variation Example)

[0208] Referring to FIGS. 67 to 69, a method for manufacturing a chip integrated module according to the eighth variation is described. In the eighth variation, first, an intermediate (84E) is prepared as described with reference to FIGS. 55 to 58.

[0209] Referring to FIG. 67, the following process is described. In this process, a bridge is bonded to a connection portion embedded in the resin (818). The bridge according to the eighth variant has a wiring layer (986) and an integrated circuit chip (988). The wiring layer (986) has wiring. By connecting a bridge electrode installed on the surface of this wiring to a pillar-shaped connection portion (806, 808), the bridge electrode and the wiring layer (986) function as a bridge.

[0210] Additionally, the wiring layer (986) and the bridge electrode formed on the wiring layer (986) are covered by a resin seal. As a result, as shown in FIG. 67, the bridge is connected to a pillar-shaped connection part while the die electrode and the wiring layer (986) are fixed by the resin (980).

[0211] Referring to FIG. 68, the following process is described. In this process, the integrated circuit chip (988) is removed from the wiring layer (986). Additionally, by cutting the resin (818), a chip integrated module of a desired size can be manufactured.

[0212] With reference to FIG. 69, a process for removing an integrated circuit chip (988) from a wiring layer (986) is described in detail. In the eighth variation, a peeling layer (996) is installed between the integrated circuit chip (988) and the insulating layer (994) of the wiring layer. By irradiating the peeling layer (996) with energy particles (981) (e.g., laser light, etc.), at least a portion of the peeling layer (996) can be decomposed (altered). By moving the area irradiated with energy particles in the scan direction indicated by the arrow, the peeling layer (996) can be decomposed entirely. By doing so, the integrated circuit chip (988) can be removed from the insulating layer (994).

[0213] Additionally, although an example of decomposing the peeling layer (996) by scanning the area to which energy particles are irradiated has been described here, it is not limited to this, and energy particles may be irradiated onto the entire peeling layer (996) at once without scanning.

[0214] Method for manufacturing an optical module

[0215] With reference to FIGS. 70 to 74, a method for manufacturing an optical module according to one embodiment of the present invention will be described.

[0216] First, a support (850) having a peeling layer (852) formed on its surface is prepared. Next, as shown in FIG. 70, a wiring layer (860) is formed on the surface of the peeling layer (852). This wiring layer (860) may have a two-layer structure, and more specifically, may have substantially the same configuration as the wiring layer (630) described with reference to FIG. 5. In this embodiment, a plurality of conductor vias are formed on the upper layer of the wiring layer (630), and an electrode is connected to each conductor via. For example, an electrode (862) to which a conductor post is connected is connected to a conductor via (861), and an electrode (864) to which an optical device driving chip is connected is connected to a conductor via (863).

[0217] Next, as illustrated in FIG. 71, a conductor post (870) and an optical device driving chip (880) are coupled to an electrode. For example, the conductor post (870) is coupled to an electrode (862). Additionally, the optical device driving chip (880) has a plurality of electrode terminals (874). The electrode terminals (874) are connected to an electrode (872) formed on the surface of the wiring layer (860) through solder (782).

[0218] Next, as illustrated in FIG. 72, a plurality of conductor posts (870) and an optical device driving chip (880) are sealed by a resin (882). By doing so, the plurality of conductor posts (870) and the optical device driving chip (880) are fixed.

[0219] Next, the peeling layer (852) and the support (850) are removed, and the peeling layer (852) remaining on the lower surface of the wiring layer (860) is removed. Additionally, the upper surface of the resin (882) is ground, and a metal layer (884) is formed on the upper surface of the optical device driving chip (880) as shown in FIG. 73.

[0220] Next, as illustrated in FIG. 74, the entire structure is inverted vertically so that the metal layer (884) becomes the lower surface, and a light element chip (890) is bonded to the upper surface of the wiring layer (860). The light element chip (890) is equipped with a light-emitting element (892), a light-receiving element (894), and a plurality of electrode terminals (896). By bonding each of the plurality of electrode terminals (896) to the electrode (866) of the wiring layer (860) through solder (868), the light element chip (890) is bonded to the wiring layer (860). Additionally, the lower side of the light element chip (890), the light-emitting element (892), the light-receiving element (894), and the plurality of electrode terminals (896) are sealed with a resin (898). By doing so, a light module (89) is manufactured.

[0221] <Example of a modified method for manufacturing a chip integrated circuit>

[0222] With reference to FIGS. 75 to 79, a method for manufacturing a chip integrated circuit according to another embodiment will be described.

[0223] First, as shown in FIG. 75, a support (900) having a peeling layer (902) formed on its surface is prepared, and various conductors are formed on the surface of the peeling layer (902). Specifically, an electrode (906) to which a conductor post is connected and a pillar-shaped connection part (908) (tall filler) to which a chip integrated module is connected are formed.

[0224] Next, as illustrated in FIG. 76, various components are formed on various conductors formed on the peeling layer (902). For example, a conductor post (907) may be formed on an electrode (906), or a chip integrated module (909) may be connected to a pillar-shaped connection part (908). The chip integrated module (909) may be connected to the pillar-shaped connection part (908) by solder installed on the pillar-shaped connection part (908). If the bridge thickness of the chip integrated module is sufficiently thin, the pillar-shaped connection part (908) may be replaced by a solder bump that has a lower height.

[0225] Next, as illustrated in FIG. 77, the formed various components are sealed with resin. Specifically, the conductor post (907), the column-shaped connection part (908), and the chip integration module (909), etc., may be sealed with resin (914). After that, the support (900) is removed from the wiring layer (904) together with the release layer (902). Additionally, the resin (914) is ground so that the conductor post (907) and the chip integration module (909) are exposed.

[0226] Next, as illustrated in FIG. 78, a wiring layer (912) is formed on the resin (914). More specifically, the wiring layer (912) is formed on the resin (914) such that the wiring included in the wiring layer (912) is connected to the exposed portion of the conductor post (907) or the exposed portion of the chip integrated module (909). For example, an electrode (916) formed on the wiring layer (912) may be connected to the conductor post (907) through a conductor via. Additionally, a contact metal (918) may be connected to the chip integrated module (909) through a conductor via.

[0227] Next, as illustrated in FIG. 79, a heat dissipation mechanism (922) is mounted on the contact metal (918). Additionally, an optical module (917) with an optical wiring (920) connected to the electrode (916) is connected. By doing so, a chip integrated body according to the present embodiment is manufactured.

[0228] Integrated Circuit Chip

[0229] FIG. 80 is a drawing showing an example of the configuration of an integrated circuit chip in one embodiment. The integrated circuit chip (35) includes a wiring layer (350), a transistor (370), and a connection layer (390) connecting the wiring layer (350) and the transistor (370).

[0230] The wiring layer (350) has a five-layer laminated structure, and each layer has a film that insulates the layers, wiring embedded in the film, and vias that connect the wiring of adjacent layers above and below. For example, the wiring (352) of the second layer and the wiring (354) of the third layer are connected through vias (353), and the wiring (354) is embedded in the insulating film (356). The film of each layer may be composed of, for example, BPSG (Boron-Phosphorous Silicate Glass). The wiring of each layer may be composed of, for example, a metal such as copper. In addition, since the wiring of the upper layer (for example, the fifth layer and the fourth layer) serves as power or ground, it may not be as fine as the wiring of other layers.

[0231] Although several representative embodiments have been described above with reference to the drawings, there are various variations of the above-described embodiments and variations. Parts of the embodiments may be appropriately modified to avoid contradictions with the above description. Furthermore, for example, parts of the above-described embodiments and variations may be combined with parts of other embodiments.

[0232] In the above embodiments, examples in which various columnar connecting parts are oriented approximately perpendicular to the die surface have been primarily described. However, not limited thereto, the various columnar connecting parts may be formed to face any direction as long as they extend toward another die. Furthermore, various dimensions, cross-sectional shapes, aspect ratios (ratio of the dimension in the cross-sectional direction to the dimension in the direction perpendicular thereto), etc., of the columnar connecting parts can be appropriately set according to requirements regarding performance and reliability, selectable manufacturing processes, etc.

[0233] In the above embodiment, when the bridge includes a chip, an example was described in which the bridge mainly includes wiring and the chip is connected to the bridge electrode through this wiring. This is not limited thereto, and the bridge may not include wiring, and the chip may be directly connected to the bridge electrode.

[0234] In addition, the above embodiments mainly describe examples in which various dies (e.g., a first die and a second die, etc.) include wiring. However, the dies may not include wiring and are not limited thereto. In this case, the integrated circuit chip of the die may be directly connected to the die electrode.

[0235] In the above embodiment, a thin film wiring layer formed on a support (900) was used as the wiring (904), but the wiring (904) is not limited thereto and can be made of various known interposers or wiring substrates. Industrial applicability

[0236] The present invention is widely applicable to semiconductor modules, etc.

Claims

Claim 1 (a) A process of forming a first connection part including a first column-shaped connection part extending outwardly of the first surface and a second connection part including a second column-shaped connection part extending outwardly of the first surface on a first surface of a first support; (b) A process of preparing a first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip and a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, wherein the first die electrode is disposed on the first connection part and the second die electrode is disposed on the second connection part, and wherein each of the first semiconductor die and the second semiconductor die is mounted on the first support; (c) A process of sealing the first semiconductor die, the second semiconductor die, the first connection part and the second connection part by a first sealing body after the process of (b); (d) A process of removing the first support after the process of (c), and further removing a part of the first column-shaped connection part and the second column-shaped connection part A method for manufacturing a semiconductor module comprising: a process of exposing a portion of each portion from the first sealing body; (e) preparing a bridge including a first bridge electrode connected to the first connection part and a second bridge electrode connected to the second connection part, and, after process (d), mounting the bridge on a structure sealed with the first sealing body such that the first bridge electrode is disposed on the first pillar-shaped connection part and the second bridge electrode is disposed on the second pillar-shaped connection part. Claim 2 A method for manufacturing a semiconductor module according to claim 1, further comprising: (f) a process of sealing the first bridge electrode and the second bridge electrode with a second sealant after the process (e). Claim 3 A method for manufacturing a semiconductor module according to claim 2, wherein the first sealant comprises a plurality of first filler particles, the second sealant comprises a plurality of second filler particles, and the average particle size of the plurality of first filler particles is larger than the average particle size of the plurality of second filler particles. Claim 4 A method for manufacturing a semiconductor module according to claim 1, wherein in process (a), each of the first connection portion and the second connection portion is formed on a seed layer of the base, and in process (b), the side of the first connection portion and the side of the second connection portion are covered with an oxide film. Claim 5 A method for manufacturing a semiconductor module according to claim 4, wherein in the above process (b), the first die electrode is joined to the first connection part through a solder material, and the second die electrode is joined to the second connection part through a solder material. Claim 6 A method for manufacturing a semiconductor module according to claim 4, wherein in the above process (e), the first bridge electrode is joined to the first connection part through a solder material, and the second bridge electrode is joined to the second connection part through a solder material. Claim 7 A method for manufacturing a semiconductor module according to claim 1, wherein in the process (e) above, the process of preparing the bridge further comprises: (e1) a process of sequentially forming a first insulating layer, wiring, and a second insulating layer on a second support; (e2) a process of bonding the second insulating layer on the second support and a substrate through a third insulating layer thicker than the second insulating layer after the process (e1); (e3) a process of removing the second support after the process (e2); (e4) a process of forming the first bridge electrode and the second bridge electrode electrically connected to the wiring on the first insulating layer after the process (e3). Claim 8 (a) a process of forming a first insulating layer on a first surface of a first support and then forming a first opening and a second opening in the first insulating layer; (b) a process of forming a first connecting part including a first pillar-shaped connecting part formed within the first opening and a second connecting part including a second pillar-shaped connecting part formed within the second opening; (c) a process of preparing a first semiconductor die having a first IC chip, a first die electrode connected to the first IC chip and a second insulating layer sealing the first die electrode, and a second semiconductor die having a second IC chip, a second die electrode connected to the second IC chip and a third insulating layer sealing the second die electrode, wherein the first die electrode is disposed on the first connecting part and the second die electrode is disposed on the second connecting part, and wherein each of the first semiconductor die and the second semiconductor die is mounted on the first support; (d) after the process of (c), the first semiconductor die and the second semiconductor die are by a first sealing body A sealing process; (e) after process (d), a process of removing the first support and also exposing a part of the first column-shaped connection portion and a part of the second column-shaped connection portion, respectively, from the first insulating layer; (f) a process of preparing a bridge including a first bridge electrode connected to the first connection portion and a second bridge electrode connected to the second connection portion, and after process (e), a process of mounting the bridge on a structure sealed with the first sealant such that the first bridge electrode is disposed on the first column-shaped connection portion and the second bridge electrode is disposed on the second column-shaped connection portion; wherein in process (c), the first insulating layer and the second insulating layer are bonded to each other, and the first die electrode is sealed by the first insulating layer and the second insulating layer, and the first insulating layer and the third insulating layer are bonded to each other, and also,A method for manufacturing a semiconductor module, wherein the second die electrode is sealed by the first insulating layer and the third insulating layer. Claim 9 A method for manufacturing a semiconductor module according to claim 8, wherein in the above process (b), the first die electrode is joined to the first connection part through a solder material, and the second die electrode is joined to the second connection part through a solder material. Claim 10 A method for manufacturing a semiconductor module according to claim 9, wherein the bridge prepared in the above process (f) further has a fourth insulating layer that seals a portion of each of the first bridge electrode and the second bridge electrode, and in the above process (f), the first bridge electrode is joined to the first connection portion through a solder material, the second bridge electrode is joined to the second connection portion through a solder material, and the first insulating layer and the fourth insulating layer are joined to each other. Claim 11 A first semiconductor die having a first IC chip and a first die electrode connected to the first IC chip, a second semiconductor die having a second IC chip and a second die electrode connected to the second IC chip, a first connection part electrically connected to the first die electrode, a second connection part electrically connected to the second die electrode, a bridge having a first bridge electrode connected to the first connection part and a second bridge electrode connected to the second connection part, and a first sealing body that seals the first semiconductor die and the second semiconductor die, wherein the first connection part is disposed between the first semiconductor die and the bridge and includes a first pillar-shaped connection part extending from one side of the first semiconductor die and the bridge toward the other side, wherein the first connection part is disposed between the first semiconductor die and the bridge and includes a second pillar-shaped connection part extending from one side of the first semiconductor die and the bridge toward the other side, wherein the first bridge electrode and the second bridge electrode are exposed from the first sealing body, and the first pillar-shaped connection part and Each of the above second pillar-shaped connecting portions is sealed in the above first seal, forming a semiconductor module. Claim 12 A semiconductor module according to claim 11, wherein each of the first bridge electrode and the second bridge electrode is sealed in a second seal. Claim 13 A semiconductor module according to claim 12, wherein the first sealant comprises a plurality of first filler particles, the second sealant comprises a plurality of second filler particles, and the average particle size of the plurality of first filler particles is larger than the average particle size of the plurality of second filler particles. Claim 14 A semiconductor module according to claim 11, wherein the side of the first connection part and the side of the second connection part are covered with an oxide film. Claim 15 A semiconductor module according to claim 11, wherein the bridge comprises a chip, a first insulating layer, a second insulating layer, and a third insulating layer stacked in order on the chip, and wiring sandwiched between the second insulating layer and the third insulating layer and connected to each of the first bridge electrode and the second bridge electrode, wherein the thickness of the first insulating layer is thicker than the thickness of the second insulating layer. Claim 16 An electronic device comprising a first die having a first electrode, a second die having a second electrode, a first connection part electrically connected to the first electrode, a second connection part electrically connected to the second electrode, and a bridge electrically connected to the first connection part and the second connection part, wherein the first connection part has a pillar-shaped connection part extending from the bridge to the first die, and further comprising a sealing member that integrally seals the first die, the second die, the first connection part and the second connection part. Claim 17 An electronic device according to claim 16, wherein the columnar connecting portion is connected to a first columnar connecting portion extending from the bridge toward the first electrode and to an end of the first columnar connecting portion, and has a second columnar connecting portion extending from the end of the first columnar connecting portion toward the first electrode, wherein the cross-sectional area of ​​the portion of the first columnar connecting portion connected to the second columnar connecting portion is larger than the cross-sectional area of ​​the portion of the second columnar connecting portion connected to the first columnar connecting portion. Claim 18 delete Claim 19 delete Claim 20 In paragraph 16, the above bridge is an electronic device connected to the above pillar-shaped connection part through solder. Claim 21 An electronic device according to claim 16, wherein the first die is connected to the first connection part by hybrid bonding, and the second die is connected to the second connection part by hybrid bonding. Claim 22 An electronic module comprising an electronic device described in paragraph 16, a wiring layer having wiring installed therein, and a connection portion electrically connecting the wiring and the electronic device. Claim 23 An electronic module according to claim 22, wherein the first die has a third electrode to which a third connection part is electrically connected, the first die, the third electrode and the third connection part are integrally sealed by a sealing member, and the third connection part penetrates the sealing member and is connected to the wiring layer. Claim 24 A method for manufacturing an electronic device comprising: a connection part forming process in which a first connection part and a second connection part are formed on a support part, the first connection part having a column-shaped connection part protruding from the support part having a column shape; a die coupling process in which, after the connection part forming process, a first electrode having a first die is coupled to the first connection part and a second electrode having a second die is coupled to the second connection part; a sealing process in which, after the die coupling process, the first die, the second die, and the first connection part are sealed with a resin; and a bridge coupling process in which, after the sealing process, a bridge is coupled to the lower part of the first connection part and the lower part of the second connection part. Claim 25 In claim 24, the first connecting portion has a first column-shaped connecting portion and a second column-shaped connecting portion, and the forming process includes a process of forming the first connecting portion on the support such that the first connecting portion protrudes from the support toward the first die, and a process of forming the second connecting portion on the first connecting portion such that the second column-shaped connecting portion protrudes from the first column-shaped connecting portion toward the first die, wherein the cross-sectional area of ​​the portion of the first column-shaped connecting portion connected to the second column-shaped connecting portion is larger than the cross-sectional area of ​​the portion of the second column-shaped connecting portion connected to the first column-shaped connecting portion, and the die joining process includes a process of connecting the first die to the second column-shaped connecting portion.

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