Reset test system, and system-on chip device including the same

Abstract

A reset test system according to the present invention comprises: a scan test controller that generates a scan test enable signal (ltest_en) indicating whether a scan test mode is activated, a scan reset control signal (ltest_reset) that controls a reset in a scan test mode, and a scan reset disable signal (ltest_rstdisable) that controls a reset to be disabled in a scan test mode; a target reset test controller that generates a target reset test mode signal (TEST_MODE) indicating whether a target is in a test mode and target reset test data (TEST_MODE_RESET); and a target reset controller that receives a scan test enable signal (ltest_en), a scan reset control signal (ltest_reset), a scan reset disable signal (ltest_rstdisable), a target reset test mode signal (TEST_MODE), target reset test data (TEST_MODE_RESET), a reset input (RESET_IN), and a function clock (CLK) of a target, outputs a reset input synchronized with the function clock when in function mode, and outputs target reset test data when a reset is activated in a scan test mode.

Description

Technology Field

[0001] The present invention relates to a reset test system and a system-on-chip including the same, and more specifically, to a reset test system and a system-on-chip including the same that transmits a test reset through the same path as a functional reset path in a reset test mode. Background Technology

[0002] A System-on-Chip (SoC) refers to a technology that integrates various function blocks—such as a central processing unit (CPU), memory, interfaces, digital signal processing circuits, and analog signal processing circuits—into a single semiconductor integrated circuit to implement a computer system or other electronic system, or to the integrated circuit (IC) itself that has been integrated using this technology. SoCs are evolving into more complex systems that include various function blocks such as processors, multimedia, graphics, interfaces, and security. A System-on-Chip can operate in a test mode to detect defects during the design and manufacturing processes and verify proper operation, and can operate in a functional mode once it passes the tests and operates normally.

[0003] Figure 1 is a block diagram illustrating a typical system-on-chip (SoC) device.

[0004] The system-on-chip device may include an input / output pad (110), a clock management unit (CMU) (120), a power management unit (PMU) (130), a reset management unit (RMU) (140), and one or more IP blocks (intellectual properties) (150, 160). When the system-on-chip device operates in a functional mode, the clock management unit (120) may generate first and second functional clocks (CLK1, CLK2) provided to each of the first and second IP blocks (150, 160).

[0005] Each of the first and second IP blocks (150, 160) is connected to a system bus and can communicate with each other through the system bus. Each of the first and second IP blocks (150, 160) may be a processor, a graphic processor, a memory controller, an input and output interface block, etc.

[0006] The clock management unit (120) includes a plurality of clock components and can provide a first function clock (CLK1) to the first IP block (150) when the first IP block (150) is operating, and provide a second function clock (CLK2) to the second IP block (160) when the second IP block (160) is operating.

[0007] The power management unit (130) includes a plurality of power components and controls the power supplied to the system-on-chip device. For example, when the system-on-chip device enters standby mode, the power management unit (130) provides a power sequence (PWR1, PWR2) to power down the first and second IP blocks (150, 160) so that the power supplied to the IP blocks is cut off. Additionally, when the system-on-chip device operates in drive mode, the power management unit (130) provides a power sequence (PWR1, PWR2) to power up the first and second IP blocks (150, 160) so that power is supplied to each IP block.

[0008] The reset management unit (140) can detect the reset mode of the system-on-chip device and transmit reset signals (RST1, RST2) to the first and second IP blocks (150, 160) through the power management unit (130) so that the hardware can be initialized. Additionally, the reset signals generated by the reset management unit (140) can also be transmitted to the power management unit (130) and the clock management unit (120) so that when the IP blocks (150, 160) are reset, the power components of the power management unit (130) and the clock components of the clock management unit (120) can also be reset.

[0009] Reset modes can be used to initialize specific parts of the system or to return the system to a specific state. Reset modes may include Power On reset (POR_reset), Pin Activated reset (PAD_reset), software reset, watchdog reset, Brown_out reset (BOR_reset), cold reset, and warm reset.

[0010] A Power On Reset (POR_reset) is a reset that occurs automatically when power is first supplied to the system. It is intended to ensure a stable boot by initializing all hardware modules and registers when the system starts for the first time, and it ensures that all registers, flip-flops, internal memory, etc., are initialized.

[0011] A Pin Activated Reset (PAD_reset) is a reset that occurs when an external reset pin is pressed, and it occurs when a user manually initializes the system. It initializes important registers and internal states, but the reset range may be limited compared to a Power On Reset.

[0012] A software reset is a reset triggered by a software command. It performs a software reset when the system encounters specific software conditions or when a problem occurs, primarily initializing CPU-related registers and specific hardware modules.

[0013] A watchdog reset is a reset that occurs automatically when the system fails to operate normally within an expected time, and it is used to recover the system in the event of a software error or an infinite loop. It occurs when the watchdog timer times out, and the entire system or part of it is reset.

[0014] A Brown Out Reset (BOR_reset) is a reset that occurs when the power supply becomes unstable or drops below a specific threshold. It is used to protect the system when the power supply is unstable, and the system may remain in a reset state until the power is restored to a stable state.

[0015] A cold reset is a reset that occurs when the power is turned off and then back on, and the entire system state can be initialized. Power-on resets and pin-activated resets can be cold resets.

[0016] A warm reset is a reset that occurs while the power is maintained, and only parts of the system are partially initialized. Only the CPU and some hardware modules are reset, while memory and other components may be retained.

[0017] In other words, depending on the various types of reset, all components of the system-on-chip device and the entire IP block may be reset, or only some IP blocks or some components may be reset.

[0018] While the system-on-chip device is operating in functional mode, it is necessary to initialize the components or IP blocks constituting the system-on-chip device to maintain the reliability, stability, and security of the system, such as for system rebooting, system error recovery, firmware / software updates, handling power supply instability, troubleshooting clock and timing issues, and responding to changes in external conditions.

[0019] The reset management unit (140) may include a function reset generation unit that generates and distributes reset signals in function mode. The function reset generation unit may receive triggers from various sources (power on, external reset pin, watchdog timer, software command, etc.), generate reset signals, and distribute them to components within the system-on-chip device so that the corresponding components are reset. The reset signals may include a power-on reset signal, a pin-activated reset signal, a cold reset signal, a soft reset signal, a specific IP block reset signal, etc.

[0020] The path through which the reset signal is transmitted when the system-on-chip operates in function mode can be called the function reset path.

[0021] FIG. 2 is a diagram illustrating a function reset path in which a reset signal is transmitted to an arbitrary reset target in function mode.

[0022] The function reset generation unit (210) receives a trigger from various reset sources and generates a reset signal. The clock management unit (220) generates a function clock (CLK) and transmits it to the target (240). Depending on the target (240), the function clock (CLK) may be a high-speed clock or a low-speed clock, and the target (240) may be one of the IP block, power components of the power management unit, clock components of the clock management unit, and internal logic circuits of each unit.

[0023] A reset signal can be transmitted to a target (240) through a functional reset path (250). The functional reset path (250) may be composed of at least one component. Depending on the reset source, the functional reset generating unit (210) may transmit a reset signal to at least one of the power components of a power management unit, the clock components of a clock management unit, IP blocks, and the internal logic circuits of each unit.

[0024] For example, in the case where the reset source is a cold reset such as power-on and external reset pin activation, the function reset generating unit (210) generates a cold reset signal, and this cold reset signal can be distributed to all components of the system and logic circuits, including all IP blocks, all power components of the power management unit, and all clock components of the clock management unit, and the target (240) can be one of all components and logic circuits of the system-on-chip device. Meanwhile, in the case where the reset source is a warm reset or software reset in which only some components of the system-on-chip device are reset, the function reset generating unit (210) provides a reset signal to only some components or logic circuits, and in this case, the target (240) can be one of those some components or logic circuits.

[0025] The reset signal generated by the function reset generation unit (210) is transmitted to the synchronization unit (230) along the function reset path (250), and the synchronization unit (230) synchronizes the reset signal with the function clock (CLK) supplied to the target (240) and outputs it to the target (240). That is, a reset signal synchronized with the function clock (CLK) of the target (240) is provided to the target (240), and when the reset signal is input to the target (240), the target (240) is initialized.

[0026] In this way, the function reset generation unit (210) generates a reset signal while the system-on-chip device is operating normally and transmits it to each IP block or component of the system through each function reset path.

[0027] Meanwhile, logic testing may be performed to functionally verify and detect defects in the digital circuits constituting the system-on-chip. Logic testing is a process that verifies the logic paths and states of digital circuits and may include scan testing, Built-In Self-Test (BIST), pattern-based testing, and reset testing. In reset testing, tests can be performed to verify whether the reset signal operates correctly and whether the state of the digital circuit is initialized after the reset.

[0028] As previously explained, in function mode, a reset signal generated by the function reset generation unit (210) can be transmitted to each of the multiple components and IP blocks constituting the system through each function reset path. That is, since each of the multiple components and IP blocks has a function reset path formed therein, it is desirable to test all function reset paths of each component and IP block during the reset test of the logic test.

[0029] However, current system-on-chip device test designs (DFT) are designed to perform reset tests only on IP blocks, rather than testing functional reset paths for all system components.

[0030] Figure 3 is a block diagram illustrating a conventional IP block reset test system.

[0031] A conventional reset test system includes a test reset generating unit (310) that outputs a test reset in test mode, and a test multiplexer (Test MUX) (320) that selectively provides to an IP block (250) a function reset generated by a function reset generating unit (210) and transmitted through a function reset path (250), and a test reset provided by the test reset generating unit (310).

[0032] The test multiplexer (320) ensures that a test reset input from the test reset generation unit (310) in test mode is provided to the IP block (250), and that a function reset generated by the function reset generation unit (210) in function mode and transmitted through the function reset path (250) is provided to the IP block (250).

[0033] This conventional reset test system is positioned immediately before the IP block (250) to provide a test reset to the IP block (250).

[0034] As such, conventional reset tests suffer from reduced test coverage because the path through which functional resets are transmitted in the functional mode of a system-on-chip device differs from the path through which test resets are transmitted in the test mode; consequently, testing is not performed on all functional reset paths. Furthermore, this leads to reduced test coverage because reset tests may not be performed on the internal logic circuits of some components or units of the system-on-chip device. In other words, although the synchronization unit is located on the functional reset path, the test reset cannot be transmitted to it, so the reset test of the synchronization unit cannot be executed during the reset test. The problem to be solved

[0035] The objective of the present invention is to provide a reset test system and a system-on-chip including the same, wherein a test reset is transmitted through the same path as the functional reset path in a reset test mode, and the reset function can be tested for each component and IP block constituting the system-on-chip during the reset test. means of solving the problem

[0036] A reset test system according to the present invention comprises: a scan test controller that generates a scan test enable signal (ltest_en) indicating whether a scan test mode is activated, a scan reset control signal (ltest_reset) that controls a reset in a scan test mode, and a scan reset disable signal (ltest_rstdisable) that controls a reset to be disabled in a scan test mode; a target reset test controller that generates a target reset test mode signal (TEST_MODE) indicating whether a target is in a test mode and target reset test data (TEST_MODE_RESET); and a target reset controller that receives a scan test enable signal (ltest_en), a scan reset control signal (ltest_reset), a scan reset disable signal (ltest_rstdisable), a target reset test mode signal (TEST_MODE), target reset test data (TEST_MODE_RESET), a reset input (RESET_IN), and a function clock (CLK) of a target, outputs a reset input synchronized with the function clock when in function mode, and outputs target reset test data when a reset is activated in a scan test mode.

[0037] Preferably, the target reset controller includes a synchronization unit that synchronizes the reset input with the target's function clock, and the synchronization unit is reset when the reset is activated in scan test mode.

[0038] Preferably, the target reset test controller is a controller based on the built-in IEEE1687 standard.

[0039] Preferably, target reset test controllers are placed corresponding to each reset domain.

[0040] Preferably, the target reset test controller includes a test mode TDR (test data register) that outputs a target reset test mode signal (TEST_MODE) indicating whether the target reset test mode is enabled or disabled, and a test control TDR (test data register) that outputs target reset test data (TEST_MODE_RESET) when the target is enabled in reset test mode.

[0041] More preferably, the test mode TDR (test data register) and test control TDR (test data register) are configured via the IJTAG (Internal Joint Test Action Group) interface.

[0042] More preferably, the target reset controller includes a first test multiplexer (TMUX) in which a scan reset control signal (ltest_reset) and a reset input (RESET_IN) are input to respective input terminals and a scan test enable signal (ltest_en) is input to a selection terminal, and which outputs one of the scan reset control signal (ltest_reset) and the reset input (RESET_IN) according to the scan test enable signal (ltest_en); and a first logical OR operator that performs a logical OR operation on the output of the first test multiplexer (731) and a scan reset disable signal (ltest_rstdisable) and outputs the result to a synchronization unit.

[0043] More preferably, the target reset controller further comprises a second OR operator that performs a logical OR operation on the output of the synchronization unit and a scan reset disable signal (ltest_rstdisable), and a second test multiplexer in which the output of the second OR operator and target reset test data (TEST_MODE_RESET) are input to respective input terminals, a target reset test mode (TEST_MODE) signal is input to a selection terminal, and one of the output of the second OR operator and the target reset test data is output according to the target reset test mode (TEST_MODE) signal.

[0044] A system-on-chip according to the present invention comprises a reset test system, wherein the reset test system comprises: a scan test controller that generates a scan test enable signal (ltest_en) indicating whether a scan test mode is enabled, a scan reset control signal (ltest_reset) that controls a reset in a scan test mode, and a scan reset disable signal (ltest_rstdisable) that controls a reset to be disabled in a scan test mode; and a target reset test controller that generates a target reset test mode signal (TEST_MODE) indicating whether a target is in a test mode and target reset test data (TEST_MODE_RESET). It includes a target reset controller that receives a scan test enable signal (ltest_en), a scan reset control signal (ltest_reset), a scan reset disable signal (ltest_rstdisable), a target reset test mode signal (TEST_MODE), target reset test data (TEST_MODE_RESET), a reset input (RESET_IN), and the target's function clock (CLK), outputs the reset input synchronized with the function clock in function mode, and outputs the target reset test data when the reset is enabled in scan test mode.

[0045] Preferably, the target reset controller includes a synchronization unit that synchronizes the reset input with the target's function clock, and the synchronization unit is reset when the reset is activated in scan test mode.

[0046] Preferably, the target reset test controller is a controller based on the built-in IEEE1687 standard.

[0047] Preferably, target reset test controllers are placed corresponding to each reset domain.

[0048] Preferably, the target reset test controller includes a test mode TDR (test data register) that outputs a target reset test mode signal (TEST_MODE) indicating whether the target reset test mode is enabled or disabled, and a test control TDR (test data register) that outputs target reset test data (TEST_MODE_RESET) when the target is enabled in reset test mode.

[0049] More preferably, the test mode TDR (test data register) and test control TDR (test data register) are configured via the IJTAG (Internal Joint Test Action Group) interface.

[0050] More preferably, the target reset controller includes a first test multiplexer (TMUX) in which a scan reset control signal (ltest_reset) and a reset input (RESET_IN) are input to respective input terminals and a scan test enable signal (ltest_en) is input to a selection terminal, and which outputs one of the scan reset control signal (ltest_reset) and the reset input (RESET_IN) according to the scan test enable signal (ltest_en); and a first logical OR operator that performs a logical OR operation on the output of the first test multiplexer (731) and a scan reset disable signal (ltest_rstdisable) and outputs the result to a synchronization unit.

[0051] More preferably, the target reset controller further comprises a second OR operator that performs a logical OR operation on the output of the synchronization unit and a scan reset disable signal (ltest_rstdisable), and a second test multiplexer in which the output of the second OR operator and target reset test data (TEST_MODE_RESET) are input to respective input terminals, a target reset test mode (TEST_MODE) signal is input to a selection terminal, and one of the output of the second OR operator and the target reset test data is output according to the target reset test mode (TEST_MODE) signal. Effects of the invention

[0052] According to the present invention, the following effects are achieved.

[0053] Since the test reset path is formed along the same path as the function reset path, the present invention allows testing whether the components constituting the function reset path operate normally, thereby expanding test coverage.

[0054] The present invention allows a reset test to be performed on a synchronization unit located on a functional reset path, thereby expanding test coverage.

[0055] The present invention can provide a test reset to the IP block and each component of the system-on-chip device when the system-on-chip device is operated in test mode, thereby enabling the reset test of each component of the system-on-chip device and the IP block to be performed smoothly.

[0056] The effects of the present invention are not limited to those mentioned above, and other unmentioned effects will be clearly understood by a person skilled in the art to which the present invention pertains (referred to as "person skilled in the art") from the description in the claims. Brief explanation of the drawing

[0057] Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein similar reference numerals indicate similar elements, but are not limited thereto. Figure 1 is a block diagram illustrating a typical system-on-chip (SoC) device. FIG. 2 is a diagram illustrating a function reset path in which a reset signal is transmitted to an arbitrary reset target in function mode. Figure 3 is a block diagram illustrating a conventional IP block reset test system. FIG. 4 is a configuration diagram of a system-on-chip device including a power management cluster (PMC) to which the present invention is applied. FIG. 5 is a configuration block diagram illustrating a reset test system applied to a reset domain including a root power manager and a domain power manager according to the present invention. FIG. 6 is a configuration block diagram illustrating a reset test system applied to a reset domain including a second power management interface and an IP block according to the present invention. FIG. 7 is a block diagram of a reset test system including one target reset controller according to the present invention. Embodiments of the present invention will be described with reference to the accompanying drawings described below, wherein similar reference numerals indicate similar elements, but are not limited thereto. Specific details for implementing the invention

[0058] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding widely known functions or configurations will be omitted if there is a risk of unnecessarily obscuring the essence of the present invention.

[0059] In the attached drawings, identical or corresponding components are assigned the same reference numerals. Additionally, in the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0060] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to fully inform a person skilled in the art of the scope of the invention.

[0061] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) may be used in a meaning commonly understood by those skilled in the art to which the present invention pertains. Additionally, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0062] For example, the term “technique” may refer to systems, methods, computer-readable instructions, modules, algorithms, hardware logic, and / or operations throughout the document as permitted by the context described above.

[0063] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components.

[0064] In the present invention, terms such as 'comprising', 'comprising', etc. may indicate the presence of features, steps, actions, elements and / or components, but do not exclude the addition of one or more other functions, steps, actions, elements, components and / or combinations thereof.

[0065] In the present invention, where a specific component is described as being 'combined,' 'combined,' 'connected,' 'associated,' or 'reacted' to any other component, the specific component may be directly combined, combined, connected, and / or associated with, or reacted to the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Additionally, in the present invention, "and / or" may include each of the one or more listed items or a combination of at least some of the one or more items.

[0066] In the present invention, terms such as 'first', 'second', etc., are used to distinguish a specific component from another component, and the components described above are not limited by these terms. For example, the 'first' component may be used to refer to an element of the same or similar form as the 'second' component.

[0067] FIG. 4 is a configuration diagram of a system-on-chip device including a power management cluster (PMC) to which the present invention is applied.

[0068] A system-on-chip device may include a power management cluster (PMC) (400). The power management cluster (400) is connected to at least one IP block (250) and may provide a power up / down sequence to the IP block (250). The IP block (250) may process the power up / down sequence to become a power up state or a power down state. A system-on-chip device may include at least one power management cluster (400).

[0069] The power management cluster (400) may include at least one domain power manager (PMD; Power Management for Domain) (420) that controls the power of the IP block (250), a root power manager (PMR; Power Management for Root) (410) that manages at least one domain power manager (420), at least one first power management interface (PMIF; Power Management Interface) (430) placed between at least one domain power manager (420) and the clock management unit (220), and at least one second power management interface (PMIF; Power Management Interface) (440) placed between at least one domain power manager (420) and the IP block (250). The clock management unit (220) may provide a function clock to the root power manager (410), the domain power manager (420), the first and second power management interfaces (430, 440), and the IP block (250), etc.

[0070] A root power manager (410) and at least one domain power manager (420) are placed in the AON (Always-On) domain area, a first power management interface (430) is placed on the clock management unit (220) side, and a second power management interface (440) is placed on the IP block (250) side.

[0071] The root power manager (410) may include a cold reset control component (411) that receives a cold reset signal and controls all components and all IP blocks of the system-on-chip device to be reset, a soft reset control component (412) that receives a soft reset signal and controls some components and some IP blocks of the system-on-chip device to be reset, a PMR internal logic circuit (413) which is a logic circuit within the root power manager itself, and a PMD connection component (414) that manages the connection with the domain power manager. A domain power manager (420) may be connected to the root power manager (410) through the PMD connection component (414). In the drawing, one domain power manager (420) is connected to the root power manager (410), but multiple domain power managers may be connected through multiple PMD connection components.

[0072] Cold reset signals and soft reset signals can be provided from a function reset generation unit. The cold reset control component (411) and the soft reset control component (412) can control the registers of the root power manager (410) and / or the domain power manager (421) to cause the logic circuits and components controlled by the corresponding registers to be reset. Additionally, the integrated driving circuit controlled by the root power manager (410) can be further reset.

[0073] The domain power manager (420) may include a PMD internal logic circuit (421) which is a logic circuit within the domain power manager itself, a CMU link control component (422) which controls the link with the clock management unit (220), and a reset component (423) for sending a reset signal to the IP block (250).

[0074] The first and second power management interfaces (430, 440) may include internal logic circuits, such as PMIF internal logic circuits (431, 441).

[0075] As previously described, the root power manager (410) and at least one domain power manager (420) are physically placed in the same AON (Always-On) domain area, the first power management interface (430) and the clock management unit (220) are physically placed in the same power domain area, and the second power management interface (440) and the IP block (250) are physically placed in the same power domain area.

[0076] In the present invention, reset domains can be distinguished based on physical power domain areas. That is, the root power manager (410) and the domain power manager (420) can form one reset domain, the first power management interface (430) and the clock management unit (220) can form one reset domain, and the second power management interface (440) and the IP block (250) can form one reset domain.

[0077] FIG. 5 is a configuration block diagram illustrating a reset test system applied to a reset domain including a root power manager and a domain power manager according to the present invention.

[0078] The reset test system may include a plurality of target reset controllers (511, 512, 513, 514) that are positioned in front of the target, receive a function reset and a function clock of the target, and selectively output a function reset or a test reset synchronized with the function clock. These target reset controllers (511, 512, 513, 514) may be positioned in the function reset path of any target. The function reset path of any target may include at least one target reset controller.

[0079] The target may include components (411, 412, 414) constituting the root power manager (410), a PMR internal logic circuit (413), components (422, 423) constituting the domain power manager (420), a PMD internal logic circuit (421), etc. For example, the function reset path of the domain power manager (420) may include a PMD connection component (414), and three target reset controllers (512, 513, 514) may be placed in the function reset path of the domain power manager (420).

[0080] The target reset controller (511) has a cold reset control component (411) as a target and can selectively output a function reset or test reset synchronized with the function clock of the cold reset control component (411) to the cold reset control component (411). The target reset controller (512) has a soft reset control component (412) and a PMR internal logic circuit (413) as targets and can selectively output a function reset or test reset synchronized with the function clock of the target to both targets. The target reset controller (513) has a PMD connection component (414) as a target and can selectively output a function reset or test reset synchronized with the function clock of the PMD connection component (414) to the PMD connection component (414). The target reset controller (514) has a domain power manager (420) as a target and can selectively output a function reset or test reset synchronized with the function clock of the domain power manager to the domain power manager (420).

[0081] At the reset input of each target reset controller, a function reset generating unit (210) sets a register, and the value of the corresponding register can be input as a function reset. Additionally, if two or more target reset controllers (511) are connected in a forward and backward manner, the reset output of the target reset controller in the forward stage may be provided as the reset input of the target reset controller in the backward stage.

[0082] The reset test system includes a scan test controller (520) that outputs a scan test enable signal (ltest_en) indicating whether the scan test mode is enabled, a scan reset control signal (ltest_reset) that controls the reset in the scan test mode, and a scan reset disable signal (ltest_rstdisable) that controls the reset to be disabled in the scan test mode to target reset controllers (511, 512, 513, 514), and a target reset test controller (530) that outputs a target reset test mode signal (TEST_MODE) indicating whether the target is in test mode and reset test data of the target (TEST_MODE_RESET) to target reset controllers (511, 512, 513, 514).

[0083] FIG. 6 is a configuration block diagram illustrating a reset test system applied to a reset domain including a second power management interface and an IP block according to the present invention.

[0084] The reset test system may include a plurality of target reset controllers (611, 612) that are positioned at the front end of the target, receive a function reset and a function clock of the target, and selectively output a function reset or a test reset synchronized with the function clock. These target reset controllers (611, 612) may be positioned in the function reset path of any target. The function reset path of any target may include at least one target reset controller. The target may include the PMIF internal logic circuit (441) and IP block (250) of the second power management interface.

[0085] The reset test system further includes a scan test controller (520) that outputs a scan test enable signal (ltest_en) indicating whether the scan test mode is enabled, a scan reset control signal (ltest_reset) that controls the reset in the scan test mode, and a scan reset disable signal (ltest_rstdisable) that controls the reset to be disabled in the scan test mode to target reset controllers (611, 612), and a target reset test controller (620) that outputs a target reset test mode signal (TEST_MODE) indicating whether the target is in test mode and reset test data of the target (TEST_MODE_RESET) to target reset controllers (611, 612).

[0086] The scan test controller (520) of FIG. 5 and the scan test controller (520) of FIG. 6 may be the same component. The target reset test controller (530) of FIG. 5 and the target reset test controller (620) of FIG. 6 perform the same function, but it is preferable to have separate target reset test controllers (530, 620) for each reset domain.

[0087] FIG. 7 is a block diagram of a reset test system including one target reset controller according to the present invention.

[0088] The reset test system according to the present invention includes a scan test controller (710) that outputs a scan test enable signal (ltest_en) indicating whether the scan test mode is activated, a scan reset control signal (ltest_reset) that controls the reset in the scan test mode, and a scan reset disable signal (ltest_rstdisable) that controls the reset to be disabled in the scan test mode; a target reset test controller (720) that outputs a target reset test mode signal (TEST_MODE) indicating whether the target is in test mode and target reset test data (TEST_MODE_RESET); and a target reset controller (730) that enables the reset function in the scan test mode and enables the target reset test data to be output to the target while the target reset test mode is activated, based on the scan test enable signal, the scan reset control signal, the scan reset disable signal, the target reset test mode signal, the target reset test data, and the reset input (RESET_IN).

[0089] The target reset controller (730) includes a synchronization unit (733) that synchronizes the function reset with the target's function clock, and the synchronization unit (733) is reset while the reset function is activated in scan test mode.

[0090] The target reset test controller (720) may include a test mode TDR (test data register) (721) that outputs a target reset test mode signal (TEST_MODE) indicating whether the target reset test mode is enabled or disabled, and a test control TDR (test data register) (722) that outputs target reset test data (TEST_MODE_RESET) when the target is enabled in reset test mode.

[0091] The target reset test controller (720) may be a controller based on the built-in IEEE1687 standard. The target reset test controller (720) can configure the test mode TDR (721) and test control TDR (722) through the IJTAG (Internal Joint Test Action Group) interface.

[0092] The test mode TDR (721) can be configured as a flip-flop and can output a target reset test mode signal to the target reset controller (730) indicating the activation / deactivation of the target reset test mode. That is, the target reset test mode signal can be a 1-bit signal.

[0093] The test control TDR (722) can be configured as a flip-flop and can output target reset test data (TEST_MODE_RESET) to the target reset controller (730). The reset test data may be a value that determines whether to reset the target or not when the reset test mode is enabled. Therefore, the target reset test data may be a 1-bit signal.

[0094] The target reset controller (730) may include a first test multiplexer (TMUX) (731) in which a scan reset control signal (ltest_reset) and a reset input (RESET_IN) are input to respective input terminals and a scan test enable signal (ltest_en) is input to a selection terminal, and which outputs one of the scan reset control signal (ltest_reset) and the reset input (RESET_IN) according to the scan test enable signal (ltest_en); and a first logical OR operator (732) that performs a logical OR operation on the output of the first test multiplexer (731) and a scan reset disable signal (ltest_rstdisable) and outputs the result to a synchronization unit (733). A function reset may be input from a register as the reset input (RESET_IN).

[0095] If the scan test enable signal (ltest_en) is in scan test activation mode, the first test multiplexer (731) selects and outputs a scan reset control signal, and if the scan test enable signal (ltest_en) is not in scan test activation mode, the first test multiplexer (731) selects and outputs a reset input (RESET_IN). The first logical OR operator (732) outputs 'High' if at least one of the output of the first test multiplexer (731) and the scan reset disable signal (ltest_rstdisable) is 'High'.

[0096] Thus, when the scan test is activated, the first test multiplexer (731) and the first logical OR operator (732) can control the scan reset control signal to reset the synchronization unit (733).

[0097] When the scan test is not activated, a reset input (RESET_IN) is input to the synchronization unit (733), and the synchronization unit (733) synchronizes the reset input with the target's function clock (CLK) and outputs it.

[0098] The target reset controller (730) includes a second logical OR operator (734) that performs a logical OR operation on the output of the synchronization unit (733) and the scan reset disable signal (ltest_rstdisable), and a second test multiplexer (735) in which the output of the second logical OR operator (734) and the target reset test data (TEST_MODE_RESET) are input to respective input terminals, a target reset test mode (TEST_MODE) signal is input to a selection terminal, and one of the output of the second logical OR operator (734) and the target reset test data (TEST_MODE_RESET) is output as a reset output (RESET_OUT) according to the target reset test mode (TEST_MODE) signal.

[0099] The operation of the reset test system according to the present invention is described below.

[0100] In the functional mode of the system-on-chip device, the first test multiplexer (731) outputs a reset input, and the first logical OR operator (732) performs a logical OR operation on the reset input and the scan reset disable signal and transmits it to the synchronization unit (733). The synchronization unit (733) outputs the reset input synchronized with the target's functional clock (CLK), which is then output to the target through the second logical OR operator (734) and the second test multiplexer (735).

[0101] Reset control of a system-on-chip device can be divided into reset control in function mode and reset control in test mode. Reset control in test mode can be divided into cases where the reset signal is controlled in general test mode and cases where the reset signal is controlled in scan test mode among test modes. In addition, scan test mode can be divided into a mode where the scan reset control signal is changed to 'low' or 'high' (Scan Capture mode) and a mode where the scan reset control signal must be fixed at 'high' (Scan Shift mode).

[0102] When the reset signal needs to be controlled in function mode, the scan test enable signal (ltest_en) becomes 'low', the scan reset disable signal (ltest_rstdisable) becomes 'low', and the target reset test mode (TEST_MODE) becomes 'low', and the reset input (RESET_IN) passes through the synchronization unit (733) and is synchronized with the function clock (CLK) and transmitted to the reset output (RESET_OUT).

[0103] When the reset signal needs to be controlled in the general test mode, the scan test enable signal (ltest_en) becomes 'low', the scan reset disable signal (ltest_rstdisable) becomes 'low', and the target reset test mode (TEST_MODE) becomes 'high', and the target reset test data (TEST_MODE_RESET) is output to the reset output (RESET_OUT) from the second test multiplexer (735).

[0104] When the scan reset control signal needs to be controlled in scan test mode, the scan test enable signal (ltest_en) becomes 'high', the scan reset disable signal (ltest_rstdisable) becomes 'low', and the target reset test mode (TEST_MODE) becomes 'low'. At this time, the first test multiplexer (731) and the first logical OR operator (732) select and output the scan reset control signal (ltest_reset) to supply the scan reset control signal (ltest_reset) to the synchronization unit (733). The synchronization unit (733) outputs the scan reset control signal (ltest_reset), and the second test multiplexer (735) outputs the scan reset control signal (ltest_reset) as a reset output (RESET_OUT).

[0105] When the scan reset signal needs to be fixed to 'high', the scan test enable signal (ltest_en) becomes 'high', the scan reset disable signal (ltest_rstdisable) becomes 'high', and the target reset test mode (TEST_MODE) becomes 'low'. At this time, the first logical OR operator (732) and the second logical OR operator (734) can always output 1 to fix the scan reset signal to 'high'.

[0106] Many variations and modifications may be made to the embodiments described above, and such elements should be understood as being one of other acceptable examples. All such modifications and variations are intended to be included within the scope of this disclosure and protected by the following claims. The embodiments according to the invention described above may be implemented in the form of program instructions that can be executed through various computer components and recorded on a computer-readable recording medium. A computer-readable recording medium may include program instructions, data files, data structures, etc., either alone or in combination. Program instructions recorded on a computer-readable recording medium may be those specifically designed and configured for the invention or may be those known and available to those skilled in the art of computer software. Examples of computer-readable recording media include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specifically configured to store and execute program instructions, such as ROM, RAM, and flash memory. Examples of program instructions include machine code, such as that generated by a compiler, as well as high-level language code that can be executed by a computer using an interpreter, etc. The hardware device may be configured to operate as one or more software modules to perform processing according to the present invention, and vice versa.

[0107] Although the present invention has been described above with specific details such as specific components, limited embodiments, and drawings, this is provided only to aid in a more comprehensive understanding of the invention, and the invention is not limited to the above embodiments, and a person skilled in the art to which the invention belongs can make various modifications and variations from this description.

[0108] Accordingly, the scope of the present invention is not limited to the embodiments described above, and all modifications equivalent to or equivalent to the claims set forth below, as well as the claims described below, shall be considered to fall within the scope of the scope of the present invention. Explanation of the symbols

[0109] 511, 512, 513, 514, 611, 612, 730: Target reset controller 520, 710: Scan test controller 530, 620, 720: Target Reset Test Controller 731: First test multiplexer 732: First logical OR operator 733: Synchronization unit 734: 2nd OR operator 735: 2nd Test Multiplexer 721: Test Mode TDR 722: Test Control TDR

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