Semiconductor package device and method of manufacturing the same

Abstract

A semiconductor package device and a method for manufacturing the same are disclosed. The disclosed semiconductor package device may include a circuit board unit comprising a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction, a molding layer disposed to form a single substrate shape together with the circuit board unit while filling the surrounding space of the circuit board unit and exposing the circuit board unit, a redistribution layer member disposed on a first surface of a package substrate comprising the circuit board unit and the molding layer, and a plurality of chips mounted on the redistribution layer member to be electrically connected to the redistribution layer member.

Description

Technology Field

[0001] The present invention relates to technology and methods related to semiconductor packages, and more specifically, to a substrate for a semiconductor package, a semiconductor package device including the same, and a method for manufacturing the same. Background Technology

[0002] Semiconductor manufacturing processes can be divided into front-end processes, which involve manufacturing wafers and etching circuits, and back-end processes, which involve packaging chips. As semiconductor miniaturization technology approaches its limits, the importance of back-end processes is increasing. In this regard, advanced packaging technologies that integrate different semiconductor chips or vertically connect multiple chips are emerging as critical technologies. Recently developed AI (artificial intelligence) and HPC (high performance computing) products can be composed of System-on-Chip (SoC) components such as High Bandwidth Memory (HBM), CPUs (Central Processing Units), Neural Processing Units (NPUs), and Graphics Processing Units (GPUs).

[0003] 2.5D (2.5-dimensional) packaging is a packaging technology that integrates multiple semiconductor chips (dies) into a single package by arranging them horizontally. The difference between 2.5D packaging and 3D packaging is that each chip is placed on an interposer, which is a packaging component. Logic chips and memory chips, among others, can be arranged horizontally on the interposer. Connectivity between chips can be improved by connecting each chip through interconnect technology.

[0004] CoWoS (chip-on-wafer-on-substrate), a type of 2.5D packaging technology, refers to the process of interconnecting two or more semiconductor chips on a wafer and then placing them on a package substrate. Memory and logic chips can be mounted planarly or stacked vertically on the interposer. To implement CoWoS, interposer technology (e.g., silicon interposer), which connects multiple chips as if they were a single die, is used as a core component. Although an interposer is a type of substrate, it is characterized by handling only signal connections without logic functions.

[0005] Interposers utilize TSVs (through silicon vias) or TMVs (through mold vias) for electrical connections and feature a configuration that increases the ball pitch. Furthermore, most cases involving the use of interposers for the interconnection of heterogeneous chips are processed at the wafer level. However, all these methods and processes have disadvantages such as low productivity, inefficiency, and relatively high production costs. Additionally, 2.5D packaging technology utilizing conventional interposers has limitations in that it is difficult to adapt to various design changes and improve performance. Prior art literature

[65535] Korean Published Patent Application No. 10-2018-0079007 The problem to be solved

[0006] The technical problem that the present invention aims to solve is to provide a semiconductor package device and a method for manufacturing the same that can increase cost efficiency and productivity and improve the performance of the device.

[0007] Furthermore, the technical problem that the present invention aims to solve is to provide a semiconductor package device and a method for manufacturing the same that can easily respond to various design changes, be easy to manufacture, and secure excellent electrical performance.

[0008] The problems that the present invention aims to solve are not limited to those mentioned above, and other unmentioned problems will be understood by those skilled in the art from the description below. means of solving the problem

[0009] According to one embodiment of the present invention, a semiconductor package device is provided, comprising: a circuit board unit including a plurality of conductive via elements extended in a vertical direction and a plurality of conductive pattern layer elements extended in a horizontal direction; a molding layer disposed to expose the circuit board unit while filling the surrounding space of the circuit board unit and forming a single substrate shape together with the circuit board unit; a redistribution layer member disposed on a first surface of a package substrate configured to include the circuit board unit and the molding layer; and a plurality of chips mounted on the redistribution layer member to be electrically connected to the redistribution layer member.

[0010] The above circuit board unit may be a printed circuit board (PCB) unit including an organic substrate.

[0011] The circuit board unit may include the organic substrate, one or more first insulating layers disposed on a first surface of the organic substrate, and one or more second insulating layers disposed on a second surface of the organic substrate opposite to the first surface, and the plurality of conductive via elements and the plurality of conductive pattern layer elements may be formed inside and between the organic substrate, the one or more first insulating layers, and the one or more second insulating layers.

[0012] The circuit board unit may include at least one of one or more embedded passive element elements and one or more embedded active element elements.

[0013] The above circuit board unit may include at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication.

[0014] A plurality of bumps may be provided on one surface of each of the plurality of chips, and the plurality of chips may be mounted on the rearrangement layer member such that the plurality of bumps are electrically connected to the rearrangement layer member.

[0015] The above plurality of chips may include heterogeneous chips.

[0016] A plurality of electrical connection elements electrically connected to the circuit board unit may be disposed on the second surface opposite to the first surface of the package substrate.

[0017] The semiconductor package device may further include: a separate rearrangement layer member disposed on a second surface opposite to the first surface of the package substrate; and a plurality of electrical connection elements disposed on the separate rearrangement layer member to be electrically connected to the separate rearrangement layer member.

[0018] The semiconductor package device may further include at least one of: at least one first passive element member disposed within the molding layer around the circuit board unit and electrically connected to the rearrangement layer member; and at least one second passive element member disposed on a second surface opposite to the first surface of the package substrate to be electrically connected to the circuit board unit.

[0019] According to another embodiment of the present invention, a method for manufacturing a semiconductor package device is provided, comprising: a step of providing a plurality of circuit board units, each including a plurality of conductive via elements extended in a vertical direction and a plurality of conductive pattern layer elements extended in a horizontal direction; a step of arranging the plurality of circuit board units on a carrier substrate so as to be spaced apart from each other in a horizontal direction, wherein each of the plurality of circuit board units is arranged in a plurality of unit package regions arranged in a two-dimensional manner; a step of forming a molding layer on the carrier substrate that fills the space between and around the plurality of circuit board units and together with them to form a single substrate shape; a step of forming a redistribution layer member on a first surface of a package substrate configured to include the plurality of circuit board units and the molding layer; a step of mounting a plurality of chips on the redistribution layer member for each of the plurality of unit package regions so as to be electrically connected to the redistribution layer member; and a step of dividing a device structure including the plurality of circuit board units, the molding layer, the redistribution layer member, and the plurality of chips into package device units corresponding to each of the plurality of unit package regions while the carrier substrate is excluded.

[0020] The above circuit board unit may be a printed circuit board (PCB) unit including an organic substrate.

[0021] The circuit board unit may include the organic substrate, one or more first insulating layers disposed on a first surface of the organic substrate, and one or more second insulating layers disposed on a second surface of the organic substrate opposite to the first surface, and the plurality of conductive via elements and the plurality of conductive pattern layer elements may be formed inside and between the organic substrate, the one or more first insulating layers, and the one or more second insulating layers.

[0022] The circuit board unit may include at least one of one or more embedded passive element elements and one or more embedded active element elements.

[0023] The above circuit board unit may include at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication.

[0024] A plurality of bumps may be provided on one surface of each of the plurality of chips, and the plurality of chips may be mounted on the rearrangement layer member such that the plurality of bumps are electrically connected to the rearrangement layer member.

[0025] The above plurality of chips may include heterogeneous chips.

[0026] The method for manufacturing the semiconductor package device may further include the step of forming a plurality of electrical connection elements electrically connected to the circuit board unit on the second surface opposite to the first surface of the substrate for the package for each of the plurality of unit package regions.

[0027] The method for manufacturing the semiconductor package device may further include the step of forming a separate rearrangement layer member on a second surface opposite to the first surface of the package substrate; and the step of forming a plurality of electrical connection elements electrically connected to the separate rearrangement layer member on the separate rearrangement layer member for each of the plurality of unit package regions.

[0028] The method for manufacturing the semiconductor package device described above may further include at least one of the steps of: arranging the plurality of circuit board units on the carrier substrate, wherein for each of the plurality of unit package regions, at least one first passive element member is arranged on the carrier substrate surrounding the circuit board unit; and for each of the plurality of unit package regions, at least one second passive element member is arranged on the second surface of the package substrate opposite to the first surface and is electrically connected to the circuit board unit.

[0029] The method for manufacturing the semiconductor package device described above may further include the step of removing the carrier substrate from the plurality of circuit board units and the molding layer between the step of forming the molding layer and the step of dividing the device structure into package device units.

[0030] An initial molding layer covering the plurality of circuit board units is formed, and a grinding or ablation process is performed on the initial molding layer to expose one side of the plurality of circuit board units. Effects of the invention

[0031] According to embodiments of the present invention, a semiconductor package device and a method for manufacturing the same can be realized, which can increase cost efficiency and productivity and improve the performance of the device. Furthermore, according to embodiments of the present invention, a semiconductor package device and a method for manufacturing the same can be realized, which can easily accommodate various design changes, be easy to manufacture, and secure excellent electrical performance.

[0032] According to one embodiment, by using a fan-out packaging process including, for example, a printed circuit board (PCB) process and a rearrangement layer (RDL) process, a cost-effective and high-productivity method for manufacturing a semiconductor package device that interconnects heterogeneous chips can be implemented. According to one embodiment, for example, by using a circuit board unit including embedded passive and active elements, the electrical performance of the package device interconnecting heterogeneous chips can be improved, process efficiency can be improved, and ease of design change can be improved. According to one embodiment, for example, by using a circuit board unit including at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication, the electrical performance of the package device interconnecting heterogeneous chips can be improved. The technology according to the embodiments can be usefully applied to various advanced packaging fields.

[0033] However, the effects of the present invention are not limited to the above effects and can be extended in various ways without departing from the technical concept and scope of the present invention. Brief explanation of the drawing

[0034] FIG. 1 is a cross-sectional view illustrating an exemplary semiconductor package device according to one embodiment of the present invention. FIG. 2 is a cross-sectional view illustrating, by way of example, a circuit board unit that can be applied to a semiconductor package device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating an exemplary semiconductor package device according to another embodiment of the present invention. FIG. 4 is a cross-sectional view illustrating, exemplarily, a circuit board unit that can be applied to a semiconductor package device according to another embodiment of the present invention. FIG. 5 is a cross-sectional view illustrating, exemplarily, a circuit board unit that can be applied to a semiconductor package device according to another embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating an exemplary semiconductor package device according to another embodiment of the present invention. FIG. 7 is a cross-sectional view illustrating, exemplarily, a circuit board unit that can be applied to a semiconductor package device according to another embodiment of the present invention. FIGS. 8a to 8g are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package device according to one embodiment of the present invention. FIGS. 9a to 9g are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package device according to another embodiment of the present invention. FIGS. 10a to 10h are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package device according to another embodiment of the present invention. Specific details for implementing the invention

[0035] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

[0036] The embodiments of the present invention described below are provided to more clearly explain the present invention to those skilled in the art, and the scope of the present invention is not limited by the following embodiments, and the following embodiments may be modified in various other forms.

[0037] The terms used herein are for describing specific embodiments and are not intended to limit the invention. Terms used herein in the singular form may include plural forms unless the context clearly indicates otherwise. Additionally, the terms “comprise” and / or “comprising” used herein specify the presence of the mentioned features, steps, numbers, actions, components, elements, and / or groups thereof, and do not exclude the presence or addition of one or more other features, steps, numbers, actions, components, elements, and / or groups thereof. Furthermore, the term “connected” used herein means not only that components are directly connected, but also includes the concept of indirectly connecting components through the interposition of additional components between them.

[0038] Furthermore, when a component is described in this specification as being located "on" another component, this includes not only cases where a component is in contact with another component, but also cases where another component exists between the two components. The term "and / or" as used in this specification includes any one of the listed items and all combinations of one or more thereof. Additionally, terms of degree such as "about" and "substantially" as used in this specification are used to mean a range of numerical values ​​or degrees or approximate values, taking into account inherent manufacturing and material tolerances, and are used to prevent an infringer from unfairly exploiting the disclosures in which precise or absolute figures provided to aid in understanding this specification are mentioned.

[0039] Embodiments of the present invention will be described in detail below with reference to the attached drawings. The sizes or thicknesses of the areas or parts depicted in the attached drawings may be slightly exaggerated for the clarity of the specification and convenience of explanation. Throughout the detailed description, the same reference numerals indicate the same components.

[0040] FIG. 1 is a cross-sectional view illustrating an exemplary semiconductor package device according to one embodiment of the present invention.

[0041] Referring to FIG. 1, a semiconductor package device according to an embodiment of the present invention may include a circuit board unit (CS10). The circuit board unit (CS10) may include a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction. The circuit board unit (CS10) may be, for example, a printed circuit board (PCB) unit including an organic substrate. The circuit board unit (CS10) may be manufactured through a PCB manufacturing process. The circuit board unit (CS10) will be described in more detail later with reference to FIG. 2.

[0042] The semiconductor package device may include a molding layer (M10) that forms a single substrate shape together with the circuit board unit (CS10) while filling the surrounding space of the circuit board unit (CS10). The molding layer (M10) may be positioned to expose the circuit board unit (CS10). For example, the molding layer (M10) may expose the upper and lower surfaces of the circuit board unit (CS10). The molding layer (M10) may have the same thickness or substantially the same thickness as the circuit board unit (CS10) and may serve to surround and secure the circuit board unit (CS10). The molding layer (M10) may include a polymer material. For example, the molding layer (M10) may include a molding compound.

[0043] The circuit board unit (CS10) and the molding layer (M10) can be said to constitute a single package substrate (S100). In other words, the package substrate (S100) can be configured to include the circuit board unit (CS10) and the molding layer (M10).

[0044] The semiconductor package device may include a redistribution layer (RDL) member (R10) disposed on a first surface of a package substrate (S100). The first surface of the package substrate (S100) may be either one of two main surfaces (upper surface and lower surface) of the package substrate (S100). The redistribution layer member (R10) may serve to redistribute the electrode pad arrangement of a circuit board unit (CS10). The redistribution layer member (R10) may be formed through processes such as forming an insulating layer having via holes (openings), forming a seed layer, forming a mask pattern, electroplating a wiring layer, and removing a mask pattern. Although the redistribution layer member (R10) is simply illustrated in FIG. 1, the redistribution layer member (R10) may include a structure in which an insulating layer (e.g., an organic insulating layer) and a wiring member layer (wiring element layer) are alternately stacked one or more times. A plurality of via holes (openings) may be formed in the insulating layer, and a conductive via element may be provided within the via holes. The conductive via element may serve as a vertical wiring. The conductive via element may also be referred to as a 'via-type wiring' or a 'via plug'.

[0045] The rearrangement layer member (R10) may include a plurality of electrode pads (P10) exposed on its surface. The plurality of electrode pads (P10) may be positioned on the opposite side of where the package substrate (S100) is placed and may be arranged two-dimensionally. At least some of the plurality of electrode pads (P10) may be electrically connected to a circuit board unit (CS10). The rearrangement layer member (R10) may serve to provide a plurality of electrode pads (P10) having a fine pitch.

[0046] The above semiconductor package device may include a plurality of chips (C10) mounted on a rearrangement layer member (R10) so as to be electrically connected to the rearrangement layer member (R10). The plurality of chips (C10) may be semiconductor chips and may be referred to as dies. According to one example, a plurality of bumps (B10) may be provided on one side of each of the plurality of chips (C10). In other words, each of the plurality of chips (C10) may include a plurality of bumps (B10) disposed on one side thereof. The plurality of bumps (B10) may be microbumps, and may have at least partially a ball shape or other shape. The plurality of bumps (B10) may be a type of electrical connection element. The plurality of chips (C10) may be mounted on the rearrangement layer member (R10) so that the plurality of bumps (B10) are electrically connected to the rearrangement layer member (R10). As a plurality of bumps (B10) are connected to a plurality of electrode pads (P10), the chip (C10) can be electrically connected to the circuit board unit (CS10) through the rearrangement layer member (R10).

[0047] According to one embodiment, the plurality of chips (C10) may include heterogeneous chips. For example, the plurality of chips (C10) may include memory chips and logic chips, and may further include other types of chips. The plurality of chips (C10) may be arranged so as to be spaced apart from each other in a horizontal direction on a rearrangement layer member (R10), and in some cases, one or more chips (i.e., dies) may be further stacked (mounted) on at least one of the plurality of chips (C10). In a semiconductor package device according to an embodiment of the present invention, the package substrate (S100) on which the rearrangement layer member (R10) is formed may be a semiconductor package substrate having an interposer function and may be used for a 2.5D package or a 3D package. According to an embodiment of the present invention, heterogeneous chips can be easily interconnected.

[0048] The semiconductor package device may further include a plurality of electrical connection elements (E10) disposed on a second surface opposite to the first surface of the package substrate (S100). Here, the second surface of the package substrate (S100) may be either one of the two main surfaces (upper surface and lower surface) of the package substrate (S100). The plurality of electrical connection elements (E10) may be disposed to be electrically connected / contacted with a circuit board unit (CS10). The plurality of electrical connection elements (E10) may include, as a non-limiting example, a solder ball or a bump. The plurality of electrical connection elements (E10) may be connected to a predetermined circuit board (e.g., a motherboard).

[0049] According to an embodiment of the present invention, a single package substrate (S100) is formed using a circuit board unit (CS10) and a molding layer (M10), and then a rearrangement layer member (R10) is formed thereon, and a plurality of chips (C10) can be mounted thereon. The plurality of chips (C10) may include two or more chips, and, for example, may be mounted in a flip-chip manner. According to such an embodiment of the present invention, a semiconductor package substrate having an interconnection function of a plurality of chips (C10) can be easily manufactured, the performance of the device can be improved, and the ease of design modification can be enhanced. In this regard, according to an embodiment of the present invention, a semiconductor package device and a method for manufacturing the same can be realized that can increase cost efficiency and productivity and improve the performance of the device. Furthermore, according to an embodiment of the present invention, a semiconductor package device and a method for manufacturing the same can be realized that are easy to respond to various design modifications, easy to manufacture, and advantageous for performance improvement.

[0050] According to one embodiment, the semiconductor package device may further include at least one of a first passive element member (PV10) disposed within a molding layer (M10) around a circuit board unit (CS10) and electrically connected to a rearrangement layer member (R10), and at least one second passive element member (PV20) disposed on a second surface opposite to the first surface of the package substrate (S100) to be electrically connected to the circuit board unit (CS10). Since the first and second passive element members (PV10, PV20) may be disposed outside the circuit board unit (CS10), they may be referred to as 'outer passive elements'. The first passive element member (PV10) may be in contact with the rearrangement layer member (R10) and may be connected to at least one of a plurality of chips (C10) through the rearrangement layer member (R10). The second passive element member (PV20) may be attached to the second surface of the package substrate (S100) together with a plurality of electrical connection elements (E10) and electrically connected / contacted with the circuit board unit (CS10). The first and second passive element members (PV10, PV20) may be capacitors or include capacitors, as a non-limiting example. By using at least one of the first and second passive element members (PV10, PV20), the electrical performance of the semiconductor package device can be improved.

[0051] FIG. 2 is a cross-sectional view illustrating, in an exemplary manner, a circuit board unit (CS10) that can be applied to a semiconductor package device according to one embodiment of the present invention.

[0052] Referring to FIG. 2, the circuit board unit (CS10) may be a PCB unit including an organic substrate (ML10). The organic substrate (ML10) may include a polymer (plastic) material. The circuit board unit (CS10) may include an organic substrate (ML10), one or more first insulating layers (NL10) disposed on a first surface of the organic substrate (ML10), and one or more second insulating layers (NL20) disposed on a second surface of the organic substrate (ML10) opposite to the first surface. The organic substrate (ML10) may be referred to as a core material layer (intermediate material layer). One or more first insulating layers (NL10) may be laminated on one surface (first surface) of the organic substrate (ML10), and one or more second insulating layers (NL20) may be laminated on the other surface (second surface) of the organic substrate (ML10). The first and second insulating layers (NL10, NL20) may be organic material layers.

[0053] A circuit board unit (CS10) may include a plurality of conductive via elements (V10) and a plurality of conductive pattern layer elements (L10) formed inside and between an organic substrate (ML10), one or more first insulating layers (NL10), and one or more second insulating layers (NL20). The plurality of conductive via elements (V10) may extend in a vertical direction, and the plurality of conductive pattern layer elements (L10) may extend in a horizontal direction. Conductive via elements (V10) may be formed inside one or more first insulating layers (NL10) and one or more second insulating layers (NL20) while stacking them on the organic substrate (ML10), and conductive pattern layer elements (L10) may be formed between them. The plurality of conductive via elements (V10) and the plurality of conductive pattern layer elements (L10) may form various types of wiring. Additionally, some of the conductive via elements (V10) may be formed to penetrate the organic substrate (ML10) or the circuit board unit (CS10). The circuit board unit (CS10) may be said to have a plurality of via-type wiring elements extended in a vertical direction. The plurality of via-type wiring elements may have a shape connecting the lower surface and the upper surface of the circuit board unit (CS10). The circuit board unit (CS10) can be easily manufactured through a PCB manufacturing process.

[0054] FIG. 3 is a cross-sectional view illustrating an exemplary semiconductor package device according to another embodiment of the present invention.

[0055] Referring to FIG. 3, a semiconductor package device according to the present embodiment may include a circuit board unit (CS11). The circuit board unit (CS11) may include a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction. The circuit board unit (CS11) may be, for example, a PCB unit including an organic substrate. In the present embodiment, the circuit board unit (CS11) may include at least one embedded passive element (PD10) and / or at least one embedded active element (AD10). The circuit board unit (CS11) may include both at least one embedded passive element (PD10) and at least one embedded active element (AD10). The passive element (PD10) may include, for example, a capacitor, a resistor, an inductor, an integrated passive device (IPD), etc., without limitation. The above active element (AD10) may include, for example but not limited to, transistors, diodes, operational amplifiers, integrated circuits (ICs), etc. Any general passive or active element used in semiconductor devices may be applicable. The circuit board unit (CS11) may be manufactured in advance according to circuit board manufacturing technology.

[0056] The circuit board unit (CS11) and the molding layer (M10) can be said to constitute a single package substrate (S101). In other words, the package substrate (S101) may be configured to include the circuit board unit (CS11) and the molding layer (M10). In FIG. 3, the remaining configuration excluding the circuit board unit (CS11) may be the same or similar as described in FIG. 1.

[0057] When the circuit board unit (CS11) is configured to include at least one embedded passive element (PD10) and / or at least one embedded active element (AD10), the electrical performance and functionality of the semiconductor package device can be further improved.

[0058] FIG. 4 is a cross-sectional view illustrating, exemplarily, a circuit board unit (CS11) that can be applied to a semiconductor package device according to another embodiment of the present invention.

[0059] Referring to FIG. 4, the circuit board unit (CS11) may basically have a configuration similar to the circuit board unit (CS10) described in FIG. 2. The circuit board unit (CS11) may include an organic substrate (ML10), one or more first insulating layers (NL10) disposed on a first surface of the organic substrate (ML10), and one or more second insulating layers (NL20) disposed on a second surface of the organic substrate (ML10) opposite to the first surface, and may include a plurality of conductive via elements (V10) and a plurality of conductive pattern layer elements (L10) formed inside and between the organic substrate (ML10), one or more first insulating layers (NL10), and one or more second insulating layers (NL20).

[0060] Additionally, the circuit board unit (CS11) may include at least one embedded passive element (PD10) and at least one embedded active element (AD10). For example, at least some of the passive element (PD10) and the active element (AD10) may be embedded within an organic substrate (ML10). However, the formation / placement locations of the passive element (PD10) and the active element (AD10) are not limited to those depicted and may vary.

[0061] FIG. 5 is a cross-sectional view illustrating, exemplarily, a circuit board unit (CS11') that can be applied to a semiconductor package device according to another embodiment of the present invention.

[0062] Referring to FIG. 5, the circuit board unit (CS11') may include at least one embedded passive element (PD10) and at least one embedded active element (AD10). At least some of the passive element (PD10) and the active element (AD10) may be embedded within the circuit board unit (CS11') outside the organic substrate (ML10).

[0063] FIG. 6 is a cross-sectional view illustrating an exemplary semiconductor package device according to another embodiment of the present invention.

[0064] Referring to FIG. 6, a semiconductor package device according to the present embodiment may include a circuit board unit (CS12). The circuit board unit (CS12) may include a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction. The circuit board unit (CS12) may be, for example, a PCB unit including an organic substrate. In the present embodiment, the circuit board unit (CS12) may be configured to include at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication. The frequency filter may be, for example, a radio frequency (RF) filter, but is not limited thereto. The communication FEM may be, for example, an RF front-end module (FEM), but is not limited thereto. The communication FEM may include an antenna member and a frequency filter member. The antenna, frequency filter, and communication FEM may be formed through device embedding technology or other device formation technology. Additionally, the circuit board unit (CS12) may further include a plurality of conductive pillar elements (PL10) formed on its surface (one surface). The plurality of conductive pillar elements (PL10) may include, for example, a metal or metallic material such as copper (Cu). The circuit board unit (CS12) may be manufactured in advance according to circuit board manufacturing technology.

[0065] The molding layer (M10) can be formed to fill the spaces between and around a plurality of conductive pillar elements (PL10), and the ends of the plurality of conductive pillar elements (PL10) may be exposed without being covered by the molding layer (M10). Accordingly, one side of the circuit board unit (CS12) having a plurality of conductive pillar elements (PL10) formed thereon can be seen as being exposed by the molding layer (M10).

[0066] The circuit board unit (CS12) and the molding layer (M10) can be said to constitute a single package substrate (S102). In other words, the package substrate (S102) can be configured to include the circuit board unit (CS12) and the molding layer (M10).

[0067] A rearrangement layer member (R10) may be disposed on a first surface of a package substrate (S102), and a plurality of chips (C10) may be mounted on the rearrangement layer member (R10). A separate rearrangement layer member (R5) may be disposed on a second surface of the package substrate (S102) opposite to the first surface. The separate rearrangement layer member (R5) may be electrically connected to a circuit board unit (CS12) through at least a plurality of conductive pillar elements (PL10). The separate rearrangement layer member (R5) may include a plurality of electrode pads (P5) exposed on its surface. The plurality of electrode pads (P5) may be disposed on the opposite side of where the package substrate (S102) is disposed and may be arranged in a two-dimensional manner. At least some of the plurality of electrode pads (P5) may be electrically connected to a circuit board unit (CS12).

[0068] A plurality of electrical connection elements (E10) may be disposed on one side of a separate rearrangement layer member (R5) to be electrically connected to the separate rearrangement layer member (R5). The plurality of electrical connection elements (E10) may be disposed on the second side of the package substrate (S102). The plurality of electrical connection elements (E10) may be connected to / contact with a plurality of electrode pads (P5). If necessary, the embodiment of FIG. 6 may also further be provided with at least one of the first passive element member (PV10) and the second passive element member (PV20) as described in FIG. 1.

[0069] In this embodiment, when the circuit board unit (CS12) is configured to include at least one of an antenna, a frequency filter, and a communication FEM, the electrical performance and functionality of the semiconductor package device can be further improved.

[0070] FIG. 7 is a cross-sectional view illustrating, by way of example, a circuit board unit (CS12) that can be applied to a semiconductor package device according to another embodiment of the present invention.

[0071] Referring to FIG. 7, the circuit board unit (CS12) may basically have a configuration similar to the circuit board unit (CS10) described in FIG. 2. The circuit board unit (CS12) may include an organic substrate (ML10), one or more first insulating layers (NL10) disposed on a first surface of the organic substrate (ML10), and one or more second insulating layers (NL20) disposed on a second surface of the organic substrate (ML10) opposite to the first surface, and may include a plurality of conductive via elements (V10) and a plurality of conductive pattern layer elements (L10) formed inside and between the organic substrate (ML10), one or more first insulating layers (NL10), and one or more second insulating layers (NL20).

[0072] Additionally, the circuit board unit (CS12) may be configured to include at least one of an antenna, a frequency filter, and a communication FEM. The antenna, frequency filter, and communication FEM may be formed through device embedding technology or other device formation technology. Additionally, the circuit board unit (CS12) may further include a plurality of conductive pillar elements (PL10) formed on its surface (one side).

[0073] FIGS. 8a to 8g are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package device according to one embodiment of the present invention.

[0074] Referring to FIG. 8a, a plurality of circuit board units (CS10) may be provided. Each of the plurality of circuit board units (CS10) may include a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction. The circuit board unit (CS10) may be, for example, a PCB unit including an organic substrate. The circuit board unit (CS10) can be easily manufactured through a PCB manufacturing process. A plurality of circuit board units (CS10) may be provided by forming circuit layers including circuit patterns on a single board substrate and then dividing (cutting) it. The circuit board unit (CS10) may include the organic substrate, one or more first insulating layers disposed on a first surface of the organic substrate, and one or more second insulating layers disposed on a second surface of the organic substrate opposite to the first surface, and the plurality of conductive via elements and the plurality of conductive pattern layer elements may be formed inside and between the organic substrate, the one or more first insulating layers, and the one or more second insulating layers. The specific configuration of the circuit board unit (CS10) may be the same as described with reference to FIG. 2. A plurality of circuit board units (CS10) may be pre-manufactured according to circuit board manufacturing technology.

[0075] Referring to FIG. 8b, a plurality of circuit board units (CS10) can be arranged on a carrier substrate (T15) such that they are spaced apart from each other in a horizontal direction. A plurality of circuit board units (CS10) can be arranged in a plurality of unit package regions (U10) arranged in a two-dimensional manner. For example, one circuit board unit (CS10) can be arranged in each of the plurality of unit package regions (U10), or one or more circuit board units (CS10) can be arranged. An adhesive layer (A15) can be provided on the carrier substrate (T15), and a plurality of circuit board units (CS10) can be attached on the adhesive layer (A15). In other words, a plurality of circuit board units (CS10) can be attached on the carrier substrate (T15) with the adhesive layer (A15) in between. The carrier substrate (T15) may be a panel or a wafer. The adhesive layer (A15) may be an adhesive film. The adhesive layer (A15) may be considered as part of the carrier substrate (T15).

[0076] In the step of placing a plurality of circuit board units (CS10) on a carrier substrate (T15), at least one first passive element member (PV10) may be placed on the carrier substrate (T15) around the circuit board unit (CS10) for each of the plurality of unit package regions (U10). The first passive element member (PV10) may be attached to an adhesive layer (A15). The first passive element member (PV10) may be a capacitor or include a capacitor, as a non-limiting example.

[0077] Referring to FIG. 8c, a molding layer (M15) can be formed on a carrier substrate (T15) to form a single substrate shape together with a plurality of circuit board units (CS10) while filling the spaces between and around them. When a first passive component member (PV10) is placed on the carrier substrate (T15), the molding layer (M15) can be formed to cover the first passive component member (PV10). The molding layer (M15) may include a polymer material. For example, the molding layer (M15) may include a molding compound. A plurality of circuit board units (CS10) and the molding layer (M15) can be said to constitute a single package substrate (S150). In other words, the package substrate (S150) may be composed of a plurality of circuit board units (CS10) and a molding layer (M15).

[0078] Referring to FIG. 8d, a rearrangement layer member (R15) can be formed on a first surface of a substrate for a package (S150) configured to include a plurality of circuit board units (CS10) and a molding layer (M15). The first surface of the substrate for the package (S150) may be either one of the two main surfaces (upper surface and lower surface) of the substrate for the package (S150). The rearrangement layer member (R15) may serve to rearrange the electrode pad arrangement of the circuit board units (CS10). The rearrangement layer member (R15) may be formed through processes such as forming an insulating layer having via holes (openings), forming a seed layer, forming a mask pattern, electroplating a wiring layer, and removing the mask pattern. Although the rearrangement layer member (R15) is simply illustrated here, the rearrangement layer member (R15) may include a structure in which an insulating layer (e.g., an organic insulating layer) and a wiring member layer (wiring element layer) are alternately stacked one or more times. A plurality of via holes (openings) may be formed in the insulating layer, and a conductive via element may be provided within the via holes. The conductive via element may serve as a vertical wiring.

[0079] The rearrangement layer member (R15) may include a plurality of electrode pads (P10) exposed on its surface. The plurality of electrode pads (P10) may be positioned on the opposite side of where the substrate for the package (S150) is placed and may be arranged two-dimensionally. In each of the plurality of unit package regions (U10), the electrode pads (P10) may be electrically connected to a circuit board unit (CS10). Additionally, the rearrangement layer member (R15) may be electrically connected to a first passive element member (PV10). The rearrangement layer member (R15) may be in contact with the first passive element member (PV10).

[0080] If necessary, the carrier substrate (T15 in FIG. 8c) may be removed from the plurality of circuit board units (CS10) and the molding layer (M15) at this stage. At this time, the adhesive layer (A15 in FIG. 8c) may also be removed. As a non-limiting example, after forming the molding layer (M15), the carrier substrate (T15 in FIG. 8c) and the adhesive layer (A15 in FIG. 8c) may be removed, and then a rearrangement layer member (R15) may be formed. The rearrangement layer member (R15) may be formed on the surface of the package substrate (S150) exposed by removing the carrier substrate (T15 in FIG. 8c) and the adhesive layer (A15 in FIG. 8c). However, this process is exemplary and may vary in many ways. The timing of the removal of the carrier substrate (T15 in FIG. 8c), etc., may vary.

[0081] Referring to FIG. 8e, for each of the plurality of unit package regions (U10), a plurality of chips (C10) can be mounted on a rearrangement layer member (R15) so as to be electrically connected to the rearrangement layer member (R15). According to one example, a plurality of bumps (B10) may be provided on one side of each of the plurality of chips (C10). In other words, each of the plurality of chips (C10) may include a plurality of bumps (B10) disposed on one side thereof. The plurality of bumps (B10) may be microbumps, and may have at least partially a ball shape or other shape. The plurality of bumps (B10) may be a type of electrical connection element. The plurality of chips (C10) may be mounted on the rearrangement layer member (R15) so that the plurality of bumps (B10) are electrically connected to the rearrangement layer member (R15). As a plurality of bumps (B10) are connected to a plurality of electrode pads (P10), the chip (C10) can be electrically connected to the circuit board unit (CS10) through the rearrangement layer member (R15).

[0082] According to one embodiment, the plurality of chips (C10) may include heterogeneous chips. For example, the plurality of chips (C10) may include memory chips and logic chips, and may further include other types of chips. In each of the plurality of unit package regions (U10), the plurality of chips (C10) may be arranged so as to be spaced apart from each other in a horizontal direction on a rearrangement layer member (R15), and in some cases, one or more chips (i.e., dies) may be further stacked (mounted) on at least one of the plurality of chips (C10).

[0083] Referring to FIG. 8f, for each of the plurality of unit package regions (U10), a plurality of electrical connection elements (E10) may be formed on a second surface opposite to the first surface of the substrate for the package (S150). The second surface of the substrate for the package (S150) may be either one of the two main surfaces (upper surface and lower surface) of the substrate for the package (S150). The plurality of electrical connection elements (E10) may be arranged to be electrically connected / contacted with a plurality of circuit board units (CS10). The plurality of electrical connection elements (E10) may include, as a non-limiting example, solder balls or bumps.

[0084] For each of the plurality of unit package regions (U10), at least one second passive element member (PV20) may be further formed on the second surface of the substrate for the package (S150). The second passive element member (PV20) may be electrically connected to the circuit board unit (CS10). The second passive element member (PV20) may be attached to the second surface of the substrate for the package (S150) together with a plurality of electrical connection elements (E10) and electrically connected / contacted with the circuit board unit (CS10). The second passive element member (PV20) may be a capacitor or include a capacitor, as a non-limiting example.

[0085] A device structure (D100) may be defined, comprising a plurality of circuit board units (CS10), a molding layer (M15), a rearrangement layer member (R15), and a plurality of chips (C10). The device structure (D100) may be configured to further include a plurality of electrical connection elements (E10), etc. The device structure (D100) may include a plurality of package device regions.

[0086] Referring to FIG. 8g, the device structure (D100 in FIG. 8f) can be divided (cut) into package device units corresponding to each of the plurality of unit package regions (U10). This can be performed according to a general cutting method. Through this, individualized semiconductor package devices (D10a, D10b, D10c) can be obtained. The semiconductor package devices (D10a, D10b, D10c) may have a configuration as described in FIG. 1.

[0087] According to an embodiment of the present invention, a semiconductor package device can be manufactured using a method similar to a fan-out package method. For example, the semiconductor package device can be manufactured according to a method similar to a fan-out panel level package (FOPLP) or fan-out wafer level package (FOWLP). As a specific example, a plurality of circuit board units may be attached to a predetermined carrier substrate, a molding layer for fixing the plurality of circuit board units may be formed on the carrier substrate, a rearrangement layer member electrically connected to the plurality of circuit board units may be formed, and then a plurality of chips may be mounted on the rearrangement layer member. The plurality of circuit board units may be attached to the carrier substrate, for example, in a face-down or face-up manner. In addition, an RDL-last method or an RDL-first method may be applied when manufacturing the semiconductor package device.

[0088] According to an embodiment of the present invention, a method for manufacturing a semiconductor package device can be implemented that can increase cost efficiency and productivity and improve the performance of the device. Furthermore, a method for manufacturing a semiconductor package device that is easy to respond to various design changes, easy to manufacture, and advantageous for improving electrical performance can be implemented. For example, by using a fan-out type packaging process including a PCB process and a rearrangement layer (RDL) process, a semiconductor package device that interconnects heterogeneous chips can be easily manufactured.

[0089] According to another embodiment, in the step of FIG. 8c, an initial molding layer covering a plurality of circuit board units (CS10) may be formed. The height of the initial molding layer may be greater than the height of the circuit board units (CS10). In other words, the initial molding layer may be formed with a thickness greater than that of the circuit board units (CS10) to cover the plurality of circuit board units (CS10). Thus, the upper surface of the circuit board units (CS10) may be covered by the initial molding layer. Subsequently, a grinding or ablation process may be performed on the initial molding layer to expose one side of the plurality of circuit board units (CS10). Through this, the surface of the molding layer processed by the grinding or ablation process and the surface of the circuit board units (CS10) may form the same (substantially the same) plane. The grinding or ablation process may be performed in the step of FIG. 8c or at an appropriate time after the step of FIG. 8c.

[0090] FIGS. 9a to 9g are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package device according to another embodiment of the present invention. In this embodiment, a circuit board unit (CS11) as described in FIG. 4 may be applied. In this embodiment, other configurations and manufacturing methods, excluding the configuration of the circuit board unit (CS11), may be the same as those in FIGS. 8a to 8g.

[0091] In the step of FIG. 9a, a plurality of circuit board units (CS11) may be provided. Each of the plurality of circuit board units (CS11) may include a plurality of conductive via elements extending in the vertical direction and a plurality of conductive pattern layer elements extending in the horizontal direction. For example, the circuit board unit (CS11) may be a PCB unit including an organic substrate. In the present embodiment, the circuit board unit (CS11) may include at least one embedded passive element (PD10) and / or at least one embedded active element (AD10). The circuit board unit (CS11) may include both at least one embedded passive element (PD10) and at least one embedded active element (AD10). The passive element (PD10) may include, for non-limiting examples, a capacitor, a resistor, an inductor, an integrated passive device (IPD), etc. The active element (AD10) may include, for non-limiting examples, a transistor, a diode, an operational amplifier, an integrated circuit (IC), etc. Multiple circuit board units (CS11) can be manufactured in advance according to circuit board manufacturing technology.

[0092] Since the steps of FIGS. 9b to 9g may correspond to the steps of FIGS. 8b to 8g, respectively, a detailed description thereof is omitted. Reference numeral S151 represents a substrate for a package, D110 represents a device structure, and D11a to D11c represent semiconductor package devices. The semiconductor package devices (D11a, D11b, D11c) may have a configuration as described in FIG. 3. When the circuit board unit (CS11) is configured to include at least one embedded passive device element (PD10) and / or at least one embedded active device element (AD10), the electrical performance and functionality of the semiconductor package device may be further improved. The formation / placement locations of the passive device element (PD10) and the active device element (AD10) in the circuit board unit (CS11) are not limited to those depicted and may vary in various ways.

[0093] FIGS. 10a to 10h are cross-sectional views illustrating an exemplary method for manufacturing a semiconductor package device according to another embodiment of the present invention. In this embodiment, a circuit board unit (CS12) as described in FIG. 6 may be applied.

[0094] Referring to FIG. 10a, a plurality of circuit board units (CS12) may be provided. Each of the plurality of circuit board units (CS12) may include a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction. For example, the circuit board unit (CS12) may be a PCB unit including an organic substrate. In this embodiment, the circuit board unit (CS12) may be configured to include at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication. The frequency filter may be, for example, an RF filter, but is not limited thereto. The communication FEM may be, for example, an RF front-end module (FEM), but is not limited thereto. The antenna, frequency filter, and communication FEM may be formed through device embedding technology or other device formation technology. Additionally, the circuit board unit (CS12) may further include a plurality of conductive pillar elements (PL10) formed on its surface (one side). A plurality of conductive pillar elements (PL10) may include, for example, a metal or metallic material such as copper (Cu). A plurality of circuit board units (CS12) may be pre-manufactured according to circuit board manufacturing technology.

[0095] Referring to FIG. 10b, a plurality of circuit board units (CS12) can be arranged on a carrier substrate (T15) so as to be spaced apart from each other in a horizontal direction. A plurality of circuit board units (CS12) can each be arranged in a plurality of unit package regions (U10) arranged in a two-dimensional manner. An adhesive layer (A15) can be provided on the carrier substrate (T15), and a plurality of circuit board units (CS12) can be attached on the adhesive layer (A15). The adhesive layer (A15) may be considered as part of the carrier substrate (T15).

[0096] Referring to FIG. 10c, a molding layer (M15) can be formed on a carrier substrate (T15) to form a single substrate shape together with a plurality of circuit board units (CS12) while filling the spaces between and around them. The molding layer (M15) can be formed to fill the spaces between and around a plurality of conductive pillar elements (PL10), and the ends of the plurality of conductive pillar elements (PL10) can be exposed without being covered by the molding layer (M15). Therefore, one side of the circuit board unit (CS12) on which the plurality of conductive pillar elements (PL10) are formed can be seen as being exposed by the molding layer (M15). The plurality of circuit board units (CS12) and the molding layer (M15) can be said to constitute a single package substrate (S152). In other words, the package substrate (S152) can be configured to include a plurality of circuit board units (CS12) and a molding layer (M15).

[0097] Referring to FIG. 10d, a rearrangement layer member (R6) can be formed on one side of a substrate for a package (S152) comprising a plurality of circuit board units (CS12) and a molding layer (M15). For convenience, the rearrangement layer member (R6) is referred to as a "separate rearrangement layer member (R6)." The separate rearrangement layer member (R6) may be formed to be electrically connected to a plurality of conductive pillar elements (PL10). The separate rearrangement layer member (R6) may include a plurality of electrode pads (P5) exposed on its surface. The plurality of electrode pads (P5) may be positioned on the opposite side of where the substrate for the package (S152) is placed and may be arranged in a two-dimensional manner. At least some of the plurality of electrode pads (P5) may be electrically connected to a plurality of circuit board units (CS12).

[0098] In this step, the carrier substrate (T15 in FIG. 10c) can be removed from the plurality of circuit board units (CS12) and the molding layer (M15). At this time, the adhesive layer (A15 in FIG. 10c) can also be removed together.

[0099] Referring to FIG. 10e, a rearrangement layer member (R15) can be formed on the other side of a substrate for a package (S152) configured to include a plurality of circuit board units (CS12) and a molding layer (M15). The rearrangement layer member (R15) can be formed on the surface of the substrate for a package (S152) exposed by removing the carrier substrate (T15 in FIG. 10c) and the adhesive layer (A15 in FIG. 10c). The rearrangement layer member (R15) may include a plurality of electrode pads (P10) exposed on its surface. The plurality of electrode pads (P10) may be placed on the opposite side of where the substrate for the package (S152) is placed and may be arranged in a two-dimensional manner.

[0100] Referring to FIG. 10f, for each of the plurality of unit package regions (U10), a plurality of chips (C10) can be mounted on a rearrangement layer member (R15) so as to be electrically connected to the rearrangement layer member (R15). According to one example, a plurality of bumps (B10) may be provided on one side of each of the plurality of chips (C10). The plurality of chips (C10) may be mounted on the rearrangement layer member (R15) so that the plurality of bumps (B10) are electrically connected to the rearrangement layer member (R15). As the plurality of bumps (B10) are connected to a plurality of electrode pads (P10), the chips (C10) may be electrically connected to a circuit board unit (CS12) through the rearrangement layer member (R15).

[0101] Referring to FIG. 10g, for each of the plurality of unit package regions (U10), a plurality of electrical connection elements (E10) can be formed on one side of a separate rearrangement layer member (R5) to be electrically connected to the separate rearrangement layer member (R5). The plurality of electrical connection elements (E10) can be placed on one side of a package substrate (S152) corresponding to the side opposite to where the plurality of chips (C10) are placed. The plurality of electrical connection elements (E10) can be connected to / contact with a plurality of electrode pads (P5).

[0102] A device structure (D120) may be defined, comprising a plurality of circuit board units (CS12), a molding layer (M15), a rearrangement layer member (R15), and a plurality of chips (C10). The device structure (D120) may be configured to further include a separate rearrangement layer member (R6) and a plurality of electrical connection elements (E10), etc. The device structure (D120) may include a plurality of package device regions.

[0103] Referring to FIG. 10h, the device structure (D120 in FIG. 10g) can be divided (cut) into package device units corresponding to each of the plurality of unit package regions (U10). Through this, individualized semiconductor package devices (D12a, D12b, D12c) can be obtained. The semiconductor package devices (D12a, D12b, D12c) may have a configuration as described in FIG. 6. When the circuit board unit (CS12) is configured to include at least one of an antenna, a frequency filter, and a communication FEM, the electrical performance and functionality of the semiconductor package device may be further improved.

[0104] Although a method for manufacturing a semiconductor package device according to the embodiments has been specifically described with reference to FIGS. 8a to 8g, FIGS. 9a to 9g and FIGS. 10a to 10h, the method for manufacturing a semiconductor package device according to the embodiments may be varied as needed.

[0105] According to the embodiments of the present invention described above, a semiconductor package device and a method for manufacturing the same can be realized, which can increase cost efficiency and productivity and improve the performance of the device. Furthermore, according to the embodiments of the present invention, a semiconductor package device and a method for manufacturing the same can be realized, which can easily accommodate various design changes, be easy to manufacture, and secure excellent electrical performance. According to one embodiment, for example, by using a fan-out type package process including a printed circuit board (PCB) process and a rearrangement layer (RDL) process, a cost-effective and highly productive method for manufacturing a semiconductor package device that interconnects heterogeneous chips can be realized. According to one embodiment, for example, by using a circuit board unit including embedded passive and active elements, the electrical performance of the package device that interconnects heterogeneous chips can be improved, process efficiency can be improved, and ease of design change can be improved. According to one embodiment, the electrical performance of a package device interconnecting heterogeneous chips can be improved by using a circuit board unit comprising, for example, at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication. The technology according to the embodiments can be usefully applied in various advanced packaging fields.

[0106] This specification discloses preferred embodiments of the present invention. Although specific terms have been used, they are used merely in a general sense to facilitate the explanation of the technical content of the invention and to aid in understanding the invention, and are not intended to limit the scope of the invention. It is obvious to those skilled in the art that, in addition to the embodiments disclosed herein, other variations based on the technical concept of the present invention are possible. Those skilled in the art will understand that the semiconductor package device and the method for manufacturing the same according to the embodiments described with reference to FIGS. 1 to 10h can be variously substituted, changed, and modified within the scope of the technical concept of the present invention. For example, it will be understood that the specific configuration of the circuit board unit can be varied. Therefore, the scope of the invention should not be determined by the described embodiments but by the technical concept described in the claims. Explanation of the symbols

[0107] * Explanation of symbols for major parts of the drawing * A15: Adhesive layer AD10: Active device element B10: Bump C10: Chip CS10~CS12: Circuit board units D100, D110, D120: Component structures D10a~D12c: Semiconductor package device E10: Electrical connection element L10: Conductive pattern layer element M10, M15: Molding layer ML10: Organic substrate NL10: First insulating layer NL20: Second insulating layer P5, P10: Electrode pads PD10: Passive element PL10: Conductive pillar element PV10: First passive element member PV20: Second passive element member R5, R6: Separate rearrangement layer members R10, R15: Rearrangement layer members S100, S101, S102: Package substrates S150, S151, S152: Substrates for packages T15: Carrier substrate U10: Unit element region V10: Conductive via element

Claims

Claim 1 A semiconductor package device comprising: a circuit board unit including a plurality of conductive via elements extending in a vertical direction and a plurality of conductive pattern layer elements extending in a horizontal direction; a molding layer disposed to expose the circuit board unit while filling the surrounding space of the circuit board unit and forming a single substrate shape together with the circuit board unit; a redistribution layer member disposed on a first surface of a package substrate comprising the circuit board unit and the molding layer; and a plurality of chips mounted on the redistribution layer member to be electrically connected to the redistribution layer member.The circuit board unit is a printed circuit board (PCB) unit including an organic substrate, the circuit board unit includes the organic substrate, one or more first insulating layers disposed on a first surface of the organic substrate, and one or more second insulating layers disposed on a second surface of the organic substrate opposite to the first surface, wherein a plurality of conductive via elements and a plurality of conductive pattern layer elements are formed inside and between the organic substrate, the one or more first insulating layers, and the one or more second insulating layers, and a portion of the plurality of conductive via elements is provided as a penetrating element penetrating the organic substrate, the molding layer has the same thickness as the circuit board unit and fixes the circuit board unit while surrounding the circuit board unit, and the one surface of the molding layer and the one surface of the circuit board unit are disposed at the same level so that the molding layer exposes one surface of the circuit board unit entirely on the first surface side of the package substrate, and the rearrangement layer member is configured on the first surface of the package substrate pre-configured by a combination of the circuit board unit and the molding layer, the one surface of the circuit board unit and the molding layer A semiconductor package device comprising a member formed to make contact at the same level as one surface, wherein a plurality of bumps are provided on one surface of each of the plurality of chips, and the plurality of chips are mounted on the rearrangement layer member in a flip-chip manner such that the plurality of bumps contact the plurality of electrode pads of the rearrangement layer member. Claim 2 delete Claim 3 delete Claim 4 In claim 1, the circuit board unit is a semiconductor package device comprising at least one of one or more embedded passive element elements and one or more embedded active element elements. Claim 5 In claim 1, the circuit board unit is a semiconductor package device comprising at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication. Claim 6 delete Claim 7 In claim 1, the plurality of chips is a semiconductor package device comprising heterogeneous chips. Claim 8 A semiconductor package device according to claim 1, wherein a plurality of electrical connection elements electrically connected to the circuit board unit are disposed on a second surface opposite to the first surface of the package substrate. Claim 9 A semiconductor package device according to claim 1, further comprising: a separate rearrangement layer member disposed on a second surface opposite to the first surface of the package substrate; and a plurality of electrical connection elements disposed on the separate rearrangement layer member to be electrically connected to the separate rearrangement layer member; wherein the circuit board unit further comprises a plurality of conductive pillar elements formed on the second surface side of the package substrate; wherein the molding layer is formed to fill between and around the plurality of conductive pillar elements, and the ends of the plurality of conductive pillar elements are exposed and not covered by the molding layer; and wherein the separate rearrangement layer member is electrically connected to the circuit board unit through the plurality of conductive pillar elements. Claim 10 A semiconductor package device according to claim 1, further comprising at least one of: at least one first passive element member disposed within the molding layer around the circuit board unit and electrically connected to the rearrangement layer member; and at least one second passive element member disposed to be electrically connected to the circuit board unit on a second surface opposite to the first surface of the package substrate. Claim 11 A method for manufacturing a semiconductor package device comprises: providing a plurality of circuit board units, each comprising a plurality of conductive via elements extended in a vertical direction and a plurality of conductive pattern layer elements extended in a horizontal direction; arranging the plurality of circuit board units on a carrier substrate such that they are spaced apart from each other in a horizontal direction, wherein each of the plurality of circuit board units is arranged in a plurality of unit package regions arranged in a two-dimensional manner; forming a molding layer on the carrier substrate that fills the spaces between and around the plurality of circuit board units and together with them to form a single substrate shape; forming a redistribution layer member on a first surface of a package substrate configured to include the plurality of circuit board units and the molding layer; mounting a plurality of chips on the redistribution layer member for each of the plurality of unit package regions so as to be electrically connected to the redistribution layer member; and dividing a device structure comprising the plurality of circuit board units, the molding layer, the redistribution layer member, and the plurality of chips into package device units corresponding to each of the plurality of unit package regions, so as to form a plurality of semiconductor package devices when the carrier substrate is excluded.The circuit board unit is a printed circuit board (PCB) unit comprising an organic substrate, wherein the circuit board unit comprises the organic substrate, one or more first insulating layers disposed on a first surface of the organic substrate, and one or more second insulating layers disposed on a second surface of the organic substrate opposite to the first surface, wherein the plurality of conductive via elements and the plurality of conductive pattern layer elements are formed inside and between the organic substrate, the one or more first insulating layers, and the one or more second insulating layers, and a portion of the plurality of conductive via elements is provided as a penetrating element penetrating the organic substrate, wherein the molding layer has the same thickness as the circuit board unit and fixes the circuit board unit by surrounding the circuit board unit, and wherein one surface of the molding layer and one surface of the circuit board unit are disposed at the same level such that the molding layer exposes one surface of the circuit board unit entirely on the first surface side of the substrate for the package, and the rearrangement layer member is the circuit board on the first surface of the substrate for the package that is pre-configured by the combination of the circuit board unit and the molding layer A method for manufacturing a semiconductor package device, wherein the member is formed to contact one surface of a unit and one surface of a molding layer at the same level, and a plurality of bumps are provided on one surface of each of the plurality of chips, and the plurality of chips are mounted on the rearrangement layer member in a flip-chip manner such that the plurality of bumps contact a plurality of electrode pads of the rearrangement layer member. Claim 12 delete Claim 13 delete Claim 14 A method for manufacturing a semiconductor package device according to claim 11, wherein the circuit board unit comprises at least one of one or more embedded passive element elements and one or more embedded active element elements. Claim 15 A method for manufacturing a semiconductor package device according to claim 11, wherein the circuit board unit comprises at least one of an antenna, a frequency filter, and a front-end module (FEM) for communication. Claim 16 delete Claim 17 In claim 11, a method for manufacturing a semiconductor package device comprising a plurality of chips, wherein the plurality of chips includes heterogeneous chips. Claim 18 A method for manufacturing a semiconductor package device according to claim 11, further comprising the step of forming a plurality of electrical connection elements electrically connected to the circuit board unit on the second surface opposite to the first surface of the substrate for the package for each of the plurality of unit package regions. Claim 19 A method for manufacturing a semiconductor package device according to claim 11, further comprising: a step of forming a separate rearrangement layer member on a second surface opposite to the first surface of the substrate for the package; and a step of forming a plurality of electrical connection elements electrically connected to the separate rearrangement layer member on the separate rearrangement layer member for each of the plurality of unit package regions; wherein, in each of the semiconductor package devices, the circuit board unit further comprises a plurality of conductive pillar elements formed on the second surface side of the substrate for the package, the molding layer is formed to fill between and around the plurality of conductive pillar elements, the ends of the plurality of conductive pillar elements are exposed and not covered by the molding layer, and the separate rearrangement layer member is electrically connected to the circuit board unit through the plurality of conductive pillar elements. Claim 20 A method for manufacturing a semiconductor package device according to claim 11, further comprising at least one of the steps of: arranging the plurality of circuit board units on the carrier substrate, wherein for each of the plurality of unit package regions, at least one first passive component member is arranged on the carrier substrate surrounding the circuit board unit; and for each of the plurality of unit package regions, at least one second passive component member is arranged on the second surface of the package substrate opposite to the first surface and is electrically connected to the circuit board unit. Claim 21 A method for manufacturing a semiconductor package device according to claim 11, further comprising the step of removing the carrier substrate from the plurality of circuit board units and the molding layer between the step of forming the molding layer and the step of dividing the device structure into package device units. Claim 22 A method for manufacturing a semiconductor package device according to claim 11, wherein an initial molding layer covering the plurality of circuit board units is formed, and a grinding or ablation process is performed on the initial molding layer to expose the surface of the plurality of circuit board units.

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