Image Sensor and Its Image Output Method and Applications

Abstract

The present invention provides an image sensor and a method for outputting an image and an application thereof. The image sensor comprises: an input circuit for generating a photocurrent by performing a first photoelectric conversion on incident light during an EVS mode operation period and generating a photocharge by performing a second photoelectric conversion on incident light during an APS mode operation period; an EVS circuit for outputting a corresponding event signal according to the difference between a first voltage corresponding to the photocurrent and a reference voltage during the first photoelectric conversion process; an APS circuit for outputting a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process in which the first photoelectric conversion continues; and a control circuit for outputting a corresponding APS image according to the grayscale signal and outputting a corresponding EVS image according to the event signal; wherein a single APS mode operation period is between adjacent EVS mode operation periods. The present invention can not only reduce the size of the image sensor but also enable the output of a multi-frame EVS image simultaneously with the output of a single-frame APS image.

Description

Technology Field

[0001] The present invention relates to the field of photosensitive element technology, and in particular to an image sensor and a method for outputting an image and its applications. Background Technology

[0002] In related technologies, a method for mutually fusing an Active Pixel Sensor (APS) and an Event-based Vision Sensor (EVS) is to achieve mutual fusion by replicating the photocurrent generated by a photodiode in the EVS to form the APS. However, this method allows a large amount of noise to easily enter during the photocurrent radiation process, which severely affects the image quality of the APS; furthermore, during the image output process, a single pixel cannot simultaneously output both an APS image and an EVS image. Additionally, both the APS and EVS require photoelectric converters to detect light, and since these converters occupy most of the space of the image sensor, they significantly increase the size of the image sensor. From this, it can be seen that image sensors applying the aforementioned fusion method have many disadvantages, such as high power consumption, high noise, and large size.

[0003] Therefore, it is necessary to improve the structure of existing image sensors. The problem to be solved

[0004] The present invention provides an image sensor, an image output method, and an application to solve the problem that the size of the image sensor implementing APS and EVS mutual fusion in related technology is relatively large and a single pixel cannot simultaneously output an APS image and an EVS image. means of solving the problem

[0005] To solve the technical problem described above, a first aspect of an embodiment of the present invention provides an image sensor comprising a pixel array composed of a plurality of pixels, wherein the pixel array is composed of two pixel types: an APS pixel and an EVS pixel; the image sensor comprises an input circuit, an APS circuit, an EVS circuit, and a control circuit; wherein the input circuit is connected to the APS circuit and the EVS circuit, and the control circuit is connected to the APS circuit and the EVS circuit; wherein the APS pixel comprises the input circuit, the APS circuit, and the control circuit, and the EVS pixel comprises the input circuit, the EVS circuit, and the control circuit; and the operation time unit of the input circuit comprises an EVS mode operation period and an APS mode operation period, wherein a single APS mode operation period is between adjacent EVS mode operation periods;

[0006] The input circuit performs a first photoelectric conversion on incident light during the EVS mode operation period and generates a corresponding photocurrent, and performs a second photoelectric conversion on incident light during the APS mode operation period and generates a corresponding photocharge;

[0007] The EVS circuit outputs a corresponding event signal according to the difference between a first voltage corresponding to the photocurrent and a reference voltage during the first photoelectric conversion process;

[0008] The above APS circuit outputs a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process in which the first photoelectric conversion continues;

[0009] The above control circuit outputs a corresponding EVS image according to the event signal and outputs a corresponding APS image according to the grayscale signal.

[0010] A second aspect of an embodiment of the present invention provides an image output method applied to an image sensor comprising a pixel array composed of a plurality of pixels, wherein the pixel array is composed of two pixel types: an APS pixel and an EVS pixel; the image sensor comprises an input circuit, an APS circuit, an EVS circuit, and a control circuit; the input circuit is connected to the APS circuit and the EVS circuit, and the control circuit is connected to the APS circuit and the EVS circuit; wherein the APS pixel comprises the input circuit, the APS circuit, and the control circuit, and the EVS pixel comprises the input circuit, the EVS circuit, and the control circuit; and the operation time unit of the input circuit comprises an EVS mode operation period and an APS mode operation period, wherein a single APS mode operation period is between adjacent EVS mode operation periods;

[0011] The above image output method is,

[0012] The input circuit comprises the steps of: performing a first photoelectric conversion for incident light during the EVS mode operation period and generating a corresponding photocurrent; and performing a second photoelectric conversion for incident light during the APS mode operation period and generating a corresponding photocharge;

[0013] The above EVS circuit outputs a corresponding event signal according to the difference between a first voltage corresponding to the photocurrent and a reference voltage during the first photoelectric conversion process;

[0014] The above APS circuit outputs a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process in which the first photoelectric conversion continues; and

[0015] The control circuit includes the step of outputting a corresponding EVS image according to the event signal and outputting a corresponding APS image according to the grayscale signal.

[0016] A third aspect of an embodiment of the present invention provides an application of an image sensor according to the first aspect of an embodiment of the present invention in a photoelectric device. Effects of the invention

[0017] As can be seen from the above description, compared to related technologies, the beneficial effects of the present invention are as follows.

[0018] The image sensor includes a pixel array composed of multiple pixels, and the pixel array is composed of two pixel types: APS pixels and EVS pixels. Specifically, the image sensor includes four circuits: an input circuit, an APS circuit, an EVS circuit, and a control circuit; wherein the working time unit of the input circuit includes an EVS mode working period and an APS mode working period, and a single APS mode working period exists between adjacent EVS mode working periods. In the present invention, the input circuit performs a first photoelectric conversion (i.e., EVS exposure) for incident light during the EVS mode working period, generates a corresponding photocurrent and supplies it to the EVS circuit to obtain a corresponding event signal, and performs a second photoelectric conversion (i.e., APS exposure) for incident light during the APS mode working period, generates a corresponding photocharge and supplies it to the APS circuit to obtain a corresponding grayscale signal; the control circuit outputs a corresponding APS image according to the grayscale signal and outputs a corresponding EVS image according to the event signal; It can be seen that the size of the image sensor can be significantly reduced by sharing the same input circuit and control circuit between the APS pixel and the EVS pixel, that is, by eliminating the need to install a separate input circuit and control circuit for each of the APS pixel and the EVS pixel.And, a single APS mode operation period is between adjacent EVS mode operation periods, which means that a portion of the period (i.e., the APS mode operation period) is allocated to perform the exposure of the APS during the exposure process of the EVS, and since the APS circuit outputs a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process in which the first photoelectric conversion continues (i.e., in the next first photoelectric conversion process after the second photoelectric conversion is completed, or within the next EVS mode operation period adjacent to the APS mode operation period), the reading of the APS does not affect the exposure and reading of the EVS, so that a multi-frame EVS image can be output simultaneously with the output of a single frame APS image, and when a single pixel contains both an APS pixel and an EVS pixel, said single pixel can output the APS image and the EVS image simultaneously, thereby realizing mutual fusion between the APS and EVS in a true sense. Brief explanation of the drawing

[0019] To more clearly explain the technical solution means in the related technology or embodiments of the present invention, the drawings necessary for describing the related technology or embodiments of the present invention are briefly introduced below. The drawings in the description below are only some embodiments of the present invention and are not all embodiments. It is obvious that a person skilled in the art can obtain other drawings based on these drawings without creative effort. FIG. 1 is a block diagram of the first module of a pixel according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a working time unit of an input circuit according to an embodiment of the present invention. FIG. 3 is a second module block diagram of a pixel according to an embodiment of the present invention. Figure 4 is a schematic diagram of the first circuit structure of a pixel according to an embodiment of the present invention. FIG. 5 is a schematic diagram of the structure of a pixel array according to an embodiment of the present invention. FIG. 6 is a schematic diagram of the first on / off state of each transistor in a pixel when the pixel structure according to an embodiment of the present invention is as shown in FIG. 4. FIG. 7 is a schematic diagram of an output image when the on / off state of each transistor in a pixel according to an embodiment of the present invention is as shown in FIG. 6. FIG. 8 is a schematic diagram of the second on / off state of each transistor in a pixel when the pixel structure according to an embodiment of the present invention is as shown in FIG. 4. FIG. 9 is a schematic diagram of an output image when the on / off state of each transistor in a pixel according to an embodiment of the present invention is as shown in FIG. 8. FIG. 10 is a schematic diagram of the second circuit structure of a pixel according to an embodiment of the present invention. FIG. 11 is a schematic diagram of the first on / off state of each transistor in a pixel when the pixel structure according to an embodiment of the present invention is as shown in FIG. 10. FIG. 12 is a schematic diagram of the second on / off state of each transistor in a pixel when the pixel structure according to an embodiment of the present invention is as shown in FIG. 10. FIG. 13 is a schematic diagram of the third circuit structure of a pixel according to an embodiment of the present invention. FIG. 14 is a schematic diagram of the on / off state of each transistor in a pixel when the pixel structure according to an embodiment of the present invention is as shown in FIG. 13. FIG. 15 is a schematic flowchart of an image output method according to an embodiment of the present invention. Specific details for implementing the invention

[0020] To make the object, technical solution, and advantages of the present invention clearer and easier to understand, the present invention is described below in a clear and complete manner, together with embodiments and corresponding drawings. In this description, identical or similar reference numerals from beginning to end indicate identical or similar elements or elements having identical or similar functions. Furthermore, each embodiment of the present invention described below is intended only for interpreting the present invention and does not limit the present invention; that is, all other embodiments obtained by a person skilled in the art without creative effort based on each embodiment of the present invention fall within the scope of protection of the present invention. Additionally, the technical features mentioned in each embodiment of the present invention described below may be combined with one another as long as they do not conflict with one another.

[0021] An image sensor is a device that converts incident light on its own photosensitive surface into a corresponding electrical signal, and generally includes CMOS (Complementary Metal Oxide Semiconductor) image sensors and DVS (Dynamic Vision Sensor); here, the CMOS image sensor is an APS (Active Pixel Sensor), and the DVS is an EVS (Event-based Vision Sensor). In recent years, the development of APS has been rapid, and applications in fields such as automotive electronics, smart manufacturing, industrial monitoring, and military reconnaissance are becoming increasingly widespread. However, under conditions of high resolution and / or high frame rates, it generates a large amount of data, which increases the power consumption of the chip and implies higher demands on the chip in terms of transmission bandwidth and data computing capabilities. On the other hand, since EVS detects only events where the intensity of incident light changes and outputs an EVS image (i.e., an event image) based on the detected event, the amount of data in the EVS is small, and thus the resolution of the EVS is also low. For this reason, the technology of mutual convergence between APS and EVS has become a hotspot in the industry.

[0022] In related technologies, the mutual fusion of APS and EVS is achieved by forming an APS through radiation of the photocurrent generated by a photodiode in the EVS. However, this method is prone to introducing a large amount of noise during the photocurrent radiation process, which severely affects the image quality of the APS; furthermore, during the image output process, a single pixel cannot simultaneously output both an APS image and an EVS image. Additionally, both APS and EVS require photoelectric converters to detect light, and since these converters can occupy most of the space of the image sensor, they significantly increase the size of the image sensor. It can be seen that image sensors applying the aforementioned fusion method have many disadvantages, such as high power consumption, high noise, and large size. To address this, an embodiment of the present invention provides an image sensor applicable to a photoelectric device; where the photoelectric device is a device that must convert incident light into a corresponding electrical signal, such as a digital camera, camera, video recorder, fax machine, image scanner, and digital TV.

[0023] Referring to FIG. 1, FIG. 1 is a first module block diagram of a pixel according to an embodiment of the present invention. An image sensor according to an embodiment of the present invention includes a pixel array composed of a plurality of pixels, and the pixel array is composed of two pixel types: an APS pixel and an EVS pixel. The image sensor includes four circuits: an input circuit (100), an APS circuit (200), an EVS circuit (300), and a control circuit (400); wherein the input circuit (100) is connected to the APS circuit (200) and the EVS circuit (300), and the control circuit (400) is connected to the APS circuit (200) and the EVS circuit (300). Here, the APS pixel includes the input circuit (100), the APS circuit (200), and the control circuit (400), and the EVS pixel includes the input circuit (100), the EVS circuit (300), and the control circuit (400); From this, it can be seen that the same input circuit (100) and the same control circuit (400) are shared between the APS pixel and the EVS pixel, that is, there is no need to install one input circuit (100) and one control circuit (400) in each of the APS pixel and the EVS pixel. It can be understood that the APS pixel outputs an APS image, the EVS pixel outputs an EVS image, and when a single pixel includes both an APS pixel and an EVS pixel, the single pixel may output an APS image or an EVS image; when a single pixel includes only an APS pixel, the single pixel may output only an APS image; and when a single pixel includes only an EVS pixel, the single pixel may output only an EVS image. Hereinafter, an image sensor according to an embodiment of the present invention is described in more detail, in the case of a single pixel that simultaneously includes an APS pixel and an EVS pixel.

[0024] In an embodiment of the present invention, the working time unit of the input circuit (100) includes an EVS mode working period and an APS mode working period, and a single APS mode working period is between adjacent EVS mode working periods; wherein, in this specification, the working time unit described may be a working time for normally outputting a 1-frame APS image. As an example, further referring to FIG. 2, FIG. 2 is a schematic diagram of the working time unit of the input circuit according to an embodiment of the present invention; wherein A1, A2, A3 and A4 are all EVS mode working periods, and B1, B2 and B3 are all APS mode working periods.

[0025] Specifically, the input circuit (100) includes a photoelectric conversion element and is configured to perform photoelectric conversion of incident light, that is, during the EVS mode operation period, performs a first photoelectric conversion for the incident light and generates a corresponding photocurrent, and during the APS mode operation period, performs a second photoelectric conversion for the incident light and generates a corresponding photocharge; wherein the first photoelectric conversion is the exposure of EVS, and the second photoelectric conversion is the exposure of APS. From this, it can be seen that a portion of the period (i.e., the APS mode operation period) is allocated to perform the exposure of APS during the EVS exposure process, that is, the exposure of EVS and the exposure of APS are performed alternately; taking A1, B1, and A2 in FIG. 2 as examples, a portion of the period (i.e., B1) is allocated to perform the exposure of APS during the EVS exposure process (i.e., a continuous period between A1 and A2). Furthermore, regarding the installation form of the input circuit (100), it may be possible to install a single input circuit (100) within each pixel of the pixel array; Alternatively, only one input circuit (100) may be installed so that all pixels of the pixel array share the same input circuit (100); or multiple input circuits (100) may be installed so that all pixels within the same array unit of the pixel array share the same input circuit (100); wherein, the pixel array may be divided into multiple array units, and each array unit includes a preset quantity of pixels. As an example, the pixels in each column of the pixel array all constitute one array unit; or, the pixels in each row of the pixel array all constitute one array unit.

[0026] Specifically, the EVS circuit (300) outputs a corresponding event signal according to the difference between a first voltage corresponding to the photocurrent and a reference voltage during the first photoelectric conversion process; where the event signal generates a corresponding EVS image. In an actual application, when a pixel is outputting an EVS image, the input circuit (100) performs a first photoelectric conversion on the incident light and outputs a corresponding photocurrent to the EVS circuit (300); then, the EVS circuit (300) outputs a corresponding event signal according to the difference between a first voltage corresponding to the received photocurrent and a reference voltage, thereby subsequently generating a corresponding EVS image using the output event signal. Here, the difference between the first voltage and the reference voltage represents a change in the intensity of the incident light (i.e., increase, decrease, or invariance), which means that the EVS circuit (300) actually outputs a corresponding event signal according to the change in the intensity of the incident light, for example, the change in the intensity of the incident light is determined by whether the difference between the first voltage and the reference voltage is greater than 0, less than 0, or equal to 0.

[0027] Specifically, the APS circuit (200) outputs a corresponding grayscale signal according to a second voltage corresponding to a photocharge during the process in which the first photoelectric conversion continues (i.e., in the next first photoelectric conversion process after the second photoelectric conversion is completed, or within the next EVS mode operation period adjacent to the APS mode operation period); wherein the grayscale signal generates a corresponding APS image. Taking A1, B1, and A2 of FIG. 2 as examples, the input circuit (100) performs a second photoelectric conversion on the incident light in B1 to generate a corresponding photocharge, and the APS circuit (200) outputs a corresponding grayscale signal according to a second voltage corresponding to the generated photocharge in A2. The process of the APS circuit (200) outputting a grayscale signal is actually the reading process of the APS, and the process of the APS circuit (200) outputting a grayscale signal is performed within the next EVS mode operation period (e.g., A2) adjacent to the APS mode operation period (e.g., B1), and the EVS operation can still be performed within A2, that is, since the reading process of the APS does not affect the exposure and reading of the EVS, it can be understood that if a single pixel contains both an APS pixel and an EVS pixel, the single pixel can output an APS image and an EVS image simultaneously.

[0028] Specifically, the control circuit (400) outputs a corresponding APS image according to a grayscale signal and outputs a corresponding EVS image according to an event signal. In an actual application, when a pixel is outputting an APS image, the APS circuit (200) outputs a corresponding grayscale signal to the control circuit (400) according to a second voltage corresponding to the received photocharge; then, the control circuit (400) outputs a corresponding APS image according to the received grayscale signal and displays it to the user. Similarly, when a pixel is outputting an EVS image, the EVS circuit (300) outputs a corresponding event signal to the control circuit (400) according to the difference between a first voltage corresponding to the received photocurrent and a reference voltage; then, the control circuit (400) outputs a corresponding EVS image according to the received event signal and displays it to the user. Additionally, regarding the installation form of the control circuit (400), a single control circuit (400) may be installed within each pixel of the pixel array; Alternatively, only one control circuit (400) may be installed so that all pixels of the pixel array share the same control circuit (400); or multiple control circuits (400) may be installed so that all pixels within the same array unit of the pixel array share the same control circuit (400).

[0029] In summary, when a single pixel includes both an APS pixel and an EVS pixel, the single pixel includes at least an APS circuit (200) and an EVS circuit (300), and in the case of an input circuit (100) and a control circuit (400), the single pixel may be shared with other pixels or installed separately.

[0030] In addition, as previously mentioned, the process in which the input circuit (100) performs a second photoelectric conversion for the incident light and generates a corresponding photocharge is actually the exposure process during APS image output. Generally, the exposure method of APS is divided into global exposure and shutter exposure. Here, global exposure refers to the process in which all pixels of a pixel array are exposed simultaneously at a specific point in time and the exposure ends simultaneously at another point in time, and after the exposure ends, all generated photocharges are transferred from the photosensitive area (i.e., input circuit (100)) to a charge detection amplifier (i.e., hereinafter floating diffusion node (FD1)), and then all pixel data (i.e., grayscale signal) of the pixel array is read one row at a time through the APS reading circuit (220); in this process, the time elapsed from when pixel data is read from the first row of pixels of the pixel array until pixel data is read from the last row of pixels of the pixel array is the reading time. In shutter exposure, the exposure time of each row of pixels in the pixel array is the same, but the exposure start and end times of pixels in different rows in the cell array are different, that is, the exposure times of pixels in different rows in the pixel array do not completely overlap, or, the exposure start time of pixels in each row in the pixel array is all later than the exposure start time of pixels in the previous row; furthermore, the photocharge generated by the row of pixels in the pixel array can only be transferred from the photosensitive area to the charge detection amplifier after the exposure of each row of pixels in the pixel array has ended, and the APS reading circuit (220) can only read the pixel data of the next row after the pixel data of that row has been read, so the time elapsed from when the pixel data of the first row of pixels in the pixel array is output by the APS reading circuit (220) until the pixel data of the last row of pixels in the pixel array is output by the APS reading circuit (220) is the reading time.

[0031] An image sensor according to an embodiment of the present invention includes a pixel array composed of a plurality of pixels, and the pixel array is composed of two pixel types: an APS pixel and an EVS pixel. Specifically, the image sensor includes four components: an input circuit (100), an APS circuit (200), an EVS circuit (300), and a control circuit (400); wherein the working time unit of the input circuit (100) includes an EVS mode working period and an APS mode working period, and a single APS mode working period exists between adjacent EVS mode working periods. In an embodiment of the present invention, the input circuit (100) performs a first photoelectric conversion (i.e., exposure of EVS) for incident light during the EVS mode working period, generates a corresponding photocurrent and supplies it to the EVS circuit (300) to obtain a corresponding event signal, and during the APS mode working period, performs a second photoelectric conversion (i.e., exposure of APS) for incident light, generates a corresponding photocharge and supplies it to the APS circuit (200) to obtain a corresponding grayscale signal; The control circuit (400) outputs a corresponding APS image according to a grayscale signal and outputs a corresponding EVS image according to an event signal; from this, it can be seen that the same input circuit (100) and the same control circuit (400) are shared between the APS pixel and the EVS pixel, that is, since there is no need to install one input circuit (100) and one control circuit (400) in each of the APS pixel and the EVS pixel, the size of the image sensor can be significantly reduced.And, a single APS mode operation period is between adjacent EVS mode operation periods, which means that a portion of the period (i.e., the APS mode operation period) is allocated to perform the exposure of the APS during the exposure process of the EVS, and since the APS circuit (200) outputs a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process in which the first photoelectric conversion continues (i.e., in the next first photoelectric conversion process after the second photoelectric conversion is completed, or within the next EVS mode operation period adjacent to the APS mode operation period), the reading of the APS does not affect the exposure and reading of the EVS, so that a multi-frame EVS image can be output simultaneously with the output of a single frame APS image, and when a single pixel contains both an APS pixel and an EVS pixel, the single pixel can output the APS image and the EVS image simultaneously, thereby realizing mutual fusion between the APS and EVS in a true sense.

[0032] In some embodiments, further referring to FIG. 3, FIG. 3 is a second module block diagram of a pixel according to an embodiment of the present invention. The EVS circuit (300) may include an EVS transmission circuit (310) and an EVS reading circuit (320); wherein the EVS transmission circuit (310) is connected to an input circuit (100) and an EVS reading circuit (320), and a control circuit (400) is connected to the EVS transmission circuit (310) and the EVS reading circuit (320). Specifically, the EVS transmission circuit (310) outputs a corresponding first voltage according to the photocurrent in the first photoelectric conversion process; and the EVS reading circuit (320) outputs a corresponding event signal according to the difference between the first voltage and the reference voltage. In this embodiment, it can be understood that the EVS circuit (300) first outputs a corresponding first voltage according to the photocurrent received through the EVS transmission circuit (310), and then outputs a corresponding event signal according to the difference between the first voltage received through the EVS reading circuit (320) and the reference voltage, thereby subsequently generating a corresponding EVS image using the output event signal. Additionally, regarding the installation form of the EVS reading circuit (320), one EVS reading circuit (320) may be installed in each pixel of the pixel array; or only one EVS reading circuit (320) may be installed so that all pixels of the pixel array share the same EVS reading circuit (320); or multiple EVS reading circuits (320) may be installed so that all pixels within the same array unit of the pixel array share the same EVS reading circuit (320).

[0033] The APS circuit (200) may include an APS transmission circuit (210) and an APS reading circuit (220); wherein the APS transmission circuit (210) is connected to the input circuit (100) and the APS reading circuit (220), and the control circuit (400) is connected to the APS transmission circuit (210) and the APS reading circuit (220). Specifically, the APS transmission circuit (210) outputs a corresponding second voltage according to the photocharge during the process of the first photoelectric conversion; and the APS reading circuit (220) outputs a corresponding grayscale signal according to the second voltage. In this embodiment, it can be understood that the APS circuit (200) first outputs a corresponding second voltage according to the photocharge received through the APS transmission circuit (210), and then outputs a corresponding grayscale signal according to the second voltage received through the APS reading circuit (220), so as to subsequently generate a corresponding APS image using the output grayscale signal. Additionally, regarding the installation form of the APS reading circuit (220), one APS reading circuit (220) may be installed in each pixel of the pixel array; or only one APS reading circuit (220) may be installed so that all pixels of the pixel array share the same APS reading circuit (220); or multiple APS reading circuits (220) may be installed so that all pixels within the same array unit of the pixel array share the same APS reading circuit (220).

[0034] As can be seen from the above, in the present embodiment, when a single pixel includes an APS pixel and an EVS pixel simultaneously, the single pixel includes at least an APS transmission circuit (210) and an EVS transmission circuit (310), and regarding the APS reading circuit (220) and the EVS reading circuit (320), the single pixel may share with other pixels or be installed separately.

[0035] In one embodiment, further referring to FIG. 4, FIG. 4 is a schematic diagram of the first circuit structure of a pixel according to an embodiment of the present invention. An APS transmission circuit (210) may include a first transmission branch, a floating diffusion node (FD1), and an output branch; wherein the first transmission branch is connected to an input circuit (100), a control circuit (400), and a floating diffusion node (FD1), and the output branch is connected to a floating diffusion node (FD1), a control circuit (400), and an APS read circuit (220). In this embodiment, the first transmission branch triggers an operating state through a control signal (TX1) transmitted by the control circuit (400) during the process of continuing the first photoelectric conversion; wherein, when the first transmission branch is in the operating state, the first transmission branch transmits the photoelectric charge generated by the input circuit (100) to the floating diffusion node (FD1). The floating diffusion node (FD1) accumulates the photoelectric charge and generates a corresponding second voltage. The output branch triggers an operation state via a control signal (SEL) transmitted by the control circuit (400); wherein, when the output branch is in an operation state, the output branch transmits a second voltage in the floating diffusion node (FD1) to the APS readout circuit (220), so that the APS readout circuit (220) subsequently outputs a corresponding grayscale signal according to the received second voltage.

[0036] Specifically, the output branch may include a first drive branch and a select branch; wherein the select branch is connected to the first drive branch, the control circuit (400), and the APS read circuit (220), and the first drive branch is also connected to the floating diffusion node (FD1). In this embodiment, the first drive branch buffers the potential of the floating diffusion node (FD1) and outputs a second voltage to the select branch. The select branch triggers an operation state via a control signal (SEL) transmitted by the control circuit (400); wherein, when the select branch is in the operation state, the select branch transmits the second voltage at the floating diffusion node (FD1) to the APS read circuit (220), so that the APS read circuit (220) subsequently outputs a corresponding grayscale signal according to the received second voltage.

[0037] Furthermore, the APS transmission circuit (210) may further include a first reset branch, and the first reset branch is connected to a floating diffusion node (FD1) and a control circuit (400). In this embodiment, the first reset branch triggers an operating state via a control signal (RST1) transmitted by the control circuit (400) after the selection branch has completed transmitting a second voltage to the APS reading circuit (220); wherein, when the first reset branch is in an operating state, the photocharge accumulated in the floating diffusion node (FD1) moves outward.

[0038] Specifically, the first reset branch may include a first reset transistor (T2), the source of the first reset transistor (T2) is connected to a floating diffusion node (FD1), the gate is connected to a control circuit (400), and the drain is connected to a power supply (VDD). In this embodiment, the first reset transistor (T2) triggers an ON state via a control signal (RST1) transmitted by the control circuit (400) after the selection branch has completed transmitting a second voltage to the APS read circuit (220); wherein, when the first reset transistor (T2) is in the ON state, the photocharge accumulated in the floating diffusion node (FD1) moves to the power supply (VDD).

[0039] For the present embodiment, still referring to FIG. 4, the EVS transmission circuit (310) may include a second reset branch and a second drive branch; wherein the second reset branch and the second drive branch are each connected to an input circuit (100), the second reset branch is also connected to a control circuit (400), and the second drive branch is also connected to an EVS reading circuit (320). In the present embodiment, the second reset branch triggers an operating state through a control signal (RST2) transmitted by the control circuit (400) during the first photoelectric conversion process; wherein, when the second reset branch is in an operating state, the second reset branch outputs a corresponding first voltage according to the photocurrent generated by the input circuit (100). The second drive branch transmits the first voltage generated by the second reset branch to the EVS reading circuit (320), so that the EVS reading circuit (320) subsequently outputs a corresponding event signal according to the difference between the received first voltage and the reference voltage.

[0040] Specifically, the second reset branch may include a second reset transistor (T5), and the drain and gate of the second reset transistor (T5) are each connected to a power supply (VDD), and the source and the second drive branch of the second reset transistor (T5) are each connected to an input circuit (100), and the gate of the second reset transistor (T5) is also connected to a control circuit (400). In this embodiment, the second reset transistor (T5) triggers an ON state through a control signal (RST2) transmitted by the control circuit (400) during the first photoelectric conversion process; when the second reset transistor (T5) is in the ON state, the second reset transistor (T5) outputs a corresponding first voltage according to the photocurrent generated by the input circuit (100); Here, the photocurrent is equal to the current between the drain and source of the second reset transistor (T5), and the first voltage is equal to the voltage between the drain and source of the second reset transistor (T5), and there is a logarithmic relationship between the photocurrent and the first voltage.

[0041] As a specific implementation of the present embodiment, referring still to FIG. 4, in the APS transmission circuit (210), in addition to the first reset branch composed of the first reset transistor (T2), other branches may also be composed of corresponding transistors, for example, the first transmission branch may include the first transmission transistor (T1), the first drive branch may include the first drive transistor (T3), and the selection branch may include the selection transistor (T4). Accordingly, in the EVS transmission circuit (310), in addition to the second reset branch composed of the second reset transistor (T5), other branches may also be composed of corresponding transistors, for example, the second drive branch may include the second drive transistor (T6).

[0042] In the specific implementation above, the APS transmission circuit (210) may include a first transmission transistor (T1), a first reset transistor (T2), a first drive transistor (T3), a select transistor (T4), and a floating diffusion node (FD1); Here, the first terminal of the first transmission transistor (T1) is connected to the input circuit (100), the second terminal of the first transmission transistor (T1), the source of the first reset transistor (T2), and the gate of the first drive transistor (T3) are each connected to the floating diffusion node (FD1), the drain of the first reset transistor (T2) and the drain of the first drive transistor (T3) are each connected to the power supply (VDD), the source of the first drive transistor (T3) is connected to the drain of the select transistor (T4), the source of the select transistor (T4) is connected to the APS reading circuit (220), and the third terminal of the first transmission transistor (T1), the gate of the first reset transistor (T2), and the gate of the select transistor (T4) are each connected to the control circuit (400).

[0043] Specifically, the first reset transistor (T2) triggers an off state according to a control signal (RST1) transmitted by the control circuit (400) during the process of continuing the first photoelectric conversion and before the first transmission transistor (T1) is in the on state. As an example, the first reset transistor (T2) can trigger its own on or off state according to the level state of the control signal (RST1), for example, when the control signal (RST1) is at a high level, the first reset transistor (T2) triggers an on state; when the control signal (RST1) is at a low level, the first reset transistor (T2) triggers an off state; and the same applies to other transistors mentioned below.

[0044] Specifically, the first transmission transistor (T1) triggers an ON state according to a control signal (TX1) transmitted by the control circuit (400) during the process in which the first photoelectric conversion continues and after the first reset transistor (T2) is in the OFF state; wherein, when the first transmission transistor (T1) is in the ON state, the first transmission transistor (T1) transmits the photocharge generated by the input circuit (100) to the floating diffusion node (FD1). Additionally, the first transmission transistor (T1) triggers an OFF state according to a control signal (TX1) transmitted by the control circuit (400) after the transmission of the photocharge generated by the input circuit (100) to the floating diffusion node (FD1) is completed during the process in which the first photoelectric conversion continues and after the transmission of the photocharge generated by the input circuit (100) to the floating diffusion node (FD1) is completed; wherein, when the first transmission transistor (T1) is in the OFF state, the first transmission transistor (T1) cannot transmit the photocharge generated by the input circuit (100) to the floating diffusion node (FD1).

[0045] Specifically, the floating diffusion node (FD1) forms a corresponding second voltage by accumulating the photocharge transmitted through the first transmission transistor (T1) during the process in which the first photoelectric conversion continues. Here, the floating diffusion node (FD1) corresponds to a charge detection amplifier in the specific implementation.

[0046] Specifically, the first drive transistor (T3) transmits the second voltage formed by the floating diffusion node (FD1) to the select transistor (T4) during the process in which the first photoelectric conversion continues. Here, in the specific implementation, the first drive transistor (T3) corresponds to a source following amplifier capable of outputting a voltage matching the second voltage to the select transistor (T4) by buffering the potential at the floating diffusion node (FD1).

[0047] Specifically, the selection transistor (T4) triggers an ON state according to a control signal (SEL) transmitted by the control circuit (400) during the process in which the first photoelectric conversion continues; whereby, when the selection transistor (T4) is in the ON state, the selection transistor (T4) transmits the received second voltage to the APS readout circuit (220), so that the APS readout circuit (220) subsequently outputs a corresponding grayscale signal according to the received second voltage. Additionally, the selection transistor (T4) triggers an OFF state according to a control signal (SEL) transmitted by the control circuit (400) after the transmission of the received second voltage to the APS readout circuit (220) is completed during the process in which the first photoelectric conversion continues, whereby, when the selection transistor (T4) is in the OFF state, the selection transistor (T4) cannot transmit the received second voltage to the APS readout circuit (220).

[0048] Specifically, the first reset transistor (T2) also triggers an ON state according to a control signal (RST1) transmitted by the control circuit (400) after the select transistor (T4) has completed transmitting the received second voltage to the APS read circuit (220); whereby, when the first reset transistor (T2) is in the ON state, the floating diffusion node (FD1) and the power supply (VDD) are short-circuited, that is, the photocharge accumulated in the floating diffusion node (FD1) moves to the power supply (VDD), thereby performing a reset on the floating diffusion node (FD1); accordingly, when the first reset transistor (T2) is in the OFF state, the photocharge accumulated in the floating diffusion node (FD1) does not move to the power supply (VDD), that is, the floating diffusion node (FD1) is not reset. When performing a reading of the APS, photocharge must be accumulated in the floating diffusion node (FD1), that is, since the floating diffusion node (FD1) cannot be reset, it can be understood that during the process of continuing the first photoelectric conversion, and before the first transmission transistor (T1) is in the ON state, the first reset transistor (T2) must be triggered to the OFF state according to the control signal (RST1) transmitted by the control circuit (400).

[0049] For the specific implementation above, referring still to FIG. 4, the EVS transmission circuit (310) may include a second reset transistor (T5) and a second drive transistor (T6); wherein the source of the second reset transistor (T5) and the gate of the second drive transistor (T6) are each connected to an input circuit (100), the drain of the second drive transistor (T6) and the drain and gate of the second reset transistor (T5) are each connected to a power supply (VDD), the source of the second drive transistor (T6) is connected to an EVS read circuit (320), and the gate of the second reset transistor (T5) is also connected to a control circuit (400). When the drain and gate of the second reset transistor (T5) are each connected to the power supply (VDD), a drain source voltage and a drain source current are formed between the drain and source of the second reset transistor (T5), and it can be understood that there is a logarithmic relationship between the formed drain source voltage and drain source current.

[0050] Specifically, the second reset transistor (T5) triggers an ON state according to a control signal (RST2) transmitted by the control circuit (400) in the first photoelectric conversion process (corresponding to A1 in FIG. 2, for example) and in the process where the first photoelectric conversion continues (corresponding to A2, A3, and A4 in FIG. 2, for example) and after the select transistor (T4) has completed transmitting the received second voltage to the APS read circuit (220), or in the process where the select transistor (T4) transmits the received second voltage to the APS read circuit (220), thereby outputting a corresponding first voltage to the second drive transistor (T6) according to the photocurrent transmitted by the input circuit (100); Here, the photocurrent is equal to the current between the drain and source of the second reset transistor (T5) (i.e., drain-source current), and the first voltage is equal to the voltage between the drain and source of the second reset transistor (T5) (i.e., drain-source voltage), and there is a logarithmic relationship between the photocurrent and the first voltage.

[0051] Specifically, the second drive transistor (T6) transmits the received first voltage to the EVS read circuit (320), so that the EVS read circuit (320) subsequently outputs a corresponding event signal according to the difference between the received first voltage and the reference voltage. Here, since the second drive transistor (T6) corresponds to a voltage buffer in the specific implementation, it can output a voltage that matches the first voltage to the EVS read circuit (320).

[0052] Specifically, the second reset transistor (T5) also triggers an off state according to a control signal (RST2) transmitted by the control circuit (400) when performing the exposure of the APS; wherein, when the second reset transistor (T5) is in the off state, it cannot output a first voltage to the second drive transistor (T6).

[0053] From the description of the specific implementation above, it can be seen that the APS transmission circuit (210) and the EVS transmission circuit (310) in the specific implementation use a total of six transistors. In this case, the photoelectric conversion element of the input circuit (100) may use a photodiode and a phototransistor, but is not limited thereto.

[0054] To clearly understand the specific implementation described above, the specific implementation is described in detail through the specific example below. Furthermore, referring to FIG. 5, FIG. 5 is a schematic diagram of the structure of a pixel array according to an embodiment of the present invention; in the embodiment, the pixel array is a 4x4 matrix (i.e., containing a total of 16 pixels), and A, B, C, and D represent the first, second, third, and fourth rows of the pixel array, respectively, i.e., the A row pixel, B row pixel, C row pixel, and D row pixel, respectively, and four APS read circuits (220) (i.e., a, b, c, and d) complete parallel reading in the column direction in the pixel array (i.e., pixels in the same column of the pixel array share the same APS read circuit), for example, when A11, A12, A13, and A14 of the A row pixels are selected, their pixel data is read by each of the four APS read circuits (220) (i.e., a, b, c, and d); Likewise, after reading the pixel data of the A row pixel, the B, C, and D row pixels can be read one row at a time through four APS reading circuits (220) (i.e., a, b, c, and d); provided, however, when the A row pixel is selected, the reading channels for the B, C, and D row pixels are closed. This is merely one embodiment, and it can be understood that the size of the pixel matrix can be set according to actual application scenarios, such as a 480x640 matrix, and that the embodiments of the present invention do not place inherent limitations thereon.

[0055] When the exposure method of APS is global exposure, further referring to FIG. 6, FIG. 6 is a schematic diagram of the first on / off state of each transistor in a pixel when the pixel structure according to an embodiment of the present invention is as illustrated in FIG. 4; where, before "-" represents a control signal (e.g., if before "-" is RST2, it represents the control signal (RST2)), and after "-" represents the row number of the pixel (e.g., if after "-" is A, it represents the A row pixel; if after "-" is A, it represents the A row pixel, B row pixel, C row pixel, D row pixel), and other schematic diagrams of on / off states are likewise. Before time T0, the pixel is performing EVS image output, and the control circuit (400) controls the RST2 of the AD row pixel to a high level, the gate and drain of the second reset transistor (T5) of the AD row pixel are short-circuited, and the first transfer transistor (T1) of the AD row pixel is in an off state. At this time, the input circuit (100) is configured to perform a first photoelectric conversion of the incident light to generate a corresponding photocurrent. The generated photocurrent is transmitted to a second reset transistor (T5), causing the second reset transistor (T5) to generate a first voltage corresponding to the photocurrent, and the second drive transistor (T6) transmits the first voltage to an EVS reading circuit (320), causing the EVS reading circuit (320) to determine a change in the intensity of the incident light according to the difference between the first voltage and the reference voltage and output a corresponding event signal. At time T0, the pixel begins to perform output of an APS image, and the control circuit (400) controls the RST2 of the AD row pixel to a low level and disconnects the second reset transistor (T5) of the AD row pixel. At this time, the input circuit (100) is configured to perform a second photoelectric conversion of the incident light to generate a corresponding photocharge.At time T1, the control circuit (400) is configured to control the RST1 of the AD row pixel to a low level, thereby turning off the first reset transistor (T2) of the AD row pixel and releasing the reset for the floating diffusion node (FD1). At time T4, the control circuit (400) controls the TX1 of the AD row pixel to a high level, thereby turning on the first transfer transistor (T1) of the AD row pixel, at which time the first transfer transistor (T1) of the AD row pixel transmits photocharges to each floating diffusion node (FD1) to form a corresponding second voltage. The first drive transistor (T3) transmits the second voltage to the select transistor (T4). At time T3, the control circuit (400) controls the SEL of the A row pixel to a high level so that the selection transistor (T4) of the A row pixel is turned on, i.e., A11, A12, A13, and A14 of the A row pixel, and reads the pixel data of A11, A12, A13, and A14 of the A row pixel through four APS reading circuits (220) (i.e., a, b, c, and d). At time T4, the control circuit (400) controls the SEL of the B row pixel to a high level so that the selection transistor (T4) of the B row pixel is turned on, i.e., B11, B12, B13, and B14 of the B row pixel, and reads the pixel data of B11, B12, B13, and B14 of the B row pixel through four APS reading circuits (220) (i.e., a, b, c, and d). At time T5, the control circuit (400) controls the SEL of the row C pixel to a high level so that the selection transistor (T4) of the row C pixel is turned on, i.e., selects C11, C12, C13 and C14 of the row C pixel, and reads the pixel data of C11, C12, C13 and C14 of the row C pixel through four APS reading circuits (220) (i.e., a, b, c and d).At time T6, the control circuit (400) controls the SEL of the D-row pixel to a high level so that the selection transistor (T4) of the D-row pixel is turned on, i.e., selects D11, D12, D13, and D14 of the D-row pixel, and reads the pixel data of D11, D12, D13, and D14 of the D-row pixel through four APS reading circuits (220) (i.e., a, b, c, and d). Thus, a complete APS image of one frame is output.

[0056] In the process described above, the reading time is from time T3 to time T7, and during the reading time, the control circuit (400) controls the RST2 of the AD row pixel to a high level, the gate and drain of the second reset transistor (T5) of the AD row pixel are short-circuited, and the first transmission transistor (T1) of the AD row pixel is turned off. At this time, the input circuit (100) is configured to perform a second photoelectric conversion of the incident light to generate a corresponding photocurrent (i.e., the pixel performs the output of the EVS image). The generated photocurrent is transmitted to the second reset transistor (T5), causing the second reset transistor (T5) to generate a corresponding first voltage according to the photocurrent, and the second drive transistor (T6) transmits the first voltage to the EVS reading circuit (320), causing the EVS reading circuit (320) to determine the change in the intensity of the incident light according to the difference between the first voltage and the reference voltage and output a corresponding event signal. In addition, the image output from the above-described process may be referenced to FIG. 7, which is a schematic diagram of the output image when the on / off state of each transistor in the pixel according to an embodiment of the present invention is as shown in FIG. 6.

[0057] In the above-described process, it can be understood that the purpose of setting the SEL of the AD row pixel in this way is to combine with the timing sequence in which the RST1 of the AD row pixel changes to a high level, that is, when the pixel of each row of A, B, C, and D rows is read, the corresponding APS reading circuit (220) makes the electrical signal in the corresponding floating diffusion node (FD1) different from RST1, thereby offsetting the imbalance of the charge detection amplifier (i.e., floating diffusion node (FD1)). Furthermore, in the above-described process, it can be understood that the embodiment of the present invention performs the exposure of the APS (i.e., the second photoelectric conversion of incident light) using a portion of the time when outputting the EVS image, and performs the EVS operation within the APS reading time, but does not affect the EVS image output.

[0058] When the exposure method of the APS is shutter exposure, further referring to FIG. 8, FIG. 8 is a schematic diagram of the second on / off state of each transistor in a pixel when the pixel structure according to an embodiment of the present invention is as illustrated in FIG. 4. At time T0, the control circuit (400) controls RST2 and RST1 of the A-row pixel to a low level so that the first reset transistor (T2) and the second reset transistor (T5) are in an off state. At this time, the input circuit (100) is configured to perform a second photoelectric conversion of the incident light to generate a corresponding photocharge. At time T3, the control circuit (400) controls TX1 of the A-row pixel to a high level so that the first transfer transistor (T1) of the A-row pixel is in an on state, and the first transfer transistor (T1) of the A-row pixel forms a corresponding second voltage by transferring the photocharge to the floating diffusion node (FD1). The first drive transistor (T3) transfers the second voltage to the select transistor (T4). At time T1, the control circuit (400) controls the SEL of the row A pixel to a high level so that the select transistor (T4) of the row A pixel is turned on, i.e., selects A11, A12, A13, and A14 of the row A pixel, and reads the pixel data of A11, A12, A13, and A14 of the row A pixel through four APS read circuits (220) (i.e., a, b, c, and d). In addition, the control circuit (400) controls the RST2 and RST1 of the row A pixel to a high level and TX1 to a low level so that the first reset transistor (T2) and the second reset transistor (T5) of the row A pixel are turned on, disconnects the first transfer transistor (T1), i.e., starts outputting the EVS image for the row A pixel at time T1. Additionally, at time T0, the control circuit (400) only needs to control RST1 to a low level before the first transmission transistor (T1) is in the ON state, so that it does not need to control RST1 of row A pixel to a low level.

[0059] Likewise, at time T1-T2, according to the process described above, B11, B12, B13, and B14 of row B pixels can be selected, and pixel data of B11, B12, B13, and B14 of row B pixels can be read through four APS reading circuits (220) (i.e., a, b, c, and d); at time T2-T3, according to the process described above, C11, C12, C13, and C14 of row C pixels can be selected, and pixel data of C11, C12, C13, and C14 of row C pixels can be read through four APS reading circuits (220) (i.e., a, b, c, and d); At time T3-T4, following the process described above, D11, D12, D13, and D14 of row D pixels can be selected, and pixel data of D11, D12, D13, and D14 of row D pixels can be read through four APS reading circuits (220) (i.e., a, b, c, and d). Here, when row A pixels perform the output of an APS image, row B, C, and D pixels can perform the output of an EVS image, and the pixels of each row do not affect each other, and after outputting the APS image corresponding to each row pixel, that is, by controlling the RST2 and RST1 of the row pixels to a high level so that the second reset transistor (T5) and the first reset transistor (T2) of the row pixels are turned on, the EVS image output operation of the row pixels can be started. In addition, the image output from the above-described process may be referenced to FIG. 9, which is a schematic diagram of the output image when the on / off state of each transistor in the pixel according to an embodiment of the present invention is as shown in FIG. 8.

[0060] In the process described above, the purpose of setting the SEL of the AD row pixel in this way is to combine with the timing sequence in which the RST1 of the AD row pixel changes to a low level, that is, when the pixel of each row of the A, B, C and D row pixels is read, the corresponding APS reading circuit (220) differentiates the electrical signal in the corresponding floating diffusion node (FD1) from the RST1, thereby offsetting the KT / C noise and the imbalance of the charge detection amplifier (i.e., floating diffusion node (FD1)) that occurs when the floating diffusion node (FD1) reset is released.

[0061] Additionally, shutter exposure can be controlled such as first row pixel exposure, second row pixel non-exposure, third row pixel exposure, fourth row pixel non-exposure, or pixel exposure at intervals of two rows, and in the non-exposed rows, pixels can perform EVS image output. For example, regarding the above-described embodiment, time-division exposure and time-division reading of row A pixels and row C pixels, and non-exposure of row B pixels and row D pixels can be controlled, in which case the pixel matrix is ​​a 2x2 matrix corresponding to APS and a 4x4 matrix corresponding to EVS. This method can be applied to output images for some regions of interest or to some applications where there are low requirements regarding the amount of image information. Of course, the shutter exposure also controls the non-immediate exposure of the second row pixel (i.e., the RST2 of the B row pixel in Fig. 8 remains at a high level even after time T1) after the pixel data of the first row pixel is read (time T1 in Fig. 8), and the second row pixel can perform the output of the EVS image even with the time difference between the completion of the pixel data reading of the first row pixel and the start of the exposure of the second row pixel.

[0062] In another embodiment, further referring to FIG. 10, FIG. 10 is a schematic diagram of a second circuit structure of a pixel according to an embodiment of the present invention. Based on the above embodiment, the EVS transmission circuit (310) may further include a second transmission branch, and the second transmission branch is connected to a second reset branch, a second drive branch, an input circuit (100), and a control circuit (400). In this embodiment, the second transmission branch triggers an operating state through a control signal (TX2) transmitted by the control circuit (400) during the first photoelectric conversion process; whereby, when the second transmission branch is in an operating state, the second transmission branch transmits a photocurrent generated by the input circuit (100) to the second reset branch.

[0063] As a specific implementation of the present embodiment, referring still to FIG. 10, the second transmission branch may be composed of a second transmission transistor (T7). That is, in the specific implementation, the EVS transmission circuit (310) has one more transmission transistor (i.e., the second transmission transistor (T7)) than in the above embodiment, and the source of the second reset transistor (T5) and the gate of the second drive transistor (T6) are each connected to the first terminal of the second transmission transistor (T7), the second terminal of the second transmission transistor (T7) is connected to the input circuit (100), and the third terminal is connected to the control circuit (400).

[0064] Specifically, the second transmission transistor (T7) triggers an ON state according to a control signal (TX2) transmitted by the control circuit (400) during the first photoelectric conversion process (corresponding to A1 in FIG. 2, for example) and during the process in which the first photoelectric conversion continues (corresponding to A2, A3, and A4 in FIG. 2, for example) and after the selection transistor (T4) has completed transmitting the received second voltage to the APS read circuit (220), or during the process in which the selection transistor (T4) transmits the received second voltage to the APS read circuit (220); wherein, when the second transmission transistor (T7) is in the ON state, the second transmission transistor (T7) transmits the photocurrent generated by the input circuit (100) to the second reset transistor (T5).

[0065] Specifically, the second transmission transistor (T7) also triggers an off state according to a control signal (TX2) transmitted by the control circuit (400) when performing the exposure of the APS; wherein, when the second transmission transistor (T7) is in the off state, the input circuit (100) cannot transmit photocurrent to the second reset transistor (T5) through the second transmission transistor (T7).

[0066] In the specific implementation above, the second transmission transistor (T7) can be understood to perform the same role as the first transmission transistor (T1) of the APS transmission circuit (210). Additionally, when the exposure method of the APS is global exposure, the on / off state of each transistor in the pixel can be referenced in FIG. 11; when the exposure method of the APS is shutter exposure, the on / off state of each transistor in the pixel can be referenced in FIG. 12; the specific operation process may be similar to the above embodiment, and the only difference from the above embodiment is that the input circuit (100) can transmit photocurrent to the second reset transistor (T5) through the second transmission transistor (T7) only when the second transmission transistor (T7) is on.

[0067] From the description of the specific implementation above, it can be seen that the APS transmission circuit (210) and the EVS transmission circuit (310) in the specific implementation use a total of 7 transistors. In this case, the photoelectric conversion element of the input circuit (100) may use a photodiode and a phototransistor, but is not limited thereto. Preferably, the photoelectric conversion element in the input circuit (100) uses a clamp photodiode.

[0068] In another embodiment, further referring to FIG. 13, FIG. 13 is a schematic diagram of a third circuit structure of a pixel according to an embodiment of the present invention. An APS transmission circuit (210) may include a floating diffusion node (FD), an output branch, and a reset branch; wherein the floating diffusion node (FD) is connected to the output branch, the input circuit (100), and the reset branch, and the output branch is also connected to the APS read circuit (220). In this embodiment, the reset branch triggers a non-working state through a control signal (RST) transmitted by the control circuit (400) during the course of the first photoelectric conversion. During the course of the first photoelectric conversion, and when the reset branch is in a non-working state, the floating diffusion node (FD) accumulates the photocharge transmitted by the input circuit (100) and generates a corresponding second voltage. The output branch triggers a working state through a control signal (SEL) transmitted by the control circuit (400); Here, when the output branch is in an operating state, the output branch transmits a second voltage in the floating diffusion node (FD) to the APS readout circuit (220), so that the APS readout circuit (220) subsequently outputs a corresponding grayscale signal according to the received second voltage.

[0069] Specifically, the output branch may include a first drive branch and a select branch; wherein the select branch is connected to the first drive branch, the control circuit (400), and the APS read circuit (220), and the first drive branch is also connected to the floating diffusion node (FD). In this embodiment, the first drive branch buffers the potential of the floating diffusion node (FD) during the course of the first photoelectric conversion and outputs a second voltage to the select branch. The select branch triggers an operating state via a control signal (SEL) transmitted by the control circuit (400); wherein, when the select branch is in the operating state, the select branch transmits the second voltage in the floating diffusion node (FD) to the APS read circuit (220), so that the APS read circuit (220) subsequently outputs a corresponding grayscale signal according to the received second voltage.

[0070] For the present embodiment, still referring to FIG. 13, the EVS transmission circuit (310) may include a second drive branch, and the second drive branch is connected to a floating diffusion node (FD) and an EVS read circuit (320). In the present embodiment, the reset branch also triggers an operating state via a control signal (RST) transmitted by the control circuit (400) during the course of the first photoelectric conversion and after the selection branch has completed transmitting the received second voltage to the APS read circuit (220); wherein, when the reset branch is in the operating state, the reset branch outputs a corresponding first voltage according to the photocurrent generated by the input circuit (100). The second drive branch transmits the first voltage to the EVS read circuit (320) so that the EVS read circuit (320) subsequently outputs a corresponding event signal according to the difference between the received first voltage and the reference voltage.

[0071] Specifically, the reset branch may include a reset transistor (T1), the source of the reset transistor (T1) is connected to a floating diffusion node (FD), the drain and gate of the reset transistor (T1) are each connected to a power supply (VDD), and the gate of the reset transistor (T1) is also connected to a control circuit (400). In this embodiment, the reset transistor (T1) triggers an off state via a control signal (RST) transmitted by the control circuit (400) during the course of the first photoelectric conversion, and triggers an on state via a control signal (RST) transmitted by the control circuit (400) during the course of the first photoelectric conversion and after the selection branch has completed transmitting a second voltage to the APS readout circuit (220); wherein, when the reset transistor (T1) is in the on state, the reset transistor (T1) outputs a corresponding first voltage according to the photocurrent generated by the input circuit (100); Here, the photocurrent is equal to the current between the drain and source of the reset transistor (T1), the first voltage is equal to the voltage between the drain and source of the reset transistor (T1), and there is a logarithmic relationship between the photocurrent and the first voltage.

[0072] As a specific implementation of the present embodiment, referring still to FIG. 13, in the APS transmission circuit (210), in addition to the reset branch composed of the reset transistor (T1), other branches may also be composed of corresponding transistors, for example, the first drive branch may include the first drive transistor (T2), and the select branch may include the select transistor (T3). Accordingly, in the EVS transmission circuit (310), the second drive branch may be composed of corresponding transistors, for example, the second drive branch may include the second drive transistor (T4).

[0073] In the specific implementation above, the APS transmission circuit (210) may include a reset transistor (T1), a first drive transistor (T2), a select transistor (T3), and a floating diffusion node (FD); wherein the input circuit (100), the EVS transmission circuit (310), the source of the reset transistor (T1) and the gate of the first drive transistor (T2) are each connected to the floating diffusion node (FD), the drain of the first drive transistor (T2) and the drain and gate of the reset transistor (T1) are each connected to a power supply (VDD), the gate of the reset transistor (T1) is also connected to a control circuit (400), the source of the first drive transistor (T2) is connected to the drain of the select transistor (T3), the source of the select transistor (T3) is connected to an APS reading circuit (220), and the gate is connected to a control circuit (400). When the drain and gate of the reset transistor (T1) are each connected to the power supply (VDD), a drain source voltage and a drain source current are formed between the drain and source of the reset transistor (T1), and it can be understood that there is a logarithmic relationship between the formed drain source voltage and drain source current.

[0074] Specifically, the reset transistor (T1) triggers an off state according to a control signal (RST) transmitted by the control circuit (400) during the process of the first photoelectric conversion continuing.

[0075] Specifically, the floating diffusion node (FD) forms a corresponding second voltage by accumulating the photocharge generated by the input circuit (100) during the process in which the first photoelectric conversion continues and when the reset transistor (T1) is in the off state. Here, the floating diffusion node (FD) corresponds to a charge detection amplifier in the specific implementation.

[0076] Specifically, the first drive transistor (T2) transmits the second voltage formed by the floating diffusion node (FD) to the select transistor (T3) during the process in which the first photoelectric conversion continues. Here, the first drive transistor (T2) corresponds to a source following amplifier capable of outputting a voltage matching the second voltage to the select transistor (T3) by buffering the potential at the floating diffusion node (FD) in the specific implementation.

[0077] Specifically, the selection transistor (T3) triggers an ON state according to a control signal (SEL) transmitted by the control circuit (400) during the course of the first photoelectric conversion; whereby, when the selection transistor (T3) is in the ON state, the selection transistor (T3) transmits the received second voltage to the APS readout circuit (220), so that the APS readout circuit (220) subsequently outputs a corresponding grayscale signal according to the received second voltage. Accordingly, the selection transistor (T3) also triggers an OFF state according to a control signal (SEL) transmitted by the control circuit (400) during the course of the first photoelectric conversion and after the selection transistor (T3) has completed transmitting the received second voltage to the APS readout circuit (220); whereby, when the selection transistor (T3) is in the OFF state, the selection transistor (T3) cannot transmit the received second voltage to the APS readout circuit (220).

[0078] For the specific implementation above, still referring to FIG. 13, the EVS transmission circuit (310) may include a second drive transistor (T4), the gate of the second drive transistor (T4) is connected to a floating diffusion node (FD), the source is connected to an EVS read circuit (320), and the drain of the second drive transistor (T4) is connected to a power supply (VDD).

[0079] Specifically, the reset transistor (T1) also triggers an ON state according to a control signal (RST) transmitted by the control circuit (400) during the first photoelectric conversion process (corresponding to A1 in FIG. 2, for example) and during the process in which the first photoelectric conversion continues (corresponding to A2, A3, and A4 in FIG. 2, for example), and after the select transistor (T3) has completed transmitting the received second voltage to the APS read circuit (220); where, when the reset transistor (T1) is in the ON state, it outputs a corresponding first voltage to the second drive transistor (T4) according to the photocurrent transmitted by the input circuit (100); where, the photocurrent is equal to the current between the drain and source of the reset transistor (T1) (i.e., drain-source current), and the first voltage is equal to the voltage between the drain and source of the reset transistor (T1) (i.e., drain-source voltage), and there is a logarithmic relationship between the photocurrent and the first voltage. It can be understood that when the reset transistor (T1) is in the off state, the first voltage cannot be output to the second drive transistor (T4).

[0080] Specifically, the second drive transistor (T4) transmits the received first voltage to the EVS read circuit (320), so that the EVS read circuit (320) subsequently outputs a corresponding event signal according to the difference between the received first voltage and the reference voltage. Here, the second drive transistor (T4) corresponds to a voltage buffer in the specific implementation above, thereby enabling the output of a voltage matching the first voltage to the EVS read circuit (320).

[0081] In the above specific implementation, the APS transmission circuit (210) of a single pixel shares the same reset transistor (T1) as the EVS transmission circuit (310), thereby making the size of the single pixel smaller and further reducing the overall size of the image sensor. Furthermore, in the above specific implementation, the APS transmission circuit (210) and the EVS transmission circuit (310) use a total of four transistors; in this case, the photoelectric conversion element in the input circuit (100) may use a photodiode and a phototransistor, but is not limited thereto.

[0082] To clearly understand the specific implementation described above, the specific implementation is described in detail below, using the pixel array still illustrated in FIG. 5 as an example. When the exposure method of the APS is shutter exposure, further referring to FIG. 14, FIG. 14 is a schematic diagram of the on / off state of each transistor in the pixel when the pixel structure according to an embodiment of the present invention is as illustrated in FIG. 13. Before time T0, the pixel is performing the output of an EVS image, and the control circuit (400) controls the RST of the AD row pixel to a high level, and the gate and drain of the reset transistor (T1) are short-circuited. At this time, the input circuit (100) is configured to perform a first photoelectric conversion of the incident light to generate a corresponding photocurrent. At time T0, the control circuit (400) controls the RST of the A row pixel to a low level, and the first drive transistor (T2) transmits a second voltage formed by the photocharge in the floating diffusion node (FD) to the select transistor (T3). The control circuit (100) controls the SEL of the A-row pixel to a high level so that the select transistor (T3) of the A-row pixel is turned on, i.e., A11, A12, A13, and A14 of the A-row pixel, and reads the pixel data of A11, A12, A13, and A14 of the A-row pixel through four APS read circuits (220) (i.e., a, b, c, and d). At time T1, the control circuit (400) controls the RST of the A-row pixel to a high level so that the A-row pixel performs the output of the EVS image. Here, the four APS read circuits (220) (i.e., a, b, c, and d) must complete reading the A-row pixel before the rising edge of the RST.

[0083] Likewise, at time T1-T2, according to the process described above, B11, B12, B13, and B14 of row B pixels can be selected, and pixel data of B11, B12, B13, and B14 of row B pixels can be read through four APS reading circuits (220) (i.e., a, b, c, and d); at time T2-T3, according to the process described above, C11, C12, C13, and C14 of row C pixels can be selected, and pixel data of C11, C12, C13, and C14 of row C pixels can be read through four APS reading circuits (220) (i.e., a, b, c, and d); At time T3-T4, following the process described above, D11, D12, D13, and D14 of the D row pixels can be selected, and the pixel data of D11, D12, D13, and D14 of the D row pixels can be read through four APS reading circuits (220) (i.e., a, b, c, and d).

[0084] It should be understood that the above-described embodiments are merely preferred implementations of the embodiments of the present invention and that the embodiments of the present invention are not the sole limitation regarding the specific configuration of a single pixel; thereby, those skilled in the art can flexibly configure it according to actual application scenarios based on the embodiments of the present invention.

[0085] Referring to FIG. 15, FIG. 15 is a schematic flowchart of an image output method according to an embodiment of the present invention. An embodiment of the present invention further provides an image output method applied to an image sensor according to an embodiment of the present invention, and the image output method includes the following steps 1501 to 1504.

[0086] Step 1501, the input circuit performs a first photoelectric conversion for incident light and generates a corresponding photocurrent during the EVS mode operation period, and performs a second photoelectric conversion for incident light and generates a corresponding photocharge during the APS mode operation period.

[0087] In an embodiment of the present invention, the input circuit (100) includes a photoelectric conversion element and is configured to perform photoelectric conversion of incident light, that is, during the EVS mode operation period, perform a first photoelectric conversion for the incident light and generate a corresponding photocurrent, and during the APS mode operation period, perform a second photoelectric conversion for the incident light and generate a corresponding photocharge; wherein the first photoelectric conversion is the exposure of EVS and the second photoelectric conversion is the exposure of APS. From this, a portion of the period (i.e., the APS mode operation period) is allocated to perform the exposure of APS during the EVS exposure process, that is, the exposure of EVS and the exposure of APS are performed alternately; for example, taking A1, B1, and A2 in FIG. 2 as examples, it can be seen that a portion of the period (i.e., B1) is allocated to perform the exposure of APS during the EVS exposure process (i.e., a continuous period between A1 and A2).

[0088] Step 1502, the EVS circuit outputs a corresponding event signal according to the difference between the first voltage corresponding to the photocurrent and the reference voltage during the first photoelectric conversion process.

[0089] In an embodiment of the present invention, the EVS circuit (300) outputs a corresponding event signal according to the difference between a first voltage corresponding to the photocurrent and a reference voltage during a first photoelectric conversion process; wherein the event signal generates a corresponding EVS image. In an actual application, when a pixel is outputting an EVS image, the input circuit (100) performs a first photoelectric conversion on the incident light and outputs a corresponding photocurrent to the EVS circuit (300); then, the EVS circuit (300) outputs a corresponding event signal according to the difference between a first voltage corresponding to the received photocurrent and a reference voltage, thereby subsequently generating a corresponding EVS image using the output event signal. Here, the difference between the first voltage and the reference voltage represents a change in the intensity of the incident light (i.e., increase, decrease, or invariance), which means that the EVS circuit (300) actually outputs a corresponding event signal according to the change in the intensity of the incident light, for example, the change in the intensity of the incident light is determined by whether the difference between the first voltage and the reference voltage is greater than 0, less than 0, or equal to 0.

[0090] Step 1503, the APS circuit outputs a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process of the first photoelectric conversion continuing.

[0091] In an embodiment of the present invention, the APS circuit (200) outputs a corresponding grayscale signal according to a second voltage corresponding to a photocharge during the process in which the first photoelectric conversion continues (i.e., in the next first photoelectric conversion process after the second photoelectric conversion is completed, or within the next EVS mode operation period adjacent to the APS mode operation period); wherein the grayscale signal generates a corresponding APS image. For example, taking A1, B1, and A2 of FIG. 2 as examples, the input circuit (100) performs a second photoelectric conversion on the incident light in B1 to generate a corresponding photocharge, and the APS circuit (200) outputs a corresponding grayscale signal according to a second voltage corresponding to the generated photocharge in A2. The process of the APS circuit (200) outputting a grayscale signal is actually the reading process of the APS, and the process of the APS circuit (200) outputting a grayscale signal is performed within the next EVS mode operation period (e.g., A2) adjacent to the APS mode operation period (e.g., B1), and the EVS operation can still be performed within A2, that is, since the reading process of the APS does not affect the exposure and reading of the EVS, it can be understood that if a single pixel contains both an APS pixel and an EVS pixel, the single pixel can output an APS image and an EVS image simultaneously.

[0092] Step 1504, the control circuit outputs a corresponding APS image according to the grayscale signal and outputs a corresponding EVS image according to the event signal.

[0093] In an embodiment of the present invention, the control circuit (400) outputs a corresponding APS image according to a grayscale signal and outputs a corresponding EVS image according to an event signal. In an actual application, when the pixel is outputting an APS image, the APS circuit (200) outputs a corresponding grayscale signal to the control circuit (400) according to a second voltage corresponding to the received photocharge; then, the control circuit (400) outputs a corresponding APS image according to the received grayscale signal and displays it to the user. Likewise, when the pixel is outputting an EVS image, the EVS circuit (300) outputs a corresponding event signal to the control circuit (400) according to the difference between a first voltage corresponding to the received photocurrent and a reference voltage; then, the control circuit (400) outputs a corresponding EVS image according to the received event signal and displays it to the user.

[0094] The steps of the method or algorithm described together with the embodiments disclosed herein may be directly implemented in hardware, a software module executed by a processor, or a combination of both. The software module may be placed in random access memory (RAM), memory, read-only memory (ROM), electrically programmable ROM, electrically erasable and programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0095] In the embodiments described above, the invention may be implemented wholly or partially through software, hardware, firmware, or any combination thereof. When implemented using software, the invention may be implemented wholly or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the invention occurs wholly or partially. The computer may be a general computer, a dedicated computer, a computer network, or other programmable device. The computer instructions may be stored on a computer-readable storage medium or transferred from one computer-readable storage medium to another computer-readable storage medium; for example, the computer instructions may be transferred from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, fiber optic, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium may be any available medium accessible to a computer or a data storage device such as a server or data center comprising one or more sets of available media. Available media may be magnetic media (e.g., floppy disk, hard disk, tape), optical media (e.g., DVD), or semiconductor media (e.g., Solid State Disk).

[0096] Furthermore, each embodiment of the present invention is described using a progressive approach, with a focus on explaining the differences between each embodiment and other embodiments; identical and similar parts between embodiments may be referenced to one another. In the case of product-type embodiments, the description is relatively simple because they are similar to method-type embodiments, and relevant details may be referred to by referring to parts of the descriptions in the method-type embodiments.

[0097] Furthermore, in the content of the invention, relational terms such as first and second, etc., are used merely to distinguish one entity or operation from another entity or operation and do not necessarily require or imply that any such actual relationship or order exists between these entities or operations. Moreover, the terms “include,” “include,” or any other variations thereof, by meaning that they include non-exclusive inclusion, a process, method, article, or facility comprising a series of elements includes not only such elements but also other elements not explicitly enumerated, or elements inherent to such process, method, article, or facility. Unless further limitation is given, an element limited by the phrase “...includes one” does not exclude the existence of other identical elements in the process, method, article, or facility comprising said element.

[0098] The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the contents of the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and general principles defined in the contents of the present invention may be implemented in other embodiments without departing from the spirit or scope of the contents of the present invention. Accordingly, the contents of the present invention are not limited to these embodiments shown in the contents of the present invention, but should conform to the broadest scope consistent with the principles and novel characteristics disclosed in the contents of the present invention.

Claims

Claim 1 An image sensor comprising a pixel array composed of a plurality of pixels, the image sensor comprising an input circuit, an APS circuit, an EVS circuit, and a control circuit, wherein each of the pixels comprises both the APS circuit and the EVS circuit; wherein the input circuit is connected to the APS circuit and the EVS circuit, and the control circuit is connected to the APS circuit and the EVS circuit; The working time unit of the input circuit is a working time for outputting a 1-frame APS image, and the working time unit includes an EVS mode working period and an APS mode working period, wherein a single APS mode working period is between adjacent EVS mode working periods; within a cycle for outputting a 1-frame APS image, the time length of the EVS mode working period is longer than the time length of the APS mode working period; the input circuit performs a first photoelectric conversion for incident light during the EVS mode working period and generates a corresponding photocurrent, and performs a second photoelectric conversion for the incident light during the APS mode working period and generates a corresponding photocharge; the EVS circuit outputs a corresponding event signal according to the difference between a first voltage corresponding to the photocurrent and a reference voltage during the first photoelectric conversion process; the APS circuit outputs a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process in which the first photoelectric conversion continues; and the control circuit outputs a corresponding EVS image according to the event signal and outputs a corresponding APS image according to the grayscale signal, characterized in that the image Sensor. Claim 2 An image sensor according to claim 1, wherein the EVS circuit comprises an EVS transmission circuit and an EVS reading circuit; wherein the EVS transmission circuit is connected to the input circuit and the EVS reading circuit, and the control circuit is connected to the EVS transmission circuit and the EVS reading circuit; wherein the EVS transmission circuit outputs a corresponding first voltage according to the photocurrent in the first photoelectric conversion process; and wherein the EVS reading circuit outputs a corresponding event signal according to the difference between the first voltage and the reference voltage. Claim 3 An image sensor according to claim 2, wherein the EVS transmission circuit includes a reset branch and a drive branch; wherein the reset branch and the drive branch are each connected to the input circuit, the reset branch is also connected to the control circuit, and the drive branch is also connected to the EVS read circuit; wherein the reset branch triggers an operating state through a first control signal transmitted by the control circuit during the first photoelectric conversion process; and when the reset branch is in the operating state, the reset branch outputs a corresponding first voltage according to the photocurrent; and wherein the drive branch transmits the first voltage to the EVS read circuit. Claim 4 An image sensor according to claim 3, wherein the reset branch includes a reset transistor, the drain and gate of the reset transistor are each connected to a power source, the source of the reset transistor and the drive branch are each connected to the input circuit, and the gate of the reset transistor is also connected to the control circuit; the reset transistor triggers an ON state through a first control signal transmitted by the control circuit during the first photoelectric conversion process; and when the reset transistor is in the ON state, the reset transistor outputs a corresponding first voltage according to the photocurrent; wherein the photocurrent is equal to the current between the drain and source of the reset transistor, the first voltage is equal to the voltage between the drain and source of the reset transistor, and there is a logarithmic relationship between the photocurrent and the first voltage. Claim 5 An image sensor according to claim 3, wherein the EVS transmission circuit further includes a transmission branch, and the transmission branch is connected to the reset branch, the drive branch, the input circuit, and the control circuit; wherein the transmission branch triggers an operating state through a second control signal transmitted by the control circuit during the first photoelectric conversion process; and wherein, when the transmission branch is in the operating state, the transmission branch transmits the photocurrent to the reset branch. Claim 6 An image sensor according to claim 2, wherein the APS circuit comprises an APS transmission circuit and an APS reading circuit; wherein the APS transmission circuit is connected to the input circuit and the APS reading circuit, and the control circuit is connected to the APS transmission circuit and the APS reading circuit; wherein the APS transmission circuit outputs a corresponding second voltage according to the photocharge during the process in which the first photoelectric conversion continues; and wherein the APS reading circuit outputs a corresponding grayscale signal according to the second voltage. Claim 7 An image sensor according to claim 6, wherein the APS transmission circuit comprises a transmission branch, a floating diffusion node, and an output branch; wherein the transmission branch is connected to the input circuit, the control circuit, and the floating diffusion node, and the output branch is connected to the floating diffusion node, the control circuit, and the APS readout circuit; wherein the transmission branch triggers an operating state through a first control signal transmitted by the control circuit during the process in which the first photoelectric conversion continues; wherein when the transmission branch is in the operating state, the transmission branch transmits the photocharge to the floating diffusion node; wherein the floating diffusion node accumulates the photocharge and generates a corresponding second voltage; wherein the output branch triggers an operating state through a second control signal transmitted by the control circuit; and wherein when the output branch is in the operating state, the output branch transmits the second voltage to the APS readout circuit. Claim 8 An image sensor according to claim 7, wherein the output branch includes a drive branch and a select branch; the select branch is connected to the drive branch, the control circuit and the APS read circuit, and the drive branch is also connected to the floating diffusion node; the drive branch buffers the potential of the floating diffusion node and outputs the second voltage to the select branch; the select branch triggers an operating state through a second control signal transmitted by the control circuit; and when the select branch is in the operating state, the select branch transmits the second voltage to the APS read circuit. Claim 9 An image sensor according to claim 7, wherein the APS transmission circuit further comprises a reset branch, the reset branch is connected to the floating diffusion node and the control circuit; after completing the transmission of the second voltage to the APS reading circuit, the reset branch triggers an operating state through a third control signal transmitted by the control circuit; and when the reset branch is in the operating state, the photocharge accumulated in the floating diffusion node moves to the outside. Claim 10 An image sensor according to claim 9, wherein the reset branch includes a reset transistor, the source of the reset transistor is connected to the floating diffusion node, the gate is connected to the control circuit, and the drain is connected to a power source; after completing the transmission of the second voltage to the APS readout circuit, the reset transistor triggers an ON state through a third control signal transmitted by the control circuit; and when the reset transistor is in the ON state, the photocharge accumulated in the floating diffusion node moves to the power source. Claim 11 An image sensor according to claim 6, wherein the APS transmission circuit comprises a floating diffusion node, an output branch, and a reset branch; wherein the floating diffusion node is connected to the output branch, the input circuit, and the reset branch, and the output branch is also connected to the APS readout circuit; wherein the reset branch triggers a non-operating state through a first control signal transmitted by the control circuit during the course of the first photoelectric conversion; wherein the floating diffusion node accumulates the photocharge and generates a corresponding second voltage when the reset branch is in the non-operating state; wherein the output branch triggers an operating state through a second control signal transmitted by the control circuit; and wherein, when the output branch is in the operating state, the output branch transmits the second voltage to the APS readout circuit. Claim 12 An image sensor according to claim 11, wherein the output branch comprises a first drive branch and a select branch; the select branch is connected to the first drive branch, the control circuit and the APS read circuit, and the first drive branch is also connected to the floating diffusion node; the first drive branch buffers the potential of the floating diffusion node and outputs the second voltage to the select branch; the select branch triggers an operating state through a second control signal transmitted by the control circuit; and when the select branch is in the operating state, the select branch transmits the second voltage to the APS read circuit. Claim 13 An image sensor according to claim 11, wherein the EVS transmission circuit includes a second drive branch, the second drive branch is connected to the floating diffusion node and the EVS read circuit; after completing the transmission of the second voltage to the APS read circuit, the reset branch also triggers an operating state through a first control signal transmitted by the control circuit; when the reset branch is in the operating state, the reset branch outputs a corresponding first voltage according to the photocurrent; and the second drive branch transmits the first voltage to the EVS read circuit. Claim 14 An image sensor according to claim 13, wherein the reset branch includes a reset transistor, the source of the reset transistor is connected to the floating diffusion node, the drain and gate of the reset transistor are each connected to a power source, and the gate of the reset transistor is also connected to the control circuit; after completing the transmission of the second voltage to the APS readout circuit, the reset transistor triggers an ON state through a first control signal transmitted by the control circuit; and when the reset transistor is in the ON state, the reset transistor outputs a corresponding first voltage according to the photocurrent; wherein the photocurrent is equal to the current between the drain and source of the reset transistor, the first voltage is equal to the voltage between the drain and source of the reset transistor, and there is a logarithmic relationship between the photocurrent and the first voltage. Claim 15 An image sensor according to claim 6, wherein all pixels within the same array unit in the pixel array share the same APS readout circuit; or all pixels in the pixel array share the same APS readout circuit; or each of all pixels in the pixel array includes one APS readout circuit. Claim 16 An image sensor according to paragraph 2, wherein all pixels within the same array unit in the pixel array share the same EVS readout circuit; or all pixels in the pixel array share the same EVS readout circuit; or each of all pixels in the pixel array includes one EVS readout circuit. Claim 17 An image sensor according to claim 1, wherein all pixels within the same array unit in the pixel array share the same control circuit; or all pixels in the pixel array share the same control circuit; or each of all pixels in the pixel array includes one control circuit. Claim 18 An image sensor according to claim 1, wherein all pixels within the same array unit in the pixel array share the same input circuit; or all pixels in the pixel array share the same input circuit; or each of all pixels in the pixel array includes one input circuit. Claim 19 An image output method applied to an image sensor comprising a pixel array composed of a plurality of pixels, wherein the image sensor comprises an input circuit, an APS circuit, an EVS circuit, and a control circuit, and each of the pixels comprises the APS circuit and the EVS circuit; wherein the input circuit is connected to the APS circuit and the EVS circuit, and the control circuit is connected to the APS circuit and the EVS circuit; The working time unit of the input circuit is a working time for outputting a 1-frame APS image, and the working time unit includes an EVS mode working period and an APS mode working period, wherein a single APS mode working period is between adjacent EVS mode working periods; within a cycle for outputting a 1-frame APS image, the time length of the EVS mode working period is longer than the time length of the APS mode working period; and the image output method comprises the steps of: the input circuit performing a first photoelectric conversion for incident light during the EVS mode working period and generating a corresponding photocurrent, and performing a second photoelectric conversion for the incident light during the APS mode working period and generating a corresponding photocharge; the EVS circuit outputting a corresponding event signal according to the difference between a first voltage corresponding to the photocurrent and a reference voltage during the first photoelectric conversion process; and the APS circuit outputting a corresponding grayscale signal according to a second voltage corresponding to the photocharge during the process in which the first photoelectric conversion continues. An image output method characterized by including the step of the control circuit outputting a corresponding EVS image according to the event signal and outputting a corresponding APS image according to the grayscale signal. Claim 20 A photoelectric device, wherein an image sensor according to any one of claims 1 to 18 is applied.

Images