Semiconductor devices, memory, and memory systems

Abstract

A semiconductor device, a memory, and a memory system are provided. The semiconductor device includes an array device and a plurality of source reading-out contacts, and the array device includes a plurality of channel structures and a source layer connected to the plurality of channel structures. The plurality of source reading-out contacts are connected to the source layer, and the plurality of source reading-out contacts and the plurality of channel structures are each located on both sides of the source layer, and the orthogonal projections of the plurality of source reading-out contacts on the source layer are distributed at equal intervals.

Description

Technology Field

[0001] Cross-reference regarding related applications

[0002] The present disclosure is based on Chinese patent application No. 202110323821.9 filed on March 26, 2021, claiming priority to this Chinese patent application, the entirety of which is incorporated by reference herein.

[0003] The present disclosure generally relates to electronic devices, and more specifically to semiconductor devices, memory, and memory systems. Background Technology

[0004] In the new 3D NAND structure, a first silicon substrate is formed first, and a plurality of array devices are formed on the front surface of the first silicon substrate and include a plurality of NAND strings, and then an array interconnection layer is formed on the plurality of NAND strings. Meanwhile, a second silicon substrate is formed, a peripheral device is formed on the second silicon substrate, and a peripheral interconnection layer is formed on the peripheral device. Then, the array interconnection layer on the array device is connected to the peripheral interconnection layer on the peripheral device using a method such as bonding. After that, the first silicon substrate is removed, and a source layer is formed on the side of the array device where the first silicon substrate was removed, and a source reading out contact, for example, an N-well pickup layer (NPU), is formed on the source layer, and after the source end is connected to the outside, the NPU is combined with an AL metal layer (connected to the peripheral device), thereby electrically connecting the array device to the peripheral device to enable signal transmission.

[0005] However, in conventional technology, the voltage drop between the NAND string and the source reading out contact fluctuates too much, affecting device performance.

[0006] The present disclosure aims to provide a semiconductor device, a memory, and a memory system to prevent the voltage drop between a NAND string and a source reading out contact from fluctuating too much in order to improve device performance.

[0007] In one aspect, the present disclosure provides a semiconductor device comprising an array device including a plurality of channel structures and a source layer connected to the plurality of channel structures, and a plurality of source reading-out contacts connected to the source layer—wherein the plurality of source reading-out contacts and the plurality of channel structures are each located on both sides of the source layer, and the orthogonal projections of the plurality of source reading-out contacts on the source layer are distributed at equal intervals.

[0008] In some embodiments, the semiconductor device further includes a plurality of rows of gate line slit structures extending along a first direction parallel to the source layer, and two adjacent rows of gate line slit structures have a first pitch between them.

[0009] In some embodiments, a plurality of source reading out contacts are arranged in a plurality of rows along a first direction, and source reading out contacts of the same row are distributed at equal intervals along the first direction.

[0010] In some embodiments, a plurality of source reading out contacts are arranged in a plurality of rows along a first direction, two adjacent rows of source reading out contacts have a second pitch between them, and the second pitch between any two adjacent rows of source reading out contacts is the same.

[0011] In some embodiments, the first pitch is the same as the second pitch.

[0012] In some embodiments, the orthogonal projection of each source leading out contact on the source layer is located between the orthogonal projections of two adjacent rows of gate line slit structures on the source layer.

[0013] In some embodiments, the orthogonal projection of each source leading out contact on the source layer is located at the center between the orthogonal projections of two adjacent rows of gate line slit structures on the source layer.

[0014] In some embodiments, the orthogonal projection of two adjacent rows of gate line slit structures on the source layer has an orthogonal projection of multiple rows of source leading out contacts on the source layer between them.

[0015] In some embodiments, the orthogonal projection of each source leading out contact on the source layer has an overlapping portion with the orthogonal projection of one of the gate line slit structures on the source layer.

[0016] In some embodiments, the source reading out contact includes a first source reading out contact and a second source reading out contact, wherein the orthogonal projection of the first source reading out contact on the source layer is located between the orthogonal projections of two adjacent rows of the gate line slit structure on the source layer, and the orthogonal projection of the second source reading out contact on the source layer has a portion that overlaps with the orthogonal projection of the gate line slit structure on the source layer.

[0017] In some embodiments, a plurality of source reading out contacts are arranged in a one-to-one correspondence with a plurality of channel structures.

[0018] In some embodiments, the orthogonal projection of the source leading out contact on the source layer is strip-shaped, and the longitudinal direction of the source leading out contact is arranged along a first direction parallel to the source layer.

[0019] In some embodiments, the orthogonal projection of the source leading out contact on the source layer is strip-shaped, and the width direction of the source leading out contact is arranged along a first direction parallel to the source layer.

[0020] In some embodiments, the orthogonal projection of the source leading out contact on the source layer is strip-shaped, and the longitudinal direction of the source leading out contact has a cut angle having a first direction parallel to the source layer.

[0021] In some embodiments, a plurality of source reading-out contacts are arranged in a plurality of rows along a first direction parallel to the source layer, and a plurality of rows of source reading-out contacts are aligned in a second direction perpendicular to the first direction and parallel to the source layer.

[0022] In some embodiments, a plurality of source reading out contacts are arranged in a plurality of rows along a first direction parallel to the source layer, and two adjacent rows of source reading out contacts are misaligned in the first direction.

[0023] In some embodiments, the semiconductor device further includes a metal interconnect layer covering a plurality of source leading out contacts.

[0024] In some embodiments, the metal interconnect layer includes a plurality of first roots that are continuously extended and parallel, and a plurality of second roots for connecting two adjacent roots among the first roots.

[0025] In some embodiments, the orthogonal projection of the source leading out contact on the source layer is strip-shaped, and a plurality of first roots cover a plurality of source leading out contacts and extend continuously along the longitudinal direction of the source leading out contact.

[0026] In some embodiments, a plurality of second routes cover a plurality of source reading out contacts, and a plurality of first routes cover a plurality of rows of gate line slit structures.

[0027] In some embodiments, the area between two adjacent routes among the first routes is the second route area, and the second routes within two adjacent routes among the second routes are interleaved.

[0028] In some embodiments, the orthogonal projection of the source leading out contact on the source layer is circular or square.

[0029] In another aspect, the present disclosure provides a memory comprising a semiconductor device provided by any one of the above embodiments and a peripheral circuit electrically connected to the semiconductor device.

[0030] In another aspect, the present disclosure provides a memory system comprising a memory provided by any one of the above embodiments and a controller electrically connected to the memory and used to control the memory to store data.

[0031] The present disclosure provides a semiconductor device, a memory, and a memory system. The semiconductor device comprises an array device and a plurality of source reading-out contacts. The array device comprises a plurality of channel structures and a source layer connected to the plurality of channel structures. The plurality of source reading-out contacts are connected to the source layer, and the plurality of source reading-out contacts and the plurality of channel structures are each located on opposite sides of the source layer. The orthogonal projection of the plurality of source reading-out contacts on the source layer is distributed at equal intervals, thereby reducing voltage drop fluctuations between the channel structures and the source reading-out contacts, controlling the voltage drop within a smaller range, and improving the performance of the semiconductor device. Brief explanation of the drawing

[0032] Specific embodiments of the present disclosure are described in detail below together with the drawings, thereby making the technical solutions of the present disclosure and other beneficial effects apparent. FIG. 1 is a top-down structural diagram I of a semiconductor device provided by a first embodiment of the present disclosure. FIG. 2 is a top-down structural diagram II of a semiconductor device provided by the first embodiment of the present disclosure. FIG. 3 is a top-down structural diagram III of a semiconductor device provided by the first embodiment of the present disclosure. FIG. 4 is a cross-sectional structural diagram according to A-A1 of FIG. 1 of the present disclosure. FIG. 5 is a top-down structural diagram of a semiconductor device having a metal interconnection layer provided by the first embodiment of the present disclosure. FIG. 6 is a top-down structural diagram I of a semiconductor device provided by a second embodiment of the present disclosure. FIG. 7 is a top-down structural diagram II of a semiconductor device provided by a second embodiment of the present disclosure. FIG. 8 is a top-down structural diagram of a semiconductor device having a metal interconnection layer provided by a second embodiment of the present disclosure. FIG. 9 is a top-down structural diagram III of a semiconductor device provided by a second embodiment of the present disclosure. FIG. 10 is a top-down structural diagram of a semiconductor device provided by a third embodiment of the present disclosure. FIG. 11 is a top-down structural diagram of a semiconductor device having a metal interconnection layer provided by a third embodiment of the present disclosure. FIG. 12 is a top-down structural diagram I of a semiconductor device provided by the fourth embodiment of the present disclosure. FIG. 13 is a top-down structural diagram I of a semiconductor device having a metal interconnection layer provided by the fourth embodiment of the present disclosure. FIG. 14 is a top-down structural diagram II of a semiconductor device provided by the fourth embodiment of the present disclosure. FIG. 15 is a top-down structural diagram II of a semiconductor device having a metal interconnection layer provided by the fourth embodiment of the present disclosure. FIG. 16 is a top-down structural diagram of a semiconductor device provided by the fifth embodiment of the present disclosure. FIG. 17 is a top-down structural diagram of a semiconductor device provided by the sixth embodiment of the present disclosure. FIG. 18 is a top-down structural diagram of a semiconductor device provided by the seventh embodiment of the present disclosure. FIG. 19 is a structural diagram of a memory provided by an embodiment of the present disclosure. FIG. 20 is a structural diagram of a memory system provided by an embodiment of the present disclosure. Specific details for implementing the invention

[0033] The technical solutions of the embodiments of the present disclosure will be clearly and completely described below together with the drawings of the embodiments of the present disclosure. Clearly, the described embodiments are only a part, not all, of the embodiments of the present disclosure. All other embodiments obtained by a person skilled in the art without creative work based on the embodiments of the present disclosure will fall within the scope of protection of the present disclosure.

[0034] It should be understood that while terms such as first, second, etc., may be used to describe various components in this specification, these components are not to be limited to such terms. These terms are used to distinguish one component from another. For example, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component without departing from the scope of this disclosure.

[0035] When one component is "on top of" and "connected" to another component, it must be understood that it may be directly on top of or connected to the other component, or that an intermediate component may exist. Other words describing the relationships between components should be interpreted in a similar manner.

[0036] As used herein, the term “layer” refers to a portion of material comprising a region having thickness. A layer may extend over the entire lower or upper structure, or it may have a range smaller than that of the lower or upper structure. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than that of the continuous structure. For example, a layer may be located between the upper surface and the lower surface of the continuous structure, or between any set of horizontal planes in between. A layer may extend horizontally, vertically, and / or along an inclined plane. A substrate may be a layer and may contain one or more layers therein and / or have one or more layers on, above, and / or below it. A layer may comprise a plurality of layers. For example, an interconnection layer may comprise one or more conductive and contact layers (where contacts, interconnection lines, and / or vertical interconnection access (VIA) are formed) and one or more dielectric layers.

[0037] As used in this specification, the term “semiconductor device” refers to a semiconductor device having a vertically oriented array structure on a side-oriented substrate, wherein the array structure extends in a direction perpendicular to the substrate. By using Cartesian coordinates to denote directions and reference the substrate or source layer in this specification, the term “first direction” refers to a direction parallel to the substrate (or source layer) denoted by “X,” the term “longitudinal direction” refers to a direction perpendicular to the substrate (or source layer) and also perpendicular to the X direction denoted by “Z,” and the term “second direction” refers to a direction perpendicular to X and Z, i.e., a direction parallel to the substrate (or source layer) and perpendicular to X, i.e., denoted by “Y.”

[0038] It should be noted that the graphic representations provided in the embodiments of the present disclosure are merely illustrative of the basic concepts of the present disclosure. The graphic representations show only the relevant components of the present disclosure and are not drawn according to the number, shape, or scale of the components during actual implementation; however, the shape, number, and scale of the various components may be changed at will during actual implementation, and the layout of the components may become more complex.

[0039] An embodiment of the present disclosure provides a semiconductor device. For example, referring to FIG. 1-4, the semiconductor device (100) may include an array device comprising a plurality of rows of gate line slit structures (10) extending in a first direction (X), a channel structure (11) located between each row of the gate line slit structures (10), and a source layer (1042) electrically connected to the plurality of channel structures (11). The semiconductor device (100) further comprises a plurality of source reading out contacts (12) electrically connected to the source layer (1042) and distributed at equal intervals on the surface of the source layer (1042), that is, the orthogonal projections of the plurality of source reading out contacts (12) on the source layer (1042) are distributed at equal intervals. The source layer is located between the channel structure (11) and the source leading out contact (12), that is, the channel structure (11) and the plurality of source leading out contacts (12) are each located in the longitudinal direction (e.g., Z direction in FIG. 1) on both sides of the source layer. The semiconductor device (100) further includes a metal interconnection layer (105) that covers the source leading out contact (12) and electrically connects the source leading out contact (12) to the metal interconnection layer (105), thereby enabling electrical connection between the external circuit and the channel structure by the metal interconnection layer (105).

[0040] In some embodiments, the gate line slit structure (10) comprises at least two rows of first gate line slit structures (101) and at least one row of second gate line slit structures (102) between two adjacent rows of first gate line slit structures (101), the first gate line slit structure (101) divides the array device into a plurality of memory blocks, the second gate line slit structure (102) divides the array device into a plurality of memory blocks, and the second gate line slit structure (102) divides the memory blocks into a plurality of finger memory blocks (G1), wherein the first gate line slit structure (101) extends continuously in a first direction (X), and the second gate line slit structure (102) is separated along a second direction (Y), i.e., has a plurality of separated segments of sub-second gate line slit structures.

[0041] In some embodiments, the distance between two adjacent rows of the first gate line slit structure (101) may be the same. In some embodiments, the distance between two adjacent rows of the second gate line slit structure (102) may be the same. In some embodiments, the distance between any two adjacent rows of the gate line slit structure (10) may be the same, for example, two adjacent rows of the gate line slit structure (10) have a first pitch (P1) in the second direction (Y), and the first pitch (P1) may refer to the distance from the top of one row of the gate line slit structure (10) to the top of the other row of the gate line slit structure (10) in two adjacent rows of the gate line slit structure (10) of FIG. 1, or the distance from the bottom of one row of the gate line slit structure (10) to the bottom of the other row of the gate line slit structure (10).

[0042] Meanwhile, referring to FIG. 4, FIG. 4 is a cross-sectional structural diagram according to A-A1 of FIG. 1 of the present disclosure. A semiconductor device (100) includes a substrate (110) in the longitudinal direction (Z), a peripheral device layer (120) on the substrate (110), a peripheral interconnect layer (102) on the peripheral device layer (120), an array interconnect layer (103) on the peripheral interconnect layer (102), an array device (104) on the array interconnect layer (103), a source reading out contact (12) on the array device (104), and a metal interconnect layer (105) on the source reading out contact (12).

[0043] In some embodiments, the array device (104) comprises a deck (1041), a channel structure (11) penetrating the deck (1041) in the longitudinal direction (Z), a gate line slit structure (not shown in the drawing) penetrating the deck (1041) in the longitudinal direction (Z), and a source layer (1042) located on the deck (1041) and electrically connected to the channel structure (11). The channel structure (11) comprises an insulating layer (111) extending along the longitudinal direction (Z), a channel layer (112) surrounding the insulating layer (111), and a memory layer (113) surrounding the channel layer (112), wherein the channel layer (112) has an end (1121) not covered by the memory layer (113). In particular, the source layer (1042) covers the end (1121) of the channel layer (112) and is connected to the channel layer (112) of the channel structure (11).

[0044] In some embodiments, the metal interconnect layer (105) may include an AL path, the source layer (1042) may be N-type doped polysilicon, and the deck (1041) is formed by alternately stacking an interlayer insulating layer and a gate layer. The top-down graphic of the source leading-out contact (12) (refer to FIG. 4) or the orthogonal projection of the source leading-out contact (12) on the source layer (1042) is circular or square, whereas in some other embodiments, the top-down graphic of the source leading-out contact (12) (refer to FIG. 4) or the orthogonal projection of the source leading-out contact (12) on the source layer (1042) may be of a different shape, e.g., strip shape, petal shape, spindle shape, dumbbell shape, etc.

[0045] When the channel layer (112) of the channel structure (11) forms an electrical connection with the source reading out contact (12) through the source layer (1042), given the length of the channel structure (11) and the thickness of the source layer (1042), the distance from the different channel structure (11) to the source reading out contact (12) depends on the distance between the channel structure (11) and the source reading out contact (12) in the XY plane, and since the distribution of the channel structure (11) around the source reading out contact (12) and the distance from the channel structure (11) to the source reading out contact (12) will affect the voltage drop, it can be understood that the distribution conditions of the source reading out contact (12) are particularly important.

[0046] In some embodiments of the present disclosure, the orthogonal projection of a plurality of source reading out contacts (12) on the source layer (1042) is arranged in an evenly spaced distribution, which can be implemented using various forms, for example, in a first direction (X) or / and a second direction (Y) or / and other directions, and for example, in some embodiments, the plurality of source reading out contacts (12) are arranged in a plurality of rows along the first direction (X), and the source reading out contacts (12) of the same row are distributed at equal intervals along the first direction (X). Alternatively, in some embodiments, the plurality of source reading out contacts (12) are arranged in a plurality of rows along the first direction (X), and the distance between any two adjacent rows of source reading out contacts (12) is equal. In contrast, in some embodiments, a plurality of source reading out contacts (12) are arranged in a plurality of rows along a first direction (X), source reading out contacts (12) of the same row are distributed at equal intervals along the first direction (X), and source reading out contacts (12) of different rows are aligned in a second direction (Y). In contrast, in some embodiments, a plurality of source reading out contacts (12) are arranged in a plurality of rows along a first direction (X), source reading out contacts (12) of the same row are distributed at equal intervals along the first direction (X), and source reading out contacts (12) of two adjacent rows are misaligned in the first direction (X). It can be understood that the above embodiments may be arbitrarily combined to obtain a plurality of arrangements of source reading out contacts (12) with an equal interval distribution. For example, source reading out contacts (12) of the same row are distributed at equal intervals along the first direction (X), while the distance between two adjacent rows of source reading out contacts (12) is the same.

[0047] In an embodiment of the present disclosure, source reading out contacts (12) within a semiconductor device (100) are distributed at even intervals on the surface of a source layer (1042), the source layer (1042) covers a channel structure (11), and the channel structure (11) is distributed relatively uniformly around each source reading out contact (12), so that the voltage drop distribution around all source reading out contacts (12) is approximately the same, so that the voltage drop between the channel structure (11) and the source reading out contacts (12) is reduced and the performance of the semiconductor device can be improved.

[0048] Referring to FIG. 1-3, FIG. 1-3 can be regarded as a structural diagram of a semiconductor device provided by a first embodiment of the present disclosure, FIG. 1 is a top-down structural diagram I of a semiconductor device provided by a first embodiment of the present disclosure, FIG. 2 is a top-down structural diagram II of a semiconductor device provided by a first embodiment of the present disclosure, and FIG. 3 is a top-down structural diagram III of a semiconductor device provided by a first embodiment of the present disclosure.

[0049] In this embodiment, two adjacent rows of source reading out contacts (12) have a second pitch (P2) in a second direction (Y) perpendicular to a first direction (X), and the second pitch (P2) may refer to the distance from the top of one row of source reading out contacts (12) to the top of one row of source reading out contacts (12) adjacent to the corresponding row of source reading out contacts (12) in FIG. 1-3, or the distance from the bottom of one row of source reading out contacts (12) to the bottom of one row of source reading out contacts (12) adjacent to the corresponding row of source reading out contacts (12).

[0050] As illustrated in FIG. 1, the first pitch (P1) of the finger memory block (G1) is smaller than the second pitch (P2) between the source reading out contacts (12). As illustrated in FIG. 2, the first pitch (P1) of the finger memory block (G1) is larger than the second pitch (P2) between the source reading out contacts (12). As illustrated in FIG. 1 and FIG. 2, the source reading out contacts (12) include a first source reading out contact (121) and a second source reading out contact (122). The projection of the first source reading out contact (121) on a plane (XY plane) formed by the source layer (1042) is located between the projections of two adjacent rows of the gate line slit structure (10) on the plane. The projection of the second source reading out contact (122) has a portion that overlaps with the projection of the gate line slit structure (10) on the plane.

[0051] As illustrated in FIG. 3, the first pitch (P1) of the finger memory block (G1) completely matches the second pitch (P2) of the source reading out contact (12) (i.e., P1 = P2), so the positions of all source reading out contacts (12) within one finger memory block (G1) are identical, and the voltage drop distribution around all source reading out contacts (12) is substantially identical.

[0052] Referring further to FIG. 3, when the source reading out contact (12) and the finger memory block (G1) are projected onto a single XY plane along the longitudinal direction (Z), each row of the source reading out contact (12) (arranged along the first direction (X)) can be located in the center of the finger memory block (G1), that is, the source reading out contact (12) is located in the center of the finger memory block (G1) in the second direction (Y), and in the second direction (Y), the channel structures (11) on both sides of the source reading out contact (12) are all symmetrically distributed, and the voltage drop distribution on both sides of the source reading out contact (12) is approximately the same. More specifically, in one finger memory block (G1), the distance (D1) from the first row of the channel structure (11) and from the ninth row of the channel structure (11) to the source reading out contact (12) is the same (same voltage drop), and the distance (D2) from the second row of the channel structure (11) and from the eighth row of the channel structure (11) to the source reading out contact (12) is also the same (same voltage drop), so that the voltage drop changes uniformly in each finger memory block (G1).

[0053] In the semiconductor device (100) provided by the first embodiment of the present disclosure, the source reading out contacts (12) are evenly distributed on the source layer (1042), and the distribution of the channel structures (11) around all the source reading out contacts (12) is approximately the same, and the voltage drop change around all the source reading out contacts (12) is approximately the same, so that the voltage drop between the source reading out contacts (12) and the channel structures (11) is relatively stable, the voltage drop can be controlled in a smaller range, and the performance of the device can be improved. In one embodiment, the source reading out contacts (12) of FIG. 3 are located in the center of the finger memory block (G1) so that the surrounding channel structures (11) are symmetrically distributed with respect to the source reading out contacts (12), for example, the channel structures (11) of region R of FIG. 3 act as channel structures (11) around the source reading out contacts (12) therein. For example, in this region R, the channel structures (11) above and below the source reading out contact (12) of FIG. 3 are symmetrically distributed, and the channel structures (11) to the left and right of the source reading out contact (12) of FIG. 3 are symmetrically distributed.

[0054] Referring again to FIG. 5, FIG. 5 is a top-down structural diagram of a semiconductor device having a metal interconnect layer provided by a first embodiment of the present disclosure. The semiconductor device (100) further includes a metal interconnect layer (13) covering a plurality of source leading out contacts (12). This embodiment takes the semiconductor device (100) of FIG. 3 as an example to illustrate the pattern of the metal interconnect layer (13) of the semiconductor device (100). The metal interconnect layer (13) includes a plurality of first roots (131) that are continuously extended and parallel, and a plurality of second roots (132) that connect two adjacent first roots (131) and intersect (e.g., perpendicularly) with the first roots (131). Therefore, since all metal routes are connected to each other, and if one of the first routes (131) is damaged somewhere, the signal can be transmitted to the damaged first route (131) through other first routes (131) and second routes (132), the stability and reliability of signal transmission can be improved.

[0055] In this embodiment, one first route (131) covers one row of source reading out contacts (12), and a second route (132) is located between two adjacent first routes (131) and is positioned perpendicular to the first route (131). The area between two adjacent routes of the first route (131) is the second route area, and the second route (132) within two adjacent areas of the second route area is interleaved.

[0056] With reference to FIG. 5, regarding the structure of the metal interconnection layer of the semiconductor device (100) of FIG. 1 and FIG. 2, it can be understood that the structure of the corresponding metal interconnection layer can be obtained by adjusting the distance between the first roots.

[0057] Referring to FIG. 6, FIG. 6 is a top-down structural diagram I of a semiconductor device provided by a second embodiment of the present disclosure. The semiconductor device (200) includes a plurality of gate line slit structures (including a first gate line slit structure (201) and a second gate line slit structure (202)) extending in a first direction (X), a channel structure (21) located between the plurality of gate line slit structures (20), a source layer electrically connected to the channel structure (21), a plurality of source leading out contacts (22) on the source layer, and a metal interconnection layer covering the plurality of source leading out contacts.

[0058] The top-down graphic of the source reading out contact (22) is strip-shaped, and the orthogonal projection of the source reading out contact (22) on the source layer is strip-shaped. The length direction of the source reading out contact (22) coincides with the first direction (X), and the width direction coincides with the second direction (Y). Source reading out contacts (22) of the same row are distributed at equal intervals along the first direction (X), and source reading out contacts (22) of different rows are aligned along the second direction (Y).

[0059] Any two adjacent rows of the gate line slit structure (20) have a first pitch (P3) in the second direction (Y), and any two adjacent rows of the source reading out contact (22) have a second pitch (P4) in the second direction (Y), and the second pitch (P4) is the same as the first pitch (P3). It should be noted that the first pitch (P3) refers to the distance from the top of one row of the gate line slit structure (20) to the top of the other row of the gate line slit structure (20) or from the bottom of one row of the gate line slit structure (20) to the bottom of the other row of the gate line slit structure (20) in any two adjacent rows of the gate line slit structure (20) of FIG. 6. The second pitch (P4) refers to the distance from the top of one row of the source reading out contact (22) to the top of the other row of the source reading out contact (22) or from the bottom of one row of the source reading out contact (22) to the bottom of the other row of the source reading out contact (22) in two adjacent rows of the source reading out contact (22) of FIG. 6.

[0060] In this embodiment, the source reading out contact (22) is located between two rows of the gate line slit structure (20) and is located in the center of the finger memory block (G2) in the second direction (Y), that is, the distance from the source reading out contact (22) to the upper row of the gate line slit structure (20) and the lower row of the gate line slit structure (20) is the same, and thus the channel structures (21) around each source reading out contact (22) are symmetrically distributed, for example, in FIG. 6, the channel structures (21) above and below the source reading out contact (22) are symmetrically distributed, and the channel structures (21) to the left and right of the source reading out contact (22) are symmetrically distributed.

[0061] Referring to the cross-section of FIG. 4, the source leading out contact (22) of the semiconductor device (200) of the second embodiment increases the contact area with the source layer in the first direction (X), thereby reducing the voltage drop due to resistance and capacitance. Meanwhile, because the size of the source leading out contact (22) increases in the first direction (X), the metal interconnection layer is more easily aligned with the source leading out contact (22) during the subsequent manufacturing of the metal interconnection layer, and the effective process window for manufacturing the source leading out contact (22) and the metal interconnection layer is also increased.

[0062] Referring to FIG. 7, FIG. 7 is a top-down structural diagram II of a semiconductor device provided by a second embodiment of the present disclosure. The semiconductor device (200) differs from the second embodiment in that the source reading out contacts (22) of different rows are not aligned one by one in the second direction (Y), and in particular, the second row of source reading out contacts (22) is misaligned with respect to the first row of source reading out contacts (22) in the first direction (X). For example, the misalignment distance of the second row of source reading out contacts (22) is W compared to the first row of source reading out contacts (22) in the first direction (X). One source reading out contact (22) of the second row is located in the middle of two adjacent source reading out contacts (22) of the first row, that is, when two adjacent source reading out contacts (22) of one row have a symmetry axis B-B1, the left and right sides of one source reading out contact (22) of another row adjacent to the corresponding row of source reading out contacts (22) are symmetric with respect to the symmetry axis B-B1. Thus, source reading out contacts (22) arranged in a misaligned manner are also evenly distributed in one memory block. In FIG. 7, the source reading out contact (22) is located in the middle of the finger memory block (G2) so that the voltage drop of each finger memory block (G2) changes uniformly, thereby improving the uniformity of device performance.

[0063] Together with FIG. 8, FIG. 8 is a top-down structural diagram of a semiconductor device having a metal interconnect layer provided by a second embodiment of the present disclosure. The semiconductor device (200) further comprises a metal interconnect layer (23) covering a plurality of source leading out contacts (22), and the metal interconnect layer (23) comprises a plurality of first roots (231) that are continuously extended and parallel, and a plurality of second roots (232) that connect two adjacent first roots (231) and intersect (e.g., perpendicularly) with the first roots (231). Thus, all metal roots are connected to each other, and if one of the first roots (231) is damaged somewhere, a signal can be transmitted to the damaged first roots (231) through other first roots (231) and second roots (232).

[0064] In the second embodiment, a plurality of first roots (231) cover a plurality of source reading out contacts (22) and extend continuously along the longitudinal direction of the source reading out contacts (22). The area between two adjacent roots among the first roots (231) is a second root area, and the second roots (232) between two adjacent roots among the second root areas are interleaved. In particular, the orthogonal projection of one second root (232) in the second row on the XY plane is located in the middle of the orthogonal projection of two adjacent second roots (232) in the first row on the XY plane so that the metal roots are uniformly distributed in the memory block.

[0065] Referring to FIG. 9, FIG. 9 is a top-down structural diagram III of a semiconductor device provided by a second embodiment of the present disclosure. The semiconductor device (200) differs from FIG. 6 in that the longitudinal direction of the source reading out contact (22) has a cut-in angle having a first direction (X), that is, the source reading out contact (22) is asymmetrically distributed in the finger memory block (G2). In this embodiment, the source reading out contact (22) is aligned in a second direction (Y). In some embodiments, the source reading out contact (22) of different rows may be interleaved in the first direction (X), and details may be referenced to FIG. 7.

[0066] Referring to FIG. 10, FIG. 10 is a top-down structural diagram of a semiconductor device provided by a third embodiment of the present disclosure. For ease of understanding, the semiconductor device (300) uses the same structural number as the semiconductor device (200) of the second embodiment. The semiconductor device (300) differs from the semiconductor device (200) in that any adjacent gate line slit structure (20) has a first pitch (P5) between them, any two adjacent rows of source leading out contacts (22') have a second pitch (P6) between them, and P5 is greater than P6. It should be noted that the first pitch (P5) refers to the distance from the top of one row of the gate line slit structure (20) to the top of the other row of the gate line slit structure (20) or from the bottom of one row of the gate line slit structure (20) to the bottom of the other row of the gate line slit structure (20) in two adjacent rows of the gate line slit structure (20) of FIG. 10. The second pitch (P6) refers to the distance from the top of one row of the source reading out contact (22) to the top of the other row of the source reading out contact (22) or from the bottom of one row of the source reading out contact (22) to the bottom of the other row of the source reading out contact (22) in two adjacent rows of the source reading out contact (22) of FIG. 10.

[0067] Referring to FIG. 10, in some embodiments, the projection of two adjacent rows of gate line slit structures (20) on the XY plane has a projection of multiple rows of source reading out contacts (22') on the plane between them, that is, the projection of adjacent gate line slit structures (20) has a projection of multiple rows of source reading out contacts (22') between them. That is, one finger memory block (G2) has multiple rows of source reading out contacts (22'). In this embodiment, one finger memory block (G2) has multiple rows of source reading out contacts (22') inside.

[0068] In some embodiments, the distance between any source reading out contact (22') and an adjacent gate line slit structure (20) is P0, and the distance between any two rows of source reading out contacts (22') is equal to 2P0. The difference between P6 and 2P0 is equal to the width of the source reading out contact (22') in the second direction (Y).

[0069] In some embodiments, when P5 = 2P6, the difference between P5 and 4P0 is equal to twice the width of the source reading out contact (22').

[0070] Referring to FIG. 11, FIG. 11 is a top-down structural diagram of a semiconductor device having a metal interconnect layer provided by a third embodiment of the present disclosure. The root distribution condition of the metal interconnect layer (23') is similar to the root distribution condition of FIG. 8, except that the number of the first root (231') increases according to the number of rows of source leading out contacts (22'), and thus the number of the second root (232') also increases.

[0071] In some embodiments, the width of the source reading out contact (22') in the second direction (Y) may be smaller than the width of the source reading out contact (22) in the second direction (Y) within the semiconductor device (200). The width of the source reading out contact (22') in the second direction (Y) may be smaller than the width of the source reading out contact (12) in the second direction (Y) within the semiconductor device (100), and the width of the source reading out contact (22') in the first direction (X) (referring to the length of the strip-type source reading out contact (22')) may be smaller than the width of the source reading out contact (12) in the first direction (X) within the semiconductor device (100). When the width of the source leading out contact (22') in the second direction (Y) is reduced, the width of the first root (231') in the metal interconnection layer (23') in the second direction (Y) can also be reduced accordingly, thereby ensuring that the pitch of the first root (231') is not too small and reducing the electrical influence between the first roots (231').

[0072] Referring to FIG. 12, FIG. 12 is a top-down structural diagram I of a semiconductor device provided by a fourth embodiment of the present disclosure. The semiconductor device (400) includes a gate line slit structure (30) (including a first gate line slit structure (301) and a second gate line slit structure (302)), a channel structure (31), a source layer, a source reading out contact (32), and a metal interconnect layer. The semiconductor device (400) differs from the semiconductor device (200) in that the azimuth angle of the source reading out contact (32) within the finger memory block (G3) is different, the length direction of the source reading out contact (32) coincides with the second direction (Y), and the width direction coincides with the first direction (X). The source reading out contacts (32) of different rows are aligned in the second direction (Y).

[0073] Referring to FIG. 13, FIG. 13 is a top-down structural diagram I of a semiconductor device having a metal interconnect layer provided by a fourth embodiment of the present disclosure. The semiconductor device (400) further includes a metal interconnect layer (33) covering a plurality of leading-out contacts (32). Taking the semiconductor device (400) of FIG. 12 as an example, the metal interconnect layer (33), which has a pattern similar to the metal interconnect layer (23) of FIG. 8, includes a plurality of first roots (331) that are continuously extended and parallel, and a plurality of second roots (332) that connect two adjacent first roots (331) and are perpendicular to the first roots (331). The plurality of first roots (331) include a plurality of source leading-out contacts (32) and are continuously extended along the longitudinal direction of the source leading-out contacts (32), and the second roots (332) in adjacent second root regions are interleaved in the second direction (Y).

[0074] Referring to FIG. 14, FIG. 14 is a top-down structural diagram II of a semiconductor device provided by a fourth embodiment of the present disclosure. The semiconductor device (400) differs from the semiconductor device (300) of the fourth embodiment in that the source reading out contacts (32) of different rows are misaligned and distributed in a first direction (X). In some embodiments, one row of source reading out contacts (32) is located in the middle of an adjacent row of source reading out contacts (32), and two rows of source reading out contacts (32) with a row gap are aligned in a second direction (Y), so that the source reading out contacts (32) are uniformly distributed in the memory block and voltage drop can be controlled within a smaller range.

[0075] Referring to FIG. 15, FIG. 15 is a top-down structural diagram II of a semiconductor device having a metal interconnection layer provided by the fourth embodiment of the present disclosure. In this embodiment, taking the semiconductor device (400) of FIG. 14 as an example, the metal interconnection layer (33) comprises a plurality of first roots (331) that are continuously extended and parallel, and a plurality of second roots (332) that connect two adjacent first roots (331) and are perpendicular to the first roots (331). As can be seen from the second embodiment of FIG. 8, the third embodiment of FIG. 11, and the fourth embodiment of FIG. 13, the continuously extended first roots (331) all extend along the longitudinal direction of the source leading out contact (32). However, in the embodiment of FIG. 15, a continuous first route (331) extends along the gate line slit structure (30), each first route (331) covers one row of the gate line slit structure (30), and two adjacent rows of the first routes (331) are connected to two ends of the source reading out contact (32). A second route (332) covers the source reading out contact (32), and the number and location of the second route (332) are the same as those of the source reading out contact (32), except that the second route (332) is longer and wider than the source reading out contact (32).

[0076] Referring to FIG. 16, FIG. 16 is a top-down structural diagram of a semiconductor device provided by the fifth embodiment of the present disclosure. For ease of understanding, the semiconductor device (500) continues to use the structural numbering from the second embodiment (200). The semiconductor device (500) differs from the semiconductor device (200) in that, when the source leading out contact (22) and the gate line slit structure (20) are projected onto a single XY plane along the longitudinal direction (Z), the source leading out contact (22) has a portion that overlaps with the gate line slit structure (20). For example, the projection of the source leading out contact (22) onto the XY plane along the longitudinal direction (Z) is symmetric with respect to the projection of the gate line slit structure (20) onto the XY plane along the longitudinal direction (Z).

[0077] In the fifth embodiment, the metal interconnect layer has the same pattern as the metal interconnect layer (23) of the second embodiment, and the metal interconnect layer of the semiconductor device (500) of the fifth embodiment can be obtained by moving the entire pattern of the metal interconnect layer (23) of FIG. 8 a certain distance in the second direction (Y) to move the metal interconnect layer (23) to a position that matches the gate line slit structure (20).

[0078] Referring to FIG. 17, FIG. 17 is a top-down structural diagram of a semiconductor device provided by the sixth embodiment of the present disclosure. For ease of understanding, the semiconductor device (600) continues to use the structural numbering from the second embodiment (200). The source reading out contact (22) has a portion that overlaps with the gate line slit structure (20) when the source reading out contact (22) and the gate line slit structure (20) are projected onto a single XY plane along the longitudinal direction (Z).

[0079] The semiconductor device (600) differs from the semiconductor device (500) of the fifth embodiment in that the first pitch (P1) between two rows of the gate line slit structure (20) is smaller than the second pitch (P2) between two rows of the source reading out contact (22) (e.g., P2 = 2P1). This distribution of the source reading out contact (22) also makes the distribution conditions of the channel structure around each source reading out contact (22) the same, that is, the channel structure (21) around the source reading out contact (22) is symmetrically distributed—the change in distance is uniform—so that the voltage drop from the channel structure (21) to the source reading out contact (22) changes uniformly, thereby improving the uniformity of the device performance.

[0080] In some embodiments, to reduce the range of voltage drop, the size of the source reading out contact (22) may be increased, which is equivalent to increasing the contact area between the source reading out contact (22) and the source layer. For example, the source reading out contact (22) of the semiconductor device (600) may be larger than the source reading out contact (22) of the semiconductor device (500).

[0081] Referring to FIG. 18, FIG. 18 is a top-down structural diagram of a semiconductor device provided by the seventh embodiment of the present disclosure. The semiconductor device (700) includes a plurality of rows of gate line slit structures (40) and a channel structure (41) between two adjacent rows of gate line slit structures (40). The gate line slit structures (40) include at least two rows of first gate line slit structures (401) and at least one row of second gate line slit structures (402) between two adjacent rows of the first gate line slit structures (401). A single finger memory block (G4) may be located between two adjacent rows of gate line slit structures (40). It should be noted that the channel structure (41) is not actually visible in the top-down view, and the structure of the channel structure (41) is illustrated in FIG. 18 only to show the positional relationship between the source reading out contact (42) and the channel structure (41).

[0082] In some embodiments, a plurality of source reading out contacts (42) are arranged in a one-to-one correspondence with a plurality of channel structures (41). In some embodiments, the plurality of channel structures (41) are distributed at equal intervals, and the plurality of source reading out contacts (42) are also distributed at equal intervals. The orthogonal projection of each source reading out contact (42) on the XY plane has a portion that overlaps with the orthogonal projection of one channel structure (41) on the XY plane. In one embodiment, the orthogonal projection of the channel structure (41) is located in the middle of the orthogonal projection of the source reading out contact (42).

[0083] Referring to FIG. 19, FIG. 19 is a structural diagram of a memory provided by an embodiment of the present disclosure. The memory (800) may be a three-dimensional memory, for example, a 3D NAND memory and a 3D NOR memory.

[0084] The memory (800) includes a semiconductor device (801) and a peripheral circuit (802). The semiconductor device (801) may be any semiconductor device in the above embodiment, and the peripheral circuit (802) may be a COMS (complementary metal oxide semiconductor). The peripheral circuit (802) is electrically connected to the semiconductor device (801) to communicate signals with the semiconductor device (801). The peripheral circuit (802) may be used for logic operations and may control and detect the switching state of various memory cells within the semiconductor device (801) through metal lines to enable the storage and reading of data.

[0085] The semiconductor device (801) includes an array device comprising a plurality of channel structures and a source layer connected to the plurality of channel structures, and a plurality of source reading-out contacts connected to the source layer. The plurality of source reading-out contacts and the plurality of channel structures are each located on both sides of the source layer, and the orthogonal projections of the plurality of source reading-out contacts on the source layer are distributed at equal intervals.

[0086] Referring to FIG. 20, FIG. 20 is a structural diagram of a memory system provided by an embodiment of the present disclosure. The memory system (900) includes a memory (901) and a controller (902). The memory (901) may be a memory of any of the embodiments and may include any semiconductor device of the embodiment. The controller (902) is electrically connected to the memory (901) and is used to control the memory (901) to store data, and the memory (901) may perform an operation of storing data based on the control of the controller (902).

[0087] In some embodiments, the memory system may be implemented as, for example, a Universal Flash Storage (UFS) device, a Solid State Disk (SSD), a multimedia card in the form of MMC, eMMC, RS-MMC and Micro-MMC, a secure digital card in the form of SD, Mini-SD and Micro-SD, a memory device of the Personal Computer Memory Card International Association (PCMCIA) card type, a memory device of the Peripheral Component Interconnect (PCI) type, a memory device of the PCI Express (PCI-E) type, a Compact Flash (CF) card, a Smart Media Card or a Memory Stick, etc.

[0088] The semiconductor device of the memory (901) includes an array device comprising a plurality of channel structures and a source layer connected to the plurality of channel structures, and a plurality of source reading-out contacts connected to the source layer. The plurality of source reading-out contacts and the plurality of channel structures are each located on both sides of the source layer, and the orthogonal projections of the plurality of source reading-out contacts on the source layer are distributed at equal intervals.

[0089] The description of the above embodiments is used merely to aid in understanding the technical solutions of the present disclosure and their core ideas. Those skilled in the art should understand that while the technical solutions described in the foregoing embodiments may be modified or parts of the technical features may be replaced with equivalents, such modifications or replacements do not cause the essence of each technical solution to depart from the scope of the technical solutions of the various embodiments of the present disclosure.

Claims

Claim 1 A semiconductor device comprising an array device including a channel structure and a source layer connected to the channel structure, a source leading-out contact connected to the source layer, and a row of gate line slit structures extending along a first direction parallel to the source layer, wherein the channel structure and the source leading-out contact are located on both sides of the source layer, two adjacent rows of the gate line slit structures have a first pitch between them, two adjacent rows of the source leading-out contacts have a second pitch between them, the first pitch is smaller than the second pitch, the orthographic projection of the source leading-out contacts on the source layer is distributed at equal intervals, and the orthographic projection of the row of the source leading-out contacts on the source layer is located between the orthographic projections of the two adjacent rows of the gate line slit structures on the source layer. Claim 2 delete Claim 3 A semiconductor device according to claim 1, wherein the source reading out contacts are arranged in a plurality of rows along the first direction, and the source reading out contacts of the same row are distributed at equal intervals along the first direction. Claim 4 A semiconductor device according to claim 1, wherein the source reading out contacts are arranged in a plurality of rows along the first direction, and the second pitch between any two adjacent rows of the source reading out contacts is the same. Claim 5 delete Claim 6 delete Claim 7 A semiconductor device according to claim 1, wherein the orthogonal projection of the row of the source leading out contact on the source layer is located at the center between the orthogonal projections of the two adjacent rows of the gate line slit structure on the source layer. Claim 8 A semiconductor device according to claim 1, wherein the orthogonal projection of the row of the gate line slit structure on the source layer is located between the orthogonal projections of the two adjacent rows of the source leading out contact on the source layer. Claim 9 A semiconductor device according to claim 1, wherein the orthogonal projection of the row of the source leading out contact on the source layer has a portion that overlaps with the orthogonal projection of one of the gate line slit structures on the source layer. Claim 10 A semiconductor device according to claim 1, wherein the source reading out contact comprises a first source reading out contact and a second source reading out contact, the orthogonal projection of the first source reading out contact on the source layer is located between the orthogonal projections of two adjacent rows of the gate line slit structure on the source layer, and the orthogonal projection of the second source reading out contact on the source layer has a portion that overlaps with the orthogonal projection of the gate line slit structure on the source layer. Claim 11 A semiconductor device according to claim 1, wherein the source reading out contact is arranged in a one-to-one correspondence with the channel structure. Claim 12 A semiconductor device according to claim 1, wherein the orthogonal projection of the source leading-out contact on the source layer is strip-shaped, and the longitudinal direction of the source leading-out contact is arranged along a first direction parallel to the source layer. Claim 13 A semiconductor device according to claim 1, wherein the orthogonal projection of the source leading-out contact on the source layer is strip-shaped, and the width direction of the source leading-out contact is arranged along a first direction parallel to the source layer. Claim 14 A semiconductor device according to claim 1, wherein the orthogonal projection of the source leading out contact on the source layer is strip-shaped, and the longitudinal direction of the source leading out contact has a cut angle having a first direction parallel to the source layer. Claim 15 A semiconductor device according to claim 1, wherein the source reading out contacts are arranged in a plurality of rows along a first direction parallel to the source layer, and the plurality of rows of the source reading out contacts are aligned in a second direction perpendicular to the first direction and parallel to the source layer. Claim 16 A semiconductor device according to claim 1, wherein the source reading out contacts are arranged in a plurality of rows along a first direction parallel to the source layer, and the two adjacent rows of the source reading out contacts are misaligned in the first direction. Claim 17 A semiconductor device according to claim 1, wherein the semiconductor device further comprises a metal interconnection layer covering the source leading out contact. Claim 18 A semiconductor device according to claim 1, wherein the orthogonal projection of the source leading out contact on the source layer is circular or square. Claim 19 A memory device comprising a semiconductor device and a peripheral circuit electrically connected to the semiconductor device, wherein the semiconductor device comprises an array device including a channel structure and a source layer connected to the channel structure, a source reading out contact connected to the source layer, and a row of gate line slit structures extending along a first direction parallel to the source layer, wherein the channel structure and the source reading out contact are located on both sides of the source layer, and two adjacent rows of the gate line slit structures have a first pitch between them, and two adjacent rows of the source reading out contacts have a second pitch between them, wherein the first pitch is smaller than the second pitch, and the orthogonal projections of the source reading out contacts on the source layer are distributed at equal intervals, and the orthogonal projections of the row of the source reading out contacts on the source layer are located between the orthogonal projections of the two adjacent rows of the gate line slit structures on the source layer. Claim 20 A memory system comprises a memory device and a controller electrically connected to the memory device and used to control the memory device for storing data, wherein the memory device comprises a semiconductor device and a peripheral circuit electrically connected to the semiconductor device, wherein the semiconductor device comprises an array device including a channel structure and a source layer connected to the channel structure, a source reading-out contact connected to the source layer, and a row of gate line slit structures extending along a first direction parallel to the source layer, wherein the channel structure and the source reading-out contact are located on both sides of the source layer, and two adjacent rows of the gate line slit structures have a first pitch between them, and two adjacent rows of the source reading-out contacts have a second pitch between them, wherein the first pitch is smaller than the second pitch, and the orthogonal projection of the source reading-out contacts on the source layer is distributed at equal intervals, and the orthogonal projection of the row of the source reading-out contacts on the source layer is the adjacent two A memory system located between the orthogonal projections of the rows. Claim 21 delete Claim 22 delete Claim 23 delete Claim 24 delete

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