Multi-transistor stack bitcell architecture

Abstract

The various embodiments described herein relate to a device having a plurality of transistors in a single stack arranged as a cross-coupled bit cell latch. Additionally, the plurality of transistors may be arranged in a multi-transistor stack configuration formed within a single monolithic semiconductor die. In some embodiments, the plurality of transistors may be arranged as bit cells for single-port memory applications.

Description

Background Technology

[0001] This section is intended to provide information regarding the understanding of the various technologies described in this specification. As the title of this section implies, this is a discussion of related technologies that by no means constitute prior art. Generally, related technologies may or may not be considered prior art. Accordingly, any references in this section should be read in this light and understood as not being an acknowledgment of any prior art.

[0002] In some modern bitcell architectures, conventional multi-transistor devices utilize traditional layout techniques and consequently face difficulties in low-density design applications, which can typically lead to unintended consequences during manufacturing processes. Consequently, traditional layout techniques can be inefficient, insufficient in density, and typically fail to provide sufficient means to implement diverse and different layout configurations. Therefore, there is a need to improve traditional layout techniques to enable efficient device manufacturing. Brief explanation of the drawing

[0003] Embodiments of various techniques are described herein with reference to the accompanying drawings. However, it should be understood that the accompanying drawings are intended to illustrate only the various embodiments described herein and are not intended to limit the embodiments of the various techniques described herein. FIG. 1a illustrates a diagram of a bitcell architecture according to various embodiments described in this specification. FIG. 1b illustrates a diagram of a multi-transistor architecture according to various embodiments described in this specification. FIGS. 2a through 2d illustrate various diagrams of a multi-transistor stack architecture according to various embodiments described herein. FIGS. 3a through 3d illustrate various diagrams of a multi-transistor stack architecture according to various embodiments described herein. FIGS. 4a through 4c illustrate various diagrams of split-gate transistor architectures according to various embodiments described herein. FIG. 5 illustrates a diagram of a method for manufacturing a bitcell architecture according to various embodiments described in this specification. Specific details for implementing the invention

[0004] The various embodiments described herein relate to manufacturing methods and techniques for single-port memory applications in physical layout designs. As some examples, the various methods and techniques described herein may provide various single-port static random access memory (SRAM) bit cell architectures using multi-stack complementary field-effect transistor (CFET) technology. Additionally, the various bit cell manufacturing methods and techniques described herein may provide novel architectures for the physical layout design of bit cell architectures of multi-transistor (e.g., 6T) single-port SRAM bit cells in stacked complementary FET technology, wherein multiple devices are placed on top of each other in a single-stack configuration. Furthermore, the various multi-transistor bit cell manufacturing methods and techniques described herein provide for various and different multi-transistor stack combinations of devices to be fabricated simultaneously and within the same single monolithic semiconductor die.

[0005] In some embodiments, the bit cell manufacturing methods and techniques described herein utilize techniques that support complementary FET (CFET) devices, wherein each device is manufactured from nano-sheets (NS) or Fin-FET devices used to form multiple devices within multiple transistor stacks within a single monolithic semiconductor die, wherein the devices are stacked on top of each other within a single multiple transistor stack. Accordingly, the various bit cell manufacturing methods and techniques described herein may provide different stack configurations, such as multiple N-type structures and multiple P-type structures, stacked in various multiple transistor stack configurations such as PPNN (P-over-P-over-N-over-N) stack configurations, NPPN (N-over-P-over-P-over-N) stack configurations, PNNP (P-over-N-over-N-over-P) stack configurations, and PNPN (P-over-N-over-P-over-N) stack configurations. In various embodiments, the gates for P-type FET (PFET) devices and N-type FET (NFET) devices may have a common gate or split gate architecture. Additionally, the bit cell manufacturing methods and techniques described herein also utilize techniques that support NP (N-over-P) devices and / or PN (P-over-N) devices or NN (N-over-N) and / or PP (P-over-P) stack configurations within the same single monolithic semiconductor die in various bit cell-related applications.

[0006] Various embodiments providing various multi-transistor bit cell architectures will be described herein with reference to FIGS. 1 through 5. Additionally, various bit cell manufacturing methods and techniques described herein may be configured to provide 6T bit cells using 4-device-stacked FET technology for physical layout design applications.

[0007] FIG. 1a illustrates a diagram (100A) of a bit cell architecture (104A) according to various embodiments described in this specification.

[0008] In some embodiments, the bit cell architecture (104A) may be implemented as a system or device having various integrated circuit (IC) components arranged and combined as a combination or assembly of parts providing physical circuit designs and various related structures. In some examples, the method of designing, providing, and constructing the bit cell architecture (104A) as an integrated system or device involves the use of various IC circuit components described herein and accordingly may implement the associated manufacturing methods and techniques. Additionally, the bit cell architecture (104A) may be integrated with computing circuits and related components on a single chip, and the bit cell architecture (104A) may be implemented in various embedded systems for automotive, electronic, mobile, server, and Internet of Things (IoT) applications.

[0009] As illustrated in FIG. 1a, the bit cell architecture (104A) can be implemented as a bit cell-related structure (108), such as a multi-transistor bit cell structure. For example, in some embodiments, the multi-transistor bit cell structure (108) can be configured as a multi-transistor (e.g., six transistors (6T)) single-port SRAM bit cell structure, wherein the six transistors (6T) include a plurality of (e.g., four) N-type metal-oxide-semiconductor (NMOS) transistors and a plurality of (e.g., two) P-type MOS (PMOS) transistors. In some examples, a passgate transistor (T1) may be coupled between a first bit line (BL) and a node (A), and another passgate transistor (T6) may be coupled between a second bit line (BLB) and a node (B), wherein the second bit line (BLB) is complementary to the first bit line (BL). Additionally, a word line (WL) is coupled to the gates of the transistors (T1, T6) so that data stored in a latch formed by a plurality of transistors (T2, T3, T4, T5) can be accessed through the word line (WL) and the complementary bit lines (BL, BLB).

[0010] Transistors (T2, T3) can be connected in series between a voltage supply (Vdd) and ground (Gnd or Vss), where node (A) is formed between a pull-up transistor (T2) and a pull-down transistor (T3). Additionally, transistors (T4, T5) can be connected in series between a voltage supply (Vdd) and ground (Gnd or Vss), where node (B) is formed between a pull-up transistor (T4) and a pull-down transistor (T5). Furthermore, transistors (T2, T3) can be cross-connected with transistors (T4, T5) so that node (A) is connected to the gates of transistors (T4, T5) and another node (B) is connected to the gates of transistors (T2, T3). As some examples, transistors (T2, T4) may refer to P-type field-effect transistors (PFETs), and transistors (T1, T3, T5, T6) may refer to N-type FETs (NFETs). However, various other configurations may be used to achieve similar results and / or behavior.

[0011] In some embodiments, referring to FIG. 1a, nodes (A, B) refer to internal nodes for routing that can be routed on the sides of a multi-transistor stack in its physical layout design, wherein nodes (A, B) may not physically intersect. Additionally, as shown in FIG. 2a, two PFET dummy cells (- - -) can be used to separate the internal nodes (A, B) from other FET cells. Additionally, two PFET dummy cells are placed on top of the multi-transistor stack to simplify device manufacturing.

[0012] FIG. 1b illustrates a diagram (100B) of a multi-transistor architecture (104B) according to various embodiments described herein. In various embodiments, the multi-transistor architecture (104B) illustrated in FIG. 1b is associated with the bit cell architecture (104A) illustrated in FIG. 1a, along with various associated components.

[0013] As illustrated in FIG. 1b, the multi-transistor architecture (104B) refers to a cross-connection on the side of a multi-transistor stack. The multi-transistor architecture (104B) has a first poly-gate stack (110) for transistors (T1, T6) and a second poly-gate stack (114) for transistors (T2, T3, T4, T5). The multi-transistor architecture (104B) has a source / drain diffusion region (120) for transistors (T1 to T6). Additionally, the multi-transistor architecture (104B) may have a local interconnection stack (118) that provides a connection to the diffusion region for node (A) and a connection to the diffusion region for node (B). In some embodiments, the first poly gate stack (110) may have a first stack of four transistors, such as 4P, 4N, 2P / 2N, or 2N having 2P as dummy cells. Additionally, the second poly gate stack (114) may have a second stack of four transistors, such as 4P, 4N, or 2P / 2N. Furthermore, the multi-transistor architecture (104B) may have one or more cross-connection connections between various components, such as a first cross-connection (124) connecting a diffusion section A to a poly gate B and a second cross-connection connecting a diffusion section B to a poly gate A. These concepts, along with various other features, behaviors, and characteristics, are described in more detail below with reference to FIGS. 2a through 2d and FIGS. 3a through 3d.

[0014] Furthermore, in various embodiments, referring to FIG. 1a, the bit cell architecture (104A) may be implemented as one or more core arrays of bit cells or memory cells, each bit cell may be configured to store at least one data bit value (e.g., a data value associated with a logical '0' or '1'). One or more core arrays may include any number of bit cells arranged in various configurations, such as two-dimensional (2D) memory arrays having a number of bit cells in any number of columns and any number of rows, which may be arranged in a 2D grid pattern for read and write memory access. However, even though an SRAM bit cell structure is illustrated and described in FIG. 1a, any other type of bit cell structure may be used to achieve similar results of the various bit cell manufacturing techniques disclosed herein. Accordingly, as various examples, each bit cell can be implemented as any type of memory including, for instance, MRAM (magneto-resistive RAM) and / or any other type of available memory.

[0015] In some embodiments, the various bit cell manufacturing methods and techniques described herein provide multiple arrangements of device stacks used to form a 6-transistor SRAM bit cell (6T) in NPPN / PNNP / NNPP stacking technologies. Additionally, the arrangement provides for manufacturing two bit cells with a double footprint using mutually independent upper-2 and lower-2 stacks. In some embodiments, the 6T bit cell may be composed of two poly pitches providing eight devices in 4-stacking device technologies. In these embodiments, four devices may be manufactured within a single poly pitch and may be used to form a cross-coupled inverter pair. The transistor stacking may refer to NPPN or PNNP. A continuous poly is etched into a PMOS to form a passgate pair for a bitline pair (or it is left as a dummy), which is described later in this specification with reference to FIGS. 2a to 2d and FIGS. 3a to 3d.

[0016] Additionally, in another embodiment, the transistor array may refer to PPNN, where two inverters may be formed by one of the following techniques. For example, the top and bottom transistors may be used to form one inverter, and the middle transistors may be used to form another inverter. Also, as another example, alternating transistors within the stack may be used to form each of the two inverters. Thus, the cross-coupled array may be formed from its sides as described below with reference to FIGS. 2a to 2d and FIGS. 3a to 3d.

[0017] Additionally, in another embodiment, the cross-coupled inverters may be formed of two consecutive polys, wherein one inverter is composed of a first poly using the upper two devices in the stack, and the other cross-coupled inverter is composed of a consecutive poly using the lower two devices in the stack. The remaining two PMOS devices in the 8-device stack may be removed (etched) to provide space that can be used to create cross-coupled connections, such as connecting the input of one inverter to the output of another inverter. The remaining NMOS devices may be used as passgate devices, wherein the entire structure may be flipped to share bitlines (BL, BLB), such as from the outputs of the passgate devices. Additionally, metal connections for the bitlines may be exchanged between the bitlines to balance capacitance. Other features related to these techniques are described later in FIGS. 2a through 2d and FIGS. 3a through 3d.

[0018] FIGS. 2a through 2d illustrate various diagrams of multi-transistor stack architectures according to various embodiments described herein. For example, FIG. 2a illustrates a side view (200A) of a multi-transistor PPNN stack architecture (204A), FIG. 2b illustrates another side view (200B) of a multi-transistor NPPN stack architecture (204B), FIG. 2c illustrates another side view (200C) of a multi-transistor PNPN stack architecture (204C), and FIG. 2d illustrates another side view (200D) of a multi-transistor PNNP stack architecture (204D). Additionally, the various multi-transistor stack architectures illustrated in FIG. 2a through 2d are associated with the bit cell architecture (104A) in FIG. 1a, along with various associated components.

[0019] As illustrated in FIG. 2a, the multi-transistor PPNN stack architecture (204A) may refer to a PPNN architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the manner described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Therefore, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (B, A) of the PPNN architecture (204A). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0020] In some embodiments, the multi-transistor PPNN stack architecture (204A) may be manufactured within a single monolithic semiconductor die having a PPNN stack configuration provided as a multi-transistor stack, such as a 4-transistor PPNN-FET stack. In FIG. 2a, the multi-transistor PPNN-FET stack may include a plurality of nanosheet (NS) or Fin-FET layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), stacked on top of another. In some examples, the PPNN nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the PPNN architecture (204A) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0021] As illustrated in FIG. 2b, the multi-transistor NPPN stack architecture (204B) may refer to an NPPN architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the same manner as described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Accordingly, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (B, A) of the NPPN architecture (204A). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0022] In some embodiments, the multi-transistor NPPN stack architecture (204B) may be fabricated within a single monolithic semiconductor die having an NPPN stack configuration provided as a multi-transistor stack, such as a 4-transistor NPPN-FET stack. In FIG. 2b, the multi-transistor NPPN-FET stack may include a plurality of nanosheet (NS) or FinFET layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), stacked on top of another. In some examples, the NPPN nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the NPPN architecture (204B) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0023] As illustrated in FIG. 2c, the multi-transistor PNPN stack architecture (204C) may refer to a PNPN architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the manner described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Therefore, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (B, A) of the PNPN architecture (204A). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0024] In some embodiments, the multi-transistor PNPN stack architecture (204C) may be fabricated within a single monolithic semiconductor die having a PNPN stack configuration provided as a multi-transistor stack, such as a 4-transistor PNPN-FET stack. In FIG. 2c, the multi-transistor PNPN-FET stack may have a plurality of nanosheet (NS) or FinFET layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), stacked on top of another. In some examples, the PNPN nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the PNPN architecture (204B) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0025] As illustrated in FIG. 2d, the multi-transistor PNNP stack architecture (204D) may refer to a PNNP architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the manner described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Therefore, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (A, B) of the PNNP architecture (204A). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0026] In some embodiments, the multi-transistor PNNP stack architecture (204D) may be fabricated within a single monolithic semiconductor die having a PNNP stack configuration provided as a multi-transistor stack, such as a 4-transistor PNNP-FET stack. In FIG. 2d, the multi-transistor PNNP-FET stack may have a plurality of nanosheet (NS) or FinFET layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), stacked on top of another. In some examples, the PNNP nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the PNNP architecture (204D) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0027] Additionally, as illustrated with reference to FIGS. 2a to 2d, any unused PP multi-transistor stacks are referred to as dummy cells and may be left floating or etched.

[0028] In various embodiments, referring to FIGS. 2a through 2d, a multi-transistor stack bit cell architecture may refer to a device having a plurality of transistors in a single stack arranged as a cross-coupled bit cell latch, wherein the plurality of transistors may be arranged in a multi-transistor stack configuration formed within a single monolithic semiconductor die. The plurality of transistors may include at least four transistors arranged within a single stack within a single monolithic semiconductor die, and the plurality of transistors may also be arranged as bit cells for single-port memory applications.

[0029] A plurality of transistors may include a plurality of N-type transistors and a plurality of P-type transistors. In various embodiments, the multi-transistor stack configuration refers to various and different stack combinations, such as, for example, a PPNN stack configuration, an NPPN stack configuration, a PNNP stack configuration, and / or a PNPN stack configuration. Additionally, in various embodiments, the plurality of transistors includes a pair of N-type transistors and a pair of P-type transistors configured to form two inverter pairs by combining a first N-type transistor from a pair of N-type transistors and a first P-type transistor from a pair of P-type transistors to form a first inverter pair of two inverter pairs, and combining a second N-type transistor from a pair of N-type transistors and a second P-type transistor from a pair of P-type transistors to form a second inverter pair of two inverter pairs. Additionally, the two inverter pairs may be cross-coupled on their sides to provide two cross-coupled inverters utilized as a cross-coupled bit cell latch. In addition, a plurality of transistors include a first passgate and a second passgate for a bit cell, wherein the first passgate is coupled between a first bit line and the first inverter of two cross-coupled inverters, and the second passgate is coupled between a second bit line and the second inverter of two cross-coupled inverters. Also, the gates of the first passgate and the second passgate are coupled to a word line for the bit cell. Additionally, as described in this specification, a plurality of transistors may include field-effect transistors (FETs), including a P-type FET (PFET) and an N-type FET (NFET).

[0030] FIGS. 3a through 3d illustrate various diagrams of multi-transistor stack architectures according to various embodiments described herein. For instance, FIG. 3a illustrates a side view (300A) of a multi-transistor PPNN stack architecture (304A), FIG. 3b illustrates another side view (300B) of a multi-transistor PNPN stack architecture (304B), FIG. 3c illustrates another side view (300C) of a multi-transistor NNPP stack architecture (304C), and FIG. 3d illustrates another side view (300D) of a multi-transistor PNNP stack architecture (304D). Additionally, the various multi-transistor stack architectures illustrated in FIG. 3a through 3d are associated with the bit cell architecture (104A) in FIG. 1a, along with various associated components.

[0031] As illustrated in FIG. 3a, the multi-transistor PPNN stack architecture (304A) may refer to a PPNN architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the manner described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Therefore, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (B, A) of the PPNN architecture (304A). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0032] In some embodiments, the multi-transistor PPNN stack architecture (304A) may be manufactured within a single monolithic semiconductor die having a PPNN stack configuration provided as a multi-transistor stack, such as a 4-transistor PPNN-FET stack. In FIG. 3a, the multi-transistor PPNN-FET stack may include a plurality of nanosheet or FinFET (NS) layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), stacked on top of another. In some examples, the PPNN nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the PPNN architecture (304A) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0033] As illustrated in FIG. 3b, the multi-transistor PNPN stack architecture (304B) may refer to a PNPN architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the same manner as described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Therefore, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (B, A) of the PNPN architecture (304B). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0034] In some embodiments, the multi-transistor PNPN stack architecture (304B) may be manufactured within a single monolithic semiconductor die having a PNPN stack configuration provided as a multi-transistor stack, such as a 4-transistor PNPN-FET stack. In FIG. 3b, the multi-transistor PNPN-FET stack may include a plurality of nanosheet (NS) or FinFET layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), which are stacked on top of each other, for example. In some examples, the PNPN nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the PNPN architecture (304B) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0035] As illustrated in FIG. 3c, the multi-transistor NNPP stack architecture (304C) may refer to an NNPP architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the manner described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Therefore, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (B, A) of the NNPP architecture (304C). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0036] In some embodiments, the multi-transistor NNPP stack architecture (304C) may be fabricated within a single monolithic semiconductor die having an NNPP stack configuration provided as a multi-transistor stack, such as a 4-transistor NNPP-FET stack. In FIG. 3c, the multi-transistor NNPP-FET stack may have a plurality of nanosheet (NS) or FinFET layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), stacked on top of another. In some examples, the NNPP nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the NNPP architecture (304C) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0037] As illustrated in FIG. 3d, the multi-transistor PNNP stack architecture (304D) may refer to a PNNP architecture having NMOS transistors (T1, T3, T5, T6) arranged to provide pass-gate transistors (T1, T6) and cross-coupled pull-down transistors (T3, T5) in the manner described with reference to the bit-cell architecture (104A) in FIG. 1a. For example, transistors (T1, T3) may be coupled in series between a first bit line (BL) and ground, and transistors (T6, T5) may be coupled in series between a second bit line (BLB) and ground. The gate of transistor (T3) may be coupled to a node (B) placed between transistors (T4, T5), and the gate of transistor (T5) may also be coupled to a node (A) placed between transistors (T2, T3). Therefore, the gates of the transistors (T3, T5) can be cross-coupled to the nodes (B, A) of the PNNP architecture (304D). In addition, the word line (WL) can be coupled to the gates of the passgate transistors (T1, T6) for its activation.

[0038] In some embodiments, the multi-transistor PNNP stack architecture (304D) may be fabricated within a single monolithic semiconductor die having a PNNP stack configuration provided as a multi-transistor stack, such as a 4-transistor PNNP-FET stack. In FIG. 3d, the multi-transistor PNNP-FET stack may have a plurality of nanosheet (NS) or FinFET layers, such as a first nanosheet or FinFET (NS_1), a second nanosheet or FinFET (NS_2), a third nanosheet or FinFET (NS_3), and a fourth nanosheet or FinFET (NS_4), stacked on top of another. In some examples, the PNNP nanosheets or FinFETs (NS_1, NS_2, NS_3, NS_4) may include gate portions coupled to different circuit components of the PNNP architecture (304D) along with local interconnect portions. For example, the NFET portions of transistors (T3, T5) can be coupled to VSS (or ground), the PFET portions of transistors (T2, T4) can be coupled to VDD, and the gate portions can be cross-coupled to nodes (A, B) with local interconnects. Also, as some examples, the NFET portions of passgate transistors (T1, T6) can be coupled between the word lines (WL) at their gates and the bit lines (BL, BLB) at their drains, respectively.

[0039] Additionally, as illustrated with reference to FIGS. 3a to 3d, any unused PP multi-transistor stacks are referred to as dummy cells and can be left floating or etched.

[0040] In various embodiments, referring to FIGS. 3a through 3d, a multi-transistor stack bit cell architecture may refer to a bit cell device having a pair of N-type devices and a pair of P-type devices, wherein the pair of N-type devices and the pair of P-type devices may be formed within a single stack in a single monolithic semiconductor die. The bit cell device may be arranged within a physical structure in various single stack configurations, such as various combinations of P-type and N-type layering in a single stack. In some examples, a pair of N-type devices and a pair of P-type devices may be placed in a single stack having a PPNN stack configuration. In other examples, a pair of N-type devices and a pair of P-type devices may be placed in a single stack having an NPPN stack configuration. In other examples, a pair of N-type devices and a pair of P-type devices may be placed in a single stack having a PNNP stack configuration. In addition, as other examples, a pair of N-type devices and a pair of P-type devices can be placed within a single stack having a PNPN stack configuration.

[0041] Furthermore, in various embodiments, a pair of N-type devices and a pair of P-type devices are cross-coupled on their sides to provide two cross-coupled inverters utilized as latches for a bit cell. Additionally, the bit cell device may include one or more pass gates, such as a first pass gate and a second pass gate, wherein the first pass gate is coupled between a first bit line and the first inverter of the two cross-coupled inverters, and the second pass gate is coupled between a second bit line and the second inverter of the two cross-coupled inverters. Additionally, the gates of the first pass gate and the second pass gate may be coupled to a word line for the bit cell. Furthermore, as described herein, a pair of N-type devices may refer to a pair of NFET devices, and a pair of P-type devices may refer to a pair of PFET devices.

[0042] FIGS. 4a through 4c illustrate various diagrams of split-gate transistor architectures according to embodiments described herein. For example, FIG. 4a illustrates a diagram (400A) of a PPNN split-gate transistor architecture (404A), FIG. 4b illustrates a diagram (400B) of an NPPN split-gate transistor architecture (404B), and FIG. 4c illustrates a diagram (400C) of a PNNP split-gate transistor architecture (404C). Split-gate architectures (404A, 404B, 404C) and various related components as illustrated in FIGS. 4a through 4c are related to the bit cell architecture (104A) in FIG. 1a and the multi-transistor stack architectures described in FIGS. 2a through 2d and FIGS. 3a through 3d.

[0043] As illustrated in FIG. 4a, the PPNN split gate related transistor architecture (404A) may include a plurality of transistors (e.g., two PFET devices and two NFET devices) arranged in a multi-transistor stack configuration. For example, the first PFET may be formed within a first PFET nanosheet or FinFET (PFET_NS_1), and the second PFET may be formed within a second PFET nanosheet or FinFET (NFET_NS_2), and these are placed within a single stack. Additionally, the first NFET may be formed within a first NFET nanosheet or FinFET (NFET_NS_1), and the second NFET may be formed within a second NFET nanosheet or FinFET (NFET_NS_2), and these are placed within a single stack. The split gate architecture (404A) may have a plurality of gates (e.g., poly gate lines) coupled to the plurality of transistors. In some examples, a first P-gate (P_GATE_1) may be coupled to a PFET_NS_1 device and a second gate (P_GATE_2) may be coupled to a PFET_NS_2 device, and also a first N-gate (N_GATE_1) may be coupled to an NFET_NS_1 device and a second N-gate (N_GATE_2) may be coupled to an NFET_NS_2 device. This arrangement provides a PPNN stack configuration fabricated and / or formed within the same single monolithic semiconductor die. Additionally, in various embodiments, a pair of P-type devices and a pair of N-type devices may be cross-coupled on their sides to provide two cross-coupled inverters that can be utilized as latches for bit cells.

[0044] As illustrated in FIG. 4b, the NPPN split gate related transistor architecture (404B) may include a plurality of transistors (e.g., two PFET devices and two NFET devices) arranged in a multi-transistor stack configuration. For example, the first PFET may be formed within a first PFET nanosheet or FinFET (PFET_NS_1), and the second PFET may be formed within a second PFET nanosheet or FinFET (NFET_NS_2), and these are placed within a single stack. Additionally, the first NFET may be formed within a first NFET nanosheet or FinFET (NFET_NS_1), and the second NFET may be formed within a second NFET nanosheet or FinFET (NFET_NS_2), and these are placed within a single stack. The split gate architecture (404B) may have a plurality of gates (e.g., poly gate lines) coupled to the plurality of transistors. In some examples, a first P-gate (P_GATE_1) may be coupled to a PFET_NS_1 device and a second gate (P_GATE_2) may be coupled to a PFET_NS_2 device, and also a first N-gate (N_GATE_1) may be coupled to an NFET_NS_1 device and a second N-gate (N_GATE_2) may be coupled to an NFET_NS_2 device. This arrangement provides an NPPN stack configuration fabricated and / or formed within the same single monolithic semiconductor die. Additionally, in various embodiments, a pair of P-type devices and a pair of N-type devices may be cross-coupled on their sides to provide two cross-coupled inverters that can be utilized as latches for bit cells.

[0045] As illustrated in FIG. 4c, the PNNP split gate related transistor architecture (404C) may include a plurality of transistors (e.g., two PFET devices and two NFET devices) arranged in a multi-transistor stack configuration. For example, the first PFET may be formed within a first PFET nanosheet or FinFET (PFET_NS_1), and the second PFET may be formed within a second PFET nanosheet or FinFET (NFET_NS_2), and these are placed within a single stack. Additionally, the first NFET may be formed within a first NFET nanosheet or FinFET (NFET_NS_1), and the second NFET may be formed within a second NFET nanosheet or FinFET (NFET_NS_2), and these are placed within a single stack. The split gate architecture (404C) includes a plurality of gates (e.g., poly gate lines) coupled to the plurality of transistors. In some examples, a first P-gate (P_GATE_1) may be coupled to a PFET_NS_1 device and a second gate (P_GATE_2) may be coupled to a PFET_NS_2 device, and also a first N-gate (N_GATE_1) may be coupled to a NFET_NS_1 device and a second N-gate (N_GATE_2) may be coupled to a NFET_NS_2 device. This arrangement provides a PNNP stack configuration fabricated and / or formed within the same single monolithic semiconductor die. Additionally, in various embodiments, a pair of P-type devices and a pair of N-type devices may be cross-coupled on their sides to provide two cross-coupled inverters that can be utilized as latches for bit cells.

[0046] In some embodiments, referring to FIGS. 4a through 4c, various split gate architectures (404A, 404B, 404C) may be replaced with a common gate architecture, wherein one or more transistors (PFET_NS_1 and / or PFET_NS_2 and / or NFET_NS_1 and / or NFET_NS_2) may be arranged and / or configured to share a single gate structure. As such, in various examples, a pair of stacked PFET devices and / or a pair of stacked NFET devices may be configured to share a single common gate structure.

[0047] FIG. 5 illustrates a diagram of a method (500) for manufacturing a bit cell architecture according to various embodiments described herein. In some embodiments, the method (500) may be configured to manufacture a multi-transistor stack bit cell architecture.

[0048] It should be understood that even though the method (500) represents the execution of operations in a specific order, in some cases, various specific parts of the operations may be executed in a different order and on different systems. In other cases, additional operations and / or steps may be added to the method (500) and / or omitted therefrom. Additionally, the method (500) may be implemented in hardware and / or software. When implemented in hardware, the method (500) may be implemented as various components and / or circuits as described herein with reference to FIGS. 1 through 4c. Additionally, when implemented in software, the method (500) may be implemented as a program and / or software instruction process configured to provide bit cell architecture methods and techniques as described herein. Furthermore, when implemented in software, various instructions associated with implementing the method (500) may be stored in memory and / or a database. For example, various types of computing devices having a processor and memory can be configured to perform the method (500).

[0049] In various embodiments, the method (500) may refer to a method of designing, providing, constructing, manufacturing, and / or fabricating various bit cell-related structures as an integrated device that may involve the use of various components and materials described herein. Additionally, bit cells may be integrated with various computing circuits and related components on a single chip, and non-volatile memory bit cells may be implemented in various embedded systems for various electronic, mobile, and / or Internet of Things (IoT) applications, including remote sensor nodes.

[0050] In block (510), the method (500) can manufacture a plurality of transistors arranged as bit cells. In block (520), the method (500) can manufacture a plurality of devices having a pair of N-type transistors and a pair of P-type transistors arranged in a single multi-transistor stack configuration and formed within the same single monolithic semiconductor die. In some examples, the plurality of transistors may include at least four transistors arranged in a single stack within a single monolithic semiconductor die, and the plurality of transistors may also be arranged as bit cells for single-port memory applications.

[0051] In block (530), the method (500) can provide a first inverter by combining (or combining) a first N-type transistor from a pair of N-type transistors and a first P-type transistor from a pair of P-type transistors. In block (540), the method (500) can provide a second inverter by combining (or combining) a second N-type transistor from a pair of N-type transistors and a second P-type transistor from a pair of P-type transistors.

[0052] In block (550), the method (500) may cross-couple a pair of N-type transistors and a pair of P-type transistors to provide a plurality of (e.g., two) cross-coupled inverters used as latches for bit cells. In some embodiments, the method (500) may cross-couple a first inverter and a second inverter to provide a plurality of (e.g., two) cross-coupled inverters used as latches for bit cells. In some embodiments, two pairs of inverters are cross-coupled on their sides to provide two cross-coupled inverters utilized as cross-coupled bit cell latches.

[0053] In various embodiments, a single multi-transistor stack configuration refers to at least one of a PPNN stack configuration, an NPPN stack configuration, a PNNP stack configuration, and a PNPN stack configuration. However, it should be understood that various other stack configurations may be utilized to achieve various bit cell manufacturing methods and techniques as described herein. Additionally, in some embodiments, a plurality of transistors may refer to field-effect transistor (FET) devices, including, for example, P-type FET (PFET) devices and N-type FET (NFET) devices.

[0054] In some embodiments, a plurality of transistors may include a first pass gate and a second pass gate for a bit cell. The first pass gate may be coupled between a first bit line and a first inverter of two cross-coupled inverters, and the second pass gate may be coupled between a second bit line and a second inverter of two cross-coupled inverters. Additionally, in some embodiments, the gates of the first pass gate and the second pass gate may be coupled to a word line for a bit cell.

[0055] Embodiments of a device having a plurality of transistors in a single stack arranged as a cross-coupled bit-cell latch are described herein. Additionally, in some embodiments, the plurality of transistors may be arranged in a multi-transistor stack configuration formed within a single monolithic semiconductor die.

[0056] Various embodiments of the bit cell are described herein. The bit cell may have a pair of N-type devices and a pair of P-type devices. In some embodiments, the pair of N-type devices and the pair of P-type devices may be formed within a single stack within a single monolithic semiconductor die.

[0057] Various embodiments of the method are described herein. The method can manufacture a plurality of transistors arranged as a bit cell. The method can manufacture a plurality of devices having a pair of N-type transistors and a pair of P-type transistors arranged in a single multi-transistor stack configuration and formed within a single monolithic semiconductor die. In some embodiments, the method can cross-couple a pair of N-type transistors and a pair of P-type transistors to provide two cross-coupled inverters used as latches for the bit cell.

[0058] The subject matter of the claims is not intended to be limited to the embodiments and examples provided herein, but to include combinations of elements of different embodiments according to the claims and modified forms of these embodiments including parts of the embodiments. It should be understood that in the development of any such embodiment, many implementation-specific decisions must be made to achieve the developer's specific goals, such as compliance with system-related and business-related constraints that may vary from embodiment to embodiment, as in any engineering or design project. Furthermore, it should be understood that while such development efforts may be complex and time-consuming, they will nevertheless be the routine work of design, fabrication, and manufacturing for those skilled in the art who have an interest in the present invention.

[0059] References to various embodiments are made in detail, and examples thereof are illustrated in the accompanying drawings. In the following detailed description, many specific details are described to provide a complete understanding of the disclosures provided herein. However, the disclosures provided herein may be practiced without these specific details. In some other cases, well-known methods, procedures, components, circuits, and networks are not described in detail so as not to unnecessarily obscure the details of the embodiments.

[0060] While terms such as first, second, etc. may be used herein to describe various elements, it should also be understood that these elements are not to be limited by these terms. These terms are used only to distinguish one element from another. For example, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element. Although the first element and the second element are both elements, they are not considered to be the same element.

[0061] The terms used in describing the disclosures provided herein are intended to describe specific embodiments and are not intended to limit the disclosures provided herein. As used in describing the disclosures provided herein and in the appended claims, singular forms (“a,” “an,” and “the”) are intended to include plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and / or” refers to and encompasses any of one or more of the associated enumerated items and all possible combinations thereof. As used herein, the terms “includes,” “including,” “comprises,” and / or “comprising” specify the presence of the mentioned features, integers, steps, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, components, and / or groups thereof.

[0062] As used herein, the term “in the case of” may be interpreted, depending on the context, to mean “when” or “at” or “in response to determining” or “in response to detecting”. Similarly, the phrase “when it is determined” or “when [the mentioned condition or event] is detected” may be interpreted, depending on the context, to mean “when it is determined” or “in response to determining” or “when [the mentioned condition or event] is detected” or “in response to detecting [the mentioned condition or event]”. The terms “up” and “down”; “upper” and “lower”; “upward” and “downward”; “lower” and “upper”; and other similar terms indicating relative positions above or below a given point or element may be used in connection with some embodiments of the various techniques described herein.

[0063] Although the foregoing describes embodiments of various techniques described in this specification, other and additional embodiments may be devised in accordance with the disclosure of this specification, and these may be determined by the following claims.

[0064] Although the subject matter is described in language specific to structural features and / or methodological operations, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or operations mentioned above. Rather, the specific features and operations mentioned above are disclosed as exemplary forms embodying the claims.

Claims

Claim 1 A device comprising a plurality of transistors in a single stack arranged as a cross-coupled bitcell latch, wherein the plurality of transistors are arranged in a multi-transistor stack configuration formed within a single monolithic semiconductor die. Claim 2 A device according to claim 1, wherein the plurality of transistors comprises at least four transistors disposed within a single stack within the single monolithic semiconductor die, and the plurality of transistors are arranged as bit cells for single-port memory applications. Claim 3 A device according to claim 1, wherein the plurality of transistors comprises a plurality of N-type transistors and a plurality of P-type transistors, and the multi-transistor stack configuration refers to a PPNN (P-over-P-over-N-over-N) stack configuration. Claim 4 A device according to claim 1, wherein the plurality of transistors comprises a plurality of N-type transistors and a plurality of P-type transistors, and the multi-transistor stack configuration refers to an NPPN (N-over-P-over-P-over-N) stack configuration. Claim 5 A device according to claim 1, wherein the plurality of transistors comprises a plurality of N-type transistors and a plurality of P-type transistors, and the multi-transistor stack configuration refers to a PNNP (P-over-N-over-N-over-P) stack configuration. Claim 6 A device according to claim 1, wherein the plurality of transistors comprises a plurality of N-type transistors and a plurality of P-type transistors, and the multi-transistor stack configuration refers to a PNPN (P-over-N-over-P-over-N) stack configuration. Claim 7 A device according to claim 1, wherein the plurality of transistors comprises a pair of N-type transistors and a pair of P-type transistors configured to form two inverter pairs by combining a first N-type transistor from a pair of N-type transistors and a first P-type transistor from a pair of P-type transistors to form a first inverter pair of two inverter pairs, and by combining a second N-type transistor from the pair of N-type transistors and a second P-type transistor from the pair of P-type transistors to form a second inverter pair of two inverter pairs, wherein the two inverter pairs are cross-coupled on their sides to provide two cross-coupled inverters utilized as the cross-coupled bit cell latch. Claim 8 A device according to claim 7, wherein the plurality of transistors include a first passgate and a second passgate for the bit cell, the first passgate is coupled between a first bit line and a first inverter of the two cross-coupled inverters, and the second passgate is coupled between a second bit line and a second inverter of the two cross-coupled inverters. Claim 9 In claim 8, the gates of the first passgate and the second passgate are coupled to a wordline for the bit cell, the device. Claim 10 A device according to claim 1, wherein the plurality of transistors comprises field-effect transistors (FETs), including P-type FETs (P-type field-effect transistors, PFETs) and N-type FETs (NFETs). Claim 11 A bit cell comprising a pair of N-type devices; and a pair of P-type devices, wherein the pair of N-type devices and the pair of P-type devices are formed within a single stack within a single monolithic semiconductor die. Claim 12 In claim 11, the bit cell, wherein the pair of N-type devices and the pair of P-type devices are disposed within the single stack having a PPNN stack configuration. Claim 13 In claim 11, the bit cell wherein the pair of N-type devices and the pair of P-type devices are disposed within the single stack having an NPPN stack configuration. Claim 14 In claim 11, the bit cell wherein the pair of N-type devices and the pair of P-type devices are disposed within the single stack having a PNNP stack configuration. Claim 15 In claim 11, the bit cell wherein the pair of N-type devices and the pair of P-type devices are disposed within the single stack having a PNPN stack configuration. Claim 16 In claim 11, the bit cell, wherein the pair of N-type devices and the pair of P-type devices are cross-coupled on their sides to provide two cross-coupled inverters utilized as latches for the bit cell. Claim 17 In claim 16, a bit cell further comprising a first pass gate and a second pass gate, wherein the first pass gate is coupled between a first bit line and the first inverter of the two cross-coupled inverters, the second pass gate is coupled between a second bit line and the second inverter of the two cross-coupled inverters, and the gates of the first pass gate and the second pass gate are coupled to a word line for the bit cell. Claim 18 In paragraph 11, the above pair of N-type devices refers to a pair of N-type field-effect transistors (NFETs), and the above pair of P-type devices refers to a pair of P-type field-effect transistors (PFETs), a bit cell. Claim 19 A method comprising: manufacturing a plurality of transistors arranged as bit cells; manufacturing a plurality of devices having a pair of N-type transistors and a pair of P-type transistors arranged in a single multi-transistor stack configuration and formed within a single monolithic semiconductor die; and cross-couple the pair of N-type transistors and the pair of P-type transistors to provide two cross-coupled inverters used as latches for the bit cells. Claim 20 In claim 19, the single multi-transistor stack configuration refers to at least one of a PPNN stack configuration, an NPPN stack configuration, a PNNP stack configuration, and a PNPN stack configuration.

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