Memory device and method of operation thereof, memory system, word line voltage control circuit

Abstract

The present disclosure provides a memory device, a method of operating the same, a memory system, and a word line voltage control circuit. The disclosed memory device comprises an array of memory cells, a plurality of word lines coupled to the memory cells, and a peripheral circuit coupled to the memory cells through the word lines. The peripheral circuit is configured to reduce a first voltage of a non-selected word line adjacent to a selected word line to a second voltage, to provide a precharge voltage to the selected word line, to increase a second voltage on the non-selected word line to a third voltage, and to float the selected word line.

Description

Technology Field

[0001] The present disclosure relates to the field of semiconductors, and in particular to memory devices and methods of operation thereof, memory systems, and word line voltage control circuits. Background Technology

[0002] As memory density continues to increase, memory cells are characterized by a shrinking physical volume, word lines within memory cells become physically closer, and capacity coupling between adjacent word lines increases. When the number of accesses to a specific row of a memory cell exceeds a threshold, it can cause data on rows adjacent to that row to become abnormal, and this phenomenon is generally referred to as row hammer.

[0003] In a first embodiment, the example of the present disclosure provides a memory, the memory comprising an array of memory cells and a peripheral circuit coupled to the array of memory cells; the array of memory cells comprises a plurality of word lines; and the peripheral circuit is configured to: begin providing a precharge voltage to a selected word line among the plurality of word lines at a first time—wherein the voltage provided on a non-selected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time prior to the first time—and to begin floating the selected word line at a third time prior to the first time—wherein the voltage provided on the adjacent non-selected word line is changed from a second voltage to a third voltage at a fourth time prior to the third time and after the first time; and the second voltage is lower than the first voltage and the third voltage.

[0004] In a second aspect, the example of the present disclosure provides a memory system comprising: a memory of the manner described above; and a controller coupled to the memory and configured to control the memory.

[0005] In a third embodiment, the example of the present disclosure provides a control circuit for a word line voltage comprising: a first voltage transmission circuit configured to provide a first transmission voltage in response to a first enable signal prior to the start of providing a precharge voltage for a selected word line; a second voltage transmission circuit configured to provide a second transmission voltage in response to a second enable signal prior to the start of floating of the selected word line and after the start of providing a precharge voltage for the selected word line; and a driving circuit for a local word line connected to both the first voltage transmission circuit and the second voltage transmission circuit, configured to connect a non-selected word line adjacent to the selected word line to the first voltage transmission circuit prior to the start of providing a precharge voltage to the selected word line, and to connect a non-selected word line adjacent to the second voltage transmission circuit prior to the start of floating of the selected word line and after the start of providing a precharge voltage to the selected word line.

[0006] In a fourth aspect, the example of the present disclosure provides a method for operating a memory, the method comprising: starting to provide a precharge voltage to a selected word line among a plurality of word lines of the memory at a first time—the voltage provided on an unselected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time prior to the first time—; and starting to float the selected word line at a third time prior to the first time—the voltage provided on an adjacent unselected word line is changed from a second voltage to a third voltage at a fourth time prior to the third time and after the first time; the second voltage is lower than the first voltage and the third voltage. Brief explanation of the drawing

[0007] In the attached drawings, unless otherwise specified, the same reference number refers to the same or similar parts or elements throughout the multiple attached drawings. The attached drawings are not necessarily in a fixed proportion. It should be understood that these attached drawings depict only some examples disclosed in accordance with the present disclosure and should not be construed as limiting the scope of the present disclosure. FIG. 1 illustrates a schematic structural diagram of an exemplary electronic device (1) including a memory according to one example of the present disclosure; FIG. 2 is a schematic diagram of an exemplary dynamic random access memory according to one example of the present disclosure; FIG. 3 is a schematic diagram of the connection of word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to one example of the present disclosure; FIG. 4 is a schematic diagram of the timing of the voltages of the associated signal, word line, and voltage transfer line when a selected word line provided by one example of the present disclosure is accessed; FIG. 5 is a structural schematic diagram of a memory provided by one example of the present disclosure; FIG. 6 is a schematic diagram of the timing of the voltages of the associated signal, word line, and voltage transfer line when a selected word line is accessed as provided by another example of the present disclosure; FIG. 7 is a schematic diagram of a partial structure of a peripheral circuit provided by one example of the present disclosure; FIG. 8a is a schematic diagram illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to one example of the present disclosure; FIG. 8b is a top view schematic diagram illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to one example of the present disclosure; FIG. 9a is a schematic diagram illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to another example of the present disclosure; FIG. 9b is a schematic top view illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to another example of the present disclosure; and FIG. 10 is a schematic flowchart of an embodiment of a method for operating a memory provided by an embodiment of the present disclosure. Specific details for implementing the invention

[0008] Exemplary embodiments disclosed in this disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of this disclosure are illustrated in the accompanying drawings, it should be understood that this disclosure may be embodied in various forms and should not be limited to the specific embodiments described herein. Rather, these examples are provided to enable a more complete understanding of this disclosure and to sufficiently convey the scope of this disclosure to those skilled in the art.

[0009] In the following description, a number of specific details are provided to provide a more complete understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other examples, to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, not all features of actual examples are described herein, and widely known functions and structures are not described in detail.

[0010] Furthermore, the accompanying drawings are merely schematic examples of the present disclosure and are not necessarily depicted in a specific proportion. Identical reference numbers in the accompanying drawings indicate identical or similar parts, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically distinct entities. These functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0011] The flowcharts illustrated in the attached drawings are for illustrative purposes only and do not necessarily include all steps. For example, some steps may be broken down, some steps may be merged or partially merged, and thus the actual order of execution may change depending on the actual situation.

[0012] The terms used herein are for the purpose of describing specific examples only and should not be construed as a limitation of this disclosure. As used herein, the singular forms “a,” “an,” and “said / the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the terms “consists of” and / or “comprising,” as used herein, identify the presence of the mentioned features, integers, steps, actions, elements, and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, actions, elements, parts, and / or groups. As used herein, the term “and / or” includes any and all combinations of the items listed in relation.

[0013] FIG. 1 illustrates a schematic diagram of an exemplary electronic device (1) having a memory according to one example of the present disclosure. The electronic device (1) may be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device inside. As illustrated in FIG. 1, the electronic device (1) may include a host (HOST) and a memory system (30), and the memory system (30) includes a memory controller (10) and one or more memories (20). The host (HOST) may be a processor of the electronic device (e.g., a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU). The host (HOST) may be configured to transmit data to the memory (20) or to receive data from the memory (20). The memory controller (10) is coupled to the memory (20) and the host (HOST) and is configured to control the memory (20). The memory controller (10) can manage data stored in the memory (20) and can communicate with the host (HOST).

[0014] The memory controller (10) may be configured to control the operation of the memory (20), for example, read, erase, write, and refresh operations. In some embodiments, the memory controller (10) is further configured to process an Error Correction Code (ECC) related to data read from or written to the memory (20). The memory controller (10) may also perform any other suitable function, for example, formatting of the memory (20).

[0015] In some specific examples, the memory controller (10) and one or more memories (20) can be integrated into various types of electronic devices, for example, the memory controller (10) can be integrated into the north bridge of a computer motherboard or directly into a computer CPU, and the multiple memories (20) can be integrated into a memory stick. That is, the memory system (30) can be implemented and packaged into different types of end electronic products.

[0016] The memory controller (10) can transmit / receive data to / from a host (HOST) and can transmit a command (CMD) and an address (ADDR) to the memory (20). The memory controller (10) may include a command generator (110), an address generator (120), a device interface (130), and a host interface (140). The host interface (140) can receive a command (CMD) and an address (ADDR) from the host (HOST), and the command generator (110) can generate an access command, a row hammer refresh command, etc. by decoding the command (CMD) received from the host (HOST), and can provide the access command and the row hammer refresh command to the memory (20) through the device interface (130). An access command may be a signal indicating to the memory (20) to write or read data by accessing a row of an array (220) of memory cells corresponding to an address (ADDR). A row hammer refresh command may be a signal instructing the memory (20) to perform an additional refresh operation on a word line adjacent to a word line that is accessed intensively within a short period of time. In other words, an additional refresh operation may be performed on a word line adjacent to a word line that is accessed multiple times within a short period of time. A large number of accesses may be the result of repeated requests to access the same word line.

[0017] An address generator (120) within the memory controller (10) can generate row addresses and column addresses to be accessed in an array of memory cells (220) by decoding an address (ADDR) received from a host interface (140). Additionally, the memory (20) can generate addresses of banks to be accessed if the array of memory cells (220) includes multiple banks.

[0018] Additionally, the memory controller (10) can control memory operations such as writing and reading by providing various signals to the memory (20) through the device interface (130). For example, the memory controller (10) can provide a write command to the memory (20). The write command instructs the memory (20) to perform a write operation and store data into the memory (20). In some examples, the memory (20) includes an array of memory cells (220) and peripheral circuits (210); the array of memory cells (220) includes a plurality of banks, each bank includes a plurality of blocks, each block includes a plurality of rows of memory cells and a plurality of columns of memory cells, each row of memory cells is coupled to a corresponding word line, and each column of memory cells is coupled to a corresponding bit line. The peripheral circuit (210) can provide a control signal (CTRL) to a row decoder and a column decoder to write data to an array of memory cells (220) or read data from an array of memory cells (220) based on a command (CMD) and an address (ADDR) received from the memory controller (10), or to refresh a memory cell included in the array of memory cells (220). In other words, the peripheral circuit (210) can perform all operations for processing data of the array of memory cells (220). The peripheral circuit (210) may include the following: a control circuit corresponding to each block, for example, a sensing amplifier (SA) and a word-line driver (WLD), etc., a control circuit corresponding to each bank, for example, a row decoder, a column decoder, etc., and a control circuit corresponding to all banks, for example, a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0019] The memory (20) may be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. The following description considers only DRAM as an example for explanation.

[0020] FIG. 2 is a schematic diagram of an exemplary dynamic random access memory according to one example of the present disclosure, and FIG. 3 is a schematic diagram of the connection of word lines, bit lines, and memory cells of an exemplary dynamic random access memory according to one example of the present disclosure.

[0021] The right side of FIG. 2 illustrates the circuit of a memory cell of a DRAM. The DRAM comprises at least one DRAM die, and each DRAM die comprises an array of memory cells, and the array of memory cells comprises a plurality of memory cells (201) arranged in an array, and each memory cell (201) comprises a transistor (T) and a capacitor (C), and the main operating principle of the memory cell is to indicate whether a binary bit is 1 or 0 depending on the amount of charge stored in the capacitor. The memory cells are arranged in an array that can be considered as a conventional mesh structure, and details of the mesh structure may be referenced to FIG. 3. The array of memory cells utilizes rows and columns to specify addresses. By specifying the intersection of rows and columns (by specifying the row address and column address of the DRAM), the memory controller can independently access each memory cell of the DRAM die and perform operations such as reading, writing, or refreshing on the data stored therein.

[0022] DRAM memory cells are essentially capacitors that store electric charge, and capacitance can leak during read, write, and refresh processes; furthermore, the read process itself is destructive. Based on this, a refresh operation needs to be performed after a read operation or if the memory cell has not been accessed for a long time.

[0023] The data stored in a memory cell is determined by the charge of the capacitor, and this charge is easily affected between refresh cycles. Drifting electrons can move in and out of the memory cell, thereby changing the charge of the memory cell. If a line of an address is accessed too many times over a short period, the memory cells in the lines adjacent to that address accumulate sufficient charge changes, which can alter the state detected for the stored value. This is the Row Hammer phenomenon. As the size decreases, changes in the state detected for the stored value affect not only adjacent rows but even close rows (which are separated by two or more rows).

[0024] FIG. 4 is a schematic diagram of the voltage timing of the associated signal, word line, and voltage transfer line when a selected word line is accessed, provided by one example of the present disclosure. The selected word line (wl) accompanying below <n>It should be noted that ) can be understood as a word line connected to a memory cell to be accessed, and the selected word line, similar to the selected word line, will determine the target memory cell to be read, written, or to which other operations will be performed; therefore, the two terms can be used interchangeably and express similar meanings; and adjacent non-selected word lines (wl<n+1 또는 n-1> ) can be understood as a word line adjacent to the physical address of the selected word line; Vneg_local <n>It can be understood as a voltage transfer line with one end coupled to the select word line and providing voltage to the select word line, and Vneg_local <n>The other end of is coupled to the power supply terminal; Vneg_local<n+1 또는 n-1> is an adjacent non-selected word line (wl) with one end<n+1 또는 n-1> It can be understood as a voltage transfer line coupled to ) and providing voltage to adjacent unselected word lines, and likewise, Vneg_local<n+1 또는 n-1> The other end of is coupled to a power supply terminal. Also, the selected word line (wl <n>Since the length of ) is long, resistance cannot be ignored, and therefore, Vneg_local <n>When coupled to, Vneg_local <n>The end of the selected word line close to is the near end of the selected word line (wl_near <n>Referred to as ), and Vneg_local <n>The end of the selected word line far from is the far end of the selected word line (wl_far <n>Referred to as ); likewise, Vneg_local<n+1 또는 n-1> The end of an adjacent unselected word line close to is the near end of an adjacent unselected word line (wl_near<n+1 또는 n-1> Referred to as ), and Vneg_local<n+1 또는 n-1> The end of an adjacent unselected word line far from is the far end of the adjacent unselected word line (wl_far<n+1 또는 n-1> It is referred to as ).

[0025] For ease of understanding, examples of the present disclosure are the far end (wl_far) of an adjacent unselected word line.<n+1 또는 n-1> ) is considered as an example for illustrative purposes, however, it is not used to limit the scope of protection of the present disclosure, and the description in the examples of the present disclosure is of the near end of an adjacent non-selected word line (wl_near<n+1 또는 n-1> It can also be applied to ).

[0026] As shown in FIG. 4, the bank selection signal (Bank_enble), the main word line selection signal (mwl_n <k>), and word line selection signal (wld <n>Under the condition that ) is enabled, the precharge control signal (xpp <n>When ) transitions from a non-enabled state to an enabled state, at the first time node (Q1), the memory begins to perform a precharge operation for the selected word line, and the near end (wl_near) of the selected word line <n>)(the part indicated by the dotted parabola after Q1 in Fig. 4) and the far end of the selected word line (wl_far <n>The time period required by )(the part illustrated by the solid line below the dotted line after Q1 in FIG. 4) to start charging from the initial voltage (vneg) to the voltage (Vpp) at the first time node (Q1) is different. The near end of the selected word line (wl_near <n>) is Vneg_local <n>It can be understood that because it is closer to, that is, because it is closer to the power supply terminal, it can be charged to the voltage (Vpp) faster. The far end of the selected word line (wl_far <n>) is Vneg_local <n>It is far from, and therefore the time required to charge to the voltage (Vpp) is longer. In FIG. 4, it is shown that the slope of the dotted parabolic portion is greater than the slope of the solid parabolic portion. Adjacent unselected word line (wl<n+1 또는 n-1> In the case of ), the far end of the adjacent unselected word line (wl_far<n+1 또는 n-1> ) is considered as an example for explanation, and the far end of the selected word line (wl_far <n>The voltage on ) starts charging from the initial voltage (vneg) to the voltage (Vpp) at the first time node (Q1), and the far end (wl_far) of the selected word line <n>During the process of voltage rise in ), the far end (wl_far) of the adjacent unselected word line<n+1 또는 n-1> The voltage at ) will gradually rise due to word line coupling. At the far end of the selected word line (wl_far <n>After ) stabilizes at voltage (Vpp), the far end (wl_far) of the adjacent unselected word line<n+1 또는 n-1> The voltage of the ) gradually decreases and returns to the same as or slightly higher than the initial voltage (vneg).

[0027] The far end of the selected word line (wl_far <n>) at voltage (Vpp), and precharge control signal (xpp <n>After ) stabilizes at the second time node (Q2) where it transitions from the enabled state to the unenabled state, the memory begins to float the selected word line.

[0028] Next, at the third time node (Q3) after a predetermined buffer time elapsed after the second time node (Q2), the selected word line begins to discharge. Here, buffer discharge can be achieved through a falling edge delay circuit. For the operation to start discharging from the voltage (Vpp) to the initial voltage (vneg) at the third time node (Q3), the near end (wl_near) of the selected word line <n>The time period required by )(the part indicated by the dotted parabola after Q3 in Fig. 4) is the far end (wl_far) of the selected word line. <n>It is shorter than required by )(the part indicated by the solid line above the dotted line after Q3 in Fig. 4). At this time, the far end (wl_far) of the selected word line. <n>During the process of the voltage rising on ), due to word line coupling, the far end (wl_far) of an adjacent unselected word line<n+1 또는 n-1> The voltage on ) gradually drops below the initial voltage (vneg). The far end of the selected word line (wl_far <n>After the voltage on ) stabilizes from the initial voltage (vneg), the far end (wl_far) of the adjacent unselected word line<n+1 또는 n-1> The voltage on ) gradually increases and returns to near the initial voltage (vneg). In this way, during the precharge operation and subsequent discharge to be performed on the selected word line, if the voltage of the adjacent unselected word line rises or falls, a large voltage difference will occur on the adjacent unselected word line due to coupling, and this voltage difference is represented as ΔV1 in FIG. 4; in one embodiment, this voltage change (ΔV1) can cause the sensing state of the stored value of the memory cell coupled to the adjacent unselected word line to change, thereby threatening data security and exacerbating the problem of row hammering; In another aspect, this voltage change (ΔV1) can also cause a risk of gate-induced drain leakage (GIDL), thereby causing hole accumulation and increasing the floating body potential, and the high floating body potential can turn on a parasitic transistor between the floating body and the drain junction, thus causing a series of problems.

[0029] Increasing the frequency of periodic refreshes can mitigate the risks caused by row hammering to some extent and ensure that each row is refreshed before row hammering causes damage sufficient to generate an error in the cell's charge. However, the method described above will consume unnecessary time or power, and thus increase system power consumption and degrade system performance. Additionally, GIDL leakage is also an unresolved hidden risk.

[0030] For that purpose, the present disclosure proposes the following embodiment to reduce the large voltage difference between adjacent unselected word lines caused by coupling, thereby mitigating the row hammer problem and GIDL leakage problem.

[0031] An example of the present disclosure provides a memory as illustrated in FIG. 5, wherein the memory (20) comprises an array of memory cells (220) and a peripheral circuit (210) coupled to the array of memory cells (220); the array of memory cells (220) comprises a plurality of word lines; and the peripheral circuit (210) is configured to: begin providing a precharge voltage to a selected word line among the plurality of word lines at a first time—wherein the voltage provided on a non-selected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time prior to the first time—and to begin floating the selected word line at a third time prior to the first time—wherein the voltage provided on an adjacent non-selected word line is changed from a second voltage to a third voltage at a fourth time prior to the third time and after the first time; and the second voltage is lower than the first voltage and the third voltage.

[0032] FIG. 6 is a schematic diagram of the voltage timing of the associated signal, word line, and voltage transfer line when a selected word line is accessed, provided by another example of the present disclosure. In some examples, by referring to FIG. 5 and FIG. 6, the peripheral circuit (210) is configured to: begin providing a precharge voltage (Vpp) to a selected word line among a plurality of word lines at a third time point (T3)—whereby the voltage provided on a non-selected word line adjacent to the selected word line is changed from a first voltage (V1) to a second voltage (V2) at a first time point (T1) prior to the third time point (T3)—; and

[0033] To start floating a selected word line at a sixth time point (T6) after a third time point (T3), the voltage provided on an adjacent unselected word line is changed from a second voltage (V2) to a third voltage (V3) at a fourth time point (T4) which is before the sixth time point (T6) and after the third time point (T3); the second voltage (V2) is lower than the first voltage (V1) and the third voltage (V3).

[0034] In one example, as illustrated in FIG. 6, a bank selection signal (Bank_enble), a main word line selection signal (mwl_n <k>), and word line selection signal (wld <n>Under the condition that ) is enabled, the precharge control signal (xpp <n>When ) transitions from an unenabled state to an enabled state, at the third time point (T3), a precharge operation for the selected word line begins to be performed, and the near end (wl_near) of the selected word line <n>)(the part indicated by the dotted parabola after T1 in Fig. 6) and the far end of the selected word line (wl_far <n>The time period required by (the part shown by the solid line below the dotted line after T1 in Fig. 6) to start charging from the first (V1) to the precharge voltage (Vpp) at the first time is different.

[0035] Bank selection signal (Bank_enble), main word line selection signal (mwl_n <k>) and word line selection signal (wld <n>It should be noted that the enable state of ) is all at a low-level voltage such as Vss, and the non-enable state is all at a high-level voltage such as Vpp or Vdd. Precharge control signal (xpp <n>The enable state of ) is at a high level voltage such as Vpp or Vdd, and the non-enable state is at a low level voltage such as Vss.

[0036] wld shown in Fig. 6 <n>represents a word line selection signal for a selected word line, and the word line selection signal corresponding to an adjacent non-selected word line is always in a non-enabled state, i.e., at a high level voltage, and is not shown in FIG. 6.

[0037] Adjacent non-selected word lines (wl<n+1 또는 n-1> In the case of ), the far end of the adjacent unselected word line (wl_far<n+1 또는 n-1> ) is considered as an example for illustrative purposes, and at the first time point (T1) prior to the third time point (T3), Vneg_local<n+1 또는 n-1> The voltage of the phase changes from the first voltage (V1) to the second voltage (V2), and the far end (wl_far) of the unselected word line adjacent to the selected word line.<n+1 또는 n-1> ) Vneg_local<n+1 또는 n-1> It can be understood that the voltage provided by changes from the first voltage (V1) to the second voltage (V2), and that the second voltage (V2) is less than the first voltage (V1). In this way, the voltage provided to the adjacent unselected word line is reduced in advance to reduce the initial voltage of the adjacent unselected word line being pulled up by coupling before the selected word line begins pre-charging at the third time point (T3). If the rising voltage difference between adjacent unselected word lines caused by the coupling effect is not essentially changed, the absolute voltage of the adjacent unselected word line after coupling and pulling up is effectively reduced.

[0038] In the example of the present disclosure, at the sixth time point (T6), the precharge control signal (xpp <n>) transitions from the enabled state to the disabled state, the memory stops the precharge operation for the selected word line, and the memory starts floating the selected word line.

[0039] In some examples, as illustrated in FIG. 6, the memory begins to float the selected word line at the sixth time point (T6), and at the seventh time point (T7) after a predetermined buffer time elapsed after the sixth time point (T6), the selected word line begins to discharge.

[0040] Adjacent non-selected word lines (wl<n+1 또는 n-1> In the case of ), the far end of the adjacent unselected word line (wl_far<n+1 또는 n-1> ) is still considered as an example for explanation, and at the fourth time point (T4), which is before the sixth time point (T6) and after the third time point (T3), Vneg_local<n+1 또는 n-1> The voltage of the phase changes from the second voltage (V2) to the third voltage (V3), and the far end (wl_far) of the unselected word line adjacent to the selected word line.<n+1 또는 n-1> ) Vneg_local<n+1 또는 n-1> It can be understood that the voltage provided by changes from the second voltage (V2) to the third voltage (V3), and that the second voltage (V2) is less than the third voltage (V3). In this way, prior to the start of floating of the selected word line, the voltage provided to the adjacent unselected word line is increased in advance to increase the initial voltage of the adjacent unselected word line being pulled up by the coupling. If the decreasing voltage difference between adjacent unselected word lines caused by the coupling effect is not essentially changed, the absolute voltage of the adjacent unselected word line being pulled down by the coupling is effectively increased.

[0041] As illustrated in FIG. 6, by reducing the voltage provided to the adjacent non-selected word line prior to the precharge of the selected word line, the final voltage being pulled up by coupling from the voltage on the adjacent non-selected word line is controlled, i.e., it is the highest voltage in the subsequent voltage change; meanwhile, by increasing the voltage provided to the adjacent non-selected word line prior to the discharge of the selected word line, the final voltage being pulled down by coupling from the voltage on the adjacent non-selected word line is controlled, i.e., it is the lowest voltage in the subsequent voltage change. Since the highest voltage causing the voltage change becomes smaller and the lowest voltage becomes larger, thus, during the charge-discharge process of the selected word line, the voltage change (ΔV2) on the adjacent non-selected word line can be effectively reduced, thereby mitigating the row hammer problem and the GIDL leakage problem.

[0042] In one example of the present disclosure, as illustrated in FIG. 6, the voltage on an adjacent unselected word line reaches a second voltage (V2) at a second time point (T2), and the duration between the first time point (T1) and the second time point (T2) is a first duration (ΔT1); the voltage on an adjacent unselected word line reaches a third voltage (V3) at a fifth time point (T5); the duration between the fourth time point (T4) and the fifth time point (T5) is a second duration (ΔT2); the time difference between the third time point (T3) and the first time point (T1) is greater than or equal to the first duration (ΔT1); and the time difference between the sixth time point (T6) and the fourth time point (T4) is greater than or equal to the second duration (ΔT2).

[0043] The voltage is Vneg_local<n+1 또는 n-1> Through , adjacent non-selected word lines (wl_<n+1 또는 n-1> If transmitted to ), Vneg_local<n+1 또는 n-1> Because the voltage of the phase changes from the first voltage (V1) to the second voltage (V2) at time (T2), the adjacent unselected word line (wl_<n+1 또는 n-1> It can be understood that the time period required by ) to begin decreasing from the first voltage (V1) to a stable second voltage (V2) is the first time period (ΔT1). Based on this, here, the time difference between the third time point (T3) and the first time point (T1) is greater than or equal to the first time length (ΔT1). Adjacent non-selected word line (wl_<n+1 또는 n-1> When the voltage on ) drops to the second voltage (V2) or thereafter, and the adjacent unselected word line (wl_<n+1 또는 n-1> ) Although the voltage on the ) has not dropped to the second voltage (V2), however, if it is between the first voltage (V1) and the second voltage (V2), the precharge operation of the selected word line begins, so the adjacent unselected word line (wl_ that is being pulled up by the coupling)<n+1 또는 n-1> It can be understood that the initial voltage of ) is not controlled to a minimum value.

[0044] Likewise, here, the time difference between the 6th time point (T6) and the 4th time point (T4) is greater than or equal to the 2nd time length (ΔT2). Adjacent non-selected word lines (wl_<n+1 또는 n-1> When the voltage on ) rises to the third voltage (V3) or thereafter, and adjacent non-selected word line (wl_<n+1 또는 n-1> ) When the voltage on the ) has not risen to the third voltage (V3), but is between the second voltage (V2) and the third voltage (V3), the discharge operation of the selected word line begins, so the adjacent unselected word line (wl_) being pulled down by the coupling<n+1 또는 n-1> It can be understood that the initial voltage of ) is not controlled to a maximum value. In this way, the control effect on the voltage change amplitude of an adjacent non-selected word line during the charge-discharge process of the selected word line is further improved by setting a first time period to ensure that the voltage on the adjacent non-selected word line reaches a second voltage (V2) before the precharge of the selected word line, and by setting a second time period to ensure that the voltage on the adjacent non-selected word line reaches a third voltage (V3) before the discharge of the selected word line.

[0045] In another example, after the first time point (T1), the timing for starting the precharge operation of the selected word line can be selected according to actual needs. For example, the precharge operation of the selected word line can be started at any time between the first time point (T1) and the second time point (T2). The precharge operation of the selected word line is adjacent to the unselected word line (wl_<n+1 또는 n-1> It can be understood that this starts before the voltage on ) drops to the second voltage (V2). In this way, adjacent unselected word lines (wl_ that are being pulled up by the coupling)<n+1 또는 n-1> While reducing the initial voltage of ), the waiting time of the precharge operation can also be controlled.

[0046] Likewise, after the fourth time point (T4), the timing for starting the discharge operation of the selected word line can be selected according to actual necessity. For example, the discharge operation of the selected word line can be started at any time between the fourth time point (T4) and the fifth time point (T5). The discharge operation of the selected word line is adjacent to the unselected word line (wl_<n+1 또는 n-1> It can be understood that the voltage on ) starts before it rises to the third voltage (V3). In this way, adjacent unselected word lines (wl_ that are being pulled down by the coupling)<n+1 또는 n-1> While increasing the initial voltage of the ) the standby time of the discharge operation can also be controlled. In some examples, the first voltage (V1) and the third voltage (V3) are the same.

[0047] In some examples, the relationship between the second voltage, the first voltage, and the precharge voltage is as follows in mathematical equation (1):

[0048] |V2|=r(Vpp-V1) (1)

[0049] Here, V1 is the first voltage, V2 is the second voltage, Vpp is the precharge voltage, and r is the coupling coefficient.

[0050] In one example, the coupling coefficient (r) = C1 / C2, where C1 represents the capacitance between the selected word line and the adjacent non-selected word line, and C2 represents the capacitance of the selected word line.

[0051] It should be noted that the word line is connected to the memory cell through the gate of the transistor (see FIG. 2), and the capacitance of the word line refers to the sum of the write capacitance and the load capacitance. The write capacitance refers to the amount of charge that is charged or discharged on the word line when data is being written to the memory cell. When a write operation is performed, it involves transferring charge between the word line and the memory cell to change the charge state of the memory cell. The size of the write capacitor is related to the amount of charge required, the size of the memory cell, etc. The load capacitance refers to the capacitance caused by other circuit components connected to the word line (e.g., read circuit, decoding circuit buffer, etc.). In some examples, the coupling factor (r) is related to the physical distance between the selected word line and the adjacent unselected word line. The smaller the physical distance between the selected word line and the adjacent unselected word line, the greater the capacitance between the selected word line and the adjacent unselected word line, and the larger the coupling factor (r).

[0052] When the first voltage (V1) and the third voltage (V3) are different, it can be understood that the relationship between the second voltage, the third voltage, and the precharge voltage is as follows in Equation (2):

[0053] |V2|=r(Vpp-V3) Equation (2)

[0054] Here, V3 is the third voltage, V2 is the second voltage, Vpp is the precharge voltage, and r is the coupling coefficient.

[0055] In the example of the present disclosure, for illustrative purposes, it is considered that the first voltage (V1) and the third voltage (V3) are identical. As illustrated in FIG. 5, the peripheral circuit (210) comprises: a first voltage generator (214), a second voltage generator (215), a first voltage transmission circuit (211), and a second voltage transmission circuit (212); the first voltage generator (214), connected to the first voltage transmission circuit (211), is configured to provide the first voltage (V1); the second voltage generator (215), connected to the second voltage transmission circuit (212), is configured to provide the second voltage (V2); and the first voltage transmission circuit (211) is configured to transmit the first voltage (V1) to an adjacent non-selected word line in response to a first control signal (wlup_enb) at a fourth time point (T4); The second voltage transmission circuit (212) is configured to transmit the second voltage (V2) to an adjacent non-selected word line in response to the second control signal (wlup_vneg2) at the first time point (T1).

[0056] In some examples, the first voltage generator (214) and the second voltage generator (215) may belong to the voltage generator of the peripheral circuit. In some specific examples, both the first voltage generator (214) and the second voltage generator (215) may include a charge pump. The first voltage generator (214) and the second voltage generator (215) may be integrated on a single charge pump having multiple outputs, or they may belong to different charge pumps.

[0057] In some examples, as illustrated in FIGS. 5 and 6, the peripheral circuit (210) further includes a control signal generating circuit (216); the control signal generating circuit (216) is configured to receive an enable control signal (wlup_en) and to provide a first control signal (wlup_enb) to a first voltage transmission circuit (211) and a second control signal (wlup_vneg2) to a second voltage transmission circuit (212).

[0058] In some examples, as illustrated in FIG. 5, the peripheral circuit further includes a plurality of driving circuits (213) for local word lines corresponding one-to-one to the word lines; the driving circuits (213) for local word lines include a main word line selection signal (mwl_n <k>), word line selection signal (wld <n>) and precharge control signal (xpp <n>In response to ), the adjacent unselected word line is configured to be connected to the first voltage transmission circuit (211) at the third time point (T3), and the adjacent unselected word line is configured to be connected to the second voltage transmission circuit (212) at the first time point (T1); wherein, the main word line selection signal (mwl_n <k>) indicates selecting one main word line among a plurality of main word lines in the peripheral device circuit, each main word line corresponds to a plurality of word lines; and the word line selection signal (wld <n>) indicates selecting one word line corresponding to the main word line among multiple word lines; precharge control signal (xpp <n>) indicates providing precharge voltage to the selected word line.

[0059] In some examples, as illustrated in FIG. 5, the control signal generation circuit (216) is connected to the first voltage transmission circuit (211) through the first node (N1); and the control signal generation circuit (216) is connected to the second voltage transmission circuit (212) through the second node (N2); both the first voltage transmission circuit (211) and the second voltage transmission circuit (212) are connected to the driving circuit (213) for the local word line through the third node (N3); and both the first voltage generator (214) and the second voltage generator (215) are connected to the control signal generation circuit (216).

[0060] In some examples, multiple driving circuits for local word lines are divided into multiple groups; each group corresponds to one first voltage generator, one second voltage generator, one first voltage transmission circuit, and one second voltage transmission circuit.

[0061] Main word line selection signal(mwl_n <k>) and word line selection signal (wld <n>It can be understood that a word line can be selected through both, and that each word line corresponds to a driver circuit for a local word line; and that a plurality of driver circuits for local word lines corresponding to a plurality of word lines have different word line selection signals (wld <n>Divided into multiple groups according to ), and a word line selection signal (wld) corresponding to all word lines of the same group <n>) is in the same level state and is a main word line selection signal (mwl_n) corresponding to an unselected word line or a selected word line of the same group. <k>) is in a different level state.

[0062] In one example, one block shares a control signal generation circuit, and the driving circuits for 16 local word lines within one block are divided into four groups, each group sharing the same first voltage generator, the same second voltage generator, the same first voltage transmission circuit, and the same second voltage transmission circuit. That is, the 16 word lines corresponding to the driving circuits for local word lines are divided into four groups, each connected to four first voltage transmission circuits and four second voltage transmission circuits, and for every four word lines, the four word lines connected to the same first voltage transmission circuit and the same second voltage transmission circuit will be selected simultaneously or will not be selected, and the corresponding word line selection signal (wld <n>) is identical.

[0063] In this way, the circuit area can be significantly reduced through a plurality of driving circuits for local word lines, each group of driving circuits for local word lines sharing one first voltage generator, one second voltage generator, one first voltage transmission circuit, and one second voltage transmission circuit.

[0064] FIG. 7 is a partial structure schematic diagram of a peripheral circuit provided by an example of the present disclosure. In some examples, as shown in FIG. 7, a first voltage transmission circuit (211) includes a first transistor (M1), and a second voltage transmission circuit (212) includes a second transistor (M2) and a third transistor (M3);

[0065] The first terminal of the first transistor receives a first control signal (wlup_enb), the second terminal is connected to a first voltage generator (not shown in FIG. 7), and the third terminal is connected to the third terminal of the second transistor (M2). The output terminal of the first voltage generator outputs a first voltage (V1), and the first voltage (V1) may be a voltage (VNEG).

[0066] The first terminal of the second transistor (M2) receives the second control signal (wlup_vneg2), and the second terminal is connected to the third terminal of the third transistor (M3).

[0067] The first terminal of the third transistor (M3) is the word line select signal (wld <n>It receives ), and the second terminal is connected to the output terminal of the second voltage generator (not shown in FIG. 7). The output terminal of the second voltage generator outputs a second voltage (V2), and the second voltage (V2) may be a voltage (VNEG2).

[0068] It can be understood that the third terminal of the first transistor (M1) and the third terminal of the second transistor (M2) are connected through the third node (N3).

[0069] In some examples, as illustrated in FIG. 7, the control signal generating circuit (216) comprises a fourth transistor (M4), a fifth transistor (M5), a sixth transistor (M6), and a seventh transistor (M7); wherein: the first terminal of the fourth transistor (M4) receives an enable control signal (wlup_en), the second terminal receives a high-level voltage such as Vpp or Vdd, and the third terminal is connected to the third terminal of the fifth transistor (M5) to output a first control signal (wlup_enb). It can be understood that the third terminal of the fourth transistor (M4) and the third terminal of the fifth transistor (M5) are connected through a first node (N1).

[0070] The first terminal of the fifth transistor (M5) is connected to the first terminal of the fourth transistor (M4), and the second terminal receives the voltage (VNEG).

[0071] The first terminal of the sixth transistor (M6) receives the first control signal (wlup_en), the second terminal receives a high-level voltage such as Vpp or Vdd, and the third terminal is connected to the third terminal of the seventh transistor (M7) to output the second control signal (wlup_vneg2). It can be understood that the third terminal of the sixth transistor (M6) and the third terminal of the seventh transistor (M7) are connected through the second node (N2).

[0072] The first terminal of the seventh transistor (M7) is connected to the first terminal of the sixth transistor (M6), and the second terminal receives the voltage (VNEG2).

[0073] In some examples, as illustrated in FIG. 4, the driving circuit (213) for the local word line includes an eighth transistor (M8), a ninth transistor (M9), and a tenth transistor (M10); where:

[0074] The first terminal of the 8th transistor (M8) is the main word line select signal (mwl_n <k>) receives, and the second terminal receives a precharge control signal (xpp <n>) receives, and the third terminal is the selected word line (wl <n>It is coupled to ).

[0075] The first terminal of the ninth transistor (M9) is the main word line select signal (mwl_n <k>) receives, the second terminal is connected to the second terminal of the 10th transistor (M10), and the third terminal is a word line (wl <n>It is coupled to ).

[0076] The first terminal of the 10th transistor (M10) is a word line select signal (wld <n>) receives, and the second terminal is connected to the N3 node, that is, the third terminal of the first transistor (M1) and the third terminal of the second transistor (M2), and the third terminal is a word line (wL <n>It is coupled to ).

[0077] In some examples, the first transistor (M1), the second transistor (M2), the third transistor (M3), the fourth transistor (M4), the fifth transistor (M5), the sixth transistor (M6), the seventh transistor (M7), the eighth transistor (M8), the ninth transistor (M9), and the tenth transistor (M10) are field-effect MOS transistors; where the first terminal of the field-effect MOS transistor is the gate, the second terminal of the field-effect MOS transistor is the source, and the third terminal of the field-effect MOS transistor is the drain.

[0078] In some examples, the first transistor (M1), the second transistor (M2), the third transistor (M3), the fifth transistor (M5), the seventh transistor (M7), the ninth transistor (M9), and the tenth transistor (M10) are N-type channel field-effect MOS transistors; and the fourth transistor (M4), the sixth transistor (M6), and the eighth transistor (M8) are P-type channel field-effect MOS transistors.

[0079] FIG. 7 shows only a driving circuit (213) for a local word line corresponding to only one word line, but it should be noted that in reality, each word line is provided with its own driving circuit (213) for a local word line.

[0080] In one example of the present disclosure, the precharge voltage is a high-level voltage; and the first voltage, the second voltage, and the third voltage are all negative voltages. In one example, the precharge voltage is Vpp, and the voltage range is from 2.2V to 2.8V; the first voltage and the third voltage are VNEG, and the voltage range is from -0.2V to -0.1V; and the second voltage is VNEG2, and the voltage range is from -0.8V to -0.4V.

[0081] The following describes in detail a method for implementing voltage supply to a non-selected word line through various specific circuits of the peripheral circuit during the process from the precharge operation to the discharge operation of the selected word line, in combination with FIGS. 6 and 7, to reduce the large pressure difference caused by coupling to an adjacent word line.

[0082] Referring to FIGS. 6 and 7, prior to the first time point (T1), the enable control signal (wlup_en) (not shown in FIG. 6) is a low-level voltage, the fourth transistor (M4) is turned on, and the fifth transistor (M5) is turned off, and thus, the first control signal (wlup_enb) provided to the first voltage transmission circuit (211) by the control signal generation circuit (216) is a high-level voltage (Vpp), the first transistor (M1) is turned on, and thus the voltage (VNEG) is transmitted to the driving circuit (213) for the local word line corresponding to the word line through the first transistor (M1) of the first voltage transmission circuit (211) which is in the turned-on state. For all word lines, the main word line selection signal (mwl_n <k>) and word line selection signal (wld <n>) is a high-level voltage (Vpp) prior to time (T1), the ninth transistor (M9) is turned on, and the tenth transistor (M10) is turned on, and based on this, the voltage provided by the first voltage transmission circuit (211) on all word lines through M9 and M10 is voltage (VNEG). Here, voltage (VNEG) is the same as the first voltage (V1) shown in FIG. 6.

[0083] At the same time, prior to time (T2), the voltage on the first node (N1) is a high level voltage (Vpp), the sixth transistor (M6) is turned off, and the seventh transistor (M7) is turned on, and thus, the second control signal (wlup_vneg2) provided to the second voltage transmission circuit (212) by the control signal generation circuit (216) is a voltage (VNEG2), and the second transistor (M2) is turned off, and thus, there is no connection between the second voltage transmission circuit (211) and the driving circuit for the local word line, that is, the second voltage transmission circuit (211) does not provide voltage to the driving circuit for the local word line.

[0084] Next, at the first time point (T1), the enable control signal (wlup_en) is changed from a low level voltage to a high level voltage, the fourth transistor (M4) is turned off, and the fifth transistor (M5) is turned on, and thus, the first control signal (wlup_enb) provided to the first voltage transmission circuit (211) by the control signal generation circuit (216) is switched from a high level voltage (Vpp) to a voltage (VNEG).

[0085] At time (T2), the voltage on the first node (N1) is also switched from a high-level voltage (Vpp) to a voltage (VNEG), the sixth transistor (M6) is turned on, and the seventh transistor (M7) is turned off, and thus the second control signal (wlup_vneg2) provided to the second voltage transmission circuit (212) by the control signal generation circuit (216) is switched from a voltage (VNEG2) to a high-level voltage (Vpp). Here, the voltage (VNEG2) is the same as the second voltage (V2) shown in FIG. 6.

[0086] Simultaneously, at the first time point (T1), for an adjacent unselected word line, the first control signal (wlup_enb) is a voltage (VNEG), and the first transistor (M1) is turned off. The second control signal (wlup_vneg2) is a high-level voltage (Vpp), and the second transistor (M2) is turned on. For an unselected word line, the word line selection signal (wld <n>) is a high-level voltage, and the third transistor (M3) is turned on. Accordingly, the voltage (VNEG2) is transmitted through the second transistor (M2) and the third transistor (M3) of the second voltage transmission circuit (212) to the driving circuit (213) for the local word line corresponding to the adjacent non-selected word line. In the case of the adjacent non-selected word line, the word line selection signal (wld <n>) is a high-level voltage, and the 10th transistor (M10) is turned on, and thus the voltage (VNEG2) is transmitted to the corresponding adjacent non-selected word line through the driving circuit (213) for the local word line. Based on this, at the first time point (T1), the voltage provided on the adjacent non-selected word line is reduced from voltage (VNEG) to voltage (VNEG2).

[0087] At the first time point (T1), for the selected word line, a word line selection signal (wld <n>) is a low-level voltage, the third transistor (M3) is turned off, the tenth transistor (M10) is turned off, and the main word line select signal (mwl_n <k>Each of ) changes from a high level to a low level at time (T1), and the precharge control signal (xpp <n>It should be noted that ) is at a low level at time (T1), at which time both the 8th transistor (M8) and the 9th transistor (M9) are turned off and the selected word line is floating, but, due to the coupling effect with the adjacent non-selected word line, the voltage on the selected word line gradually decreases from the voltage (VNEG).

[0088] Next, at the third time point (T3), for the selected word line, the precharge control signal (xpp <n>) changes from a low level voltage to a high level voltage, and the main word line select signal (mwl_n <k>) is a low-level voltage, and the word line select signal (wld <n>) is a low level voltage, at which time the 8th transistor (M8) is turned on, the 9th transistor (M9) and the 10th transistor (M10) are turned off, and the driving circuit (213) for the local word line corresponding to the selected word line begins to provide a precharge voltage (Vpp) to the selected word line through the 8th transistor (M8).

[0089] At the same time, at the third time point (T3), the voltage (VNEG2) is still transmitted to the corresponding adjacent non-selected word line through the driving circuit (213) for the local word line. However, due to the coupling effect with the selected word line, the voltage on the adjacent non-selected word line begins to gradually increase from the voltage (VNEG2).

[0090] Next, at the fourth time point (T4), the driving circuit (213) for the local word line corresponding to the selected word line still provides a precharge voltage (Vpp) to the selected word line through the eighth transistor (M8).

[0091] Simultaneously, at the fourth time point (T4), for an adjacent unselected word line, the first control signal (wlup_enb) is switched from the voltage (VNEG) to a high-level voltage (Vpp), and the first transistor (M1) is turned on. The second control signal (wlup_vneg2) is switched from the high-level voltage (Vpp) to the voltage (VNEG2), and the second transistor (M2) is turned off. The word line selection signal (wld <n>) is a high-level voltage, and the third transistor (M3) is turned on. At this time, the voltage (VNEG) is transmitted through the first transistor (M1) of the first voltage transmission circuit (211) to the driving circuit (213) for the local word line corresponding to the adjacent non-selected word line. In the case of the adjacent non-selected word line, the word line selection signal (wld <n>) is a high level voltage, and the 10th transistor (M10) is turned on, and thus, the voltage (VNEG) is transmitted to the corresponding adjacent non-selected word line through the driving circuit (213) for the local word line.

[0092] At the fourth time point (T4), it can be understood that the voltage provided on the adjacent non-selected word line changes from voltage (VNEG2) to voltage (VNEG). Here, voltage (VNEG) is the same as the third voltage (V3) shown in FIG. 6.

[0093] Next, at the 6th time point (T6), for the selected word line, the precharge control signal (xpp <n>The voltage is changed from a high level voltage to a low level voltage, the eighth transistor (M8) is turned off, the driving circuit (213) for the local word line corresponding to the selected word line stops providing the precharge voltage (Vpp) for the selected word line, and the memory starts floating the selected word line.

[0094] Next, at the seventh time point (T7) after a predetermined buffer time elapsed after the sixth time point (T6), the selected word line begins to discharge. Here, the buffer discharge can be achieved through a falling edge delay circuit (not shown in FIG. 7). At this time, the voltage provided to the adjacent non-selected word line by the driving circuit (213) for the local word line corresponding to the adjacent non-selected word line is still VNEG, however, due to the coupling effect with the selected word line, the voltage on the adjacent non-selected word line begins to gradually decrease from the VNEG voltage.

[0095] As mentioned earlier, as the memory size is reduced, the physical distance between word lines will be further reduced, and the row hammer can affect not only the word lines of adjacent lines, but even the word lines of nearby lines (two or more adjacent lines).

[0096] Based on this, in some examples, when the selected word line is the Nth word line, the adjacent non-selected word lines include at least the (N-1)th word line and the (N+1)th word line.

[0097] In some specific examples, adjacent non-selected word lines include additional word lines spaced apart by M word lines from the selected word line; where M is a natural number and 1 ≤ M ≤ 4.

[0098] Here, M can be determined based on the range of surrounding rows affected by the row hammer in actual application.

[0099] In one example, if the selected word line is the 6th word line, the adjacent unselected word lines include the 5th word line and the 7th word line. The adjacent unselected word lines may also include the 4th word line and the 8th word line, the 3rd word line and the 9th word line, and the 2nd word line and the 10th word line.

[0100] It should be noted that if adjacent non-selected word lines include multiple word lines, each word line will receive a corresponding voltage according to the timing required by the examples of the present disclosure.

[0101] In some examples, for each adjacent unselected word line of a plurality of adjacent unselected word lines, each adjacent unselected word line may drop from the same second voltage (V2) from the first voltage (V1) when rising coupling begins, and each adjacent unselected word line may rise from the same third voltage (V3) from the second voltage (V2) when down coupling begins.

[0102] In some other examples, for each adjacent unselected word line of a plurality of adjacent unselected word lines, each adjacent unselected word line may drop from a first voltage (V1) to a different second voltage (V2) in advance when rising coupling begins, and each adjacent unselected word line may rise from the second voltage (V2) to a different third voltage (V3) in advance when down coupling begins. Here, the adjustment value between the different second voltages (V2) and the adjustment value between the different third voltages (V3) may be determined according to the distance between each adjacent unselected word line and the selected word line. For example, the smaller the distance, the greater the coupling effect, the greater the absolute value of the difference between the first voltage (V1) and the second voltage (V2), and the greater the absolute value of the difference between the second voltage (V2) and the third voltage (V3); As the distance increases, the coupling effect becomes smaller, the absolute value of the difference between the first voltage (V1) and the second voltage (V2) becomes smaller, and the absolute value of the difference between the second voltage (V2) and the third voltage (V3) becomes smaller.

[0103] It can be understood that as the distance between an adjacent non-selected word line and a selected word line increases, the absolute value of the voltage difference between the second voltage and the first voltage decreases. For example, the greater the distance between the selected word line and the adjacent non-selected word line, the smaller the capacitance between the selected word line and the adjacent non-selected word line becomes, the smaller the coupling coefficient (r) becomes, and the smaller the influence of the selected word line on the adjacent non-selected word line becomes, and thus, when the absolute value of the voltage difference between the second voltage and the first voltage is small, interference of the selected word line on the adjacent non-selected word line can be prevented.

[0104] Due to improvements in the row hammer problem, the refresh frequency of memory caused by the row hammer problem can be reduced to some extent, and consequently, the power consumption of the memory can also be reduced to some extent, and as the power consumption decreases, the complexity of the memory's peripheral circuits can also be reduced.

[0105] FIG. 8a is a schematic diagram illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to one example of the present disclosure; FIG. 8b is a schematic top view illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to one example of the present disclosure.

[0106] As illustrated in FIG. 8a, an array of memory cells (220) and peripheral circuits (210) are arranged in parallel. More specifically, the array of memory cells comprises M banks, each bank comprises N blocks, at least one side of each block is provided with a control circuit corresponding to the block, at least one side of each bank is provided with a control circuit corresponding to the bank, every K of the M banks form a bank row, M banks form M / K bank rows, and peripheral circuits corresponding to all banks are provided between two central bank rows. Here, it should be noted that M, N, and K are all positive integers, and M is an integer multiple of K.

[0107] In one example, as illustrated in FIG. 8b, an array (220) of memory cells comprises 16 banks (Bank0-Bank15), each bank comprises a plurality of blocks, each block is surrounded by a corresponding block (SA and WLD), both sides of each bank are equipped with a column decoder and a row decoder corresponding to the bank, every 4 banks form a bank row, 16 banks form 4 bank rows, and a control circuit corresponding to all banks is provided between the two central bank rows. It should be noted that the number of banks in FIG. 8b is used merely as an example and is not used to limit the number of banks in the memory in this disclosure.

[0108] As mentioned above, in order to suppress coupling effects in the examples of the present disclosure, a first voltage generator (214), a second voltage generator (215), a control signal generating circuit (216), a first voltage transmission circuit (211) and a second voltage transmission circuit (212), etc. are added. However, in the arrangement of the array of memory cells and peripheral circuits shown in FIGS. 8a and 8b, there may not be any extra positions to place these newly added circuits. Considering that the array of memory cells of the DRAM occupies a larger area than that of the peripheral circuits, in some examples, the array of memory cells of the DRAM and the peripheral circuits are stacked and electrically connected through bonding, and there may also be some extra space in the semiconductor layer where the peripheral circuits are located, and this extra space can be used to place the newly added circuits described above.

[0109] FIG. 9a is a schematic diagram illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to another example of the present disclosure; FIG. 9b is a schematic top view illustrating the distribution of an array of memory cells and peripheral circuits in an exemplary memory according to another example of the present disclosure.

[0110] As illustrated in FIG. 9a, the first semiconductor structure (100) is positioned on the second semiconductor structure (200). The first semiconductor structure (100) includes an array (220) of memory cells, and the second semiconductor structure (200) includes a peripheral device circuit (210).

[0111] In FIG. 9b, the first semiconductor structure corresponding to FIG. 9a is positioned above the second semiconductor structure, the structure corresponding to the solid line in FIG. 9b is positioned within the first semiconductor structure, and the structure corresponding to the dotted line is positioned within the second semiconductor structure; it should be noted that for ease of understanding, the structure within the second semiconductor structure is shown through a perspective view. That is, in the enlarged view corresponding to each block in FIG. 9b, the solid line represents the enlarged portion of the block, and the dotted line represents the structure within the second semiconductor structure at a position immediately below the block.

[0112] In one example, as illustrated in FIG. 9b, an array of memory cells (220) comprises 16 banks (Bank0-Bank15), each bank comprises a plurality of blocks, and a first voltage generator (214), a second voltage generator (215), a control signal generation circuit (216), a first voltage transmission circuit (211), and a second voltage transmission circuit (212) are provided immediately below each block, and depending on actual needs, a control signal generation circuit (216) shared by the blocks, and a plurality of first voltage generators (214), a plurality of second voltage generators (215), a plurality of first voltage transmission circuits (211), and a plurality of second voltage transmission circuits (212) corresponding to the blocks may be provided immediately below the blocks.

[0113] It should be noted that in FIG. 9b, the number of control signal generation circuits (216), first voltage generators (214), a plurality of second voltage generators (215), first voltage transmission circuits (211) and second voltage transmission circuits (212) is used merely as an example and is not used to limit the number and location of corresponding circuits in memory in the present disclosure.

[0114] In addition to the newly added circuit described above, it should be noted that if space permits, the SA and WLD corresponding to each block can be set immediately below the block, that is, within the dotted box shown in FIG. 9b.

[0115] In some specific examples, the array of memory cells (220) and the peripheral circuit (210) are bonded in a manner including, but not limited to, hybrid bonding, anodic bonding, melt bonding, transfer bonding, adhesive bonding, eutectic bonding, etc.

[0116] When the memory is stacked by bonding, newly added circuits and related circuits, such as SA and WLD in the example of the present disclosure, may be placed below the array. Due to the way the stacking is configured, no additional area costs are incurred.

[0117] With the development of memory such as DRAM, process means are utilized to improve or eliminate leakage induced by line hammer, but as the scale of the process becomes increasingly large, the effect is limited. An example of the present disclosure improves the neighboring word line coupling effect from the perspective of design control without increasing memory overhead.

[0118] FIG. 10 is a schematic flowchart of an embodiment of a method for operating a memory provided by an embodiment of the present disclosure. An example of the present disclosure provides a method for operating a memory, and the method for operating a memory specifically comprises the following steps:

[0119] Step (S10): At a first time, a precharge voltage is started to be provided to a selected word line among a plurality of word lines of memory; the voltage provided on a non-selected word line adjacent to the selected word line is changed from a first voltage to a second voltage at a second time, which is prior to the first time;

[0120] Step (S20): Start plotting the selected word line at the third time, which is after the first time; the voltage provided on the adjacent unselected word line is changed from the second voltage to the third voltage at the fourth time, which is before the third time and after the first time; the second voltage is lower than the first voltage and the third voltage.

[0121] The method will be described below with reference to FIGS. 6 and FIGS. 10. Regarding the structure of the memory, reference may be made to the relevant description of the example described above, which will not be repeated here.

[0122] In some examples, at a third time point (T3), a precharge voltage (Vpp) is started to be provided to a selected word line among a plurality of word lines; the voltage provided on an unselected word line adjacent to the selected word line is changed from a first voltage (V1) to a second voltage (V2) at a first time point (T1) prior to the third time point (T3); and at a sixth time point (T6) prior to the third time point (T3), the selected word line is started to be floated; the voltage provided on an adjacent unselected word line is changed from a second voltage (V2) to a third voltage (V3) at a fourth time point (T4) prior to the sixth time point (T6) and after the third time point (T3); and the second voltage (V2) is lower than the first voltage (V1) and the third voltage (V3).

[0123] By reducing the voltage provided to the adjacent non-selected word line before the precharge of the selected word line, the final voltage from the voltage on the adjacent non-selected word line being pulled up by coupling is controlled, i.e., it is the highest voltage in the subsequent voltage change; meanwhile, by increasing the voltage provided to the adjacent non-selected word line before the discharge of the selected word line, the final voltage from the voltage on the adjacent non-selected word line being pulled down by coupling is controlled, i.e., it is the lowest voltage in the subsequent voltage change. In this way, during the charge-discharge process of the selected word line, the voltage change on the adjacent non-selected word line can be effectively reduced, the alteration of the contents and bit inversion of the adjacent memory cell can be prevented, and thereby, data security can be protected.

[0124] In some examples, the voltage on an adjacent unselected word line reaches a second voltage (V2) at a second time point (T2), and the duration between the first time point (T1) and the second time point (T2) is a first duration (ΔT1); the voltage on an adjacent unselected word line reaches a third voltage (V3) at a fifth time point (T5); the duration between the fourth time point (T4) and the fifth time point (T5) is a second duration (ΔT2); the time difference between the third time point (T3) and the first time point (T1) is greater than or equal to the first duration (ΔT1); and the time difference between the sixth time point (T6) and the fourth time point (T4) is greater than or equal to the second duration (ΔT2).

[0125] In this way, the control effect on the voltage change amplitude of an adjacent non-selected word line during the charge-discharge process of a selected word line is further improved by setting a first time period to ensure that the voltage on the adjacent non-selected word line reaches a second voltage before the precharge of the selected word line, and by setting a second time period to ensure that the voltage on the adjacent non-selected word line reaches a third voltage before the discharge of the selected word line.

[0126] In some examples, the first voltage (V1) and the third voltage (V3) are the same.

[0127] Examples of the present disclosure further provide a memory system, the memory system comprising: at least one memory as disclosed in one example of the present disclosure; and a controller coupled to the memory and configured to control the memory.

[0128] Here, memory can be understood by referring to the memory of the aforementioned example of the present disclosure. The internal configuration of the memory system can be understood by referring to the aforementioned memory system.

[0129] Examples of the present disclosure further provide a control circuit for a word line voltage comprising: a first voltage transmission circuit configured to provide a first transmission voltage in response to a first enable signal prior to the start of providing a precharge voltage for a selected word line; a second voltage transmission circuit configured to provide a second transmission voltage in response to a second enable signal prior to the start of floating of the selected word line and after the start of providing a precharge voltage for the selected word line; and a driving circuit for a local word line connected to both the first voltage transmission circuit and the second voltage transmission circuit, configured to connect a non-selected word line adjacent to the selected word line to the first voltage transmission circuit prior to the start of providing a precharge voltage for the selected word line, and to connect a non-selected word line adjacent to the second voltage transmission circuit prior to the start of floating of the selected word line and after the start of providing a precharge voltage for the selected word line.

[0130] Here, the structure of the first voltage transmission circuit described above can be understood by referring to the second voltage transmission circuit of FIG. 7, and the second voltage transmission circuit described above can be understood by referring to the first voltage transmission circuit shown in FIG. 7.

[0131] The first enable signal described above can be understood by referring to the second control signal (wlup_vneg2) shown in FIG. 7, and the first transmission voltage described above can be understood by referring to the second voltage (V2) shown in FIG. 6. The second enable signal described above can be understood by referring to the first control signal (wlup_enb) shown in FIG. 7, and the second transmission voltage described above can be understood by referring to the first voltage (V1) shown in FIG. 6.

[0132] The methods disclosed in the various method examples provided in this disclosure can be optionally combined without conflict to obtain new method examples.

[0133] Features disclosed in the various device examples provided in this disclosure can be optionally combined without conflict to obtain new device examples.

[0134] The foregoing is merely a specific embodiment of the present disclosure, and the claims of the present disclosure are not limited to such specific examples; any modifications or alternatives within the technical scope disclosed in the present disclosure that can be readily devised by a person skilled in the art should fall within the scope of the claims of the present disclosure.

[0135] Examples of the present disclosure provide a memory and a method of operating the same, a memory system, and a control circuit for a word line voltage. The memory controls the final voltage from the voltage on the adjacent non-selected word line that is pulled up by coupling by reducing the voltage provided to the adjacent non-selected word line prior to the precharge of the selected word line, i.e., it is the highest voltage in the subsequent voltage change; meanwhile, it controls the final voltage from the voltage on the adjacent non-selected word line that is pulled down by coupling by increasing the voltage provided to the adjacent non-selected word line prior to the discharge of the selected word line, i.e., it is the lowest voltage in the subsequent voltage change. Because the highest voltage causing the voltage change becomes smaller and the lowest voltage becomes larger, thus, during the charge-discharge process of the selected word line, the voltage change on the adjacent non-selected word line can be effectively reduced, thereby mitigating the row hammer problem and the GIDL leakage problem.< / n> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / k> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n> < / n>

Claims

Claim 1 A memory device comprising: an array of memory cells; a plurality of word lines coupled to the memory cells; and a peripheral circuit coupled to the memory cells through the word lines and configured to reduce a first voltage on at least one non-selected word line adjacent to a selected word line to a second voltage; provide a precharge voltage to the selected word line after the at least one non-selected word line reaches the second voltage; increase the second voltage on the at least one non-selected word line to a third voltage; and float the selected word line after the at least one non-selected word line reaches the third voltage. Claim 2 delete Claim 3 A memory device according to claim 1, wherein the first voltage is substantially the same as the third voltage. Claim 4 A memory device according to paragraph 3, wherein the magnitude of the second voltage is the value obtained by multiplying the difference between the precharge voltage and the first voltage by a coupling coefficient. Claim 5 In paragraph 3, the peripheral device circuit comprises: a first voltage transmission circuit configured to supply the first voltage to the at least one non-selected word line in response to a first control signal; and a second voltage transmission circuit configured to supply the second voltage to the at least one non-selected word line in response to a second control signal, a memory device. Claim 6 In claim 5, the peripheral device circuit further comprises a control signal generating circuit, and the control signal generating circuit is configured to provide the first control signal to the first voltage transmission circuit and provide the second control signal to the second voltage transmission circuit in response to an enable control signal, a memory device. Claim 7 In claim 6, the peripheral circuit further comprises a plurality of driving circuits configured to cause at least one non-selected word line adjacent to the selected word line to be connected to the first voltage transmission circuit or the second voltage transmission circuit in response to a main word line selection signal, a word line selection signal, and a precharge control signal; wherein the main word line selection signal indicates a selected main word line among a group of main word lines corresponding to a subset of the plurality of word lines, the word line selection signal indicates the selected word line corresponding to the selected main word line in the subset of word lines, and the precharge control signal indicates providing the precharge voltage to the selected word line, a memory device. Claim 8 In claim 7, the memory device further comprises a first voltage generator and a second voltage generator connected to the control signal generation circuit; wherein the control signal generation circuit is connected to the first voltage transmission circuit at a first node and to the second voltage transmission circuit at a second node, and the first voltage transmission circuit and the second voltage transmission circuit are connected to the plurality of driving circuits at a third node. Claim 9 A memory device according to claim 7, wherein the plurality of driving circuits each comprise a plurality of groups of local word line driving circuits corresponding to one first voltage generator, one second voltage generator, one first voltage transmission circuit, and one second voltage transmission circuit. Claim 10 In claim 8, the first voltage transmission circuit comprises a first transistor - the first terminal of the first transistor receives the first control signal; the second terminal of the first transistor is connected to the first voltage generator; and the third terminal of the first transistor is connected to the third terminal of the second transistor - and the second voltage transmission circuit comprises a second transistor - the first terminal of the second transistor receives the second control signal and the second terminal of the second transistor is connected to the third terminal of the third transistor - and the third transistor - the first terminal of the third transistor receives the word line select signal and the second terminal of the third transistor is connected to the second voltage generator - a memory device. Claim 11 In claim 10, the first transistor, the second transistor, and the third transistor comprise a metal-oxide-semiconductor field-effect transistor (MOSFET); and the first terminal of the MOSFET is a gate, the second terminal of the MOSFET is a source, and the third terminal of the MOSFET is a drain, a memory device. Claim 12 A memory device according to claim 1, wherein the precharge voltage includes a positive voltage; and the first voltage, the second voltage, and the third voltage include a negative voltage. Claim 13 In claim 1, the memory device comprises a Dynamic Random Access Memory (DRAM) device. Claim 14 In paragraph 13, a memory device in which the array of memory cells and the peripheral device circuit are coupled by bonding. Claim 15 A memory device according to claim 1, wherein the selected word line is the Nth word line, and the at least one non-selected word line includes the (N-1) word line and the (N+1) word line. Claim 16 A memory device according to claim 15, wherein at least one non-selected word line further comprises a word line spaced apart from the selected word line by M word lines, M is a natural number, and 1 ≤ M ≤ 4. Claim 17 In claim 15, a memory device wherein the magnitude of the voltage difference between the second voltage and the first voltage decreases as the distance between the at least one non-selected word line and the selected word line increases. Claim 18 A memory system comprising at least one memory device - said at least one memory device comprises: an array of memory cells; a plurality of word lines coupled to said memory cells; and a peripheral circuit coupled to said memory cells through said word lines, configured to reduce a first voltage on a non-selected word line adjacent to a selected word line to a second voltage, provide a precharge voltage to said selected word line after the non-selected word line reaches the second voltage, increase the second voltage on said non-selected word line to a third voltage, and float said selected word line after the non-selected word line reaches the third voltage -; and a memory controller configured to control said at least one memory device through said peripheral circuit. Claim 19 A method for operating a memory device, comprising: determining a selected word line among a plurality of word lines coupled to an array of memory cells of the memory device; reducing a first voltage on at least one non-selected word line adjacent to the selected word line to a second voltage; providing a precharge voltage to the selected word line after the at least one non-selected word line reaches the second voltage; increasing the second voltage on the at least one non-selected word line to a third voltage; and floating the selected word line after the at least one non-selected word line reaches the third voltage. Claim 20 delete Claim 21 delete Claim 22 delete Claim 23 delete

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